diff --git a/llvm/lib/Target/X86/X86InstrMisc.td b/llvm/lib/Target/X86/X86InstrMisc.td index bd178f3a27fe7..a39b805927137 100644 --- a/llvm/lib/Target/X86/X86InstrMisc.td +++ b/llvm/lib/Target/X86/X86InstrMisc.td @@ -1159,67 +1159,51 @@ let Predicates = [HasRDSEED], Defs = [EFLAGS], SchedRW = [WriteSystem] in { //===----------------------------------------------------------------------===// // LZCNT Instruction // +multiclass Lzcnt o, string m, SDPatternOperator node, X86TypeInfo t, + SchedWrite schedrr, SchedWrite schedrm, string suffix = ""> { + def rr#suffix : ITy, + TB, Sched<[schedrr]>; + def rm#suffix : ITy, + TB, Sched<[schedrm]>; +} + let Predicates = [HasLZCNT], Defs = [EFLAGS] in { - def LZCNT16rr : I<0xBD, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), - "lzcnt{w}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, (ctlz GR16:$src)), (implicit EFLAGS)]>, - TB, XS, OpSize16, Sched<[WriteLZCNT]>; - def LZCNT16rm : I<0xBD, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), - "lzcnt{w}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, (ctlz (loadi16 addr:$src))), - (implicit EFLAGS)]>, TB, XS, OpSize16, Sched<[WriteLZCNTLd]>; - - def LZCNT32rr : I<0xBD, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), - "lzcnt{l}\t{$src, $dst|$dst, $src}", - [(set GR32:$dst, (ctlz GR32:$src)), (implicit EFLAGS)]>, - TB, XS, OpSize32, Sched<[WriteLZCNT]>; - def LZCNT32rm : I<0xBD, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), - "lzcnt{l}\t{$src, $dst|$dst, $src}", - [(set GR32:$dst, (ctlz (loadi32 addr:$src))), - (implicit EFLAGS)]>, TB, XS, OpSize32, Sched<[WriteLZCNTLd]>; - - def LZCNT64rr : RI<0xBD, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), - "lzcnt{q}\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, (ctlz GR64:$src)), (implicit EFLAGS)]>, - TB, XS, Sched<[WriteLZCNT]>; - def LZCNT64rm : RI<0xBD, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), - "lzcnt{q}\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, (ctlz (loadi64 addr:$src))), - (implicit EFLAGS)]>, TB, XS, Sched<[WriteLZCNTLd]>; + defm LZCNT16 : Lzcnt<0xBD, "lzcnt", ctlz, Xi16, WriteLZCNT, WriteLZCNTLd>, OpSize16, XS; + defm LZCNT32 : Lzcnt<0xBD, "lzcnt", ctlz, Xi32, WriteLZCNT, WriteLZCNTLd>, OpSize32, XS; + defm LZCNT64 : Lzcnt<0xBD, "lzcnt", ctlz, Xi64, WriteLZCNT, WriteLZCNTLd>, XS; + + defm LZCNT16 : Lzcnt<0xF5, "lzcnt", null_frag, Xi16, WriteLZCNT, WriteLZCNTLd, "_EVEX">, PL, PD; + defm LZCNT32 : Lzcnt<0xF5, "lzcnt", null_frag, Xi32, WriteLZCNT, WriteLZCNTLd, "_EVEX">, PL; + defm LZCNT64 : Lzcnt<0xF5, "lzcnt", null_frag, Xi64, WriteLZCNT, WriteLZCNTLd, "_EVEX">, PL; } +defm LZCNT16 : Lzcnt<0xF5, "lzcnt", null_frag, Xi16, WriteLZCNT, WriteLZCNTLd, "_NF">, NF, PD; +defm LZCNT32 : Lzcnt<0xF5, "lzcnt", null_frag, Xi32, WriteLZCNT, WriteLZCNTLd, "_NF">, NF; +defm LZCNT64 : Lzcnt<0xF5, "lzcnt", null_frag, Xi64, WriteLZCNT, WriteLZCNTLd, "_NF">, NF; + //===----------------------------------------------------------------------===// // BMI Instructions // let Predicates = [HasBMI], Defs = [EFLAGS] in { - def TZCNT16rr : I<0xBC, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), - "tzcnt{w}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, (cttz GR16:$src)), (implicit EFLAGS)]>, - TB, XS, OpSize16, Sched<[WriteTZCNT]>; - def TZCNT16rm : I<0xBC, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), - "tzcnt{w}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, (cttz (loadi16 addr:$src))), - (implicit EFLAGS)]>, TB, XS, OpSize16, Sched<[WriteTZCNTLd]>; - - def TZCNT32rr : I<0xBC, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), - "tzcnt{l}\t{$src, $dst|$dst, $src}", - [(set GR32:$dst, (cttz GR32:$src)), (implicit EFLAGS)]>, - TB, XS, OpSize32, Sched<[WriteTZCNT]>; - def TZCNT32rm : I<0xBC, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), - "tzcnt{l}\t{$src, $dst|$dst, $src}", - [(set GR32:$dst, (cttz (loadi32 addr:$src))), - (implicit EFLAGS)]>, TB, XS, OpSize32, Sched<[WriteTZCNTLd]>; - - def TZCNT64rr : RI<0xBC, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), - "tzcnt{q}\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, (cttz GR64:$src)), (implicit EFLAGS)]>, - TB, XS, Sched<[WriteTZCNT]>; - def TZCNT64rm : RI<0xBC, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), - "tzcnt{q}\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, (cttz (loadi64 addr:$src))), - (implicit EFLAGS)]>, TB, XS, Sched<[WriteTZCNTLd]>; + defm TZCNT16 : Lzcnt<0xBC, "tzcnt", cttz, Xi16, WriteTZCNT, WriteTZCNTLd>, OpSize16, XS; + defm TZCNT32 : Lzcnt<0xBC, "tzcnt", cttz, Xi32, WriteTZCNT, WriteTZCNTLd>, OpSize32, XS; + defm TZCNT64 : Lzcnt<0xBC, "tzcnt", cttz, Xi64, WriteTZCNT, WriteTZCNTLd>, XS; + + defm TZCNT16 : Lzcnt<0xF4, "tzcnt", null_frag, Xi16, WriteTZCNT, WriteTZCNTLd, "_EVEX">, PL, PD; + defm TZCNT32 : Lzcnt<0xF4, "tzcnt", null_frag, Xi32, WriteTZCNT, WriteTZCNTLd, "_EVEX">, PL; + defm TZCNT64 : Lzcnt<0xF4, "tzcnt", null_frag, Xi64, WriteTZCNT, WriteTZCNTLd, "_EVEX">, PL; } +defm TZCNT16 : Lzcnt<0xF4, "tzcnt", null_frag, Xi16, WriteTZCNT, WriteTZCNTLd, "_NF">, NF, PD; +defm TZCNT32 : Lzcnt<0xF4, "tzcnt", null_frag, Xi32, WriteTZCNT, WriteTZCNTLd, "_NF">, NF; +defm TZCNT64 : Lzcnt<0xF4, "tzcnt", null_frag, Xi64, WriteTZCNT, WriteTZCNTLd, "_NF">, NF; + multiclass Bls { let SchedRW = [WriteBLS] in { def rr#Suffix : UnaryOpR<0xF3, RegMRM, m, unaryop_ndd_args, t, diff --git a/llvm/lib/Target/X86/X86InstrSSE.td b/llvm/lib/Target/X86/X86InstrSSE.td index 16ae69a518d9e..459b5b03507c7 100644 --- a/llvm/lib/Target/X86/X86InstrSSE.td +++ b/llvm/lib/Target/X86/X86InstrSSE.td @@ -5757,38 +5757,19 @@ defm VTESTPDY : avx_bittest<0x0F, "vtestpd", VR256, f256mem, loadv4f64, v4f64, //===----------------------------------------------------------------------===// let Defs = [EFLAGS], Predicates = [HasPOPCNT] in { - def POPCNT16rr : I<0xB8, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src), - "popcnt{w}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, (ctpop GR16:$src)), (implicit EFLAGS)]>, - Sched<[WritePOPCNT]>, OpSize16, TB, XS; - def POPCNT16rm : I<0xB8, MRMSrcMem, (outs GR16:$dst), (ins i16mem:$src), - "popcnt{w}\t{$src, $dst|$dst, $src}", - [(set GR16:$dst, (ctpop (loadi16 addr:$src))), - (implicit EFLAGS)]>, - Sched<[WritePOPCNT.Folded]>, OpSize16, TB, XS; - - def POPCNT32rr : I<0xB8, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src), - "popcnt{l}\t{$src, $dst|$dst, $src}", - [(set GR32:$dst, (ctpop GR32:$src)), (implicit EFLAGS)]>, - Sched<[WritePOPCNT]>, OpSize32, TB, XS; - - def POPCNT32rm : I<0xB8, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), - "popcnt{l}\t{$src, $dst|$dst, $src}", - [(set GR32:$dst, (ctpop (loadi32 addr:$src))), - (implicit EFLAGS)]>, - Sched<[WritePOPCNT.Folded]>, OpSize32, TB, XS; - - def POPCNT64rr : RI<0xB8, MRMSrcReg, (outs GR64:$dst), (ins GR64:$src), - "popcnt{q}\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, (ctpop GR64:$src)), (implicit EFLAGS)]>, - Sched<[WritePOPCNT]>, TB, XS; - def POPCNT64rm : RI<0xB8, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), - "popcnt{q}\t{$src, $dst|$dst, $src}", - [(set GR64:$dst, (ctpop (loadi64 addr:$src))), - (implicit EFLAGS)]>, - Sched<[WritePOPCNT.Folded]>, TB, XS; + defm POPCNT16 : Lzcnt<0xB8, "popcnt", ctpop, Xi16, WritePOPCNT, WritePOPCNT.Folded>, OpSize16, XS; + defm POPCNT32 : Lzcnt<0xB8, "popcnt", ctpop, Xi32, WritePOPCNT, WritePOPCNT.Folded>, OpSize32, XS; + defm POPCNT64 : Lzcnt<0xB8, "popcnt", ctpop, Xi64, WritePOPCNT, WritePOPCNT.Folded>, XS; + + defm POPCNT16 : Lzcnt<0x88, "popcnt", null_frag, Xi16, WritePOPCNT, WritePOPCNT.Folded, "_EVEX">, PL, PD; + defm POPCNT32 : Lzcnt<0x88, "popcnt", null_frag, Xi32, WritePOPCNT, WritePOPCNT.Folded, "_EVEX">, PL; + defm POPCNT64 : Lzcnt<0x88, "popcnt", null_frag, Xi64, WritePOPCNT, WritePOPCNT.Folded, "_EVEX">, PL; } +defm POPCNT16 : Lzcnt<0x88, "popcnt", null_frag, Xi16, WritePOPCNT, WritePOPCNT.Folded, "_NF">, NF, PD; +defm POPCNT32 : Lzcnt<0x88, "popcnt", null_frag, Xi32, WritePOPCNT, WritePOPCNT.Folded, "_NF">, NF; +defm POPCNT64 : Lzcnt<0x88, "popcnt", null_frag, Xi64, WritePOPCNT, WritePOPCNT.Folded, "_NF">, NF; + // SS41I_unop_rm_int_v16 - SSE 4.1 unary operator whose type is v8i16. multiclass SS41I_unop_rm_int_v16 opc, string OpcodeStr, SDNode OpNode, PatFrag ld_frag, diff --git a/llvm/test/MC/Disassembler/X86/apx/lzcnt.txt b/llvm/test/MC/Disassembler/X86/apx/lzcnt.txt new file mode 100644 index 0000000000000..6e41cf4c2b04f --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/lzcnt.txt @@ -0,0 +1,50 @@ +# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +# ATT: {evex} lzcntw %dx, %ax +# INTEL: {evex} lzcnt ax, dx +0x62,0xf4,0x7d,0x08,0xf5,0xc2 + +# ATT: {nf} lzcntw %dx, %ax +# INTEL: {nf} lzcnt ax, dx +0x62,0xf4,0x7d,0x0c,0xf5,0xc2 + +# ATT: {evex} lzcntl %ecx, %edx +# INTEL: {evex} lzcnt edx, ecx +0x62,0xf4,0x7c,0x08,0xf5,0xd1 + +# ATT: {nf} lzcntl %ecx, %edx +# INTEL: {nf} lzcnt edx, ecx +0x62,0xf4,0x7c,0x0c,0xf5,0xd1 + +# ATT: {evex} lzcntq %r9, %r15 +# INTEL: {evex} lzcnt r15, r9 +0x62,0x54,0xfc,0x08,0xf5,0xf9 + +# ATT: {nf} lzcntq %r9, %r15 +# INTEL: {nf} lzcnt r15, r9 +0x62,0x54,0xfc,0x0c,0xf5,0xf9 + +# ATT: {evex} lzcntw 123(%r8,%rax,4), %dx +# INTEL: {evex} lzcnt dx, word ptr [r8 + 4*rax + 123] +0x62,0xd4,0x7d,0x08,0xf5,0x54,0x80,0x7b + +# ATT: {nf} lzcntw 123(%r8,%rax,4), %dx +# INTEL: {nf} lzcnt dx, word ptr [r8 + 4*rax + 123] +0x62,0xd4,0x7d,0x0c,0xf5,0x54,0x80,0x7b + +# ATT: {evex} lzcntl 123(%r8,%rax,4), %ecx +# INTEL: {evex} lzcnt ecx, dword ptr [r8 + 4*rax + 123] +0x62,0xd4,0x7c,0x08,0xf5,0x4c,0x80,0x7b + +# ATT: {nf} lzcntl 123(%r8,%rax,4), %ecx +# INTEL: {nf} lzcnt ecx, dword ptr [r8 + 4*rax + 123] +0x62,0xd4,0x7c,0x0c,0xf5,0x4c,0x80,0x7b + +# ATT: {evex} lzcntq 123(%r8,%rax,4), %r9 +# INTEL: {evex} lzcnt r9, qword ptr [r8 + 4*rax + 123] +0x62,0x54,0xfc,0x08,0xf5,0x4c,0x80,0x7b + +# ATT: {nf} lzcntq 123(%r8,%rax,4), %r9 +# INTEL: {nf} lzcnt r9, qword ptr [r8 + 4*rax + 123] +0x62,0x54,0xfc,0x0c,0xf5,0x4c,0x80,0x7b diff --git a/llvm/test/MC/Disassembler/X86/apx/popcnt.txt b/llvm/test/MC/Disassembler/X86/apx/popcnt.txt new file mode 100644 index 0000000000000..d6ceef62f286f --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/popcnt.txt @@ -0,0 +1,50 @@ +# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +# ATT: {evex} popcntw %dx, %ax +# INTEL: {evex} popcnt ax, dx +0x62,0xf4,0x7d,0x08,0x88,0xc2 + +# ATT: {nf} popcntw %dx, %ax +# INTEL: {nf} popcnt ax, dx +0x62,0xf4,0x7d,0x0c,0x88,0xc2 + +# ATT: {evex} popcntl %ecx, %edx +# INTEL: {evex} popcnt edx, ecx +0x62,0xf4,0x7c,0x08,0x88,0xd1 + +# ATT: {nf} popcntl %ecx, %edx +# INTEL: {nf} popcnt edx, ecx +0x62,0xf4,0x7c,0x0c,0x88,0xd1 + +# ATT: {evex} popcntq %r9, %r15 +# INTEL: {evex} popcnt r15, r9 +0x62,0x54,0xfc,0x08,0x88,0xf9 + +# ATT: {nf} popcntq %r9, %r15 +# INTEL: {nf} popcnt r15, r9 +0x62,0x54,0xfc,0x0c,0x88,0xf9 + +# ATT: {evex} popcntw 123(%r8,%rax,4), %dx +# INTEL: {evex} popcnt dx, word ptr [r8 + 4*rax + 123] +0x62,0xd4,0x7d,0x08,0x88,0x54,0x80,0x7b + +# ATT: {nf} popcntw 123(%r8,%rax,4), %dx +# INTEL: {nf} popcnt dx, word ptr [r8 + 4*rax + 123] +0x62,0xd4,0x7d,0x0c,0x88,0x54,0x80,0x7b + +# ATT: {evex} popcntl 123(%r8,%rax,4), %ecx +# INTEL: {evex} popcnt ecx, dword ptr [r8 + 4*rax + 123] +0x62,0xd4,0x7c,0x08,0x88,0x4c,0x80,0x7b + +# ATT: {nf} popcntl 123(%r8,%rax,4), %ecx +# INTEL: {nf} popcnt ecx, dword ptr [r8 + 4*rax + 123] +0x62,0xd4,0x7c,0x0c,0x88,0x4c,0x80,0x7b + +# ATT: {evex} popcntq 123(%r8,%rax,4), %r9 +# INTEL: {evex} popcnt r9, qword ptr [r8 + 4*rax + 123] +0x62,0x54,0xfc,0x08,0x88,0x4c,0x80,0x7b + +# ATT: {nf} popcntq 123(%r8,%rax,4), %r9 +# INTEL: {nf} popcnt r9, qword ptr [r8 + 4*rax + 123] +0x62,0x54,0xfc,0x0c,0x88,0x4c,0x80,0x7b diff --git a/llvm/test/MC/Disassembler/X86/apx/tzcnt.txt b/llvm/test/MC/Disassembler/X86/apx/tzcnt.txt new file mode 100644 index 0000000000000..8c404f2e176fd --- /dev/null +++ b/llvm/test/MC/Disassembler/X86/apx/tzcnt.txt @@ -0,0 +1,50 @@ +# RUN: llvm-mc -triple x86_64 -disassemble %s | FileCheck %s --check-prefix=ATT +# RUN: llvm-mc -triple x86_64 -disassemble -output-asm-variant=1 %s | FileCheck %s --check-prefix=INTEL + +# ATT: {evex} tzcntw %dx, %ax +# INTEL: {evex} tzcnt ax, dx +0x62,0xf4,0x7d,0x08,0xf4,0xc2 + +# ATT: {nf} tzcntw %dx, %ax +# INTEL: {nf} tzcnt ax, dx +0x62,0xf4,0x7d,0x0c,0xf4,0xc2 + +# ATT: {evex} tzcntl %ecx, %edx +# INTEL: {evex} tzcnt edx, ecx +0x62,0xf4,0x7c,0x08,0xf4,0xd1 + +# ATT: {nf} tzcntl %ecx, %edx +# INTEL: {nf} tzcnt edx, ecx +0x62,0xf4,0x7c,0x0c,0xf4,0xd1 + +# ATT: {evex} tzcntq %r9, %r15 +# INTEL: {evex} tzcnt r15, r9 +0x62,0x54,0xfc,0x08,0xf4,0xf9 + +# ATT: {nf} tzcntq %r9, %r15 +# INTEL: {nf} tzcnt r15, r9 +0x62,0x54,0xfc,0x0c,0xf4,0xf9 + +# ATT: {evex} tzcntw 123(%r8,%rax,4), %dx +# INTEL: {evex} tzcnt dx, word ptr [r8 + 4*rax + 123] +0x62,0xd4,0x7d,0x08,0xf4,0x54,0x80,0x7b + +# ATT: {nf} tzcntw 123(%r8,%rax,4), %dx +# INTEL: {nf} tzcnt dx, word ptr [r8 + 4*rax + 123] +0x62,0xd4,0x7d,0x0c,0xf4,0x54,0x80,0x7b + +# ATT: {evex} tzcntl 123(%r8,%rax,4), %ecx +# INTEL: {evex} tzcnt ecx, dword ptr [r8 + 4*rax + 123] +0x62,0xd4,0x7c,0x08,0xf4,0x4c,0x80,0x7b + +# ATT: {nf} tzcntl 123(%r8,%rax,4), %ecx +# INTEL: {nf} tzcnt ecx, dword ptr [r8 + 4*rax + 123] +0x62,0xd4,0x7c,0x0c,0xf4,0x4c,0x80,0x7b + +# ATT: {evex} tzcntq 123(%r8,%rax,4), %r9 +# INTEL: {evex} tzcnt r9, qword ptr [r8 + 4*rax + 123] +0x62,0x54,0xfc,0x08,0xf4,0x4c,0x80,0x7b + +# ATT: {nf} tzcntq 123(%r8,%rax,4), %r9 +# INTEL: {nf} tzcnt r9, qword ptr [r8 + 4*rax + 123] +0x62,0x54,0xfc,0x0c,0xf4,0x4c,0x80,0x7b diff --git a/llvm/test/MC/X86/apx/lzcnt-att.s b/llvm/test/MC/X86/apx/lzcnt-att.s new file mode 100644 index 0000000000000..ba5c4b56cd031 --- /dev/null +++ b/llvm/test/MC/X86/apx/lzcnt-att.s @@ -0,0 +1,38 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s + +# CHECK: {evex} lzcntw %dx, %ax +# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xf5,0xc2] + {evex} lzcntw %dx, %ax +# CHECK: {nf} lzcntw %dx, %ax +# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0xf5,0xc2] + {nf} lzcntw %dx, %ax +# CHECK: {evex} lzcntl %ecx, %edx +# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf5,0xd1] + {evex} lzcntl %ecx, %edx +# CHECK: {nf} lzcntl %ecx, %edx +# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xf5,0xd1] + {nf} lzcntl %ecx, %edx +# CHECK: {evex} lzcntq %r9, %r15 +# CHECK: encoding: [0x62,0x54,0xfc,0x08,0xf5,0xf9] + {evex} lzcntq %r9, %r15 +# CHECK: {nf} lzcntq %r9, %r15 +# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0xf5,0xf9] + {nf} lzcntq %r9, %r15 +# CHECK: {evex} lzcntw 123(%r8,%rax,4), %dx +# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xf5,0x54,0x80,0x7b] + {evex} lzcntw 123(%r8,%rax,4), %dx +# CHECK: {nf} lzcntw 123(%r8,%rax,4), %dx +# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0xf5,0x54,0x80,0x7b] + {nf} lzcntw 123(%r8,%rax,4), %dx +# CHECK: {evex} lzcntl 123(%r8,%rax,4), %ecx +# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xf5,0x4c,0x80,0x7b] + {evex} lzcntl 123(%r8,%rax,4), %ecx +# CHECK: {nf} lzcntl 123(%r8,%rax,4), %ecx +# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xf5,0x4c,0x80,0x7b] + {nf} lzcntl 123(%r8,%rax,4), %ecx +# CHECK: {evex} lzcntq 123(%r8,%rax,4), %r9 +# CHECK: encoding: [0x62,0x54,0xfc,0x08,0xf5,0x4c,0x80,0x7b] + {evex} lzcntq 123(%r8,%rax,4), %r9 +# CHECK: {nf} lzcntq 123(%r8,%rax,4), %r9 +# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0xf5,0x4c,0x80,0x7b] + {nf} lzcntq 123(%r8,%rax,4), %r9 diff --git a/llvm/test/MC/X86/apx/lzcnt-intel.s b/llvm/test/MC/X86/apx/lzcnt-intel.s new file mode 100644 index 0000000000000..c3301be6bc275 --- /dev/null +++ b/llvm/test/MC/X86/apx/lzcnt-intel.s @@ -0,0 +1,38 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s + +# CHECK: {evex} lzcnt ax, dx +# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xf5,0xc2] + {evex} lzcnt ax, dx +# CHECK: {nf} lzcnt ax, dx +# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0xf5,0xc2] + {nf} lzcnt ax, dx +# CHECK: {evex} lzcnt edx, ecx +# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf5,0xd1] + {evex} lzcnt edx, ecx +# CHECK: {nf} lzcnt edx, ecx +# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xf5,0xd1] + {nf} lzcnt edx, ecx +# CHECK: {evex} lzcnt r15, r9 +# CHECK: encoding: [0x62,0x54,0xfc,0x08,0xf5,0xf9] + {evex} lzcnt r15, r9 +# CHECK: {nf} lzcnt r15, r9 +# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0xf5,0xf9] + {nf} lzcnt r15, r9 +# CHECK: {evex} lzcnt dx, word ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xf5,0x54,0x80,0x7b] + {evex} lzcnt dx, word ptr [r8 + 4*rax + 123] +# CHECK: {nf} lzcnt dx, word ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0xf5,0x54,0x80,0x7b] + {nf} lzcnt dx, word ptr [r8 + 4*rax + 123] +# CHECK: {evex} lzcnt ecx, dword ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xf5,0x4c,0x80,0x7b] + {evex} lzcnt ecx, dword ptr [r8 + 4*rax + 123] +# CHECK: {nf} lzcnt ecx, dword ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xf5,0x4c,0x80,0x7b] + {nf} lzcnt ecx, dword ptr [r8 + 4*rax + 123] +# CHECK: {evex} lzcnt r9, qword ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0x54,0xfc,0x08,0xf5,0x4c,0x80,0x7b] + {evex} lzcnt r9, qword ptr [r8 + 4*rax + 123] +# CHECK: {nf} lzcnt r9, qword ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0xf5,0x4c,0x80,0x7b] + {nf} lzcnt r9, qword ptr [r8 + 4*rax + 123] diff --git a/llvm/test/MC/X86/apx/popcnt-att.s b/llvm/test/MC/X86/apx/popcnt-att.s new file mode 100644 index 0000000000000..a25c27cc3a1b2 --- /dev/null +++ b/llvm/test/MC/X86/apx/popcnt-att.s @@ -0,0 +1,38 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s + +# CHECK: {evex} popcntw %dx, %ax +# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0x88,0xc2] + {evex} popcntw %dx, %ax +# CHECK: {nf} popcntw %dx, %ax +# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0x88,0xc2] + {nf} popcntw %dx, %ax +# CHECK: {evex} popcntl %ecx, %edx +# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0x88,0xd1] + {evex} popcntl %ecx, %edx +# CHECK: {nf} popcntl %ecx, %edx +# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0x88,0xd1] + {nf} popcntl %ecx, %edx +# CHECK: {evex} popcntq %r9, %r15 +# CHECK: encoding: [0x62,0x54,0xfc,0x08,0x88,0xf9] + {evex} popcntq %r9, %r15 +# CHECK: {nf} popcntq %r9, %r15 +# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0x88,0xf9] + {nf} popcntq %r9, %r15 +# CHECK: {evex} popcntw 123(%r8,%rax,4), %dx +# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0x88,0x54,0x80,0x7b] + {evex} popcntw 123(%r8,%rax,4), %dx +# CHECK: {nf} popcntw 123(%r8,%rax,4), %dx +# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0x88,0x54,0x80,0x7b] + {nf} popcntw 123(%r8,%rax,4), %dx +# CHECK: {evex} popcntl 123(%r8,%rax,4), %ecx +# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0x88,0x4c,0x80,0x7b] + {evex} popcntl 123(%r8,%rax,4), %ecx +# CHECK: {nf} popcntl 123(%r8,%rax,4), %ecx +# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0x88,0x4c,0x80,0x7b] + {nf} popcntl 123(%r8,%rax,4), %ecx +# CHECK: {evex} popcntq 123(%r8,%rax,4), %r9 +# CHECK: encoding: [0x62,0x54,0xfc,0x08,0x88,0x4c,0x80,0x7b] + {evex} popcntq 123(%r8,%rax,4), %r9 +# CHECK: {nf} popcntq 123(%r8,%rax,4), %r9 +# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0x88,0x4c,0x80,0x7b] + {nf} popcntq 123(%r8,%rax,4), %r9 diff --git a/llvm/test/MC/X86/apx/popcnt-intel.s b/llvm/test/MC/X86/apx/popcnt-intel.s new file mode 100644 index 0000000000000..12c514de39fb5 --- /dev/null +++ b/llvm/test/MC/X86/apx/popcnt-intel.s @@ -0,0 +1,38 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s + +# CHECK: {evex} popcnt ax, dx +# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0x88,0xc2] + {evex} popcnt ax, dx +# CHECK: {nf} popcnt ax, dx +# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0x88,0xc2] + {nf} popcnt ax, dx +# CHECK: {evex} popcnt edx, ecx +# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0x88,0xd1] + {evex} popcnt edx, ecx +# CHECK: {nf} popcnt edx, ecx +# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0x88,0xd1] + {nf} popcnt edx, ecx +# CHECK: {evex} popcnt r15, r9 +# CHECK: encoding: [0x62,0x54,0xfc,0x08,0x88,0xf9] + {evex} popcnt r15, r9 +# CHECK: {nf} popcnt r15, r9 +# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0x88,0xf9] + {nf} popcnt r15, r9 +# CHECK: {evex} popcnt dx, word ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0x88,0x54,0x80,0x7b] + {evex} popcnt dx, word ptr [r8 + 4*rax + 123] +# CHECK: {nf} popcnt dx, word ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0x88,0x54,0x80,0x7b] + {nf} popcnt dx, word ptr [r8 + 4*rax + 123] +# CHECK: {evex} popcnt ecx, dword ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0x88,0x4c,0x80,0x7b] + {evex} popcnt ecx, dword ptr [r8 + 4*rax + 123] +# CHECK: {nf} popcnt ecx, dword ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0x88,0x4c,0x80,0x7b] + {nf} popcnt ecx, dword ptr [r8 + 4*rax + 123] +# CHECK: {evex} popcnt r9, qword ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0x54,0xfc,0x08,0x88,0x4c,0x80,0x7b] + {evex} popcnt r9, qword ptr [r8 + 4*rax + 123] +# CHECK: {nf} popcnt r9, qword ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0x88,0x4c,0x80,0x7b] + {nf} popcnt r9, qword ptr [r8 + 4*rax + 123] diff --git a/llvm/test/MC/X86/apx/tzcnt-att.s b/llvm/test/MC/X86/apx/tzcnt-att.s new file mode 100644 index 0000000000000..e2d7494863cab --- /dev/null +++ b/llvm/test/MC/X86/apx/tzcnt-att.s @@ -0,0 +1,38 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding %s | FileCheck %s + +# CHECK: {evex} tzcntw %dx, %ax +# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xf4,0xc2] + {evex} tzcntw %dx, %ax +# CHECK: {nf} tzcntw %dx, %ax +# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0xf4,0xc2] + {nf} tzcntw %dx, %ax +# CHECK: {evex} tzcntl %ecx, %edx +# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf4,0xd1] + {evex} tzcntl %ecx, %edx +# CHECK: {nf} tzcntl %ecx, %edx +# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xf4,0xd1] + {nf} tzcntl %ecx, %edx +# CHECK: {evex} tzcntq %r9, %r15 +# CHECK: encoding: [0x62,0x54,0xfc,0x08,0xf4,0xf9] + {evex} tzcntq %r9, %r15 +# CHECK: {nf} tzcntq %r9, %r15 +# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0xf4,0xf9] + {nf} tzcntq %r9, %r15 +# CHECK: {evex} tzcntw 123(%r8,%rax,4), %dx +# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xf4,0x54,0x80,0x7b] + {evex} tzcntw 123(%r8,%rax,4), %dx +# CHECK: {nf} tzcntw 123(%r8,%rax,4), %dx +# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0xf4,0x54,0x80,0x7b] + {nf} tzcntw 123(%r8,%rax,4), %dx +# CHECK: {evex} tzcntl 123(%r8,%rax,4), %ecx +# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xf4,0x4c,0x80,0x7b] + {evex} tzcntl 123(%r8,%rax,4), %ecx +# CHECK: {nf} tzcntl 123(%r8,%rax,4), %ecx +# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xf4,0x4c,0x80,0x7b] + {nf} tzcntl 123(%r8,%rax,4), %ecx +# CHECK: {evex} tzcntq 123(%r8,%rax,4), %r9 +# CHECK: encoding: [0x62,0x54,0xfc,0x08,0xf4,0x4c,0x80,0x7b] + {evex} tzcntq 123(%r8,%rax,4), %r9 +# CHECK: {nf} tzcntq 123(%r8,%rax,4), %r9 +# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0xf4,0x4c,0x80,0x7b] + {nf} tzcntq 123(%r8,%rax,4), %r9 diff --git a/llvm/test/MC/X86/apx/tzcnt-intel.s b/llvm/test/MC/X86/apx/tzcnt-intel.s new file mode 100644 index 0000000000000..694424c2863f5 --- /dev/null +++ b/llvm/test/MC/X86/apx/tzcnt-intel.s @@ -0,0 +1,38 @@ +# RUN: llvm-mc -triple x86_64 -show-encoding -x86-asm-syntax=intel -output-asm-variant=1 %s | FileCheck %s + +# CHECK: {evex} tzcnt ax, dx +# CHECK: encoding: [0x62,0xf4,0x7d,0x08,0xf4,0xc2] + {evex} tzcnt ax, dx +# CHECK: {nf} tzcnt ax, dx +# CHECK: encoding: [0x62,0xf4,0x7d,0x0c,0xf4,0xc2] + {nf} tzcnt ax, dx +# CHECK: {evex} tzcnt edx, ecx +# CHECK: encoding: [0x62,0xf4,0x7c,0x08,0xf4,0xd1] + {evex} tzcnt edx, ecx +# CHECK: {nf} tzcnt edx, ecx +# CHECK: encoding: [0x62,0xf4,0x7c,0x0c,0xf4,0xd1] + {nf} tzcnt edx, ecx +# CHECK: {evex} tzcnt r15, r9 +# CHECK: encoding: [0x62,0x54,0xfc,0x08,0xf4,0xf9] + {evex} tzcnt r15, r9 +# CHECK: {nf} tzcnt r15, r9 +# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0xf4,0xf9] + {nf} tzcnt r15, r9 +# CHECK: {evex} tzcnt dx, word ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0xd4,0x7d,0x08,0xf4,0x54,0x80,0x7b] + {evex} tzcnt dx, word ptr [r8 + 4*rax + 123] +# CHECK: {nf} tzcnt dx, word ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0xd4,0x7d,0x0c,0xf4,0x54,0x80,0x7b] + {nf} tzcnt dx, word ptr [r8 + 4*rax + 123] +# CHECK: {evex} tzcnt ecx, dword ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0xd4,0x7c,0x08,0xf4,0x4c,0x80,0x7b] + {evex} tzcnt ecx, dword ptr [r8 + 4*rax + 123] +# CHECK: {nf} tzcnt ecx, dword ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0xd4,0x7c,0x0c,0xf4,0x4c,0x80,0x7b] + {nf} tzcnt ecx, dword ptr [r8 + 4*rax + 123] +# CHECK: {evex} tzcnt r9, qword ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0x54,0xfc,0x08,0xf4,0x4c,0x80,0x7b] + {evex} tzcnt r9, qword ptr [r8 + 4*rax + 123] +# CHECK: {nf} tzcnt r9, qword ptr [r8 + 4*rax + 123] +# CHECK: encoding: [0x62,0x54,0xfc,0x0c,0xf4,0x4c,0x80,0x7b] + {nf} tzcnt r9, qword ptr [r8 + 4*rax + 123] diff --git a/llvm/test/TableGen/x86-fold-tables.inc b/llvm/test/TableGen/x86-fold-tables.inc index aa412fafb22ec..abeef29c80edf 100644 --- a/llvm/test/TableGen/x86-fold-tables.inc +++ b/llvm/test/TableGen/x86-fold-tables.inc @@ -754,8 +754,11 @@ static const X86FoldTableEntry Table1[] = { {X86::LWPVAL32rri, X86::LWPVAL32rmi, 0}, {X86::LWPVAL64rri, X86::LWPVAL64rmi, 0}, {X86::LZCNT16rr, X86::LZCNT16rm, 0}, + {X86::LZCNT16rr_NF, X86::LZCNT16rm_NF, 0}, {X86::LZCNT32rr, X86::LZCNT32rm, 0}, + {X86::LZCNT32rr_NF, X86::LZCNT32rm_NF, 0}, {X86::LZCNT64rr, X86::LZCNT64rm, 0}, + {X86::LZCNT64rr_NF, X86::LZCNT64rm_NF, 0}, {X86::MMX_CVTPD2PIrr, X86::MMX_CVTPD2PIrm, TB_ALIGN_16}, {X86::MMX_CVTPI2PDrr, X86::MMX_CVTPI2PDrm, 0}, {X86::MMX_CVTPS2PIrr, X86::MMX_CVTPS2PIrm, TB_NO_REVERSE}, @@ -864,8 +867,11 @@ static const X86FoldTableEntry Table1[] = { {X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_NO_REVERSE}, {X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_NO_REVERSE}, {X86::POPCNT16rr, X86::POPCNT16rm, 0}, + {X86::POPCNT16rr_NF, X86::POPCNT16rm_NF, 0}, {X86::POPCNT32rr, X86::POPCNT32rm, 0}, + {X86::POPCNT32rr_NF, X86::POPCNT32rm_NF, 0}, {X86::POPCNT64rr, X86::POPCNT64rm, 0}, + {X86::POPCNT64rr_NF, X86::POPCNT64rm_NF, 0}, {X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16}, {X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16}, {X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16}, @@ -1103,8 +1109,11 @@ static const X86FoldTableEntry Table1[] = { {X86::T1MSKC32rr, X86::T1MSKC32rm, 0}, {X86::T1MSKC64rr, X86::T1MSKC64rm, 0}, {X86::TZCNT16rr, X86::TZCNT16rm, 0}, + {X86::TZCNT16rr_NF, X86::TZCNT16rm_NF, 0}, {X86::TZCNT32rr, X86::TZCNT32rm, 0}, + {X86::TZCNT32rr_NF, X86::TZCNT32rm_NF, 0}, {X86::TZCNT64rr, X86::TZCNT64rm, 0}, + {X86::TZCNT64rr_NF, X86::TZCNT64rm_NF, 0}, {X86::TZMSK32rr, X86::TZMSK32rm, 0}, {X86::TZMSK64rr, X86::TZMSK64rm, 0}, {X86::UCOMISDrr, X86::UCOMISDrm, 0},