diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp index 914d2a5ef1485..f067e96b8aca2 100644 --- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -587,6 +587,11 @@ static bool hoistAndMergeSGPRInits(unsigned Reg, } bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) { + // Only need to run this in SelectionDAG path. + if (MF.getProperties().hasProperty( + MachineFunctionProperties::Property::Selected)) + return false; + const GCNSubtarget &ST = MF.getSubtarget(); MRI = &MF.getRegInfo(); TRI = ST.getRegisterInfo(); diff --git a/llvm/lib/Target/AMDGPU/SIFixupVectorISel.cpp b/llvm/lib/Target/AMDGPU/SIFixupVectorISel.cpp index a0119297b112f..8e3402b537b3b 100644 --- a/llvm/lib/Target/AMDGPU/SIFixupVectorISel.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixupVectorISel.cpp @@ -217,6 +217,11 @@ static bool fixupGlobalSaddr(MachineBasicBlock &MBB, } bool SIFixupVectorISel::runOnMachineFunction(MachineFunction &MF) { + // Only need to run this in SelectionDAG path. + if (MF.getProperties().hasProperty( + MachineFunctionProperties::Property::Selected)) + return false; + if (skipFunction(MF.getFunction())) return false; diff --git a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp index 1d45e6241d225..236a24a02ece0 100644 --- a/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp +++ b/llvm/lib/Target/AMDGPU/SILowerI1Copies.cpp @@ -452,6 +452,11 @@ static unsigned insertUndefLaneMask(MachineBasicBlock &MBB) { /// all others, because phi lowering looks through copies and can therefore /// often make copy lowering unnecessary. bool SILowerI1Copies::runOnMachineFunction(MachineFunction &TheMF) { + // Only need to run this in SelectionDAG path. + if (TheMF.getProperties().hasProperty( + MachineFunctionProperties::Property::Selected)) + return false; + MF = &TheMF; MRI = &MF->getRegInfo(); DT = &getAnalysis();