diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index 62f33a5738dfaa..831f7fadaa621e 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -207,15 +207,13 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
     assert(hasVInstructions() && "Expected V extension");
     return hasVInstructionsI64() ? 64 : 32;
   }
-  unsigned getMinVLen() const { return ZvlLen; }
-  unsigned getMaxVLen() const { return 65536; }
   unsigned getRealMinVLen() const {
     unsigned VLen = getMinRVVVectorSizeInBits();
-    return VLen == 0 ? getMinVLen() : VLen;
+    return VLen == 0 ? getArchMinVLen() : VLen;
   }
   unsigned getRealMaxVLen() const {
     unsigned VLen = getMaxRVVVectorSizeInBits();
-    return VLen == 0 ? getMaxVLen() : VLen;
+    return VLen == 0 ? getArchMaxVLen() : VLen;
   }
   RISCVABI::ABI getTargetABI() const { return TargetABI; }
   bool isRegisterReservedByUser(Register i) const {
@@ -253,6 +251,11 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   unsigned getMaxRVVVectorSizeInBits() const;
   unsigned getMinRVVVectorSizeInBits() const;
 
+  // Return the known range for the bit length of RVV data registers as indicated
+  // by -march and -mattr.
+  unsigned getArchMinVLen() const { return ZvlLen; }
+  unsigned getArchMaxVLen() const { return 65536; }
+
 public:
   const CallLowering *getCallLowering() const override;
   InstructionSelector *getInstructionSelector() const override;