diff --git a/llvm/test/CodeGen/AMDGPU/offset-split-flat.ll b/llvm/test/CodeGen/AMDGPU/offset-split-flat.ll index 7e8d9ae929c0b..0beee2f066101 100644 --- a/llvm/test/CodeGen/AMDGPU/offset-split-flat.ll +++ b/llvm/test/CodeGen/AMDGPU/offset-split-flat.ll @@ -1,7 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s -; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s -; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11 %s +; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s +; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s +; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s +; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s +; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s +; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s ; Test splitting flat instruction offsets into the low and high bits ; when the offset doesn't fit in the offset field. @@ -44,15 +47,15 @@ define i8 @flat_inst_valu_offset_11bit_max(ptr %p) { ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-LABEL: flat_inst_valu_offset_11bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x7ff, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] +; GFX10-SDAG-LABEL: flat_inst_valu_offset_11bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x7ff, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: flat_inst_valu_offset_11bit_max: ; GFX11: ; %bb.0: @@ -61,6 +64,19 @@ define i8 @flat_inst_valu_offset_11bit_max(ptr %p) { ; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:2047 ; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_11bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_mov_b64 s[4:5], 0x7ff +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 2047 %load = load i8, ptr %gep, align 4 ret i8 %load @@ -74,15 +90,15 @@ define i8 @flat_inst_valu_offset_12bit_max(ptr %p) { ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-LABEL: flat_inst_valu_offset_12bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0xfff, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] +; GFX10-SDAG-LABEL: flat_inst_valu_offset_12bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xfff, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: flat_inst_valu_offset_12bit_max: ; GFX11: ; %bb.0: @@ -91,142 +107,320 @@ define i8 @flat_inst_valu_offset_12bit_max(ptr %p) { ; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:4095 ; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_12bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_mov_b64 s[4:5], 0xfff +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 4095 %load = load i8, ptr %gep, align 4 ret i8 %load } define i8 @flat_inst_valu_offset_13bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_13bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_13bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x1fff, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_13bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:4095 -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_13bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_13bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1fff, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_13bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:4095 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_13bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], 0x1fff +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_13bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_mov_b64 s[4:5], 0x1fff +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_13bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_mov_b64 s[0:1], 0x1fff +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 8191 %load = load i8, ptr %gep, align 4 ret i8 %load } define i8 @flat_inst_valu_offset_neg_11bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_neg_11bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff800, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_neg_11bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_neg_11bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_neg_11bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff800, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_neg_11bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_neg_11bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff800, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_neg_11bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0xf800 +; GFX9-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_neg_11bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0xf800 +; GFX10-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_neg_11bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0xf800 +; GFX11-GISEL-NEXT: s_mov_b32 s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 -2048 %load = load i8, ptr %gep, align 4 ret i8 %load } define i8 @flat_inst_valu_offset_neg_12bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_neg_12bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_neg_12bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_neg_12bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_neg_12bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_neg_12bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_neg_12bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_neg_12bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0xf000 +; GFX9-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_neg_12bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0xf000 +; GFX10-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_neg_12bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0xf000 +; GFX11-GISEL-NEXT: s_mov_b32 s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 -4096 %load = load i8, ptr %gep, align 4 ret i8 %load } define i8 @flat_inst_valu_offset_neg_13bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_neg_13bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffe000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_neg_13bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffe000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_neg_13bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffe000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_neg_13bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffe000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_neg_13bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffe000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_neg_13bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffe000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_neg_13bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0xe000 +; GFX9-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_neg_13bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0xe000 +; GFX10-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_neg_13bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0xe000 +; GFX11-GISEL-NEXT: s_mov_b32 s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 -8192 %load = load i8, ptr %gep, align 4 ret i8 %load @@ -240,15 +434,15 @@ define i8 @flat_inst_valu_offset_2x_11bit_max(ptr %p) { ; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-LABEL: flat_inst_valu_offset_2x_11bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0xfff, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] +; GFX10-SDAG-LABEL: flat_inst_valu_offset_2x_11bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xfff, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: flat_inst_valu_offset_2x_11bit_max: ; GFX11: ; %bb.0: @@ -257,176 +451,393 @@ define i8 @flat_inst_valu_offset_2x_11bit_max(ptr %p) { ; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:4095 ; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_2x_11bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_mov_b64 s[4:5], 0xfff +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 4095 %load = load i8, ptr %gep, align 4 ret i8 %load } define i8 @flat_inst_valu_offset_2x_12bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_2x_12bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_2x_12bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x1fff, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_2x_12bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:4095 -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_2x_12bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_2x_12bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1fff, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_2x_12bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:4095 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_2x_12bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], 0x1fff +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_2x_12bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_mov_b64 s[4:5], 0x1fff +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_2x_12bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_mov_b64 s[0:1], 0x1fff +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 8191 %load = load i8, ptr %gep, align 4 ret i8 %load } define i8 @flat_inst_valu_offset_2x_13bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_2x_13bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x3000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_2x_13bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x3fff, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_2x_13bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x3000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:4095 -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_2x_13bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x3000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_2x_13bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x3fff, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_2x_13bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x3000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:4095 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_2x_13bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], 0x3fff +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_2x_13bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_mov_b64 s[4:5], 0x3fff +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_2x_13bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_mov_b64 s[0:1], 0x3fff +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 16383 %load = load i8, ptr %gep, align 4 ret i8 %load } define i8 @flat_inst_valu_offset_2x_neg_11bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_2x_neg_11bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_2x_neg_11bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_2x_neg_11bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_2x_neg_11bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_2x_neg_11bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_2x_neg_11bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_2x_neg_11bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0xf000 +; GFX9-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_2x_neg_11bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0xf000 +; GFX10-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_2x_neg_11bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0xf000 +; GFX11-GISEL-NEXT: s_mov_b32 s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 -4096 %load = load i8, ptr %gep, align 4 ret i8 %load } define i8 @flat_inst_valu_offset_2x_neg_12bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_2x_neg_12bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffe000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_2x_neg_12bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffe000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_2x_neg_12bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffe000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_2x_neg_12bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffe000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_2x_neg_12bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffe000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_2x_neg_12bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffe000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_2x_neg_12bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0xe000 +; GFX9-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_2x_neg_12bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0xe000 +; GFX10-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_2x_neg_12bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0xe000 +; GFX11-GISEL-NEXT: s_mov_b32 s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 -8192 %load = load i8, ptr %gep, align 4 ret i8 %load } define i8 @flat_inst_valu_offset_2x_neg_13bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_2x_neg_13bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffc000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_2x_neg_13bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffc000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_2x_neg_13bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffc000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_2x_neg_13bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffc000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_2x_neg_13bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffc000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_2x_neg_13bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffc000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_2x_neg_13bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0xc000 +; GFX9-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_2x_neg_13bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0xc000 +; GFX10-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_2x_neg_13bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0xc000 +; GFX11-GISEL-NEXT: s_mov_b32 s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 -16384 %load = load i8, ptr %gep, align 4 ret i8 %load @@ -434,34 +845,76 @@ define i8 @flat_inst_valu_offset_2x_neg_13bit_max(ptr %p) { ; Fill 11-bit low-bits (1ull << 33) | 2047 define i8 @flat_inst_valu_offset_64bit_11bit_split0(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_64bit_11bit_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] offset:2047 -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_64bit_11bit_split0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x7ff, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_64bit_11bit_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:2047 -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] offset:2047 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_split0: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x7ff, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:2047 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x7ff +; GFX9-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_split0: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x7ff +; GFX10-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x7ff +; GFX11-GISEL-NEXT: s_mov_b32 s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 8589936639 %load = load i8, ptr %gep, align 4 ret i8 %load @@ -469,34 +922,76 @@ define i8 @flat_inst_valu_offset_64bit_11bit_split0(ptr %p) { ; Fill 11-bit low-bits (1ull << 33) | 2048 define i8 @flat_inst_valu_offset_64bit_11bit_split1(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_64bit_11bit_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] offset:2048 -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_64bit_11bit_split1: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_64bit_11bit_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:2048 -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] offset:2048 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_split1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:2048 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x800 +; GFX9-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_split1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x800 +; GFX10-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x800 +; GFX11-GISEL-NEXT: s_mov_b32 s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 8589936640 %load = load i8, ptr %gep, align 4 ret i8 %load @@ -504,34 +999,76 @@ define i8 @flat_inst_valu_offset_64bit_11bit_split1(ptr %p) { ; Fill 12-bit low-bits (1ull << 33) | 4095 define i8 @flat_inst_valu_offset_64bit_12bit_split0(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_64bit_12bit_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_64bit_12bit_split0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0xfff, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_64bit_12bit_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:4095 -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_split0: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xfff, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:4095 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0xfff +; GFX9-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_split0: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0xfff +; GFX10-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0xfff +; GFX11-GISEL-NEXT: s_mov_b32 s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 8589938687 %load = load i8, ptr %gep, align 4 ret i8 %load @@ -539,34 +1076,76 @@ define i8 @flat_inst_valu_offset_64bit_12bit_split0(ptr %p) { ; Fill 12-bit low-bits (1ull << 33) | 4096 define i8 @flat_inst_valu_offset_64bit_12bit_split1(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_64bit_12bit_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_64bit_12bit_split1: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_64bit_12bit_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_split1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x1000 +; GFX9-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_split1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x1000 +; GFX10-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x1000 +; GFX11-GISEL-NEXT: s_mov_b32 s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 8589938688 %load = load i8, ptr %gep, align 4 ret i8 %load @@ -574,34 +1153,76 @@ define i8 @flat_inst_valu_offset_64bit_12bit_split1(ptr %p) { ; Fill 13-bit low-bits (1ull << 33) | 8191 define i8 @flat_inst_valu_offset_64bit_13bit_split0(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_64bit_13bit_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_64bit_13bit_split0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x1fff, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_64bit_13bit_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:4095 -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_split0: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1fff, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:4095 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x1fff +; GFX9-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_split0: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x1fff +; GFX10-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x1fff +; GFX11-GISEL-NEXT: s_mov_b32 s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 8589942783 %load = load i8, ptr %gep, align 4 ret i8 %load @@ -609,34 +1230,76 @@ define i8 @flat_inst_valu_offset_64bit_13bit_split0(ptr %p) { ; Fill 13-bit low-bits (1ull << 33) | 8192 define i8 @flat_inst_valu_offset_64bit_13bit_split1(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_64bit_13bit_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_64bit_13bit_split1: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_64bit_13bit_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_split1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x2000 +; GFX9-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_split1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x2000 +; GFX10-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x2000 +; GFX11-GISEL-NEXT: s_mov_b32 s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 8589942784 %load = load i8, ptr %gep, align 4 ret i8 %load @@ -644,35 +1307,77 @@ define i8 @flat_inst_valu_offset_64bit_13bit_split1(ptr %p) { ; Fill 11-bit low-bits, negative high bits (1ull << 63) | 2047 define i8 @flat_inst_valu_offset_64bit_11bit_neg_high_split0(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x7ff, v0 -; GFX9-NEXT: v_bfrev_b32_e32 v2, 1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x7ff, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x7ff, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x7ff, v0 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v2, 1 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x7ff, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x7ff, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x7ff +; GFX9-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x7ff +; GFX10-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x7ff +; GFX11-GISEL-NEXT: s_brev_b32 s1, 1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 -9223372036854773761 %load = load i8, ptr %gep, align 4 ret i8 %load @@ -680,35 +1385,77 @@ define i8 @flat_inst_valu_offset_64bit_11bit_neg_high_split0(ptr %p) { ; Fill 11-bit low-bits, negative high bits (1ull << 63) | 2048 define i8 @flat_inst_valu_offset_64bit_11bit_neg_high_split1(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x800, v0 -; GFX9-NEXT: v_bfrev_b32_e32 v2, 1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x800, v0 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v2, 1 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x800 +; GFX9-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x800 +; GFX10-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_11bit_neg_high_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x800 +; GFX11-GISEL-NEXT: s_brev_b32 s1, 1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 -9223372036854773760 %load = load i8, ptr %gep, align 4 ret i8 %load @@ -716,35 +1463,77 @@ define i8 @flat_inst_valu_offset_64bit_11bit_neg_high_split1(ptr %p) { ; Fill 12-bit low-bits, negative high bits (1ull << 63) | 4095 define i8 @flat_inst_valu_offset_64bit_12bit_neg_high_split0(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xfff, v0 -; GFX9-NEXT: v_bfrev_b32_e32 v2, 1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0xfff, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xfff, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xfff, v0 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v2, 1 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xfff, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xfff, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0xfff +; GFX9-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0xfff +; GFX10-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0xfff +; GFX11-GISEL-NEXT: s_brev_b32 s1, 1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 -9223372036854771713 %load = load i8, ptr %gep, align 4 ret i8 %load @@ -752,35 +1541,77 @@ define i8 @flat_inst_valu_offset_64bit_12bit_neg_high_split0(ptr %p) { ; Fill 12-bit low-bits, negative high bits (1ull << 63) | 4096 define i8 @flat_inst_valu_offset_64bit_12bit_neg_high_split1(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_bfrev_b32_e32 v2, 1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v2, 1 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x1000 +; GFX9-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x1000 +; GFX10-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_12bit_neg_high_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x1000 +; GFX11-GISEL-NEXT: s_brev_b32 s1, 1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 -9223372036854771712 %load = load i8, ptr %gep, align 4 ret i8 %load @@ -788,35 +1619,77 @@ define i8 @flat_inst_valu_offset_64bit_12bit_neg_high_split1(ptr %p) { ; Fill 13-bit low-bits, negative high bits (1ull << 63) | 8191 define i8 @flat_inst_valu_offset_64bit_13bit_neg_high_split0(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1fff, v0 -; GFX9-NEXT: v_bfrev_b32_e32 v2, 1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x1fff, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1fff, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1fff, v0 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v2, 1 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1fff, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1fff, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x1fff +; GFX9-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x1fff +; GFX10-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x1fff +; GFX11-GISEL-NEXT: s_brev_b32 s1, 1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 -9223372036854767617 %load = load i8, ptr %gep, align 4 ret i8 %load @@ -824,35 +1697,77 @@ define i8 @flat_inst_valu_offset_64bit_13bit_neg_high_split0(ptr %p) { ; Fill 13-bit low-bits, negative high bits (1ull << 63) | 8192 define i8 @flat_inst_valu_offset_64bit_13bit_neg_high_split1(ptr %p) { -; GFX9-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 -; GFX9-NEXT: v_bfrev_b32_e32 v2, 1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX10-NEXT: flat_load_ubyte v0, v[0:1] -; GFX10-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v2, 1 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-SDAG-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x2000 +; GFX9-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x2000 +; GFX10-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: flat_load_ubyte v0, v[0:1] +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: flat_inst_valu_offset_64bit_13bit_neg_high_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x2000 +; GFX11-GISEL-NEXT: s_brev_b32 s1, 1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr %p, i64 -9223372036854767616 %load = load i8, ptr %gep, align 4 ret i8 %load @@ -982,18 +1897,18 @@ define amdgpu_kernel void @flat_inst_salu_offset_12bit_max(ptr %p) { } define amdgpu_kernel void @flat_inst_salu_offset_13bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_13bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_13bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_13bit_max: ; GFX10: ; %bb.0: @@ -1008,18 +1923,45 @@ define amdgpu_kernel void @flat_inst_salu_offset_13bit_max(ptr %p) { ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_13bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0x1000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, s1, s0 -; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:4095 glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_13bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0x1000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 0, s1, s0 +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:4095 glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_13bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0x1fff +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_13bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x1fff +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 0 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 8191 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1027,18 +1969,18 @@ define amdgpu_kernel void @flat_inst_salu_offset_13bit_max(ptr %p) { } define amdgpu_kernel void @flat_inst_salu_offset_neg_11bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_neg_11bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff800, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_neg_11bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff800, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_neg_11bit_max: ; GFX10: ; %bb.0: @@ -1053,18 +1995,45 @@ define amdgpu_kernel void @flat_inst_salu_offset_neg_11bit_max(ptr %p) { ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_neg_11bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0xfffff800, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 -; GFX11-NEXT: flat_load_u8 v0, v[0:1] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_neg_11bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0xfffff800, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_neg_11bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0xfffff800 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_neg_11bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0xfffff800 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 -2048 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1072,18 +2041,18 @@ define amdgpu_kernel void @flat_inst_salu_offset_neg_11bit_max(ptr %p) { } define amdgpu_kernel void @flat_inst_salu_offset_neg_12bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_neg_12bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_neg_12bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_neg_12bit_max: ; GFX10: ; %bb.0: @@ -1098,18 +2067,45 @@ define amdgpu_kernel void @flat_inst_salu_offset_neg_12bit_max(ptr %p) { ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_neg_12bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0xfffff000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 -; GFX11-NEXT: flat_load_u8 v0, v[0:1] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_neg_12bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0xfffff000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_neg_12bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0xfffff000 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_neg_12bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0xfffff000 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 -4096 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1117,18 +2113,18 @@ define amdgpu_kernel void @flat_inst_salu_offset_neg_12bit_max(ptr %p) { } define amdgpu_kernel void @flat_inst_salu_offset_neg_13bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_neg_13bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffe000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_neg_13bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffe000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_neg_13bit_max: ; GFX10: ; %bb.0: @@ -1143,18 +2139,45 @@ define amdgpu_kernel void @flat_inst_salu_offset_neg_13bit_max(ptr %p) { ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_neg_13bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0xffffe000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 -; GFX11-NEXT: flat_load_u8 v0, v[0:1] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_neg_13bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0xffffe000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_neg_13bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0xffffe000 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_neg_13bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0xffffe000 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 -8192 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1203,18 +2226,18 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_11bit_max(ptr %p) { } define amdgpu_kernel void @flat_inst_salu_offset_2x_12bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_2x_12bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_2x_12bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_2x_12bit_max: ; GFX10: ; %bb.0: @@ -1229,18 +2252,45 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_12bit_max(ptr %p) { ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_2x_12bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0x1000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, s1, s0 -; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:4095 glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_2x_12bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0x1000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 0, s1, s0 +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:4095 glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_2x_12bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0x1fff +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_2x_12bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x1fff +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 0 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 8191 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1248,18 +2298,18 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_12bit_max(ptr %p) { } define amdgpu_kernel void @flat_inst_salu_offset_2x_13bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_2x_13bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x3000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_2x_13bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x3000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_2x_13bit_max: ; GFX10: ; %bb.0: @@ -1274,18 +2324,45 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_13bit_max(ptr %p) { ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_2x_13bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0x3000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, s1, s0 -; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:4095 glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_2x_13bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0x3000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 0, s1, s0 +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:4095 glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_2x_13bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0x3fff +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_2x_13bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x3fff +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 0 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 16383 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1293,18 +2370,18 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_13bit_max(ptr %p) { } define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_11bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_2x_neg_11bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_2x_neg_11bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_2x_neg_11bit_max: ; GFX10: ; %bb.0: @@ -1319,18 +2396,45 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_11bit_max(ptr %p) { ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_2x_neg_11bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0xfffff000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 -; GFX11-NEXT: flat_load_u8 v0, v[0:1] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_2x_neg_11bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0xfffff000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_2x_neg_11bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0xfffff000 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_2x_neg_11bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0xfffff000 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 -4096 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1338,18 +2442,18 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_11bit_max(ptr %p) { } define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_12bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_2x_neg_12bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffe000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_2x_neg_12bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffe000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_2x_neg_12bit_max: ; GFX10: ; %bb.0: @@ -1364,18 +2468,45 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_12bit_max(ptr %p) { ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_2x_neg_12bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0xffffe000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 -; GFX11-NEXT: flat_load_u8 v0, v[0:1] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_2x_neg_12bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0xffffe000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_2x_neg_12bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0xffffe000 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_2x_neg_12bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0xffffe000 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 -8192 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1383,18 +2514,18 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_12bit_max(ptr %p) { } define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_13bit_max(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_2x_neg_13bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffc000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_2x_neg_13bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffc000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_2x_neg_13bit_max: ; GFX10: ; %bb.0: @@ -1409,18 +2540,45 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_13bit_max(ptr %p) { ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_2x_neg_13bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0xffffc000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 -; GFX11-NEXT: flat_load_u8 v0, v[0:1] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_2x_neg_13bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0xffffc000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_2x_neg_13bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0xffffc000 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_2x_neg_13bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0xffffc000 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 -16384 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1429,17 +2587,17 @@ define amdgpu_kernel void @flat_inst_salu_offset_2x_neg_13bit_max(ptr %p) { ; Fill 11-bit low-bits (1ull << 33) | 2047 define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_split0(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_64bit_11bit_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_add_co_u32_e64 v0, vcc, 0, s0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] offset:2047 glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_64bit_11bit_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e64 v0, vcc, 0, s0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] offset:2047 glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_64bit_11bit_split0: ; GFX10: ; %bb.0: @@ -1454,18 +2612,45 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_split0(ptr %p) { ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_64bit_11bit_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 -; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:2047 glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_11bit_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:2047 glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_11bit_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0x7ff +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_64bit_11bit_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x7ff +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 8589936639 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1474,17 +2659,17 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_split0(ptr %p) { ; Fill 11-bit low-bits (1ull << 33) | 2048 define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_split1(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_64bit_11bit_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_add_co_u32_e64 v0, vcc, 0, s0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] offset:2048 glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_64bit_11bit_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e64 v0, vcc, 0, s0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] offset:2048 glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_64bit_11bit_split1: ; GFX10: ; %bb.0: @@ -1499,18 +2684,45 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_split1(ptr %p) { ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_64bit_11bit_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 -; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:2048 glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_11bit_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:2048 glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_11bit_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0x800 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_64bit_11bit_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x800 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 8589936640 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1519,17 +2731,17 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_split1(ptr %p) { ; Fill 12-bit low-bits (1ull << 33) | 4095 define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_split0(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_64bit_12bit_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_add_co_u32_e64 v0, vcc, 0, s0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_64bit_12bit_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e64 v0, vcc, 0, s0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_64bit_12bit_split0: ; GFX10: ; %bb.0: @@ -1544,18 +2756,45 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_split0(ptr %p) { ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_64bit_12bit_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 -; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:4095 glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_12bit_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:4095 glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_12bit_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0xfff +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_64bit_12bit_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0xfff +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 8589938687 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1564,18 +2803,18 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_split0(ptr %p) { ; Fill 12-bit low-bits (1ull << 33) | 4096 define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_split1(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_64bit_12bit_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_64bit_12bit_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_64bit_12bit_split1: ; GFX10: ; %bb.0: @@ -1590,18 +2829,45 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_split1(ptr %p) { ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_64bit_12bit_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0x1000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 -; GFX11-NEXT: flat_load_u8 v0, v[0:1] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_12bit_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0x1000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_12bit_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0x1000 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_64bit_12bit_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x1000 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 8589938688 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1610,18 +2876,18 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_split1(ptr %p) { ; Fill 13-bit low-bits (1ull << 33) | 8191 define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_split0(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_64bit_13bit_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_64bit_13bit_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] offset:4095 glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_64bit_13bit_split0: ; GFX10: ; %bb.0: @@ -1636,18 +2902,45 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_split0(ptr %p) { ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_64bit_13bit_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0x1000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 -; GFX11-NEXT: flat_load_u8 v0, v[0:1] offset:4095 glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_13bit_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0x1000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:4095 glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_13bit_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0x1fff +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_64bit_13bit_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x1fff +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 8589942783 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1656,18 +2949,18 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_split0(ptr %p) { ; Fill 13-bit low-bits (1ull << 33) | 8192 define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_split1(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_64bit_13bit_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v1, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_64bit_13bit_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_64bit_13bit_split1: ; GFX10: ; %bb.0: @@ -1682,18 +2975,45 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_split1(ptr %p) { ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_64bit_13bit_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0x2000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 -; GFX11-NEXT: flat_load_u8 v0, v[0:1] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_13bit_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0x2000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_13bit_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0x2000 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_64bit_13bit_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x2000 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 8589942784 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1702,19 +3022,19 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_split1(ptr %p) { ; Fill 11-bit low-bits, negative high bits (1ull << 63) | 2047 define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_neg_high_split0(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: v_bfrev_b32_e32 v1, 1 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v2, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x7ff, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x7ff, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split0: ; GFX10: ; %bb.0: @@ -1729,19 +3049,46 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_neg_high_split0(ptr ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x7ff, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x7ff, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0x7ff +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x7ff +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 -9223372036854773761 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1750,19 +3097,19 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_neg_high_split0(ptr ; Fill 11-bit low-bits, negative high bits (1ull << 63) | 2048 define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_neg_high_split1(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: v_bfrev_b32_e32 v1, 1 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v2, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x800, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x800, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split1: ; GFX10: ; %bb.0: @@ -1777,19 +3124,46 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_neg_high_split1(ptr ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0x800 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_64bit_11bit_neg_high_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x800 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 -9223372036854773760 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1798,19 +3172,19 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_11bit_neg_high_split1(ptr ; Fill 12-bit low-bits, negative high bits (1ull << 63) | 4095 define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_neg_high_split0(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: v_bfrev_b32_e32 v1, 1 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v2, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xfff, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xfff, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split0: ; GFX10: ; %bb.0: @@ -1825,19 +3199,46 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_neg_high_split0(ptr ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xfff, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xfff, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0xfff +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0xfff +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 -9223372036854771713 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1846,19 +3247,19 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_neg_high_split0(ptr ; Fill 12-bit low-bits, negative high bits (1ull << 63) | 4096 define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_neg_high_split1(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: v_bfrev_b32_e32 v1, 1 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v2, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split1: ; GFX10: ; %bb.0: @@ -1873,19 +3274,46 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_neg_high_split1(ptr ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0x1000 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_64bit_12bit_neg_high_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x1000 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 -9223372036854771712 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1894,19 +3322,19 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_12bit_neg_high_split1(ptr ; Fill 13-bit low-bits, negative high bits (1ull << 63) | 8191 define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_neg_high_split0(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: v_bfrev_b32_e32 v1, 1 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v2, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1fff, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1fff, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split0: ; GFX10: ; %bb.0: @@ -1921,19 +3349,46 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_neg_high_split0(ptr ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1fff, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1fff, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0x1fff +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x1fff +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 -9223372036854767617 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef @@ -1942,19 +3397,19 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_neg_high_split0(ptr ; Fill 13-bit low-bits, negative high bits (1ull << 63) | 8192 define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_neg_high_split1(ptr %p) { -; GFX9-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX9-NEXT: v_bfrev_b32_e32 v1, 1 -; GFX9-NEXT: s_waitcnt lgkmcnt(0) -; GFX9-NEXT: v_mov_b32_e32 v0, s0 -; GFX9-NEXT: v_mov_b32_e32 v2, s1 -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc -; GFX9-NEXT: flat_load_ubyte v0, v[0:1] glc -; GFX9-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX9-NEXT: flat_store_byte v[0:1], v0 -; GFX9-NEXT: s_endpgm +; GFX9-SDAG-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v1, 1 +; GFX9-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-SDAG-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, s1 +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v2, vcc +; GFX9-SDAG-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: flat_store_byte v[0:1], v0 +; GFX9-SDAG-NEXT: s_endpgm ; ; GFX10-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split1: ; GFX10: ; %bb.0: @@ -1969,19 +3424,46 @@ define amdgpu_kernel void @flat_inst_salu_offset_64bit_13bit_neg_high_split1(ptr ; GFX10-NEXT: flat_store_byte v[0:1], v0 ; GFX10-NEXT: s_endpgm ; -; GFX11-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: flat_load_u8 v0, v[0:1] glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX11-NEXT: flat_store_b8 v[0:1], v0 -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX11-SDAG-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm +; +; GFX9-GISEL-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX9-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-GISEL-NEXT: s_add_u32 s0, s0, 0x2000 +; GFX9-GISEL-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX9-GISEL-NEXT: flat_load_ubyte v0, v[0:1] glc +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: flat_store_byte v[0:1], v0 +; GFX9-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: flat_inst_salu_offset_64bit_13bit_neg_high_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x2000 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 0x80000000 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: flat_load_u8 v0, v[0:1] glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: flat_store_b8 v[0:1], v0 +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm %gep = getelementptr i8, ptr %p, i64 -9223372036854767616 %load = load volatile i8, ptr %gep, align 1 store i8 %load, ptr undef diff --git a/llvm/test/CodeGen/AMDGPU/offset-split-global.ll b/llvm/test/CodeGen/AMDGPU/offset-split-global.ll index 1ed006b621ae4..50345adb5e0cd 100644 --- a/llvm/test/CodeGen/AMDGPU/offset-split-global.ll +++ b/llvm/test/CodeGen/AMDGPU/offset-split-global.ll @@ -1,7 +1,10 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 %s -; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX10 %s -; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX11 %s +; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s +; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-SDAG %s +; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-SDAG %s +; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s +; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10,GFX10-GISEL %s +; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-GISEL %s ; Test splitting flat instruction offsets into the low and high bits ; when the offset doesn't fit in the offset field. @@ -70,15 +73,18 @@ define i8 @global_inst_valu_offset_12bit_max(ptr addrspace(1) %p) { ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-LABEL: global_inst_valu_offset_12bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] +; GFX10-GISEL-LABEL: global_inst_valu_offset_12bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_mov_b64 s[4:5], 0xfff +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: global_inst_valu_offset_12bit_max: ; GFX11: ; %bb.0: @@ -87,40 +93,89 @@ define i8 @global_inst_valu_offset_12bit_max(ptr addrspace(1) %p) { ; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:4095 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_12bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 4095 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load } define i8 @global_inst_valu_offset_13bit_max(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_13bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:4095 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_13bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x1800, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_13bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:4095 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_13bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], 0x1fff +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_13bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_mov_b64 s[4:5], 0x1fff +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_13bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_mov_b64 s[0:1], 0x1fff +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_13bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:4095 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_13bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1800, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_13bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off offset:4095 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 8191 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load @@ -162,15 +217,19 @@ define i8 @global_inst_valu_offset_neg_12bit_max(ptr addrspace(1) %p) { ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-LABEL: global_inst_valu_offset_neg_12bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] +; GFX10-GISEL-LABEL: global_inst_valu_offset_neg_12bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0xf000 +; GFX10-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: global_inst_valu_offset_neg_12bit_max: ; GFX11: ; %bb.0: @@ -179,40 +238,92 @@ define i8 @global_inst_valu_offset_neg_12bit_max(ptr addrspace(1) %p) { ; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:-4096 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_neg_12bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 -4096 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load } define i8 @global_inst_valu_offset_neg_13bit_max(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_neg_13bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffe000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_neg_13bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffe000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_neg_13bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffe000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_neg_13bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0xe000 +; GFX9-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_neg_13bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0xe000 +; GFX10-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_neg_13bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0xe000 +; GFX11-GISEL-NEXT: s_mov_b32 s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_neg_13bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffe000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_neg_13bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffe000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_neg_13bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffe000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 -8192 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load @@ -226,15 +337,18 @@ define i8 @global_inst_valu_offset_2x_11bit_max(ptr addrspace(1) %p) { ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-LABEL: global_inst_valu_offset_2x_11bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] +; GFX10-GISEL-LABEL: global_inst_valu_offset_2x_11bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_mov_b64 s[4:5], 0xfff +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: global_inst_valu_offset_2x_11bit_max: ; GFX11: ; %bb.0: @@ -243,74 +357,162 @@ define i8 @global_inst_valu_offset_2x_11bit_max(ptr addrspace(1) %p) { ; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:4095 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_2x_11bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 4095 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load } define i8 @global_inst_valu_offset_2x_12bit_max(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_2x_12bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:4095 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_2x_12bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x1800, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_2x_12bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:4095 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_2x_12bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], 0x1fff +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_2x_12bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_mov_b64 s[4:5], 0x1fff +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_2x_12bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_mov_b64 s[0:1], 0x1fff +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_2x_12bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:4095 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_2x_12bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1800, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_2x_12bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off offset:4095 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 8191 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load } define i8 @global_inst_valu_offset_2x_13bit_max(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_2x_13bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x3000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:4095 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_2x_13bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x3800, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_2x_13bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x3000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:4095 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_2x_13bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_mov_b64 s[4:5], 0x3fff +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_2x_13bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_mov_b64 s[4:5], 0x3fff +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_2x_13bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_mov_b64 s[0:1], 0x3fff +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_2x_13bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x3000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:4095 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_2x_13bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x3800, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_2x_13bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x3000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off offset:4095 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 16383 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load @@ -324,15 +526,19 @@ define i8 @global_inst_valu_offset_2x_neg_11bit_max(ptr addrspace(1) %p) { ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-LABEL: global_inst_valu_offset_2x_neg_11bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] +; GFX10-GISEL-LABEL: global_inst_valu_offset_2x_neg_11bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0xf000 +; GFX10-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX11-LABEL: global_inst_valu_offset_2x_neg_11bit_max: ; GFX11: ; %bb.0: @@ -341,74 +547,168 @@ define i8 @global_inst_valu_offset_2x_neg_11bit_max(ptr addrspace(1) %p) { ; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:-4096 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_2x_neg_11bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xfffff000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 -4096 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load } define i8 @global_inst_valu_offset_2x_neg_12bit_max(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_2x_neg_12bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffe000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_2x_neg_12bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffe000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_2x_neg_12bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffe000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_2x_neg_12bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0xe000 +; GFX9-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_2x_neg_12bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0xe000 +; GFX10-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_2x_neg_12bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0xe000 +; GFX11-GISEL-NEXT: s_mov_b32 s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_2x_neg_12bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffe000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_2x_neg_12bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffe000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_2x_neg_12bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffe000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 -8192 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load } define i8 @global_inst_valu_offset_2x_neg_13bit_max(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_2x_neg_13bit_max: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffc000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_2x_neg_13bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffc000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_2x_neg_13bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffc000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_2x_neg_13bit_max: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0xc000 +; GFX9-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_2x_neg_13bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0xc000 +; GFX10-GISEL-NEXT: s_mov_b32 s5, -1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_2x_neg_13bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0xc000 +; GFX11-GISEL-NEXT: s_mov_b32 s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_2x_neg_13bit_max: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffc000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_2x_neg_13bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffc000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_2x_neg_13bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0xffffc000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, -1, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 -16384 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load @@ -416,34 +716,76 @@ define i8 @global_inst_valu_offset_2x_neg_13bit_max(ptr addrspace(1) %p) { ; Fill 11-bit low-bits (1ull << 33) | 2047 define i8 @global_inst_valu_offset_64bit_11bit_split0(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_64bit_11bit_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_64bit_11bit_split0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_64bit_11bit_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:2047 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_64bit_11bit_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x7ff +; GFX9-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_64bit_11bit_split0: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x7ff +; GFX10-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_64bit_11bit_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x7ff +; GFX11-GISEL-NEXT: s_mov_b32 s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_split0: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off offset:2047 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589936639 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load @@ -451,34 +793,76 @@ define i8 @global_inst_valu_offset_64bit_11bit_split0(ptr addrspace(1) %p) { ; Fill 11-bit low-bits (1ull << 33) | 2048 define i8 @global_inst_valu_offset_64bit_11bit_split1(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_64bit_11bit_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:2048 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_64bit_11bit_split1: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_64bit_11bit_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:2048 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_64bit_11bit_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x800 +; GFX9-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_64bit_11bit_split1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x800 +; GFX10-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_64bit_11bit_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x800 +; GFX11-GISEL-NEXT: s_mov_b32 s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:2048 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_split1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off offset:2048 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589936640 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load @@ -486,34 +870,76 @@ define i8 @global_inst_valu_offset_64bit_11bit_split1(ptr addrspace(1) %p) { ; Fill 12-bit low-bits (1ull << 33) | 4095 define i8 @global_inst_valu_offset_64bit_12bit_split0(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_64bit_12bit_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:4095 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_64bit_12bit_split0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_64bit_12bit_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:4095 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_64bit_12bit_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0xfff +; GFX9-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_64bit_12bit_split0: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0xfff +; GFX10-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_64bit_12bit_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0xfff +; GFX11-GISEL-NEXT: s_mov_b32 s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:4095 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_split0: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off offset:4095 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589938687 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load @@ -521,34 +947,76 @@ define i8 @global_inst_valu_offset_64bit_12bit_split0(ptr addrspace(1) %p) { ; Fill 12-bit low-bits (1ull << 33) | 4096 define i8 @global_inst_valu_offset_64bit_12bit_split1(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_64bit_12bit_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_64bit_12bit_split1: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_64bit_12bit_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_64bit_12bit_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x1000 +; GFX9-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_64bit_12bit_split1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x1000 +; GFX10-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_64bit_12bit_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x1000 +; GFX11-GISEL-NEXT: s_mov_b32 s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_split1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589938688 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load @@ -556,34 +1024,76 @@ define i8 @global_inst_valu_offset_64bit_12bit_split1(ptr addrspace(1) %p) { ; Fill 13-bit low-bits (1ull << 33) | 8191 define i8 @global_inst_valu_offset_64bit_13bit_split0(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_64bit_13bit_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:4095 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_64bit_13bit_split0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x1800, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_64bit_13bit_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:4095 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_64bit_13bit_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x1fff +; GFX9-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_64bit_13bit_split0: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x1fff +; GFX10-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_64bit_13bit_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x1fff +; GFX11-GISEL-NEXT: s_mov_b32 s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:4095 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_split0: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1800, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off offset:4095 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589942783 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load @@ -591,34 +1101,76 @@ define i8 @global_inst_valu_offset_64bit_13bit_split0(ptr addrspace(1) %p) { ; Fill 13-bit low-bits (1ull << 33) | 8192 define i8 @global_inst_valu_offset_64bit_13bit_split1(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_64bit_13bit_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_64bit_13bit_split1: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_64bit_13bit_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_64bit_13bit_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x2000 +; GFX9-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_64bit_13bit_split1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x2000 +; GFX10-GISEL-NEXT: s_mov_b32 s5, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_64bit_13bit_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x2000 +; GFX11-GISEL-NEXT: s_mov_b32 s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, 2, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_split1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 2, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589942784 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load @@ -626,35 +1178,77 @@ define i8 @global_inst_valu_offset_64bit_13bit_split1(ptr addrspace(1) %p) { ; Fill 11-bit low-bits, negative high bits (1ull << 63) | 2047 define i8 @global_inst_valu_offset_64bit_11bit_neg_high_split0(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_bfrev_b32_e32 v2, 1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:-2049 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:-2049 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x7ff +; GFX9-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split0: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x7ff +; GFX10-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x7ff +; GFX11-GISEL-NEXT: s_brev_b32 s1, 1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v2, 1 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:-2049 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split0: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off offset:-2049 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854773761 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load @@ -662,35 +1256,77 @@ define i8 @global_inst_valu_offset_64bit_11bit_neg_high_split0(ptr addrspace(1) ; Fill 11-bit low-bits, negative high bits (1ull << 63) | 2048 define i8 @global_inst_valu_offset_64bit_11bit_neg_high_split1(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_bfrev_b32_e32 v2, 1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:-2048 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split1: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:-2048 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x800 +; GFX9-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x800 +; GFX10-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x800 +; GFX11-GISEL-NEXT: s_brev_b32 s1, 1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v2, 1 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:-2048 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x800, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_11bit_neg_high_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off offset:-2048 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854773760 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load @@ -698,35 +1334,77 @@ define i8 @global_inst_valu_offset_64bit_11bit_neg_high_split1(ptr addrspace(1) ; Fill 12-bit low-bits, negative high bits (1ull << 63) | 4095 define i8 @global_inst_valu_offset_64bit_12bit_neg_high_split0(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_bfrev_b32_e32 v2, 1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:-1 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0xfff +; GFX9-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split0: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0xfff +; GFX10-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0xfff +; GFX11-GISEL-NEXT: s_brev_b32 s1, 1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v2, 1 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split0: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off offset:-1 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854771713 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load @@ -734,35 +1412,77 @@ define i8 @global_inst_valu_offset_64bit_12bit_neg_high_split0(ptr addrspace(1) ; Fill 12-bit low-bits, negative high bits (1ull << 63) | 4096 define i8 @global_inst_valu_offset_64bit_12bit_neg_high_split1(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 -; GFX9-NEXT: v_bfrev_b32_e32 v2, 1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x1000 +; GFX9-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x1000 +; GFX10-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x1000 +; GFX11-GISEL-NEXT: s_brev_b32 s1, 1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x1000, v0 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v2, 1 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_12bit_neg_high_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x1000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854771712 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load @@ -770,35 +1490,77 @@ define i8 @global_inst_valu_offset_64bit_12bit_neg_high_split1(ptr addrspace(1) ; Fill 13-bit low-bits, negative high bits (1ull << 63) | 8191 define i8 @global_inst_valu_offset_64bit_13bit_neg_high_split0(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split0: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 -; GFX9-NEXT: v_bfrev_b32_e32 v2, 1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:-1 -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split0: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x1fff +; GFX9-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split0: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x1fff +; GFX10-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x1fff +; GFX11-GISEL-NEXT: s_brev_b32 s1, 1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split0: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v2, 1 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split0: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:-1 +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off offset:-1 +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854767617 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load @@ -806,35 +1568,77 @@ define i8 @global_inst_valu_offset_64bit_13bit_neg_high_split0(ptr addrspace(1) ; Fill 13-bit low-bits, negative high bits (1ull << 63) | 8192 define i8 @global_inst_valu_offset_64bit_13bit_neg_high_split1(ptr addrspace(1) %p) { -; GFX9-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1: -; GFX9: ; %bb.0: -; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 -; GFX9-NEXT: v_bfrev_b32_e32 v2, 1 -; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc -; GFX9-NEXT: global_load_ubyte v0, v[0:1], off -; GFX9-NEXT: s_waitcnt vmcnt(0) -; GFX9-NEXT: s_setpc_b64 s[30:31] -; -; GFX10-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX10-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 -; GFX10-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: s_setpc_b64 s[30:31] -; -; GFX11-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 -; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo -; GFX11-NEXT: global_load_u8 v0, v[0:1], off -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_setpc_b64 s[30:31] +; GFX9-GISEL-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1: +; GFX9-GISEL: ; %bb.0: +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-GISEL-NEXT: s_movk_i32 s4, 0x2000 +; GFX9-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX9-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v0, v2 +; GFX9-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, v1, v3, vcc +; GFX9-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-GISEL-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-GISEL-NEXT: s_movk_i32 s4, 0x2000 +; GFX10-GISEL-NEXT: s_brev_b32 s5, 1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v2, s4 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v3, s5 +; GFX10-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX10-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-GISEL-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-GISEL-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-GISEL-NEXT: s_movk_i32 s0, 0x2000 +; GFX11-GISEL-NEXT: s_brev_b32 s1, 1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 +; GFX11-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-GISEL-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1: +; GFX9-SDAG: ; %bb.0: +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0x2000, v0 +; GFX9-SDAG-NEXT: v_bfrev_b32_e32 v2, 1 +; GFX9-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, v2, v1, vcc +; GFX9-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX10-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-SDAG-LABEL: global_inst_valu_offset_64bit_13bit_neg_high_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-SDAG-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x2000, v0 +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0x80000000, v1, vcc_lo +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31] %gep = getelementptr i8, ptr addrspace(1) %p, i64 -9223372036854767616 %load = load i8, ptr addrspace(1) %gep, align 4 ret i8 %load @@ -1036,16 +1840,18 @@ define amdgpu_kernel void @global_inst_salu_offset_neg_12bit_max(ptr addrspace(1 ; GFX9-NEXT: global_store_byte v[0:1], v0, off ; GFX9-NEXT: s_endpgm ; -; GFX10-LABEL: global_inst_salu_offset_neg_12bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, s0, 0xfffff000, s0 -; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, -1, s1, s0 -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_store_byte v[0:1], v0, off -; GFX10-NEXT: s_endpgm +; GFX10-GISEL-LABEL: global_inst_salu_offset_neg_12bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-GISEL-NEXT: s_add_u32 s0, s0, 0xfffff000 +; GFX10-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: global_store_byte v[0:1], v0, off +; GFX10-GISEL-NEXT: s_endpgm ; ; GFX11-LABEL: global_inst_salu_offset_neg_12bit_max: ; GFX11: ; %bb.0: @@ -1057,6 +1863,17 @@ define amdgpu_kernel void @global_inst_salu_offset_neg_12bit_max(ptr addrspace(1 ; GFX11-NEXT: global_store_b8 v[0:1], v0, off ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX10-SDAG-LABEL: global_inst_salu_offset_neg_12bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-SDAG-NEXT: v_add_co_u32 v0, s0, 0xfffff000, s0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e64 v1, s0, -1, s1, s0 +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: global_store_byte v[0:1], v0, off +; GFX10-SDAG-NEXT: s_endpgm %gep = getelementptr i8, ptr addrspace(1) %p, i64 -4096 %load = load volatile i8, ptr addrspace(1) %gep, align 1 store i8 %load, ptr addrspace(1) undef @@ -1076,29 +1893,56 @@ define amdgpu_kernel void @global_inst_salu_offset_neg_13bit_max(ptr addrspace(1 ; GFX9-NEXT: global_store_byte v[0:1], v0, off ; GFX9-NEXT: s_endpgm ; -; GFX10-LABEL: global_inst_salu_offset_neg_13bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, s0, 0xffffe000, s0 -; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, -1, s1, s0 -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_store_byte v[0:1], v0, off -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: global_inst_salu_offset_neg_13bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0xffffe000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 -; GFX11-NEXT: global_load_u8 v0, v[0:1], off glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b8 v[0:1], v0, off -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX10-GISEL-LABEL: global_inst_salu_offset_neg_13bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-GISEL-NEXT: s_add_u32 s0, s0, 0xffffe000 +; GFX10-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: global_store_byte v[0:1], v0, off +; GFX10-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: global_inst_salu_offset_neg_13bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0xffffe000 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm +; +; GFX10-SDAG-LABEL: global_inst_salu_offset_neg_13bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-SDAG-NEXT: v_add_co_u32 v0, s0, 0xffffe000, s0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e64 v1, s0, -1, s1, s0 +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: global_store_byte v[0:1], v0, off +; GFX10-SDAG-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: global_inst_salu_offset_neg_13bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0xffffe000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm %gep = getelementptr i8, ptr addrspace(1) %p, i64 -8192 %load = load volatile i8, ptr addrspace(1) %gep, align 1 store i8 %load, ptr addrspace(1) undef @@ -1227,16 +2071,18 @@ define amdgpu_kernel void @global_inst_salu_offset_2x_neg_11bit_max(ptr addrspac ; GFX9-NEXT: global_store_byte v[0:1], v0, off ; GFX9-NEXT: s_endpgm ; -; GFX10-LABEL: global_inst_salu_offset_2x_neg_11bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, s0, 0xfffff000, s0 -; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, -1, s1, s0 -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_store_byte v[0:1], v0, off -; GFX10-NEXT: s_endpgm +; GFX10-GISEL-LABEL: global_inst_salu_offset_2x_neg_11bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-GISEL-NEXT: s_add_u32 s0, s0, 0xfffff000 +; GFX10-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: global_store_byte v[0:1], v0, off +; GFX10-GISEL-NEXT: s_endpgm ; ; GFX11-LABEL: global_inst_salu_offset_2x_neg_11bit_max: ; GFX11: ; %bb.0: @@ -1248,6 +2094,17 @@ define amdgpu_kernel void @global_inst_salu_offset_2x_neg_11bit_max(ptr addrspac ; GFX11-NEXT: global_store_b8 v[0:1], v0, off ; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) ; GFX11-NEXT: s_endpgm +; +; GFX10-SDAG-LABEL: global_inst_salu_offset_2x_neg_11bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-SDAG-NEXT: v_add_co_u32 v0, s0, 0xfffff000, s0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e64 v1, s0, -1, s1, s0 +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: global_store_byte v[0:1], v0, off +; GFX10-SDAG-NEXT: s_endpgm %gep = getelementptr i8, ptr addrspace(1) %p, i64 -4096 %load = load volatile i8, ptr addrspace(1) %gep, align 1 store i8 %load, ptr addrspace(1) undef @@ -1267,29 +2124,56 @@ define amdgpu_kernel void @global_inst_salu_offset_2x_neg_12bit_max(ptr addrspac ; GFX9-NEXT: global_store_byte v[0:1], v0, off ; GFX9-NEXT: s_endpgm ; -; GFX10-LABEL: global_inst_salu_offset_2x_neg_12bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, s0, 0xffffe000, s0 -; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, -1, s1, s0 -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_store_byte v[0:1], v0, off -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: global_inst_salu_offset_2x_neg_12bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0xffffe000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 -; GFX11-NEXT: global_load_u8 v0, v[0:1], off glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b8 v[0:1], v0, off -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX10-GISEL-LABEL: global_inst_salu_offset_2x_neg_12bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-GISEL-NEXT: s_add_u32 s0, s0, 0xffffe000 +; GFX10-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: global_store_byte v[0:1], v0, off +; GFX10-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: global_inst_salu_offset_2x_neg_12bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0xffffe000 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm +; +; GFX10-SDAG-LABEL: global_inst_salu_offset_2x_neg_12bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-SDAG-NEXT: v_add_co_u32 v0, s0, 0xffffe000, s0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e64 v1, s0, -1, s1, s0 +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: global_store_byte v[0:1], v0, off +; GFX10-SDAG-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: global_inst_salu_offset_2x_neg_12bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0xffffe000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm %gep = getelementptr i8, ptr addrspace(1) %p, i64 -8192 %load = load volatile i8, ptr addrspace(1) %gep, align 1 store i8 %load, ptr addrspace(1) undef @@ -1309,29 +2193,56 @@ define amdgpu_kernel void @global_inst_salu_offset_2x_neg_13bit_max(ptr addrspac ; GFX9-NEXT: global_store_byte v[0:1], v0, off ; GFX9-NEXT: s_endpgm ; -; GFX10-LABEL: global_inst_salu_offset_2x_neg_13bit_max: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, s0, 0xffffc000, s0 -; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, -1, s1, s0 -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_store_byte v[0:1], v0, off -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: global_inst_salu_offset_2x_neg_13bit_max: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0xffffc000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 -; GFX11-NEXT: global_load_u8 v0, v[0:1], off glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b8 v[0:1], v0, off -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX10-GISEL-LABEL: global_inst_salu_offset_2x_neg_13bit_max: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-GISEL-NEXT: s_add_u32 s0, s0, 0xffffc000 +; GFX10-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: global_store_byte v[0:1], v0, off +; GFX10-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: global_inst_salu_offset_2x_neg_13bit_max: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0xffffc000 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, -1 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm +; +; GFX10-SDAG-LABEL: global_inst_salu_offset_2x_neg_13bit_max: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-SDAG-NEXT: v_add_co_u32 v0, s0, 0xffffc000, s0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e64 v1, s0, -1, s1, s0 +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: global_store_byte v[0:1], v0, off +; GFX10-SDAG-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: global_inst_salu_offset_2x_neg_13bit_max: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0xffffc000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm %gep = getelementptr i8, ptr addrspace(1) %p, i64 -16384 %load = load volatile i8, ptr addrspace(1) %gep, align 1 store i8 %load, ptr addrspace(1) undef @@ -1352,29 +2263,56 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_11bit_split0(ptr addrsp ; GFX9-NEXT: global_store_byte v[0:1], v0, off ; GFX9-NEXT: s_endpgm ; -; GFX10-LABEL: global_inst_salu_offset_64bit_11bit_split0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, s0, 0, s0 -; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, 2, s1, s0 -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_store_byte v[0:1], v0, off -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: global_inst_salu_offset_64bit_11bit_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 -; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:2047 glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b8 v[0:1], v0, off -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX10-GISEL-LABEL: global_inst_salu_offset_64bit_11bit_split0: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-GISEL-NEXT: s_add_u32 s0, s0, 0x7ff +; GFX10-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: global_store_byte v[0:1], v0, off +; GFX10-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: global_inst_salu_offset_64bit_11bit_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x7ff +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm +; +; GFX10-SDAG-LABEL: global_inst_salu_offset_64bit_11bit_split0: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-SDAG-NEXT: v_add_co_u32 v0, s0, 0, s0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e64 v1, s0, 2, s1, s0 +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 glc dlc +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: global_store_byte v[0:1], v0, off +; GFX10-SDAG-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: global_inst_salu_offset_64bit_11bit_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off offset:2047 glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589936639 %load = load volatile i8, ptr addrspace(1) %gep, align 1 store i8 %load, ptr addrspace(1) undef @@ -1395,29 +2333,56 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_11bit_split1(ptr addrsp ; GFX9-NEXT: global_store_byte v[0:1], v0, off ; GFX9-NEXT: s_endpgm ; -; GFX10-LABEL: global_inst_salu_offset_64bit_11bit_split1: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, s0, 0x800, s0 -; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, 2, s1, s0 -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_store_byte v[0:1], v0, off -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: global_inst_salu_offset_64bit_11bit_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 -; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:2048 glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b8 v[0:1], v0, off -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX10-GISEL-LABEL: global_inst_salu_offset_64bit_11bit_split1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-GISEL-NEXT: s_add_u32 s0, s0, 0x800 +; GFX10-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: global_store_byte v[0:1], v0, off +; GFX10-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: global_inst_salu_offset_64bit_11bit_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x800 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm +; +; GFX10-SDAG-LABEL: global_inst_salu_offset_64bit_11bit_split1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-SDAG-NEXT: v_add_co_u32 v0, s0, 0x800, s0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e64 v1, s0, 2, s1, s0 +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: global_store_byte v[0:1], v0, off +; GFX10-SDAG-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: global_inst_salu_offset_64bit_11bit_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off offset:2048 glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589936640 %load = load volatile i8, ptr addrspace(1) %gep, align 1 store i8 %load, ptr addrspace(1) undef @@ -1438,29 +2403,56 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_12bit_split0(ptr addrsp ; GFX9-NEXT: global_store_byte v[0:1], v0, off ; GFX9-NEXT: s_endpgm ; -; GFX10-LABEL: global_inst_salu_offset_64bit_12bit_split0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, s0, 0x800, s0 -; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, 2, s1, s0 -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_store_byte v[0:1], v0, off -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: global_inst_salu_offset_64bit_12bit_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 -; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:4095 glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b8 v[0:1], v0, off -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX10-GISEL-LABEL: global_inst_salu_offset_64bit_12bit_split0: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-GISEL-NEXT: s_add_u32 s0, s0, 0xfff +; GFX10-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: global_store_byte v[0:1], v0, off +; GFX10-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: global_inst_salu_offset_64bit_12bit_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0xfff +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm +; +; GFX10-SDAG-LABEL: global_inst_salu_offset_64bit_12bit_split0: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-SDAG-NEXT: v_add_co_u32 v0, s0, 0x800, s0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e64 v1, s0, 2, s1, s0 +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 glc dlc +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: global_store_byte v[0:1], v0, off +; GFX10-SDAG-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: global_inst_salu_offset_64bit_12bit_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off offset:4095 glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589938687 %load = load volatile i8, ptr addrspace(1) %gep, align 1 store i8 %load, ptr addrspace(1) undef @@ -1481,29 +2473,56 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_12bit_split1(ptr addrsp ; GFX9-NEXT: global_store_byte v[0:1], v0, off ; GFX9-NEXT: s_endpgm ; -; GFX10-LABEL: global_inst_salu_offset_64bit_12bit_split1: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, s0, 0x1000, s0 -; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, 2, s1, s0 -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_store_byte v[0:1], v0, off -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: global_inst_salu_offset_64bit_12bit_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0x1000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 -; GFX11-NEXT: global_load_u8 v0, v[0:1], off glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b8 v[0:1], v0, off -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX10-GISEL-LABEL: global_inst_salu_offset_64bit_12bit_split1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-GISEL-NEXT: s_add_u32 s0, s0, 0x1000 +; GFX10-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: global_store_byte v[0:1], v0, off +; GFX10-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: global_inst_salu_offset_64bit_12bit_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x1000 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm +; +; GFX10-SDAG-LABEL: global_inst_salu_offset_64bit_12bit_split1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-SDAG-NEXT: v_add_co_u32 v0, s0, 0x1000, s0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e64 v1, s0, 2, s1, s0 +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: global_store_byte v[0:1], v0, off +; GFX10-SDAG-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: global_inst_salu_offset_64bit_12bit_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0x1000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589938688 %load = load volatile i8, ptr addrspace(1) %gep, align 1 store i8 %load, ptr addrspace(1) undef @@ -1524,29 +2543,56 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_13bit_split0(ptr addrsp ; GFX9-NEXT: global_store_byte v[0:1], v0, off ; GFX9-NEXT: s_endpgm ; -; GFX10-LABEL: global_inst_salu_offset_64bit_13bit_split0: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, s0, 0x1800, s0 -; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, 2, s1, s0 -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_store_byte v[0:1], v0, off -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: global_inst_salu_offset_64bit_13bit_split0: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0x1000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 -; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:4095 glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b8 v[0:1], v0, off -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX10-GISEL-LABEL: global_inst_salu_offset_64bit_13bit_split0: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-GISEL-NEXT: s_add_u32 s0, s0, 0x1fff +; GFX10-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: global_store_byte v[0:1], v0, off +; GFX10-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: global_inst_salu_offset_64bit_13bit_split0: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x1fff +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm +; +; GFX10-SDAG-LABEL: global_inst_salu_offset_64bit_13bit_split0: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-SDAG-NEXT: v_add_co_u32 v0, s0, 0x1800, s0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e64 v1, s0, 2, s1, s0 +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off offset:2047 glc dlc +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: global_store_byte v[0:1], v0, off +; GFX10-SDAG-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: global_inst_salu_offset_64bit_13bit_split0: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0x1000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off offset:4095 glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589942783 %load = load volatile i8, ptr addrspace(1) %gep, align 1 store i8 %load, ptr addrspace(1) undef @@ -1567,29 +2613,56 @@ define amdgpu_kernel void @global_inst_salu_offset_64bit_13bit_split1(ptr addrsp ; GFX9-NEXT: global_store_byte v[0:1], v0, off ; GFX9-NEXT: s_endpgm ; -; GFX10-LABEL: global_inst_salu_offset_64bit_13bit_split1: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 -; GFX10-NEXT: s_waitcnt lgkmcnt(0) -; GFX10-NEXT: v_add_co_u32 v0, s0, 0x2000, s0 -; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, 2, s1, s0 -; GFX10-NEXT: global_load_ubyte v0, v[0:1], off glc dlc -; GFX10-NEXT: s_waitcnt vmcnt(0) -; GFX10-NEXT: global_store_byte v[0:1], v0, off -; GFX10-NEXT: s_endpgm -; -; GFX11-LABEL: global_inst_salu_offset_64bit_13bit_split1: -; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_add_co_u32 v0, s0, 0x2000, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 -; GFX11-NEXT: global_load_u8 v0, v[0:1], off glc dlc -; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b8 v[0:1], v0, off -; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) -; GFX11-NEXT: s_endpgm +; GFX10-GISEL-LABEL: global_inst_salu_offset_64bit_13bit_split1: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-GISEL-NEXT: s_add_u32 s0, s0, 0x2000 +; GFX10-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, s1 +; GFX10-GISEL-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX10-GISEL-NEXT: global_store_byte v[0:1], v0, off +; GFX10-GISEL-NEXT: s_endpgm +; +; GFX11-GISEL-LABEL: global_inst_salu_offset_64bit_13bit_split1: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-GISEL-NEXT: s_add_u32 s0, s0, 0x2000 +; GFX11-GISEL-NEXT: s_addc_u32 s1, s1, 2 +; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-GISEL-NEXT: global_load_u8 v0, v[0:1], off glc dlc +; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX11-GISEL-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-GISEL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-GISEL-NEXT: s_endpgm +; +; GFX10-SDAG-LABEL: global_inst_salu_offset_64bit_13bit_split1: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24 +; GFX10-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-SDAG-NEXT: v_add_co_u32 v0, s0, 0x2000, s0 +; GFX10-SDAG-NEXT: v_add_co_ci_u32_e64 v1, s0, 2, s1, s0 +; GFX10-SDAG-NEXT: global_load_ubyte v0, v[0:1], off glc dlc +; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX10-SDAG-NEXT: global_store_byte v[0:1], v0, off +; GFX10-SDAG-NEXT: s_endpgm +; +; GFX11-SDAG-LABEL: global_inst_salu_offset_64bit_13bit_split1: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: s_load_b64 s[0:1], s[0:1], 0x24 +; GFX11-SDAG-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-SDAG-NEXT: v_add_co_u32 v0, s0, 0x2000, s0 +; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 2, s1, s0 +; GFX11-SDAG-NEXT: global_load_u8 v0, v[0:1], off glc dlc +; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX11-SDAG-NEXT: global_store_b8 v[0:1], v0, off +; GFX11-SDAG-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-SDAG-NEXT: s_endpgm %gep = getelementptr i8, ptr addrspace(1) %p, i64 8589942784 %load = load volatile i8, ptr addrspace(1) %gep, align 1 store i8 %load, ptr addrspace(1) undef