From db85cd729a0e3bd26e1ff27a510ab04272ba0a27 Mon Sep 17 00:00:00 2001 From: Lian Wang Date: Tue, 1 Mar 2022 07:35:19 +0000 Subject: [PATCH] [RISCV] Add FMV_W_X and FMV_H_X instrutions to hasAllNBitUsers Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D120699 --- llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 06e32eb2827aac..0bb6ac8b7b0116 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -1850,6 +1850,7 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits) const { case RISCV::CTZW: case RISCV::CPOPW: case RISCV::SLLI_UW: + case RISCV::FMV_W_X: case RISCV::FCVT_H_W: case RISCV::FCVT_H_WU: case RISCV::FCVT_S_W: @@ -1873,6 +1874,7 @@ bool RISCVDAGToDAGISel::hasAllNBitUsers(SDNode *Node, unsigned Bits) const { return false; break; case RISCV::SEXT_H: + case RISCV::FMV_H_X: case RISCV::ZEXT_H_RV32: case RISCV::ZEXT_H_RV64: if (Bits < 16)