diff --git a/llvm/include/llvm/CodeGen/RDFRegisters.h b/llvm/include/llvm/CodeGen/RDFRegisters.h
index 4b7ace48ff0e3..7bbf11c9ebd14 100644
--- a/llvm/include/llvm/CodeGen/RDFRegisters.h
+++ b/llvm/include/llvm/CodeGen/RDFRegisters.h
@@ -84,6 +84,8 @@ struct RegisterRef {
   constexpr bool isUnit() const { return isUnitId(Reg); }
   constexpr bool isMask() const { return isMaskId(Reg); }
 
+  constexpr unsigned idx() const { return toIdx(Reg); }
+
   constexpr operator bool() const {
     return !isReg() || (Reg != 0 && Mask.any());
   }
@@ -103,10 +105,18 @@ struct RegisterRef {
     return Register::isStackSlot(Id);
   }
 
-  static RegisterId toUnitId(unsigned Idx) {
-    return Register::index2VirtReg(Idx);
+  static constexpr RegisterId toUnitId(unsigned Idx) {
+    return Idx | MCRegister::VirtualRegFlag;
+  }
+
+  static constexpr unsigned toIdx(RegisterId Id) {
+    // Not using virtReg2Index or stackSlot2Index, because they are
+    // not constexpr.
+    if (isUnitId(Id))
+      return Id & ~MCRegister::VirtualRegFlag;
+    // RegId and MaskId are unchanged.
+    return Id;
   }
-  static unsigned toRegUnit(RegisterId U) { return Register::virtReg2Index(U); }
 
   bool operator<(RegisterRef) const = delete;
   bool operator==(RegisterRef) const = delete;
diff --git a/llvm/lib/CodeGen/RDFRegisters.cpp b/llvm/lib/CodeGen/RDFRegisters.cpp
index 5af6822ecfacb..7e6d33b1825e6 100644
--- a/llvm/lib/CodeGen/RDFRegisters.cpp
+++ b/llvm/lib/CodeGen/RDFRegisters.cpp
@@ -332,13 +332,13 @@ bool PhysicalRegisterInfo::less(RegisterRef A, RegisterRef B) const {
 
 void PhysicalRegisterInfo::print(raw_ostream &OS, RegisterRef A) const {
   if (A.Reg == 0 || A.isReg()) {
-    if (0 < A.Reg && A.Reg < TRI.getNumRegs())
-      OS << TRI.getName(A.Reg);
+    if (0 < A.idx() && A.idx() < TRI.getNumRegs())
+      OS << TRI.getName(A.idx());
     else
       OS << printReg(A.Reg, &TRI);
     OS << PrintLaneMaskShort(A.Mask);
   } else if (A.isUnit()) {
-    OS << printRegUnit(A.toRegUnit(A.Reg), &TRI);
+    OS << printRegUnit(A.idx(), &TRI);
   } else {
     assert(A.isMask());
     OS << '#' << format("%08x", A.Reg);