diff --git a/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll b/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
index f7a3f2e9f4185..6aa07e7846a66 100644
--- a/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
+++ b/llvm/test/CodeGen/AArch64/neon-bitwise-instructions.ll
@@ -885,6 +885,14 @@ define <4 x i32> @vselect_constant_cond_v4i32(<4 x i32> %a, <4 x i32> %b) {
   ret <4 x i32> %c
 }
 
+; CHECK: .byte   0
+; CHECK: .byte   8
+; CHECK: .byte   2
+; CHECK: .byte   9
+; CHECK: .byte   4
+; CHECK: .byte   5
+; CHECK: .byte   6
+; CHECK: .byte   7
 define <8 x i8> @vselect_equivalent_shuffle_v8i8(<8 x i8> %a, <8 x i8> %b) {
 ; CHECK-LABEL: vselect_equivalent_shuffle_v8i8:
 ; CHECK:       // %bb.0:
@@ -899,6 +907,15 @@ define <8 x i8> @vselect_equivalent_shuffle_v8i8(<8 x i8> %a, <8 x i8> %b) {
   ret <8 x i8> %c
 }
 
+; CHECK-LABEL: .LCPI90_0:
+; CHECK-NEXT: .byte   0
+; CHECK-NEXT: .byte   8
+; CHECK-NEXT: .byte   2
+; CHECK-NEXT: .byte   9
+; CHECK-NEXT: .byte   4
+; CHECK-NEXT: .byte   5
+; CHECK-NEXT: .byte   6
+; CHECK-NEXT: .byte   7
 define <8 x i8> @vselect_equivalent_shuffle_v8i8_zero(<8 x i8> %a) {
 ; CHECK-LABEL: vselect_equivalent_shuffle_v8i8_zero:
 ; CHECK:       // %bb.0:
@@ -912,30 +929,113 @@ define <8 x i8> @vselect_equivalent_shuffle_v8i8_zero(<8 x i8> %a) {
   ret <8 x i8> %c
 }
 
+; CHECK-LABEL: .LCPI91_0:
+; CHECK-NEXT: .byte   24
+; CHECK-NEXT: .byte   16
+; CHECK-NEXT: .byte   26
+; CHECK-NEXT: .byte   17
+; CHECK-NEXT: .byte   28
+; CHECK-NEXT: .byte   29
+; CHECK-NEXT: .byte   30
+; CHECK-NEXT: .byte   31
+define <8 x i8> @vselect_equivalent_shuffle_v8i8_zeroswap(<8 x i8> %a) {
+; CHECK-LABEL: vselect_equivalent_shuffle_v8i8_zeroswap:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adrp x8, .LCPI91_0
+; CHECK-NEXT:    // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT:    mov v0.d[1], v0.d[0]
+; CHECK-NEXT:    ldr d1, [x8, :lo12:.LCPI91_0]
+; CHECK-NEXT:    tbl v0.8b, { v0.16b }, v1.8b
+; CHECK-NEXT:    ret
+  %c = shufflevector <8 x i8> zeroinitializer, <8 x i8> %a, <8 x i32> <i32 8, i32 0, i32 10, i32 1, i32 12, i32 13, i32 14, i32 15>
+  ret <8 x i8> %c
+}
+
+; CHECK-LABEL: .LCPI92_0:
+; CHECK-NEXT: .byte   0
+; CHECK-NEXT: .byte   1
+; CHECK-NEXT: .byte   16
+; CHECK-NEXT: .byte   17
+; CHECK-NEXT: .byte   4
+; CHECK-NEXT: .byte   5
+; CHECK-NEXT: .byte   18
+; CHECK-NEXT: .byte   19
+; CHECK-NEXT: .byte   8
+; CHECK-NEXT: .byte   9
+; CHECK-NEXT: .byte   10
+; CHECK-NEXT: .byte   11
+; CHECK-NEXT: .byte   12
+; CHECK-NEXT: .byte   13
+; CHECK-NEXT: .byte   14
+; CHECK-NEXT: .byte   15
 define <8 x i16> @vselect_equivalent_shuffle_v8i16(<8 x i16> %a, <8 x i16> %b) {
 ; CHECK-LABEL: vselect_equivalent_shuffle_v8i16:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI91_0
+; CHECK-NEXT:    adrp x8, .LCPI92_0
 ; CHECK-NEXT:    // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1
 ; CHECK-NEXT:    // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1
-; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI91_0]
+; CHECK-NEXT:    ldr q2, [x8, :lo12:.LCPI92_0]
 ; CHECK-NEXT:    tbl v0.16b, { v0.16b, v1.16b }, v2.16b
 ; CHECK-NEXT:    ret
   %c = shufflevector <8 x i16> %a, <8 x i16> %b, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %c
 }
 
+; CHECK-LABEL: .LCPI93_0:
+; CHECK-NEXT: .byte   0
+; CHECK-NEXT: .byte   1
+; CHECK-NEXT: .byte   16
+; CHECK-NEXT: .byte   17
+; CHECK-NEXT: .byte   4
+; CHECK-NEXT: .byte   5
+; CHECK-NEXT: .byte   18
+; CHECK-NEXT: .byte   19
+; CHECK-NEXT: .byte   8
+; CHECK-NEXT: .byte   9
+; CHECK-NEXT: .byte   10
+; CHECK-NEXT: .byte   11
+; CHECK-NEXT: .byte   12
+; CHECK-NEXT: .byte   13
+; CHECK-NEXT: .byte   14
+; CHECK-NEXT: .byte   15
 define <8 x i16> @vselect_equivalent_shuffle_v8i16_zero(<8 x i16> %a) {
 ; CHECK-LABEL: vselect_equivalent_shuffle_v8i16_zero:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    adrp x8, .LCPI92_0
-; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI92_0]
+; CHECK-NEXT:    adrp x8, .LCPI93_0
+; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI93_0]
 ; CHECK-NEXT:    tbl v0.16b, { v0.16b }, v1.16b
 ; CHECK-NEXT:    ret
   %c = shufflevector <8 x i16> %a, <8 x i16> zeroinitializer, <8 x i32> <i32 0, i32 8, i32 2, i32 9, i32 4, i32 5, i32 6, i32 7>
   ret <8 x i16> %c
 }
 
+; CHECK: .byte   0
+; CHECK: .byte   1
+; CHECK: .byte   16
+; CHECK: .byte   17
+; CHECK: .byte   4
+; CHECK: .byte   5
+; CHECK: .byte   18
+; CHECK: .byte   19
+; CHECK: .byte   8
+; CHECK: .byte   9
+; CHECK: .byte   10
+; CHECK: .byte   11
+; CHECK: .byte   12
+; CHECK: .byte   13
+; CHECK: .byte   14
+; CHECK: .byte   15
+define <8 x i16> @vselect_equivalent_shuffle_v8i16_zeroswap(<8 x i16> %a) {
+; CHECK-LABEL: vselect_equivalent_shuffle_v8i16_zeroswap:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    adrp x8, .LCPI94_0
+; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI94_0]
+; CHECK-NEXT:    tbl v0.16b, { v0.16b }, v1.16b
+; CHECK-NEXT:    ret
+  %c = shufflevector <8 x i16> zeroinitializer, <8 x i16> %a, <8 x i32> <i32 8, i32 0, i32 10, i32 1, i32 12, i32 13, i32 14, i32 15>
+  ret <8 x i16> %c
+}
+
 define <4 x i16> @vselect_equivalent_shuffle_v4i16(<4 x i16> %a, <4 x i16> %b) {
 ; CHECK-LABEL: vselect_equivalent_shuffle_v4i16:
 ; CHECK:       // %bb.0: