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Fix zero-width bitfield extracts to emit 0
Fixes #55129
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jroelofs committed May 3, 2022
1 parent 15d20b9 commit e1c808b
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Showing 2 changed files with 25 additions and 0 deletions.
8 changes: 8 additions & 0 deletions llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
Expand Up @@ -4384,6 +4384,14 @@ bool CombinerHelper::matchBitfieldExtractFromShrAnd(
if (ShrAmt < 0 || ShrAmt >= Size)
return false;

// If the shift subsumes the mask, emit the 0 directly.
if (0 == (SMask >> ShrAmt)) {
MatchInfo = [=](MachineIRBuilder &B) {
B.buildConstant(Dst, 0);
};
return true;
}

// Check that ubfx can do the extraction, with no holes in the mask.
uint64_t UMask = SMask;
UMask |= maskTrailingOnes<uint64_t>(ShrAmt);
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Expand Up @@ -188,3 +188,20 @@ body: |
%4:_(s32) = G_LSHR %3, %2
$w0 = COPY %4(s32)
...
---
name: zero_from_large_shift
legalized: true
body: |
bb.1.entry:
; CHECK-LABEL: name: zero_from_large_shift
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: $x0 = COPY [[C]](s64)
%2:_(s32) = COPY $w0
%1:_(s8) = G_TRUNC %2:_(s32)
%3:_(s8) = G_ASSERT_ZEXT %1:_, 1
%5:_(s64) = G_CONSTANT i64 1
%7:_(s64) = G_ANYEXT %3:_(s8)
%4:_(s64) = G_AND %7:_, %5:_
%6:_(s64) = G_LSHR %4:_, %5:_(s64)
$x0 = COPY %6:_(s64)
...

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