diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h index 6e333073ffcb7..3bee9734d8a15 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CallLowering.h @@ -252,7 +252,8 @@ class CallLowering { /// This is overridable primarily for targets to maintain compatibility with /// hacks around the existing DAG call lowering infrastructure. virtual LLT getStackValueStoreType(const DataLayout &DL, - const CCValAssign &VA) const; + const CCValAssign &VA, + ISD::ArgFlagsTy Flags) const; /// The specified value has been assigned to a physical register, /// handle the appropriate COPY (either to or from) and mark any diff --git a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp index 4431d68312293..282414170a8df 100644 --- a/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CallLowering.cpp @@ -156,10 +156,16 @@ void CallLowering::setArgFlags(CallLowering::ArgInfo &Arg, unsigned OpIdx, const AttributeList &Attrs = FuncInfo.getAttributes(); addArgFlagsFromAttributes(Flags, Attrs, OpIdx); + PointerType *PtrTy = dyn_cast(Arg.Ty->getScalarType()); + if (PtrTy) { + Flags.setPointer(); + Flags.setPointerAddrSpace(PtrTy->getPointerAddressSpace()); + } + Align MemAlign = DL.getABITypeAlign(Arg.Ty); if (Flags.isByVal() || Flags.isInAlloca() || Flags.isPreallocated()) { assert(OpIdx >= AttributeList::FirstArgIndex); - Type *ElementTy = cast(Arg.Ty)->getElementType(); + Type *ElementTy = PtrTy->getElementType(); auto Ty = Attrs.getAttribute(OpIdx, Attribute::ByVal).getValueAsType(); Flags.setByValSize(DL.getTypeAllocSize(Ty ? Ty : ElementTy)); @@ -347,6 +353,14 @@ static void buildCopyFromRegs(MachineIRBuilder &B, ArrayRef OrigRegs, .getReg(0); } + // Sometimes pointers are passed zero extended. + LLT OrigTy = MRI.getType(OrigRegs[0]); + if (OrigTy.isPointer()) { + LLT IntPtrTy = LLT::scalar(OrigTy.getSizeInBits()); + B.buildIntToPtr(OrigRegs[0], B.buildTrunc(IntPtrTy, SrcReg)); + return; + } + B.buildTrunc(OrigRegs[0], SrcReg); return; } @@ -690,7 +704,7 @@ bool CallLowering::handleAssignments(ValueHandler &Handler, // TODO: The memory size may be larger than the value we need to // store. We may need to adjust the offset for big endian targets. - LLT MemTy = Handler.getStackValueStoreType(DL, VA); + LLT MemTy = Handler.getStackValueStoreType(DL, VA, Flags); MachinePointerInfo MPO; Register StackAddr = Handler.getStackAddress( @@ -1026,13 +1040,26 @@ bool CallLowering::resultsCompatible(CallLoweringInfo &Info, } LLT CallLowering::ValueHandler::getStackValueStoreType( - const DataLayout &DL, const CCValAssign &VA) const { + const DataLayout &DL, const CCValAssign &VA, ISD::ArgFlagsTy Flags) const { const MVT ValVT = VA.getValVT(); - if (ValVT != MVT::iPTR) - return LLT(ValVT); + if (ValVT != MVT::iPTR) { + LLT ValTy(ValVT); + + // We lost the pointeriness going through CCValAssign, so try to restore it + // based on the flags. + if (Flags.isPointer()) { + LLT PtrTy = LLT::pointer(Flags.getPointerAddrSpace(), + ValTy.getScalarSizeInBits()); + if (ValVT.isVector()) + return LLT::vector(ValTy.getElementCount(), PtrTy); + return PtrTy; + } + + return ValTy; + } - /// FIXME: We need to get the correct pointer address space. - return LLT::pointer(0, DL.getPointerSize(0)); + unsigned AddrSpace = Flags.getPointerAddrSpace(); + return LLT::pointer(AddrSpace, DL.getPointerSize(AddrSpace)); } void CallLowering::ValueHandler::copyArgumentMemory( @@ -1073,6 +1100,14 @@ Register CallLowering::ValueHandler::extendRegister(Register ValReg, LocTy = LLT::scalar(MaxSizeBits); } + const LLT ValRegTy = MRI.getType(ValReg); + if (ValRegTy.isPointer()) { + // The x32 ABI wants to zero extend 32-bit pointers to 64-bit registers, so + // we have to cast to do the extension. + LLT IntPtrTy = LLT::scalar(ValRegTy.getSizeInBits()); + ValReg = MIRBuilder.buildPtrToInt(IntPtrTy, ValReg).getReg(0); + } + switch (VA.getLocInfo()) { default: break; case CCValAssign::Full: diff --git a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp index 611ae1a5a4b9f..dcc6a44c5452d 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64CallLowering.cpp @@ -146,8 +146,8 @@ struct IncomingArgHandler : public CallLowering::IncomingValueHandler { return AddrReg.getReg(0); } - LLT getStackValueStoreType(const DataLayout &, - const CCValAssign &VA) const override { + LLT getStackValueStoreType(const DataLayout &, const CCValAssign &VA, + ISD::ArgFlagsTy Flags) const override { return getStackValueStoreTypeHack(VA); } @@ -262,8 +262,8 @@ struct OutgoingArgHandler : public CallLowering::OutgoingValueHandler { /// we invert the interpretation of ValVT and LocVT in certain cases. This is /// for compatability with the DAG call lowering implementation, which we're /// currently building on top of. - LLT getStackValueStoreType(const DataLayout &, - const CCValAssign &VA) const override { + LLT getStackValueStoreType(const DataLayout &, const CCValAssign &VA, + ISD::ArgFlagsTy Flags) const override { return getStackValueStoreTypeHack(VA); } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll index 70c7d6a52e342..8b541f942f4b6 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-call.ll @@ -3724,10 +3724,10 @@ define amdgpu_kernel void @test_call_external_void_func_v32i32_p3_p5() #0 { ; CHECK: G_STORE [[UV31]](s32), [[PTR_ADD1]](p5) :: (store (s32) into stack, align 16, addrspace 5) ; CHECK: [[C4:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[PTR_ADD2:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C4]](s32) - ; CHECK: G_STORE [[LOAD2]](p3), [[PTR_ADD2]](p5) :: (store (s32) into stack + 4, addrspace 5) + ; CHECK: G_STORE [[LOAD2]](p3), [[PTR_ADD2]](p5) :: (store (p3) into stack + 4, addrspace 5) ; CHECK: [[C5:%[0-9]+]]:_(s32) = G_CONSTANT i32 8 ; CHECK: [[PTR_ADD3:%[0-9]+]]:_(p5) = G_PTR_ADD [[COPY21]], [[C5]](s32) - ; CHECK: G_STORE [[LOAD3]](p5), [[PTR_ADD3]](p5) :: (store (s32) into stack + 8, align 8, addrspace 5) + ; CHECK: G_STORE [[LOAD3]](p5), [[PTR_ADD3]](p5) :: (store (p5) into stack + 8, align 8, addrspace 5) ; CHECK: [[COPY22:%[0-9]+]]:_(<4 x s32>) = COPY $private_rsrc_reg ; CHECK: $sgpr0_sgpr1_sgpr2_sgpr3 = COPY [[COPY22]](<4 x s32>) ; CHECK: $sgpr4_sgpr5 = COPY [[COPY11]](p4) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll index 5474bd0bd9c0b..4654688ec1d83 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-function-args.ll @@ -2147,9 +2147,9 @@ define void @void_func_v32i32_p3_p5_i16(<32 x i32> %arg0, i8 addrspace(3)* %arg1 ; CHECK: [[COPY31:%[0-9]+]]:_(s32) = COPY $vgpr31 ; CHECK: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY4]](s32), [[COPY5]](s32), [[COPY6]](s32), [[COPY7]](s32), [[COPY8]](s32), [[COPY9]](s32), [[COPY10]](s32), [[COPY11]](s32), [[COPY12]](s32), [[COPY13]](s32), [[COPY14]](s32), [[COPY15]](s32), [[COPY16]](s32), [[COPY17]](s32), [[COPY18]](s32), [[COPY19]](s32), [[COPY20]](s32), [[COPY21]](s32), [[COPY22]](s32), [[COPY23]](s32), [[COPY24]](s32), [[COPY25]](s32), [[COPY26]](s32), [[COPY27]](s32), [[COPY28]](s32), [[COPY29]](s32), [[COPY30]](s32), [[COPY31]](s32) ; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.1 - ; CHECK: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load (s32) from %fixed-stack.1, align 16, addrspace 5) + ; CHECK: [[LOAD:%[0-9]+]]:_(p3) = G_LOAD [[FRAME_INDEX]](p5) :: (invariant load (p3) from %fixed-stack.1, align 16, addrspace 5) ; CHECK: [[FRAME_INDEX1:%[0-9]+]]:_(p5) = G_FRAME_INDEX %fixed-stack.0 - ; CHECK: [[LOAD1:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load (s32) from %fixed-stack.0, addrspace 5) + ; CHECK: [[LOAD1:%[0-9]+]]:_(p5) = G_LOAD [[FRAME_INDEX1]](p5) :: (invariant load (p5) from %fixed-stack.0, addrspace 5) ; CHECK: [[COPY32:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 ; CHECK: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF ; CHECK: [[COPY33:%[0-9]+]]:_(p1) = COPY [[DEF]](p1) diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll index 8eaba740e3d2f..f7e58c4355172 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-irtranslator.ll @@ -267,7 +267,7 @@ define i32 @test_ptr_arg_on_stack(i32 %a0, i32 %a1, i32 %a2, i32 %a3, i32* %p) { ; CHECK: id: [[P:[0-9]+]]{{.*}}offset: 0{{.*}}size: 4 ; CHECK: liveins: $r0, $r1, $r2, $r3 ; CHECK: [[FIP:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.[[P]] -; CHECK: [[VREGP:%[0-9]+]]:_(p0) = G_LOAD [[FIP]](p0){{.*}}load (s32) +; CHECK: [[VREGP:%[0-9]+]]:_(p0) = G_LOAD [[FIP]](p0){{.*}}load (p0) ; CHECK: [[VREGV:%[0-9]+]]:_(s32) = G_LOAD [[VREGP]](p0){{.*}}load (s32) ; CHECK: $r0 = COPY [[VREGV]] ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0 diff --git a/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll b/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll index e30f4315d9653..d2e73235b0e4c 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/arm-param-lowering.ll @@ -41,7 +41,7 @@ define arm_aapcscc i32* @test_call_simple_stack_params(i32 *%a, i32 %b) { ; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP2]], [[OFF2]](s32) -; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store (s32) +; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store (p0) ; ARM: BL @simple_stack_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; THUMB: tBL 14 /* CC::al */, $noreg, @simple_stack_params_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; CHECK: [[RVREG:%[0-9]+]]:_(p0) = COPY $r0 diff --git a/llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll b/llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll index e0ea6d78dbaf0..104a78506a4d7 100644 --- a/llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll +++ b/llvm/test/CodeGen/ARM/GlobalISel/irtranslator-varargs-lowering.ll @@ -19,7 +19,7 @@ define arm_aapcscc i32 @test_call_to_varargs_with_ints(i32 *%a, i32 %b) { ; CHECK: [[SP2:%[0-9]+]]:_(p0) = COPY $sp ; CHECK: [[OFF2:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; CHECK: [[FI2:%[0-9]+]]:_(p0) = G_PTR_ADD [[SP2]], [[OFF2]](s32) -; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store (s32) +; CHECK: G_STORE [[AVREG]](p0), [[FI2]](p0){{.*}}store (p0) ; ARM: BL @int_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; THUMB: tBL 14 /* CC::al */, $noreg, @int_varargs_target, csr_aapcs, implicit-def $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit $r3, implicit-def $r0 ; CHECK: [[RVREG:%[0-9]+]]:_(s32) = COPY $r0 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll index 9782a7b777442..23bd1c3d6d69e 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/irtranslator/pointers.ll @@ -24,7 +24,7 @@ define i32 @ptr_arg_on_stack(i32 %x1, i32 %x2, i32 %x3, i32 %x4, i32* %p) { ; MIPS32: [[COPY2:%[0-9]+]]:_(s32) = COPY $a2 ; MIPS32: [[COPY3:%[0-9]+]]:_(s32) = COPY $a3 ; MIPS32: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; MIPS32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (s32) from %fixed-stack.0, align 8) + ; MIPS32: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (load (p0) from %fixed-stack.0, align 8) ; MIPS32: [[LOAD1:%[0-9]+]]:_(s32) = G_LOAD [[LOAD]](p0) :: (load (s32) from %ir.p) ; MIPS32: $v0 = COPY [[LOAD1]](s32) ; MIPS32: RetRA implicit $v0 diff --git a/llvm/test/CodeGen/X86/GlobalISel/GV.ll b/llvm/test/CodeGen/X86/GlobalISel/GV.ll index 0e333ea120102..3721d7273d97d 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/GV.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/GV.ll @@ -26,6 +26,7 @@ define dso_local i32* @test_global_ptrv() #3 { ; X32ABI-LABEL: test_global_ptrv: ; X32ABI: # %bb.0: # %entry ; X32ABI-NEXT: leal g_int, %eax +; X32ABI-NEXT: movl %eax, %eax ; X32ABI-NEXT: retq entry: ret i32* @g_int diff --git a/llvm/test/CodeGen/X86/GlobalISel/frameIndex.ll b/llvm/test/CodeGen/X86/GlobalISel/frameIndex.ll index f4f19352546ae..1b9f7643f9ee6 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/frameIndex.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/frameIndex.ll @@ -3,8 +3,8 @@ ; RUN: llc -mtriple=x86_64-linux-gnu -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X64 ; RUN: llc -mtriple=i386-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X32 ; RUN: llc -mtriple=i386-linux-gnu -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X32 -; RUN: llc -mtriple=x86_64-linux-gnux32 -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X32ABI -; RUN: llc -mtriple=x86_64-linux-gnux32 -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X32ABI +; RUN: llc -mtriple=x86_64-linux-gnux32 -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X32ABI-GISEL +; RUN: llc -mtriple=x86_64-linux-gnux32 -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X32ABI-SDAG define i32* @allocai32() { ; X64-LABEL: allocai32: @@ -21,6 +21,16 @@ define i32* @allocai32() { ; X32-NEXT: .cfi_def_cfa_offset 4 ; X32-NEXT: retl ; +; X32ABI-GISEL-LABEL: allocai32: +; X32ABI-GISEL: # %bb.0: +; X32ABI-GISEL-NEXT: leal -{{[0-9]+}}(%rsp), %eax +; X32ABI-GISEL-NEXT: movl %eax, %eax +; X32ABI-GISEL-NEXT: retq +; +; X32ABI-SDAG-LABEL: allocai32: +; X32ABI-SDAG: # %bb.0: +; X32ABI-SDAG-NEXT: leal -{{[0-9]+}}(%rsp), %eax +; X32ABI-SDAG-NEXT: retq ; X32ABI-LABEL: allocai32: ; X32ABI: # %bb.0: ; X32ABI-NEXT: leal -{{[0-9]+}}(%rsp), %eax diff --git a/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll b/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll index 666da92e43383..f3e4de73e0d95 100644 --- a/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll +++ b/llvm/test/CodeGen/X86/GlobalISel/irtranslator-callingconv.ll @@ -317,7 +317,7 @@ define i32 * @test_memop_i32(i32 * %p1) { ; X86-LABEL: name: test_memop_i32 ; X86: bb.1 (%ir-block.0): ; X86: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X86: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s32) from %fixed-stack.0, align 16) + ; X86: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (p0) from %fixed-stack.0, align 16) ; X86: $eax = COPY [[LOAD]](p0) ; X86: RET 0, implicit $eax ; X64-LABEL: name: test_memop_i32 @@ -540,7 +540,7 @@ define void @test_indirect_call(void()* %func) { ; X86-LABEL: name: test_indirect_call ; X86: bb.1 (%ir-block.0): ; X86: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X86: [[LOAD:%[0-9]+]]:gr32(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s32) from %fixed-stack.0, align 16) + ; X86: [[LOAD:%[0-9]+]]:gr32(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (p0) from %fixed-stack.0, align 16) ; X86: ADJCALLSTACKDOWN32 0, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X86: CALL32r [[LOAD]](p0), csr_32, implicit $esp, implicit $ssp ; X86: ADJCALLSTACKUP32 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp @@ -563,7 +563,7 @@ define void @test_abi_exts_call(i8* %addr) { ; X86-LABEL: name: test_abi_exts_call ; X86: bb.1 (%ir-block.0): ; X86: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X86: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s32) from %fixed-stack.0, align 16) + ; X86: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (p0) from %fixed-stack.0, align 16) ; X86: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[LOAD]](p0) :: (load (s8) from %ir.addr) ; X86: ADJCALLSTACKDOWN32 4, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X86: [[COPY:%[0-9]+]]:_(p0) = COPY $esp @@ -621,16 +621,16 @@ define void @test_variadic_call_1(i8** %addr_ptr, i32* %val_ptr) { ; X86-LABEL: name: test_variadic_call_1 ; X86: bb.1 (%ir-block.0): ; X86: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; X86: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s32) from %fixed-stack.1, align 16) + ; X86: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (p0) from %fixed-stack.1, align 16) ; X86: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X86: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s32) from %fixed-stack.0) + ; X86: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (p0) from %fixed-stack.0) ; X86: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[LOAD]](p0) :: (load (p0) from %ir.addr_ptr) ; X86: [[LOAD3:%[0-9]+]]:_(s32) = G_LOAD [[LOAD1]](p0) :: (load (s32) from %ir.val_ptr) ; X86: ADJCALLSTACKDOWN32 8, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X86: [[COPY:%[0-9]+]]:_(p0) = COPY $esp ; X86: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; X86: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32) - ; X86: G_STORE [[LOAD2]](p0), [[PTR_ADD]](p0) :: (store (s32) into stack, align 1) + ; X86: G_STORE [[LOAD2]](p0), [[PTR_ADD]](p0) :: (store (p0) into stack, align 1) ; X86: [[COPY1:%[0-9]+]]:_(p0) = COPY $esp ; X86: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; X86: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s32) @@ -662,16 +662,16 @@ define void @test_variadic_call_2(i8** %addr_ptr, double* %val_ptr) { ; X86-LABEL: name: test_variadic_call_2 ; X86: bb.1 (%ir-block.0): ; X86: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1 - ; X86: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s32) from %fixed-stack.1, align 16) + ; X86: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (p0) from %fixed-stack.1, align 16) ; X86: [[FRAME_INDEX1:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 - ; X86: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (s32) from %fixed-stack.0) + ; X86: [[LOAD1:%[0-9]+]]:_(p0) = G_LOAD [[FRAME_INDEX1]](p0) :: (invariant load (p0) from %fixed-stack.0) ; X86: [[LOAD2:%[0-9]+]]:_(p0) = G_LOAD [[LOAD]](p0) :: (load (p0) from %ir.addr_ptr) ; X86: [[LOAD3:%[0-9]+]]:_(s64) = G_LOAD [[LOAD1]](p0) :: (load (s64) from %ir.val_ptr, align 4) ; X86: ADJCALLSTACKDOWN32 12, 0, 0, implicit-def $esp, implicit-def $eflags, implicit-def $ssp, implicit $esp, implicit $ssp ; X86: [[COPY:%[0-9]+]]:_(p0) = COPY $esp ; X86: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; X86: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s32) - ; X86: G_STORE [[LOAD2]](p0), [[PTR_ADD]](p0) :: (store (s32) into stack, align 1) + ; X86: G_STORE [[LOAD2]](p0), [[PTR_ADD]](p0) :: (store (p0) into stack, align 1) ; X86: [[COPY1:%[0-9]+]]:_(p0) = COPY $esp ; X86: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 4 ; X86: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY1]], [[C1]](s32) diff --git a/llvm/test/CodeGen/X86/GlobalISel/x32-irtranslator.ll b/llvm/test/CodeGen/X86/GlobalISel/x32-irtranslator.ll new file mode 100644 index 0000000000000..e3e8c1aa45c50 --- /dev/null +++ b/llvm/test/CodeGen/X86/GlobalISel/x32-irtranslator.ll @@ -0,0 +1,29 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +; RUN: llc -global-isel -mtriple=x86_64-linux-gnux32 -stop-after=irtranslator -verify-machineinstrs < %s -o - | FileCheck -check-prefix=X32ABI %s + +define i32* @ret_ptr() { + ; X32ABI-LABEL: name: ret_ptr + ; X32ABI: bb.1 (%ir-block.0): + ; X32ABI: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF + ; X32ABI: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load (p0) from `i32** undef`) + ; X32ABI: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[LOAD]](p0) + ; X32ABI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[PTRTOINT]](s32) + ; X32ABI: $rax = COPY [[ZEXT]](s64) + ; X32ABI: RET 0, implicit $rax + %ptr = load i32*, i32** undef + ret i32* %ptr +} + +define void @arg_ptr(i32* %ptr) { + ; X32ABI-LABEL: name: arg_ptr + ; X32ABI: bb.1 (%ir-block.0): + ; X32ABI: liveins: $rdi + ; X32ABI: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi + ; X32ABI: [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY]](s64) + ; X32ABI: [[INTTOPTR:%[0-9]+]]:_(p0) = G_INTTOPTR [[TRUNC]](s32) + ; X32ABI: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1 + ; X32ABI: G_STORE [[C]](s32), [[INTTOPTR]](p0) :: (store (s32) into %ir.ptr) + ; X32ABI: RET 0 + store i32 1, i32* %ptr + ret void +}