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[VE][NFC] Disable VP tests
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VP tests recently added don't work on Release mode.  They work on
Debug mode, so I disable them on Release mode to make tests work.
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kaz7 committed Dec 10, 2020
1 parent bfcd362 commit e954ba2
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Showing 13 changed files with 13 additions and 0 deletions.
1 change: 1 addition & 0 deletions llvm/test/CodeGen/VE/Vector/vp_add.ll
@@ -1,3 +1,4 @@
; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s

; CHECK: t{{[0-9]+}}: v256i32 = vp_add [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/VE/Vector/vp_and.ll
@@ -1,3 +1,4 @@
; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s

; CHECK: t{{[0-9]+}}: v256i32 = vp_and [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/VE/Vector/vp_ashr.ll
@@ -1,3 +1,4 @@
; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s

; CHECK: t{{[0-9]+}}: v256i32 = vp_ashr [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/VE/Vector/vp_lshr.ll
@@ -1,3 +1,4 @@
; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s

; CHECK: t{{[0-9]+}}: v256i32 = vp_lshr [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/VE/Vector/vp_mul.ll
@@ -1,3 +1,4 @@
; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s

; CHECK: t{{[0-9]+}}: v256i32 = vp_mul [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/VE/Vector/vp_or.ll
@@ -1,3 +1,4 @@
; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s

; CHECK: t{{[0-9]+}}: v256i32 = vp_or [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/VE/Vector/vp_sdiv.ll
@@ -1,3 +1,4 @@
; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s

; CHECK: t{{[0-9]+}}: v256i32 = vp_sdiv [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/VE/Vector/vp_shl.ll
@@ -1,3 +1,4 @@
; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s

; CHECK: t{{[0-9]+}}: v256i32 = vp_shl [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/VE/Vector/vp_srem.ll
@@ -1,3 +1,4 @@
; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s

; CHECK: t{{[0-9]+}}: v256i32 = vp_srem [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/VE/Vector/vp_sub.ll
@@ -1,3 +1,4 @@
; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s

; CHECK: t{{[0-9]+}}: v256i32 = vp_sub [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/VE/Vector/vp_udiv.ll
@@ -1,3 +1,4 @@
; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s

; CHECK: t{{[0-9]+}}: v256i32 = vp_udiv [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/VE/Vector/vp_urem.ll
@@ -1,3 +1,4 @@
; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s

; CHECK: t{{[0-9]+}}: v256i32 = vp_urem [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
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1 change: 1 addition & 0 deletions llvm/test/CodeGen/VE/Vector/vp_xor.ll
@@ -1,3 +1,4 @@
; REQUIRES: asserts
; RUN: not --crash llc %s -march=ve -mattr=+vpu -o /dev/null |& FileCheck %s

; CHECK: t{{[0-9]+}}: v256i32 = vp_xor [[A:t[0-9]+]], [[B:t[0-9]+]], [[MASK:t[0-9]+]], [[EVL:t[0-9]+]]
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