[VE] Support Transfer Control Instructions in MC layer

Summary:
Add regression tests of asmparser, mccodeemitter, and disassembler for
transfer control instructions.  Add FENCEI/FENCEM/FENCEC/SVOB instructions
also.  Add new instruction format to represent FENCE* instructions too.

Differential Revision: https://reviews.llvm.org/D81440

llvm/lib/Target/VE/AsmParser/VEAsmParser.cpp

@@ -218,6 +218,17 @@ class VEOperand : public MCParsedAsmOperand {
     }
     return false;
   }
+  bool isUImm2() {
+    if (!isImm())
+      return false;
+
+    // Constant case
+    if (const auto *ConstExpr = dyn_cast<MCConstantExpr>(Imm.Val)) {
+      int64_t Value = ConstExpr->getValue();
+      return isUInt<2>(Value);
+    }
+    return false;
+  }
   bool isUImm3() {
     if (!isImm())
       return false;
@@ -404,6 +415,10 @@ class VEOperand : public MCParsedAsmOperand {
     addImmOperands(Inst, N);
   }
 
+  void addUImm2Operands(MCInst &Inst, unsigned N) const {
+    addImmOperands(Inst, N);
+  }
+
   void addUImm3Operands(MCInst &Inst, unsigned N) const {
     addImmOperands(Inst, N);
   }

llvm/lib/Target/VE/VEInstrFormats.td

@@ -133,6 +133,28 @@ class RR<bits<8>opVal, dag outs, dag ins, string asmstr, list<dag> pattern = []>
   let Inst{3-0} = cfw;
 }
 
+// RRFENCE type is special RR type for a FENCE instruction.
+class RRFENCE<bits<8>opVal, dag outs, dag ins, string asmstr,
+              list<dag> pattern = []>
+   : InstVE<outs, ins, asmstr, pattern> {
+  bits<1> avo = 0;
+  bits<1> lf = 0;
+  bits<1> sf = 0;
+  bits<1> c2 = 0;
+  bits<1> c1 = 0;
+  bits<1> c0 = 0;
+  let op = opVal;
+  let Inst{55} = avo;
+  let Inst{54-50} = 0;
+  let Inst{49} = lf;
+  let Inst{48} = sf;
+  let Inst{47-43} = 0;
+  let Inst{42} = c2;
+  let Inst{41} = c1;
+  let Inst{40} = c0;
+  let Inst{39-0} = 0;
+}
+
 //-----------------------------------------------------------------------------
 // Section 5.5 RW Type
 //-----------------------------------------------------------------------------

llvm/lib/Target/VE/VEInstrInfo.td

@@ -125,6 +125,15 @@ def zero : Operand<i32>, PatLeaf<(imm), [{
 def uimm1 : Operand<i32>, PatLeaf<(imm), [{
     return isUInt<1>(N->getZExtValue()); }]>;
 
+// uimm2 - Generic immediate value.
+def UImm2AsmOperand : AsmOperandClass {
+  let Name = "UImm2";
+}
+def uimm2 : Operand<i32>, PatLeaf<(imm), [{
+    return isUInt<2>(N->getZExtValue()); }], ULO7> {
+  let ParserMatchClass = UImm2AsmOperand;
+}
+
 // uimm3 - Generic immediate value.
 def UImm3AsmOperand : AsmOperandClass {
   let Name = "UImm3";
@@ -926,11 +935,30 @@ defm ST1B : STOREm<"st1b", 0x15, I32, i32, truncstorei8>;
 // Section 8.2.18 - TS3AM (Test and Set 3 AM)
 // Section 8.2.19 - ATMAM (Atomic AM)
 // Section 8.2.20 - CAS (Compare and Swap)
+
 //-----------------------------------------------------------------------------
 // Section 8.3 - Transfer Control Instructions
 //-----------------------------------------------------------------------------
+
 // Section 8.3.1 - FENCE (Fence)
+let hasSideEffects = 1 in {
+  let avo = 1 in def FENCEI : RRFENCE<0x20, (outs), (ins), "fencei">;
+  def FENCEM : RRFENCE<0x20, (outs), (ins uimm2:$kind), "fencem $kind"> {
+    bits<2> kind;
+    let lf = kind{1};
+    let sf = kind{0};
+  }
+  def FENCEC : RRFENCE<0x20, (outs), (ins uimm3:$kind), "fencec $kind"> {
+    bits<3> kind;
+    let c2 = kind{2};
+    let c1 = kind{1};
+    let c0 = kind{0};
+  }
+}
+
 // Section 8.3.2 - SVOB (Set Vector Out-of-order memory access Boundary)
+let sx = 0, cy = 0, sy = 0, cz = 0, sz = 0, hasSideEffects = 1 in
+def SVOB : RR<0x30, (outs), (ins), "svob">;
 
 //-----------------------------------------------------------------------------
 // Section 8.4 - Fixed-point Operation Instructions

llvm/test/MC/VE/FENCE.s

@@ -0,0 +1,48 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: fencei
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x80,0x20]
+fencei
+
+# CHECK-INST: fencem 1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x20]
+fencem 1
+
+# CHECK-INST: fencem 2
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x02,0x20]
+fencem 2
+
+# CHECK-INST: fencem 3
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x20]
+fencem 3
+
+# CHECK-INST: fencec 1
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x20]
+fencec 1
+
+# CHECK-INST: fencec 2
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x02,0x00,0x20]
+fencec 2
+
+# CHECK-INST: fencec 3
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x20]
+fencec 3
+
+# CHECK-INST: fencec 4
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x04,0x00,0x20]
+fencec 4
+
+# CHECK-INST: fencec 5
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x05,0x00,0x20]
+fencec 5
+
+# CHECK-INST: fencec 6
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x06,0x00,0x20]
+fencec 6
+
+# CHECK-INST: fencec 7
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x07,0x00,0x20]
+fencec 7

llvm/test/MC/VE/SVOB.s

@@ -0,0 +1,8 @@
+# RUN: llvm-mc -triple=ve --show-encoding < %s \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+# RUN: llvm-mc -triple=ve -filetype=obj < %s | llvm-objdump -d - \
+# RUN:     | FileCheck %s --check-prefixes=CHECK-INST
+
+# CHECK-INST: svob
+# CHECK-ENCODING: encoding: [0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x30]
+svob