diff --git a/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll b/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
index 635be23cf6725f..66f06cde47eb4f 100644
--- a/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
+++ b/llvm/test/CodeGen/RISCV/rv64i-exhaustive-w-insts.ll
@@ -1645,9 +1645,6 @@ define signext i32 @sext_sraiw_zext(i32 zeroext %a) nounwind {
   ret i32 %1
 }
 
-; TODO: sraiw could be selected rather than sext.w and srli. Alternatively,
-; the srli could be merged in to the shifts used for zero-extension.
-
 define zeroext i32 @zext_sraiw_aext(i32 %a) nounwind {
 ; RV64I-LABEL: zext_sraiw_aext:
 ; RV64I:       # %bb.0:
@@ -1669,9 +1666,6 @@ define zeroext i32 @zext_sraiw_sext(i32 signext %a) nounwind {
   ret i32 %1
 }
 
-; TODO: sraiw could be selected rather than sext.w and srli. Alternatively,
-; the srli could be merged in to the shifts used for zero-extension.
-
 define zeroext i32 @zext_sraiw_zext(i32 zeroext %a) nounwind {
 ; RV64I-LABEL: zext_sraiw_zext:
 ; RV64I:       # %bb.0: