From eb072b5a6a2c4b27236d6f4ecbe57012783ce626 Mon Sep 17 00:00:00 2001 From: Sjoerd Meijer Date: Thu, 30 May 2019 14:34:29 +0000 Subject: [PATCH] [ARM] Change the MC names for VMAXNM/VMINNM Now the NEON ones have a prefix "NEON_", and the VFP ones have a prefix "VFP_". This is so that the regex in ARMScheduleA57.td can be made to match both of _those_ classes of VMAXNM without also matching the MVE ones that are going to be introduced soon. NFCI. Patch by Simon Tatham. Differential Revision: https://reviews.llvm.org/D60700 llvm-svn: 362097 --- llvm/lib/Target/ARM/ARMInstrNEON.td | 64 +++++++++++++-------------- llvm/lib/Target/ARM/ARMInstrVFP.td | 4 +- llvm/lib/Target/ARM/ARMScheduleA57.td | 3 +- 3 files changed, 36 insertions(+), 35 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMInstrNEON.td b/llvm/lib/Target/ARM/ARMInstrNEON.td index 3aa44313a2783..effee0fcd387b 100644 --- a/llvm/lib/Target/ARM/ARMInstrNEON.td +++ b/llvm/lib/Target/ARM/ARMInstrNEON.td @@ -5537,22 +5537,22 @@ def VMAXhq : N3VQInt<0, 0, 0b01, 0b1111, 0, N3RegFrm, IIC_VBINQ, // VMAXNM let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in { - def VMAXNMNDf : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1, - N3RegFrm, NoItinerary, "vmaxnm", "f32", - v2f32, v2f32, fmaxnum, 1>, - Requires<[HasV8, HasNEON]>; - def VMAXNMNQf : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1, - N3RegFrm, NoItinerary, "vmaxnm", "f32", - v4f32, v4f32, fmaxnum, 1>, - Requires<[HasV8, HasNEON]>; - def VMAXNMNDh : N3VDIntnp<0b00110, 0b01, 0b1111, 0, 1, - N3RegFrm, NoItinerary, "vmaxnm", "f16", - v4f16, v4f16, fmaxnum, 1>, - Requires<[HasV8, HasNEON, HasFullFP16]>; - def VMAXNMNQh : N3VQIntnp<0b00110, 0b01, 0b1111, 1, 1, - N3RegFrm, NoItinerary, "vmaxnm", "f16", - v8f16, v8f16, fmaxnum, 1>, - Requires<[HasV8, HasNEON, HasFullFP16]>; + def NEON_VMAXNMNDf : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1, + N3RegFrm, NoItinerary, "vmaxnm", "f32", + v2f32, v2f32, fmaxnum, 1>, + Requires<[HasV8, HasNEON]>; + def NEON_VMAXNMNQf : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1, + N3RegFrm, NoItinerary, "vmaxnm", "f32", + v4f32, v4f32, fmaxnum, 1>, + Requires<[HasV8, HasNEON]>; + def NEON_VMAXNMNDh : N3VDIntnp<0b00110, 0b01, 0b1111, 0, 1, + N3RegFrm, NoItinerary, "vmaxnm", "f16", + v4f16, v4f16, fmaxnum, 1>, + Requires<[HasV8, HasNEON, HasFullFP16]>; + def NEON_VMAXNMNQh : N3VQIntnp<0b00110, 0b01, 0b1111, 1, 1, + N3RegFrm, NoItinerary, "vmaxnm", "f16", + v8f16, v8f16, fmaxnum, 1>, + Requires<[HasV8, HasNEON, HasFullFP16]>; } // VMIN : Vector Minimum @@ -5579,22 +5579,22 @@ def VMINhq : N3VQInt<0, 0, 0b11, 0b1111, 0, N3RegFrm, IIC_VBINQ, // VMINNM let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in { - def VMINNMNDf : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1, - N3RegFrm, NoItinerary, "vminnm", "f32", - v2f32, v2f32, fminnum, 1>, - Requires<[HasV8, HasNEON]>; - def VMINNMNQf : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1, - N3RegFrm, NoItinerary, "vminnm", "f32", - v4f32, v4f32, fminnum, 1>, - Requires<[HasV8, HasNEON]>; - def VMINNMNDh : N3VDIntnp<0b00110, 0b11, 0b1111, 0, 1, - N3RegFrm, NoItinerary, "vminnm", "f16", - v4f16, v4f16, fminnum, 1>, - Requires<[HasV8, HasNEON, HasFullFP16]>; - def VMINNMNQh : N3VQIntnp<0b00110, 0b11, 0b1111, 1, 1, - N3RegFrm, NoItinerary, "vminnm", "f16", - v8f16, v8f16, fminnum, 1>, - Requires<[HasV8, HasNEON, HasFullFP16]>; + def NEON_VMINNMNDf : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1, + N3RegFrm, NoItinerary, "vminnm", "f32", + v2f32, v2f32, fminnum, 1>, + Requires<[HasV8, HasNEON]>; + def NEON_VMINNMNQf : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1, + N3RegFrm, NoItinerary, "vminnm", "f32", + v4f32, v4f32, fminnum, 1>, + Requires<[HasV8, HasNEON]>; + def NEON_VMINNMNDh : N3VDIntnp<0b00110, 0b11, 0b1111, 0, 1, + N3RegFrm, NoItinerary, "vminnm", "f16", + v4f16, v4f16, fminnum, 1>, + Requires<[HasV8, HasNEON, HasFullFP16]>; + def NEON_VMINNMNQh : N3VQIntnp<0b00110, 0b11, 0b1111, 1, 1, + N3RegFrm, NoItinerary, "vminnm", "f16", + v8f16, v8f16, fminnum, 1>, + Requires<[HasV8, HasNEON, HasFullFP16]>; } // Vector Pairwise Operations. diff --git a/llvm/lib/Target/ARM/ARMInstrVFP.td b/llvm/lib/Target/ARM/ARMInstrVFP.td index 88405a83b4e28..6f042d39a4c4e 100644 --- a/llvm/lib/Target/ARM/ARMInstrVFP.td +++ b/llvm/lib/Target/ARM/ARMInstrVFP.td @@ -533,8 +533,8 @@ multiclass vmaxmin_inst { } } -defm VMAXNM : vmaxmin_inst<"vmaxnm", 0, fmaxnum>; -defm VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>; +defm VFP_VMAXNM : vmaxmin_inst<"vmaxnm", 0, fmaxnum>; +defm VFP_VMINNM : vmaxmin_inst<"vminnm", 1, fminnum>; // Match reassociated forms only if not sign dependent rounding. def : Pat<(fmul (fneg DPR:$a), (f64 DPR:$b)), diff --git a/llvm/lib/Target/ARM/ARMScheduleA57.td b/llvm/lib/Target/ARM/ARMScheduleA57.td index 6db6eda317abf..de970ae2e17de 100644 --- a/llvm/lib/Target/ARM/ARMScheduleA57.td +++ b/llvm/lib/Target/ARM/ARMScheduleA57.td @@ -1174,7 +1174,8 @@ def : InstRW<[A57Write_8cyc_1V], (instregex // ASIMD FP max/min def : InstRW<[A57Write_5cyc_1V], (instregex - "(VMAX|VMIN)(fd|fq|hd|hq)", "(VPMAX|VPMIN)(f|h)", "VMAXNM", "VMINNM")>; + "(VMAX|VMIN)(fd|fq|hd|hq)", "(VPMAX|VPMIN)(f|h)", "(NEON|VFP)_VMAXNM", + "(NEON|VFP)_VMINNM")>; // ASIMD FP multiply def A57WriteVMUL_VecFP : SchedWriteRes<[A57UnitV]> { let Latency = 5; }