diff --git a/llvm/test/CodeGen/RISCV/setcc-logic.ll b/llvm/test/CodeGen/RISCV/setcc-logic.ll
index 2107c17d1ec070..c6316609df2cfe 100644
--- a/llvm/test/CodeGen/RISCV/setcc-logic.ll
+++ b/llvm/test/CodeGen/RISCV/setcc-logic.ll
@@ -118,3 +118,195 @@ define i1 @and_icmps_const_not1bit_diff(i32 %x) nounwind {
   %r = and i1 %a, %b
   ret i1 %r
 }
+
+define i1 @and_icmp_sge(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
+; RV32I-LABEL: and_icmp_sge:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slt a0, a0, a1
+; RV32I-NEXT:    not a0, a0
+; RV32I-NEXT:    slt a1, a2, a3
+; RV32I-NEXT:    xori a1, a1, 1
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: and_icmp_sge:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slt a0, a0, a1
+; RV64I-NEXT:    not a0, a0
+; RV64I-NEXT:    slt a1, a2, a3
+; RV64I-NEXT:    xori a1, a1, 1
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+  %cmp1 = icmp sge i32 %a, %b
+  %cmp2 = icmp sge i32 %c, %d
+  %and = and i1 %cmp1, %cmp2
+  ret i1 %and
+}
+
+define i1 @and_icmp_sle(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
+; RV32I-LABEL: and_icmp_sle:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    not a0, a0
+; RV32I-NEXT:    slt a1, a3, a2
+; RV32I-NEXT:    xori a1, a1, 1
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: and_icmp_sle:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slt a0, a1, a0
+; RV64I-NEXT:    not a0, a0
+; RV64I-NEXT:    slt a1, a3, a2
+; RV64I-NEXT:    xori a1, a1, 1
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+  %cmp1 = icmp sle i32 %a, %b
+  %cmp2 = icmp sle i32 %c, %d
+  %and = and i1 %cmp1, %cmp2
+  ret i1 %and
+}
+
+define i1 @and_icmp_uge(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
+; RV32I-LABEL: and_icmp_uge:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    sltu a0, a0, a1
+; RV32I-NEXT:    not a0, a0
+; RV32I-NEXT:    sltu a1, a2, a3
+; RV32I-NEXT:    xori a1, a1, 1
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: and_icmp_uge:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sltu a0, a0, a1
+; RV64I-NEXT:    not a0, a0
+; RV64I-NEXT:    sltu a1, a2, a3
+; RV64I-NEXT:    xori a1, a1, 1
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+  %cmp1 = icmp uge i32 %a, %b
+  %cmp2 = icmp uge i32 %c, %d
+  %and = and i1 %cmp1, %cmp2
+  ret i1 %and
+}
+
+define i1 @and_icmp_ule(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
+; RV32I-LABEL: and_icmp_ule:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    sltu a0, a1, a0
+; RV32I-NEXT:    not a0, a0
+; RV32I-NEXT:    sltu a1, a3, a2
+; RV32I-NEXT:    xori a1, a1, 1
+; RV32I-NEXT:    and a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: and_icmp_ule:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sltu a0, a1, a0
+; RV64I-NEXT:    not a0, a0
+; RV64I-NEXT:    sltu a1, a3, a2
+; RV64I-NEXT:    xori a1, a1, 1
+; RV64I-NEXT:    and a0, a0, a1
+; RV64I-NEXT:    ret
+  %cmp1 = icmp ule i32 %a, %b
+  %cmp2 = icmp ule i32 %c, %d
+  %and = and i1 %cmp1, %cmp2
+  ret i1 %and
+}
+
+define i1 @or_icmp_sge(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
+; RV32I-LABEL: or_icmp_sge:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slt a0, a0, a1
+; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    slt a1, a2, a3
+; RV32I-NEXT:    xori a1, a1, 1
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: or_icmp_sge:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slt a0, a0, a1
+; RV64I-NEXT:    xori a0, a0, 1
+; RV64I-NEXT:    slt a1, a2, a3
+; RV64I-NEXT:    xori a1, a1, 1
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    ret
+  %cmp1 = icmp sge i32 %a, %b
+  %cmp2 = icmp sge i32 %c, %d
+  %and = or i1 %cmp1, %cmp2
+  ret i1 %and
+}
+
+define i1 @or_icmp_sle(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
+; RV32I-LABEL: or_icmp_sle:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    slt a0, a1, a0
+; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    slt a1, a3, a2
+; RV32I-NEXT:    xori a1, a1, 1
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: or_icmp_sle:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    slt a0, a1, a0
+; RV64I-NEXT:    xori a0, a0, 1
+; RV64I-NEXT:    slt a1, a3, a2
+; RV64I-NEXT:    xori a1, a1, 1
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    ret
+  %cmp1 = icmp sle i32 %a, %b
+  %cmp2 = icmp sle i32 %c, %d
+  %and = or i1 %cmp1, %cmp2
+  ret i1 %and
+}
+
+define i1 @or_icmp_uge(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
+; RV32I-LABEL: or_icmp_uge:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    sltu a0, a0, a1
+; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    sltu a1, a2, a3
+; RV32I-NEXT:    xori a1, a1, 1
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: or_icmp_uge:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sltu a0, a0, a1
+; RV64I-NEXT:    xori a0, a0, 1
+; RV64I-NEXT:    sltu a1, a2, a3
+; RV64I-NEXT:    xori a1, a1, 1
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    ret
+  %cmp1 = icmp uge i32 %a, %b
+  %cmp2 = icmp uge i32 %c, %d
+  %and = or i1 %cmp1, %cmp2
+  ret i1 %and
+}
+
+define i1 @or_icmp_ule(i32 signext %a, i32 signext %b, i32 signext %c, i32 signext %d) nounwind {
+; RV32I-LABEL: or_icmp_ule:
+; RV32I:       # %bb.0:
+; RV32I-NEXT:    sltu a0, a1, a0
+; RV32I-NEXT:    xori a0, a0, 1
+; RV32I-NEXT:    sltu a1, a3, a2
+; RV32I-NEXT:    xori a1, a1, 1
+; RV32I-NEXT:    or a0, a0, a1
+; RV32I-NEXT:    ret
+;
+; RV64I-LABEL: or_icmp_ule:
+; RV64I:       # %bb.0:
+; RV64I-NEXT:    sltu a0, a1, a0
+; RV64I-NEXT:    xori a0, a0, 1
+; RV64I-NEXT:    sltu a1, a3, a2
+; RV64I-NEXT:    xori a1, a1, 1
+; RV64I-NEXT:    or a0, a0, a1
+; RV64I-NEXT:    ret
+  %cmp1 = icmp ule i32 %a, %b
+  %cmp2 = icmp ule i32 %c, %d
+  %and = or i1 %cmp1, %cmp2
+  ret i1 %and
+}