diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h index c5b955f93af63..4bf4bede01328 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h +++ b/lldb/source/Plugins/Process/Utility/RegisterInfoPOSIX_riscv64.h @@ -35,6 +35,11 @@ class RegisterInfoPOSIX_riscv64 uint32_t fcsr; }; + struct VPR { + // The size should be VLEN*32 in bits, but we don't have VLEN here. + void *vpr; + }; + RegisterInfoPOSIX_riscv64(const lldb_private::ArchSpec &target_arch, lldb_private::Flags flags); diff --git a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h b/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h index 42c73abc4a1ae..8ea2046279256 100644 --- a/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h +++ b/lldb/source/Plugins/Process/Utility/RegisterInfos_riscv64.h @@ -42,6 +42,9 @@ using namespace riscv_dwarf; // FPR register kinds array for vector registers #define FPR64_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind) +// VPR register kinds array for vector registers +#define VPR_KIND(reg, generic_kind) KIND_HELPER(reg, generic_kind) + // Defines a 64-bit general purpose register #define DEFINE_GPR64(reg, generic_kind) DEFINE_GPR64_ALT(reg, reg, generic_kind) @@ -64,6 +67,16 @@ using namespace riscv_dwarf; FPR64_KIND(fpr_##reg, generic_kind), nullptr, nullptr, nullptr, \ } +#define DEFINE_VPR(reg, generic_kind) DEFINE_VPR_ALT(reg, reg, generic_kind) + +// Defines a scalable vector register, with default size 128 bits +// The byte offset 0 is a placeholder, which should be corrected at runtime. +#define DEFINE_VPR_ALT(reg, alt, generic_kind) \ + { \ + #reg, #alt, 16, 0, lldb::eEncodingVector, lldb::eFormatVectorOfUInt8, \ + VPR_KIND(vpr_##reg, generic_kind), nullptr, nullptr \ + } + // clang-format on static lldb_private::RegisterInfo g_register_infos_riscv64_le[] = { @@ -135,6 +148,39 @@ static lldb_private::RegisterInfo g_register_infos_riscv64_le[] = { DEFINE_FPR64_ALT(ft10, f30, LLDB_INVALID_REGNUM), DEFINE_FPR64_ALT(ft11, f31, LLDB_INVALID_REGNUM), DEFINE_FPR_ALT(fcsr, nullptr, 4, LLDB_INVALID_REGNUM), + + DEFINE_VPR(v0, LLDB_INVALID_REGNUM), + DEFINE_VPR(v1, LLDB_INVALID_REGNUM), + DEFINE_VPR(v2, LLDB_INVALID_REGNUM), + DEFINE_VPR(v3, LLDB_INVALID_REGNUM), + DEFINE_VPR(v4, LLDB_INVALID_REGNUM), + DEFINE_VPR(v5, LLDB_INVALID_REGNUM), + DEFINE_VPR(v6, LLDB_INVALID_REGNUM), + DEFINE_VPR(v7, LLDB_INVALID_REGNUM), + DEFINE_VPR(v8, LLDB_INVALID_REGNUM), + DEFINE_VPR(v9, LLDB_INVALID_REGNUM), + DEFINE_VPR(v10, LLDB_INVALID_REGNUM), + DEFINE_VPR(v11, LLDB_INVALID_REGNUM), + DEFINE_VPR(v12, LLDB_INVALID_REGNUM), + DEFINE_VPR(v13, LLDB_INVALID_REGNUM), + DEFINE_VPR(v14, LLDB_INVALID_REGNUM), + DEFINE_VPR(v15, LLDB_INVALID_REGNUM), + DEFINE_VPR(v16, LLDB_INVALID_REGNUM), + DEFINE_VPR(v17, LLDB_INVALID_REGNUM), + DEFINE_VPR(v18, LLDB_INVALID_REGNUM), + DEFINE_VPR(v19, LLDB_INVALID_REGNUM), + DEFINE_VPR(v20, LLDB_INVALID_REGNUM), + DEFINE_VPR(v21, LLDB_INVALID_REGNUM), + DEFINE_VPR(v22, LLDB_INVALID_REGNUM), + DEFINE_VPR(v23, LLDB_INVALID_REGNUM), + DEFINE_VPR(v24, LLDB_INVALID_REGNUM), + DEFINE_VPR(v25, LLDB_INVALID_REGNUM), + DEFINE_VPR(v26, LLDB_INVALID_REGNUM), + DEFINE_VPR(v27, LLDB_INVALID_REGNUM), + DEFINE_VPR(v28, LLDB_INVALID_REGNUM), + DEFINE_VPR(v29, LLDB_INVALID_REGNUM), + DEFINE_VPR(v30, LLDB_INVALID_REGNUM), + DEFINE_VPR(v31, LLDB_INVALID_REGNUM), }; #endif // DECLARE_REGISTER_INFOS_RISCV64_STRUCT