diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir
index 3f73252f830baf..3600ba6efb5f33 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-smed3.mir
@@ -148,3 +148,39 @@ body: |
     %6:vgpr(s32) = G_SMIN %3, %5
     S_ENDPGM 0, implicit %6, implicit %5
 ...
+
+---
+name: smed3_s32_vvv_reuse_bounds
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+
+    ; GFX6-LABEL: name: smed3_s32_vvv_reuse_bounds
+    ; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+    ; GFX6-NEXT: {{  $}}
+    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+    ; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+    ; GFX6-NEXT: [[V_MAX_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[COPY]], [[COPY1]], implicit $exec
+    ; GFX6-NEXT: [[V_MIN_I32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[COPY]], [[COPY1]], implicit $exec
+    ; GFX6-NEXT: [[V_MIN_I32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[COPY2]], [[V_MAX_I32_e64_]], implicit $exec
+    ; GFX6-NEXT: [[V_MAX_I32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[V_MIN_I32_e64_1]], [[V_MIN_I32_e64_]], implicit $exec
+    ; GFX6-NEXT: [[V_MIN_I32_e64_2:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[COPY3]], [[V_MAX_I32_e64_]], implicit $exec
+    ; GFX6-NEXT: [[V_MAX_I32_e64_2:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[V_MIN_I32_e64_2]], [[V_MIN_I32_e64_]], implicit $exec
+    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_MAX_I32_e64_1]], implicit [[V_MAX_I32_e64_2]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vgpr(s32) = COPY $vgpr2
+    %3:vgpr(s32) = COPY $vgpr3
+    %4:vgpr(s32) = G_SMAX %0, %1
+    %5:vgpr(s32) = G_SMIN %0, %1
+    %6:vgpr(s32) = G_SMIN %2, %4
+    %7:vgpr(s32) = G_SMAX %6, %5
+    %8:vgpr(s32) = G_SMIN %3, %4
+    %9:vgpr(s32) = G_SMAX %8, %5
+    S_ENDPGM 0, implicit %7, implicit %9
+...
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir
index 56069c2b73beed..89b615a2e643aa 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-umed3.mir
@@ -148,3 +148,39 @@ body: |
     %6:vgpr(s32) = G_UMIN %3, %5
     S_ENDPGM 0, implicit %6, implicit %5
 ...
+
+---
+name: smed3_s32_vvv_reuse_bounds
+legalized: true
+regBankSelected: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+
+    ; GFX6-LABEL: name: smed3_s32_vvv_reuse_bounds
+    ; GFX6: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3
+    ; GFX6-NEXT: {{  $}}
+    ; GFX6-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GFX6-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
+    ; GFX6-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
+    ; GFX6-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
+    ; GFX6-NEXT: [[V_MAX_U32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[COPY]], [[COPY1]], implicit $exec
+    ; GFX6-NEXT: [[V_MIN_U32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[COPY]], [[COPY1]], implicit $exec
+    ; GFX6-NEXT: [[V_MIN_U32_e64_1:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[COPY2]], [[V_MAX_U32_e64_]], implicit $exec
+    ; GFX6-NEXT: [[V_MAX_U32_e64_1:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[V_MIN_U32_e64_1]], [[V_MIN_U32_e64_]], implicit $exec
+    ; GFX6-NEXT: [[V_MIN_U32_e64_2:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[COPY3]], [[V_MAX_U32_e64_]], implicit $exec
+    ; GFX6-NEXT: [[V_MAX_U32_e64_2:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[V_MIN_U32_e64_2]], [[V_MIN_U32_e64_]], implicit $exec
+    ; GFX6-NEXT: S_ENDPGM 0, implicit [[V_MAX_U32_e64_1]], implicit [[V_MAX_U32_e64_2]]
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s32) = COPY $vgpr1
+    %2:vgpr(s32) = COPY $vgpr2
+    %3:vgpr(s32) = COPY $vgpr3
+    %4:vgpr(s32) = G_UMAX %0, %1
+    %5:vgpr(s32) = G_UMIN %0, %1
+    %6:vgpr(s32) = G_UMIN %2, %4
+    %7:vgpr(s32) = G_UMAX %6, %5
+    %8:vgpr(s32) = G_UMIN %3, %4
+    %9:vgpr(s32) = G_UMAX %8, %5
+    S_ENDPGM 0, implicit %7, implicit %9
+...