diff --git a/llvm/include/llvm/IR/IntrinsicsPowerPC.td b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
index cfd3b0b7566daa4..f7c5b1638cdc8af 100644
--- a/llvm/include/llvm/IR/IntrinsicsPowerPC.td
+++ b/llvm/include/llvm/IR/IntrinsicsPowerPC.td
@@ -28,6 +28,10 @@ let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
     [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
   def int_ppc_dcbtst: Intrinsic<[], [llvm_ptr_ty],
     [IntrArgMemOnly, NoCapture<ArgIndex<0>>]>;
+  def int_ppc_dcbt_with_hint: Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
+    [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
+  def int_ppc_dcbtst_with_hint: Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty],
+    [IntrArgMemOnly, NoCapture<ArgIndex<0>>, ImmArg<ArgIndex<1>>]>;
   def int_ppc_dcbz  : Intrinsic<[], [llvm_ptr_ty], []>;
   def int_ppc_dcbzl : Intrinsic<[], [llvm_ptr_ty], []>;
 
@@ -36,6 +40,8 @@ let TargetPrefix = "ppc" in {  // All intrinsics start with "llvm.ppc.".
 
   // sync instruction (i.e. sync 0, a.k.a hwsync)
   def int_ppc_sync : Intrinsic<[], [], []>;
+  // isync instruction
+  def int_ppc_isync : Intrinsic<[], [], []>;
   // lwsync is sync 1
   def int_ppc_lwsync : Intrinsic<[], [], []>;
   // eieio instruction
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 3eceb3c511d3758..edf1730af71ffac 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1835,6 +1835,11 @@ def : Pat<(prefetch xoaddr:$dst, (i32 1), imm, (i32 1)),
 def : Pat<(prefetch xoaddr:$dst, (i32 0), imm, (i32 0)),
           (ICBT 0, xoaddr:$dst)>, Requires<[HasICBT]>; // inst prefetch (for read)
 
+def : Pat<(int_ppc_dcbt_with_hint xoaddr:$dst, i32:$TH),
+          (DCBT i32:$TH, xoaddr:$dst)>;
+def : Pat<(int_ppc_dcbtst_with_hint xoaddr:$dst, i32:$TH),
+          (DCBTST i32:$TH, xoaddr:$dst)>;
+
 // Atomic operations
 // FIXME: some of these might be used with constant operands. This will result
 // in constant materialization instructions that may be redundant. We currently
@@ -4506,6 +4511,7 @@ def DCBFx  : PPCAsmPseudo<"dcbf $dst", (ins memrr:$dst)>;
 def DCBFL  : PPCAsmPseudo<"dcbfl $dst", (ins memrr:$dst)>;
 def DCBFLP : PPCAsmPseudo<"dcbflp $dst", (ins memrr:$dst)>;
 
+def : Pat<(int_ppc_isync),  (ISYNC)>;
 def : Pat<(int_ppc_dcbfl xoaddr:$dst),
           (DCBF 1, xoaddr:$dst)>;
 def : Pat<(int_ppc_dcbflp xoaddr:$dst),
diff --git a/llvm/test/CodeGen/PowerPC/dcbt.ll b/llvm/test/CodeGen/PowerPC/dcbt.ll
new file mode 100644
index 000000000000000..2559a2cf2f07036
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/dcbt.ll
@@ -0,0 +1,67 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:     -verify-machineinstrs -ppc-asm-full-reg-names \
+; RUN:     -ppc-vsr-nums-as-vr | FileCheck %s
+
+define void @dcbt_with_hint_test1(i8* %a) {
+; CHECK-LABEL: dcbt_with_hint_test1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    dcbt 0, r3
+; CHECK-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.dcbt.with.hint(i8* %a, i32 0)
+  ret void
+}
+
+define void @dcbt_with_hint_test2(i8* %a) {
+; CHECK-LABEL: dcbt_with_hint_test2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    dcbt 0, r3, 8
+; CHECK-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.dcbt.with.hint(i8* %a, i32 8)
+  ret void
+}
+
+define void @dcbt_with_hint_test3(i8* %a) {
+; CHECK-LABEL: dcbt_with_hint_test3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    dcbt 0, r3, 15
+; CHECK-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.dcbt.with.hint(i8* %a, i32 15)
+  ret void
+}
+
+define void @dcbtst_with_hint_test1(i8* %a) {
+; CHECK-LABEL: dcbtst_with_hint_test1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    dcbtst 0, r3
+; CHECK-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.dcbtst.with.hint(i8* %a, i32 0)
+  ret void
+}
+
+define void @dcbtst_with_hint_test2(i8* %a) {
+; CHECK-LABEL: dcbtst_with_hint_test2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    dcbtst 0, r3, 8
+; CHECK-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.dcbtst.with.hint(i8* %a, i32 8)
+  ret void
+}
+
+define void @dcbtst_with_hint_test3(i8* %a) {
+; CHECK-LABEL: dcbtst_with_hint_test3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    dcbtst 0, r3, 15
+; CHECK-NEXT:    blr
+entry:
+  tail call void @llvm.ppc.dcbtst.with.hint(i8* %a, i32 15)
+  ret void
+}
+
+declare void @llvm.ppc.dcbt.with.hint(i8*, i32)
+declare void @llvm.ppc.dcbtst.with.hint(i8*, i32)
diff --git a/llvm/test/CodeGen/PowerPC/isync.ll b/llvm/test/CodeGen/PowerPC/isync.ll
new file mode 100644
index 000000000000000..77677434744d5cc
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/isync.ll
@@ -0,0 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu < %s \
+; RUN:     -verify-machineinstrs -ppc-asm-full-reg-names \
+; RUN:     -ppc-vsr-nums-as-vr | FileCheck %s
+
+define void @isync_test() {
+; CHECK-LABEL: isync_test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    isync
+; CHECK-NEXT:    blr
+
+entry:
+  tail call void @llvm.ppc.isync()
+  ret void
+}
+
+declare void @llvm.ppc.isync()