938 changes: 632 additions & 306 deletions llvm/test/CodeGen/AArch64/insertextract.ll
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9 changes: 3 additions & 6 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/combine-extract-vector-load.mir
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Expand Up @@ -28,16 +28,13 @@ tracksRegLiveness: true
body: |
bb.0:
; CHECK-LABEL: name: test_ptradd_crash__offset_wider
; CHECK: [[C:%[0-9]+]]:_(s128) = G_CONSTANT i128 3
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[C]](s128)
; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK-NEXT: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[TRUNC]], [[C1]](s64)
; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[SHL]](s64)
; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 12
; CHECK-NEXT: [[INTTOPTR:%[0-9]+]]:_(p1) = G_INTTOPTR [[C]](s64)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[INTTOPTR]](p1) :: (load (s32), addrspace 1)
; CHECK-NEXT: $sgpr0 = COPY [[LOAD]](s32)
; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $sgpr0
%1:_(p1) = G_CONSTANT i64 0
%3:_(s128) = G_CONSTANT i128 3
%3:_(s32) = G_CONSTANT i32 3
%0:_(<4 x s32>) = G_LOAD %1 :: (load (<4 x s32>) from `ptr addrspace(1) null`, addrspace 1)
%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %3
$sgpr0 = COPY %2
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4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/irtranslator-non-integral-address-spaces-vectors.ll
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Expand Up @@ -48,10 +48,10 @@ define <2 x ptr addrspace(7)> @gep_vector_splat(<2 x ptr addrspace(7)> %ptrs, i6
; CHECK-NEXT: [[COPY11:%[0-9]+]]:_(s32) = COPY $vgpr11
; CHECK-NEXT: [[MV2:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY10]](s32), [[COPY11]](s32)
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<2 x p8>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[DEF2:%[0-9]+]]:_(<2 x s32>) = G_IMPLICIT_DEF
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV2]](s64), [[C]](s64)
; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[DEF]], [[MV2]](s64), [[C]](s32)
; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s64>) = G_SHUFFLE_VECTOR [[IVEC]](<2 x s64>), [[DEF]], shufflemask(0, 0)
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s32>) = G_TRUNC [[SHUF]](<2 x s64>)
; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<2 x s32>) = G_ADD [[BUILD_VECTOR1]], [[TRUNC]]
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6 changes: 4 additions & 2 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extract-vector-elt.mir
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Expand Up @@ -294,7 +294,8 @@ body: |
; CHECK-NEXT: $vgpr0 = COPY [[COPY]](s32)
%0:_(<2 x s1>) = G_IMPLICIT_DEF
%1:_(s1) = G_CONSTANT i1 false
%2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %1
%4:_(s32) = G_ZEXT %1
%2:_(s1) = G_EXTRACT_VECTOR_ELT %0, %4
%3:_(s32) = G_ANYEXT %2
$vgpr0 = COPY %3
...
Expand Down Expand Up @@ -948,7 +949,8 @@ body: |
; CHECK-NEXT: $vgpr0 = COPY [[EVEC]](s32)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(s64) = COPY $vgpr2_vgpr3
%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %1
%3:_(s32) = G_TRUNC %1
%2:_(s32) = G_EXTRACT_VECTOR_ELT %0, %3
$vgpr0 = COPY %2
...
---
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5 changes: 3 additions & 2 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-extractelement-crash.mir
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Expand Up @@ -18,8 +18,9 @@ body: |
%7:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %6(s32), %5(s32)
%8:_(s1) = G_CONSTANT i1 1
%9:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %8(s1)
%10:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %9(s32), %8(s1)
%11:_(s32) = G_ZEXT %8
%9:_(s32) = G_EXTRACT_VECTOR_ELT %0(<2 x s32>), %11(s32)
%10:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0(<2 x s32>), %9(s32), %11(s32)
SI_RETURN
...
28 changes: 4 additions & 24 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-insert-vector-elt.mir
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Expand Up @@ -82,7 +82,8 @@ body: |
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s64) = COPY $vgpr3_vgpr4
%3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
%4:_(s32) = G_TRUNC %2
%3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
$vgpr0_vgpr1 = COPY %3
...

Expand All @@ -105,7 +106,8 @@ body: |
%0:_(<16 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
%1:_(s32) = COPY $vgpr16
%2:_(s64) = COPY $vgpr17_vgpr18
%3:_(<16 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
%4:_(s32) = G_TRUNC %2
%3:_(<16 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %4
S_ENDPGM 0, implicit %3
...

Expand All @@ -131,28 +133,6 @@ body: |
S_ENDPGM 0, implicit %3
...

---
name: insert_vector_elt_0_v2s32_s8

body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2
; CHECK-LABEL: name: insert_vector_elt_0_v2s32_s8
; CHECK: liveins: $vgpr0_vgpr1, $vgpr2
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr2
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>)
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY1]](s32), [[UV1]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>)
%0:_(<2 x s32>) = COPY $vgpr0_vgpr1
%1:_(s32) = COPY $vgpr2
%2:_(s8) = G_CONSTANT i8 0
%3:_(<2 x s32>) = G_INSERT_VECTOR_ELT %0, %1, %2
$vgpr0_vgpr1 = COPY %3
...

---
name: insert_vector_elt_0_v2i8_i32

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305 changes: 155 additions & 150 deletions llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/insertelement.ll
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300 changes: 150 additions & 150 deletions llvm/test/CodeGen/RISCV/GlobalISel/irtranslator/shufflevector.ll
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