90 changes: 46 additions & 44 deletions llvm/test/CodeGen/RISCV/rvv/vmsbf-rv32.ll → llvm/test/CodeGen/RISCV/rvv/vmsbf.ll
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Original file line number Diff line number Diff line change
@@ -1,11 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs \
; RUN: < %s | FileCheck %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v \
; RUN: -verify-machineinstrs | FileCheck %s
declare <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
<vscale x 1 x i1>,
i32);
iXLen);

define <vscale x 1 x i1> @intrinsic_vmsbf_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1) nounwind {
define <vscale x 1 x i1> @intrinsic_vmsbf_m_nxv1i1(<vscale x 1 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu
Expand All @@ -15,17 +17,17 @@ define <vscale x 1 x i1> @intrinsic_vmsbf_m_nxv1i1(<vscale x 1 x i1> %0, i32 %1)
entry:
%a = call <vscale x 1 x i1> @llvm.riscv.vmsbf.nxv1i1(
<vscale x 1 x i1> %0,
i32 %1)
iXLen %1)
ret <vscale x 1 x i1> %a
}

declare <vscale x 1 x i1> @llvm.riscv.vmsbf.mask.nxv1i1(
<vscale x 1 x i1>,
<vscale x 1 x i1>,
<vscale x 1 x i1>,
i32);
iXLen);

define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
define <vscale x 1 x i1> @intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1(<vscale x 1 x i1> %0, <vscale x 1 x i1> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv1i1_nxv1i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
Expand All @@ -39,15 +41,15 @@ entry:
<vscale x 1 x i1> %0,
<vscale x 1 x i1> %1,
<vscale x 1 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 1 x i1> %a
}

declare <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
<vscale x 2 x i1>,
i32);
iXLen);

define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1) nounwind {
define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu
Expand All @@ -57,17 +59,17 @@ define <vscale x 2 x i1> @intrinsic_vmsbf_m_nxv2i1(<vscale x 2 x i1> %0, i32 %1)
entry:
%a = call <vscale x 2 x i1> @llvm.riscv.vmsbf.nxv2i1(
<vscale x 2 x i1> %0,
i32 %1)
iXLen %1)
ret <vscale x 2 x i1> %a
}

declare <vscale x 2 x i1> @llvm.riscv.vmsbf.mask.nxv2i1(
<vscale x 2 x i1>,
<vscale x 2 x i1>,
<vscale x 2 x i1>,
i32);
iXLen);

define <vscale x 2 x i1> @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
define <vscale x 2 x i1> @intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1(<vscale x 2 x i1> %0, <vscale x 2 x i1> %1, <vscale x 2 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv2i1_nxv2i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
Expand All @@ -81,15 +83,15 @@ entry:
<vscale x 2 x i1> %0,
<vscale x 2 x i1> %1,
<vscale x 2 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 2 x i1> %a
}

declare <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
<vscale x 4 x i1>,
i32);
iXLen);

define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1) nounwind {
define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu
Expand All @@ -99,17 +101,17 @@ define <vscale x 4 x i1> @intrinsic_vmsbf_m_nxv4i1(<vscale x 4 x i1> %0, i32 %1)
entry:
%a = call <vscale x 4 x i1> @llvm.riscv.vmsbf.nxv4i1(
<vscale x 4 x i1> %0,
i32 %1)
iXLen %1)
ret <vscale x 4 x i1> %a
}

declare <vscale x 4 x i1> @llvm.riscv.vmsbf.mask.nxv4i1(
<vscale x 4 x i1>,
<vscale x 4 x i1>,
<vscale x 4 x i1>,
i32);
iXLen);

define <vscale x 4 x i1> @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
define <vscale x 4 x i1> @intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1(<vscale x 4 x i1> %0, <vscale x 4 x i1> %1, <vscale x 4 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv4i1_nxv4i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
Expand All @@ -123,15 +125,15 @@ entry:
<vscale x 4 x i1> %0,
<vscale x 4 x i1> %1,
<vscale x 4 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 4 x i1> %a
}

declare <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
<vscale x 8 x i1>,
i32);
iXLen);

define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1) nounwind {
define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu
Expand All @@ -141,17 +143,17 @@ define <vscale x 8 x i1> @intrinsic_vmsbf_m_nxv8i1(<vscale x 8 x i1> %0, i32 %1)
entry:
%a = call <vscale x 8 x i1> @llvm.riscv.vmsbf.nxv8i1(
<vscale x 8 x i1> %0,
i32 %1)
iXLen %1)
ret <vscale x 8 x i1> %a
}

declare <vscale x 8 x i1> @llvm.riscv.vmsbf.mask.nxv8i1(
<vscale x 8 x i1>,
<vscale x 8 x i1>,
<vscale x 8 x i1>,
i32);
iXLen);

define <vscale x 8 x i1> @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
define <vscale x 8 x i1> @intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1(<vscale x 8 x i1> %0, <vscale x 8 x i1> %1, <vscale x 8 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv8i1_nxv8i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
Expand All @@ -165,15 +167,15 @@ entry:
<vscale x 8 x i1> %0,
<vscale x 8 x i1> %1,
<vscale x 8 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 8 x i1> %a
}

declare <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
<vscale x 16 x i1>,
i32);
iXLen);

define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, i32 %1) nounwind {
define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu
Expand All @@ -183,17 +185,17 @@ define <vscale x 16 x i1> @intrinsic_vmsbf_m_nxv16i1(<vscale x 16 x i1> %0, i32
entry:
%a = call <vscale x 16 x i1> @llvm.riscv.vmsbf.nxv16i1(
<vscale x 16 x i1> %0,
i32 %1)
iXLen %1)
ret <vscale x 16 x i1> %a
}

declare <vscale x 16 x i1> @llvm.riscv.vmsbf.mask.nxv16i1(
<vscale x 16 x i1>,
<vscale x 16 x i1>,
<vscale x 16 x i1>,
i32);
iXLen);

define <vscale x 16 x i1> @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
define <vscale x 16 x i1> @intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1(<vscale x 16 x i1> %0, <vscale x 16 x i1> %1, <vscale x 16 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv16i1_nxv16i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
Expand All @@ -207,15 +209,15 @@ entry:
<vscale x 16 x i1> %0,
<vscale x 16 x i1> %1,
<vscale x 16 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 16 x i1> %a
}

declare <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
<vscale x 32 x i1>,
i32);
iXLen);

define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, i32 %1) nounwind {
define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu
Expand All @@ -225,17 +227,17 @@ define <vscale x 32 x i1> @intrinsic_vmsbf_m_nxv32i1(<vscale x 32 x i1> %0, i32
entry:
%a = call <vscale x 32 x i1> @llvm.riscv.vmsbf.nxv32i1(
<vscale x 32 x i1> %0,
i32 %1)
iXLen %1)
ret <vscale x 32 x i1> %a
}

declare <vscale x 32 x i1> @llvm.riscv.vmsbf.mask.nxv32i1(
<vscale x 32 x i1>,
<vscale x 32 x i1>,
<vscale x 32 x i1>,
i32);
iXLen);

define <vscale x 32 x i1> @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
define <vscale x 32 x i1> @intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1(<vscale x 32 x i1> %0, <vscale x 32 x i1> %1, <vscale x 32 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv32i1_nxv32i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
Expand All @@ -249,15 +251,15 @@ entry:
<vscale x 32 x i1> %0,
<vscale x 32 x i1> %1,
<vscale x 32 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 32 x i1> %a
}

declare <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
<vscale x 64 x i1>,
i32);
iXLen);

define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, i32 %1) nounwind {
define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, iXLen %1) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_m_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, mu
Expand All @@ -267,17 +269,17 @@ define <vscale x 64 x i1> @intrinsic_vmsbf_m_nxv64i1(<vscale x 64 x i1> %0, i32
entry:
%a = call <vscale x 64 x i1> @llvm.riscv.vmsbf.nxv64i1(
<vscale x 64 x i1> %0,
i32 %1)
iXLen %1)
ret <vscale x 64 x i1> %a
}

declare <vscale x 64 x i1> @llvm.riscv.vmsbf.mask.nxv64i1(
<vscale x 64 x i1>,
<vscale x 64 x i1>,
<vscale x 64 x i1>,
i32);
iXLen);

define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, i32 %3) nounwind {
define <vscale x 64 x i1> @intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1(<vscale x 64 x i1> %0, <vscale x 64 x i1> %1, <vscale x 64 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vmsbf_mask_m_nxv64i1_nxv64i1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v10, v0
Expand All @@ -291,6 +293,6 @@ entry:
<vscale x 64 x i1> %0,
<vscale x 64 x i1> %1,
<vscale x 64 x i1> %2,
i32 %3)
iXLen %3)
ret <vscale x 64 x i1> %a
}
2,074 changes: 0 additions & 2,074 deletions llvm/test/CodeGen/RISCV/rvv/vmul-rv64.ll
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818 changes: 412 additions & 406 deletions llvm/test/CodeGen/RISCV/rvv/vmul-rv32.ll → llvm/test/CodeGen/RISCV/rvv/vmul.ll
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2,074 changes: 0 additions & 2,074 deletions llvm/test/CodeGen/RISCV/rvv/vmulh-rv64.ll
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818 changes: 412 additions & 406 deletions llvm/test/CodeGen/RISCV/rvv/vmulh-rv32.ll → llvm/test/CodeGen/RISCV/rvv/vmulh.ll
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2,122 changes: 0 additions & 2,122 deletions llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv32.ll
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770 changes: 412 additions & 358 deletions llvm/test/CodeGen/RISCV/rvv/vmulhsu-rv64.ll → llvm/test/CodeGen/RISCV/rvv/vmulhsu.ll
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2,122 changes: 0 additions & 2,122 deletions llvm/test/CodeGen/RISCV/rvv/vmulhu-rv32.ll
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770 changes: 412 additions & 358 deletions llvm/test/CodeGen/RISCV/rvv/vmulhu-rv64.ll → llvm/test/CodeGen/RISCV/rvv/vmulhu.ll
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1,762 changes: 0 additions & 1,762 deletions llvm/test/CodeGen/RISCV/rvv/vrsub-rv64.ll
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708 changes: 368 additions & 340 deletions llvm/test/CodeGen/RISCV/rvv/vrsub-rv32.ll → llvm/test/CodeGen/RISCV/rvv/vrsub.ll
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