324 changes: 197 additions & 127 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -528,6 +528,14 @@ class RISCVVPseudo {
// SEW = 0 is used to denote that the Pseudo is not SEW specific (or unknown).
bits<8> SEW = 0;
bit NeedBeInPseudoTable = 1;
// TargetOverlapConstraintType indicates that these instructions can
// overlap between source operands and destination operands.
// 1 -> default value, remain current constraint
// 2 -> narrow case
// 3 -> widen case
// TODO: Add TargetOverlapConstraintType into PseudosTable for further
// query.
bits<2> TargetOverlapConstraintType = 1;
}

// The actual table.
Expand Down Expand Up @@ -866,7 +874,8 @@ class VPseudoILoadNoMask<VReg RetClass,
int EEW,
bits<3> LMUL,
bit Ordered,
bit EarlyClobber> :
bit EarlyClobber,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMem:$rs1, IdxClass:$rs2, AVL:$vl,
ixlenimm:$sew, ixlenimm:$policy), []>,
Expand All @@ -879,14 +888,16 @@ class VPseudoILoadNoMask<VReg RetClass,
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $dest", "$rd = $dest");
let TargetOverlapConstraintType = TargetConstraintType;
}

class VPseudoILoadMask<VReg RetClass,
VReg IdxClass,
int EEW,
bits<3> LMUL,
bit Ordered,
bit EarlyClobber> :
bit EarlyClobber,
int TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge,
GPRMem:$rs1, IdxClass:$rs2,
Expand All @@ -897,6 +908,7 @@ class VPseudoILoadMask<VReg RetClass,
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !if(!eq(EarlyClobber, 1), "@earlyclobber $rd, $rd = $merge", "$rd = $merge");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
Expand Down Expand Up @@ -1006,7 +1018,8 @@ class VPseudoNullaryPseudoM<string BaseInst> :

class VPseudoUnaryNoMask<DAGOperand RetClass,
DAGOperand OpClass,
string Constraint = ""> :
string Constraint = "",
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge, OpClass:$rs2,
AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
Expand All @@ -1015,14 +1028,16 @@ class VPseudoUnaryNoMask<DAGOperand RetClass,
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
}

class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,
DAGOperand OpClass,
string Constraint = ""> :
string Constraint = "",
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge, OpClass:$rs2, ixlenimm:$rm,
AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
Expand All @@ -1031,6 +1046,7 @@ class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
Expand All @@ -1040,7 +1056,8 @@ class VPseudoUnaryNoMaskRoundingMode<DAGOperand RetClass,

class VPseudoUnaryMask<VReg RetClass,
VReg OpClass,
string Constraint = ""> :
string Constraint = "",
int TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
VMaskOp:$vm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
Expand All @@ -1049,6 +1066,7 @@ class VPseudoUnaryMask<VReg RetClass,
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
Expand Down Expand Up @@ -1168,22 +1186,25 @@ class VPseudoUnaryAnyMask<VReg RetClass,
class VPseudoBinaryNoMask<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
string Constraint> :
string Constraint,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = Constraint;
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
}

class VPseudoBinaryNoMaskTU<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
string Constraint> :
string Constraint,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1, AVL:$vl,
ixlenimm:$sew, ixlenimm:$policy), []>,
Expand All @@ -1192,6 +1213,7 @@ class VPseudoBinaryNoMaskTU<VReg RetClass,
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
Expand All @@ -1201,14 +1223,16 @@ class VPseudoBinaryNoMaskRoundingMode<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
string Constraint,
int UsesVXRM_ = 1> :
int UsesVXRM_ = 1,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge, Op1Class:$rs2, Op2Class:$rs1, ixlenimm:$rm,
AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
Expand All @@ -1220,7 +1244,8 @@ class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class,
string Constraint,
int UsesVXRM_> :
int UsesVXRM_,
int TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge,
Op1Class:$rs2, Op2Class:$rs1,
Expand All @@ -1230,6 +1255,7 @@ class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
let mayLoad = 0;
let mayStore = 0;
let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
Expand All @@ -1243,7 +1269,8 @@ class VPseudoBinaryMaskPolicyRoundingMode<VReg RetClass,
// This allows maskedoff and rs2 to be the same register.
class VPseudoTiedBinaryNoMask<VReg RetClass,
DAGOperand Op2Class,
string Constraint> :
string Constraint,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew,
ixlenimm:$policy), []>,
Expand All @@ -1252,6 +1279,7 @@ class VPseudoTiedBinaryNoMask<VReg RetClass,
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $rs2"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
Expand All @@ -1261,7 +1289,8 @@ class VPseudoTiedBinaryNoMask<VReg RetClass,

class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
DAGOperand Op2Class,
string Constraint> :
string Constraint,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs2, Op2Class:$rs1,
ixlenimm:$rm,
Expand All @@ -1272,6 +1301,7 @@ class VPseudoTiedBinaryNoMaskRoundingMode<VReg RetClass,
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $rs2"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
Expand Down Expand Up @@ -1329,7 +1359,8 @@ class VPseudoBinaryMask<VReg RetClass,
class VPseudoBinaryMaskPolicy<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class,
string Constraint> :
string Constraint,
int TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge,
Op1Class:$rs2, Op2Class:$rs1,
Expand All @@ -1339,6 +1370,7 @@ class VPseudoBinaryMaskPolicy<VReg RetClass,
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
Expand Down Expand Up @@ -1389,14 +1421,16 @@ class VPseudoTernaryMaskPolicyRoundingMode<VReg RetClass,
class VPseudoBinaryMOutNoMask<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
string Constraint> :
string Constraint,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins Op1Class:$rs2, Op2Class:$rs1, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = Constraint;
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
}
Expand All @@ -1405,7 +1439,8 @@ class VPseudoBinaryMOutNoMask<VReg RetClass,
class VPseudoBinaryMOutMask<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class,
string Constraint> :
string Constraint,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$merge,
Op1Class:$rs2, Op2Class:$rs1,
Expand All @@ -1415,6 +1450,7 @@ class VPseudoBinaryMOutMask<VReg RetClass,
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
let UsesMaskPolicy = 1;
Expand All @@ -1425,7 +1461,8 @@ class VPseudoBinaryMOutMask<VReg RetClass,
// This allows maskedoff and rs2 to be the same register.
class VPseudoTiedBinaryMask<VReg RetClass,
DAGOperand Op2Class,
string Constraint> :
string Constraint,
int TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge,
Op2Class:$rs1,
Expand All @@ -1435,6 +1472,7 @@ class VPseudoTiedBinaryMask<VReg RetClass,
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
Expand All @@ -1444,7 +1482,8 @@ class VPseudoTiedBinaryMask<VReg RetClass,

class VPseudoTiedBinaryMaskRoundingMode<VReg RetClass,
DAGOperand Op2Class,
string Constraint> :
string Constraint,
int TargetConstraintType = 1> :
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge,
Op2Class:$rs1,
Expand All @@ -1456,6 +1495,7 @@ class VPseudoTiedBinaryMaskRoundingMode<VReg RetClass,
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $merge"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasVecPolicyOp = 1;
Expand All @@ -1470,7 +1510,8 @@ class VPseudoBinaryCarryIn<VReg RetClass,
DAGOperand Op2Class,
LMULInfo MInfo,
bit CarryIn,
string Constraint> :
string Constraint,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
!if(CarryIn,
(ins Op1Class:$rs2, Op2Class:$rs1,
Expand All @@ -1482,6 +1523,7 @@ class VPseudoBinaryCarryIn<VReg RetClass,
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = Constraint;
let TargetOverlapConstraintType = TargetConstraintType;
let HasVLOp = 1;
let HasSEWOp = 1;
let VLMul = MInfo.value;
Expand Down Expand Up @@ -1529,7 +1571,8 @@ class VPseudoTernaryNoMask<VReg RetClass,
class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class,
string Constraint> :
string Constraint,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
Expand All @@ -1538,6 +1581,7 @@ class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $rs3"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVecPolicyOp = 1;
let HasVLOp = 1;
let HasSEWOp = 1;
Expand All @@ -1546,7 +1590,8 @@ class VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class,
string Constraint> :
string Constraint,
int TargetConstraintType = 1> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
ixlenimm:$rm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []>,
Expand All @@ -1555,6 +1600,7 @@ class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $rs3"], ",");
let TargetOverlapConstraintType = TargetConstraintType;
let HasVecPolicyOp = 1;
let HasVLOp = 1;
let HasSEWOp = 1;
Expand Down Expand Up @@ -1888,12 +1934,14 @@ multiclass VPseudoILoad<bit Ordered> {
defvar Vreg = dataEMUL.vrclass;
defvar IdxVreg = idxEMUL.vrclass;
defvar HasConstraint = !ne(dataEEW, idxEEW);
defvar TypeConstraints =
!if(!eq(dataEEW, idxEEW), 1, !if(!gt(dataEEW, idxEEW), !if(!ge(idxEMULOctuple, 8), 3, 1), 2));
let VLMul = dataEMUL.value in {
def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo :
VPseudoILoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint>,
VPseudoILoadNoMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint, TypeConstraints>,
VLXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
VPseudoILoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint>,
VPseudoILoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint, TypeConstraints>,
RISCVMaskedPseudo<MaskIdx=3>,
VLXSched<dataEEW, Ordered, DataLInfo, IdxLInfo>;
}
Expand Down Expand Up @@ -2071,13 +2119,14 @@ multiclass VPseudoBinary<VReg RetClass,
DAGOperand Op2Class,
LMULInfo MInfo,
string Constraint = "",
int sew = 0> {
int sew = 0,
int TargetConstraintType = 1> {
let VLMul = MInfo.value, SEW=sew in {
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
def suffix : VPseudoBinaryNoMaskTU<RetClass, Op1Class, Op2Class,
Constraint>;
Constraint, TargetConstraintType>;
def suffix # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
Constraint>,
Constraint, TargetConstraintType>,
RISCVMaskedPseudo<MaskIdx=3>;
}
}
Expand All @@ -2101,16 +2150,19 @@ multiclass VPseudoBinaryRoundingMode<VReg RetClass,
LMULInfo MInfo,
string Constraint = "",
int sew = 0,
int UsesVXRM = 1> {
int UsesVXRM = 1,
int TargetConstraintType = 1> {
let VLMul = MInfo.value, SEW=sew in {
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
def suffix : VPseudoBinaryNoMaskRoundingMode<RetClass, Op1Class, Op2Class,
Constraint, UsesVXRM>;
Constraint, UsesVXRM,
TargetConstraintType>;
def suffix # "_MASK" : VPseudoBinaryMaskPolicyRoundingMode<RetClass,
Op1Class,
Op2Class,
Constraint,
UsesVXRM>,
UsesVXRM,
TargetConstraintType>,
RISCVMaskedPseudo<MaskIdx=3>;
}
}
Expand All @@ -2120,13 +2172,14 @@ multiclass VPseudoBinaryM<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
LMULInfo MInfo,
string Constraint = ""> {
string Constraint = "",
int TargetConstraintType = 1> {
let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoBinaryMOutNoMask<RetClass, Op1Class, Op2Class,
Constraint>;
Constraint, TargetConstraintType>;
let ForceTailAgnostic = true in
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
Op2Class, Constraint>,
Op2Class, Constraint, TargetConstraintType>,
RISCVMaskedPseudo<MaskIdx=3>;
}
}
Expand All @@ -2151,24 +2204,26 @@ multiclass VPseudoBinaryEmul<VReg RetClass,
multiclass VPseudoTiedBinary<VReg RetClass,
DAGOperand Op2Class,
LMULInfo MInfo,
string Constraint = ""> {
string Constraint = "",
int TargetConstraintType = 1> {
let VLMul = MInfo.value in {
def "_" # MInfo.MX # "_TIED": VPseudoTiedBinaryNoMask<RetClass, Op2Class,
Constraint>;
Constraint, TargetConstraintType>;
def "_" # MInfo.MX # "_MASK_TIED" : VPseudoTiedBinaryMask<RetClass, Op2Class,
Constraint>;
Constraint, TargetConstraintType>;
}
}

multiclass VPseudoTiedBinaryRoundingMode<VReg RetClass,
DAGOperand Op2Class,
LMULInfo MInfo,
string Constraint = ""> {
string Constraint = "",
int TargetConstraintType = 1> {
let VLMul = MInfo.value in {
def "_" # MInfo.MX # "_TIED":
VPseudoTiedBinaryNoMaskRoundingMode<RetClass, Op2Class, Constraint>;
VPseudoTiedBinaryNoMaskRoundingMode<RetClass, Op2Class, Constraint, TargetConstraintType>;
def "_" # MInfo.MX # "_MASK_TIED" :
VPseudoTiedBinaryMaskRoundingMode<RetClass, Op2Class, Constraint>;
VPseudoTiedBinaryMaskRoundingMode<RetClass, Op2Class, Constraint, TargetConstraintType>;
}
}

Expand Down Expand Up @@ -2280,22 +2335,23 @@ multiclass VPseudoVALU_MM<bit Commutable = 0> {
// destination register group is legal. Otherwise, it is illegal.
multiclass VPseudoBinaryW_VV<LMULInfo m> {
defm _VV : VPseudoBinary<m.wvrclass, m.vrclass, m.vrclass, m,
"@earlyclobber $rd">;
"@earlyclobber $rd", TargetConstraintType=3>;
}

multiclass VPseudoBinaryW_VV_RM<LMULInfo m> {
defm _VV : VPseudoBinaryRoundingMode<m.wvrclass, m.vrclass, m.vrclass, m,
"@earlyclobber $rd", UsesVXRM=0>;
"@earlyclobber $rd", UsesVXRM=0,
TargetConstraintType=3>;
}

multiclass VPseudoBinaryW_VX<LMULInfo m> {
defm "_VX" : VPseudoBinary<m.wvrclass, m.vrclass, GPR, m,
"@earlyclobber $rd">;
"@earlyclobber $rd", TargetConstraintType=3>;
}

multiclass VPseudoBinaryW_VI<Operand ImmType, LMULInfo m> {
defm "_VI" : VPseudoBinary<m.wvrclass, m.vrclass, ImmType, m,
"@earlyclobber $rd">;
"@earlyclobber $rd", TargetConstraintType=3>;
}

multiclass VPseudoBinaryW_VF<LMULInfo m, FPR_Info f> {
Expand All @@ -2308,46 +2364,50 @@ multiclass VPseudoBinaryW_VF_RM<LMULInfo m, FPR_Info f> {
defm "_V" # f.FX : VPseudoBinaryRoundingMode<m.wvrclass, m.vrclass,
f.fprclass, m,
"@earlyclobber $rd",
UsesVXRM=0>;
UsesVXRM=0,
TargetConstraintType=3>;
}

multiclass VPseudoBinaryW_WV<LMULInfo m> {
defm _WV : VPseudoBinary<m.wvrclass, m.wvrclass, m.vrclass, m,
"@earlyclobber $rd">;
"@earlyclobber $rd", TargetConstraintType=3>;
defm _WV : VPseudoTiedBinary<m.wvrclass, m.vrclass, m,
"@earlyclobber $rd">;
"@earlyclobber $rd", TargetConstraintType=3>;
}

multiclass VPseudoBinaryW_WV_RM<LMULInfo m> {
defm _WV : VPseudoBinaryRoundingMode<m.wvrclass, m.wvrclass, m.vrclass, m,
"@earlyclobber $rd", UsesVXRM=0>;
"@earlyclobber $rd", UsesVXRM=0, TargetConstraintType=3>;
defm _WV : VPseudoTiedBinaryRoundingMode<m.wvrclass, m.vrclass, m,
"@earlyclobber $rd">;
"@earlyclobber $rd", TargetConstraintType=3>;
}

multiclass VPseudoBinaryW_WX<LMULInfo m> {
defm "_WX" : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m>;
defm "_WX" : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m, /*Constraint*/ "", TargetConstraintType=3>;
}

multiclass VPseudoBinaryW_WF<LMULInfo m, FPR_Info f> {
multiclass VPseudoBinaryW_WF<LMULInfo m, FPR_Info f, int TargetConstraintType = 1> {
defm "_W" # f.FX : VPseudoBinary<m.wvrclass, m.wvrclass,
f.fprclass, m>;
f.fprclass, m, /*Constraint*/ "", TargetConstraintType=TargetConstraintType>;
}

multiclass VPseudoBinaryW_WF_RM<LMULInfo m, FPR_Info f> {
defm "_W" # f.FX : VPseudoBinaryRoundingMode<m.wvrclass, m.wvrclass,
f.fprclass, m,
UsesVXRM=0>;
Constraint="",
sew=0,
UsesVXRM=0,
TargetConstraintType=3>;
}

// Narrowing instructions like vnsrl/vnsra/vnclip(u) don't need @earlyclobber
// if the source and destination have an LMUL<=1. This matches this overlap
// exception from the spec.
// "The destination EEW is smaller than the source EEW and the overlap is in the
// lowest-numbered part of the source register group."
multiclass VPseudoBinaryV_WV<LMULInfo m> {
multiclass VPseudoBinaryV_WV<LMULInfo m, int TargetConstraintType = 1> {
defm _WV : VPseudoBinary<m.vrclass, m.wvrclass, m.vrclass, m,
!if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
!if(!ge(m.octuple, 8), "@earlyclobber $rd", ""), TargetConstraintType=TargetConstraintType>;
}

multiclass VPseudoBinaryV_WV_RM<LMULInfo m> {
Expand All @@ -2356,9 +2416,9 @@ multiclass VPseudoBinaryV_WV_RM<LMULInfo m> {
"@earlyclobber $rd", "")>;
}

multiclass VPseudoBinaryV_WX<LMULInfo m> {
multiclass VPseudoBinaryV_WX<LMULInfo m, int TargetConstraintType = 1> {
defm _WX : VPseudoBinary<m.vrclass, m.wvrclass, GPR, m,
!if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
!if(!ge(m.octuple, 8), "@earlyclobber $rd", ""), TargetConstraintType=TargetConstraintType>;
}

multiclass VPseudoBinaryV_WX_RM<LMULInfo m> {
Expand All @@ -2367,9 +2427,9 @@ multiclass VPseudoBinaryV_WX_RM<LMULInfo m> {
"@earlyclobber $rd", "")>;
}

multiclass VPseudoBinaryV_WI<LMULInfo m> {
multiclass VPseudoBinaryV_WI<LMULInfo m, int TargetConstraintType = 1> {
defm _WI : VPseudoBinary<m.vrclass, m.wvrclass, uimm5, m,
!if(!ge(m.octuple, 8), "@earlyclobber $rd", "")>;
!if(!ge(m.octuple, 8), "@earlyclobber $rd", ""), TargetConstraintType=TargetConstraintType>;
}

multiclass VPseudoBinaryV_WI_RM<LMULInfo m> {
Expand All @@ -2383,13 +2443,14 @@ multiclass VPseudoBinaryV_WI_RM<LMULInfo m> {
// For vadc and vsbc, CarryIn == 1 and CarryOut == 0
multiclass VPseudoBinaryV_VM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
string Constraint = "",
bit Commutable = 0> {
bit Commutable = 0,
int TargetConstraintType = 1> {
let isCommutable = Commutable in
def "_VV" # !if(CarryIn, "M", "") # "_" # m.MX :
VPseudoBinaryCarryIn<!if(CarryOut, VR,
!if(!and(CarryIn, !not(CarryOut)),
GetVRegNoV0<m.vrclass>.R, m.vrclass)),
m.vrclass, m.vrclass, m, CarryIn, Constraint>;
m.vrclass, m.vrclass, m, CarryIn, Constraint, TargetConstraintType>;
}

multiclass VPseudoTiedBinaryV_VM<LMULInfo m> {
Expand All @@ -2399,12 +2460,12 @@ multiclass VPseudoTiedBinaryV_VM<LMULInfo m> {
}

multiclass VPseudoBinaryV_XM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
string Constraint = ""> {
string Constraint = "", int TargetConstraintType = 1> {
def "_VX" # !if(CarryIn, "M", "") # "_" # m.MX :
VPseudoBinaryCarryIn<!if(CarryOut, VR,
!if(!and(CarryIn, !not(CarryOut)),
GetVRegNoV0<m.vrclass>.R, m.vrclass)),
m.vrclass, GPR, m, CarryIn, Constraint>;
m.vrclass, GPR, m, CarryIn, Constraint, TargetConstraintType>;
}

multiclass VPseudoTiedBinaryV_XM<LMULInfo m> {
Expand All @@ -2428,12 +2489,12 @@ multiclass VPseudoVMRG_FM {
}

multiclass VPseudoBinaryV_IM<LMULInfo m, bit CarryOut = 0, bit CarryIn = 1,
string Constraint = ""> {
string Constraint = "", int TargetConstraintType = 1> {
def "_VI" # !if(CarryIn, "M", "") # "_" # m.MX :
VPseudoBinaryCarryIn<!if(CarryOut, VR,
!if(!and(CarryIn, !not(CarryOut)),
GetVRegNoV0<m.vrclass>.R, m.vrclass)),
m.vrclass, simm5, m, CarryIn, Constraint>;
m.vrclass, simm5, m, CarryIn, Constraint, TargetConstraintType>;
}

multiclass VPseudoTiedBinaryV_IM<LMULInfo m> {
Expand Down Expand Up @@ -2541,45 +2602,45 @@ multiclass VPseudoVRCP_V_RM {
}
}

multiclass PseudoVEXT_VF2 {
multiclass PseudoVEXT_VF2<int TargetConstraintType = 1> {
defvar constraints = "@earlyclobber $rd";
foreach m = MxListVF2 in {
defvar mx = m.MX;
let VLMul = m.value in {
def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f2vrclass, constraints>,
def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f2vrclass, constraints, TargetConstraintType>,
SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>;
def "_" # mx # "_MASK" :
VPseudoUnaryMask<m.vrclass, m.f2vrclass, constraints>,
VPseudoUnaryMask<m.vrclass, m.f2vrclass, constraints, TargetConstraintType>,
RISCVMaskedPseudo<MaskIdx=2>,
SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>;
}
}
}

multiclass PseudoVEXT_VF4 {
multiclass PseudoVEXT_VF4<int TargetConstraintType = 1> {
defvar constraints = "@earlyclobber $rd";
foreach m = MxListVF4 in {
defvar mx = m.MX;
let VLMul = m.value in {
def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f4vrclass, constraints>,
def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f4vrclass, constraints, TargetConstraintType>,
SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>;
def "_" # mx # "_MASK" :
VPseudoUnaryMask<m.vrclass, m.f4vrclass, constraints>,
VPseudoUnaryMask<m.vrclass, m.f4vrclass, constraints, TargetConstraintType>,
RISCVMaskedPseudo<MaskIdx=2>,
SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>;
}
}
}

multiclass PseudoVEXT_VF8 {
multiclass PseudoVEXT_VF8<int TargetConstraintType = 1> {
defvar constraints = "@earlyclobber $rd";
foreach m = MxListVF8 in {
defvar mx = m.MX;
let VLMul = m.value in {
def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f8vrclass, constraints>,
def "_" # mx : VPseudoUnaryNoMask<m.vrclass, m.f8vrclass, constraints, TargetConstraintType>,
SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>;
def "_" # mx # "_MASK" :
VPseudoUnaryMask<m.vrclass, m.f8vrclass, constraints>,
VPseudoUnaryMask<m.vrclass, m.f8vrclass, constraints, TargetConstraintType>,
RISCVMaskedPseudo<MaskIdx=2>,
SchedUnary<"WriteVExtV", "ReadVExtV", mx, forceMergeOpRead=true>;
}
Expand All @@ -2597,26 +2658,26 @@ multiclass PseudoVEXT_VF8 {
// lowest-numbered part of the source register group".
// With LMUL<=1 the source and dest occupy a single register so any overlap
// is in the lowest-numbered part.
multiclass VPseudoBinaryM_VV<LMULInfo m> {
multiclass VPseudoBinaryM_VV<LMULInfo m, int TargetConstraintType = 1> {
defm _VV : VPseudoBinaryM<VR, m.vrclass, m.vrclass, m,
!if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
!if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>;
}

multiclass VPseudoBinaryM_VX<LMULInfo m> {
multiclass VPseudoBinaryM_VX<LMULInfo m, int TargetConstraintType = 1> {
defm "_VX" :
VPseudoBinaryM<VR, m.vrclass, GPR, m,
!if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
!if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>;
}

multiclass VPseudoBinaryM_VF<LMULInfo m, FPR_Info f> {
multiclass VPseudoBinaryM_VF<LMULInfo m, FPR_Info f, int TargetConstraintType = 1> {
defm "_V" # f.FX :
VPseudoBinaryM<VR, m.vrclass, f.fprclass, m,
!if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
!if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>;
}

multiclass VPseudoBinaryM_VI<LMULInfo m> {
multiclass VPseudoBinaryM_VI<LMULInfo m, int TargetConstraintType = 1> {
defm _VI : VPseudoBinaryM<VR, m.vrclass, simm5, m,
!if(!ge(m.octuple, 16), "@earlyclobber $rd", "")>;
!if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>;
}

multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
Expand Down Expand Up @@ -2922,7 +2983,7 @@ multiclass VPseudoVWALU_VV_VX {
defm "" : VPseudoBinaryW_VV<m>,
SchedBinary<"WriteVIWALUV", "ReadVIWALUV", "ReadVIWALUV", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryW_VX<m>,
defm "" : VPseudoBinaryW_VX<m>,
SchedBinary<"WriteVIWALUX", "ReadVIWALUV", "ReadVIWALUX", mx,
forceMergeOpRead=true>;
}
Expand Down Expand Up @@ -3057,13 +3118,13 @@ multiclass VPseudoVCALUM_VM_XM_IM<string Constraint> {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=Constraint,
Commutable=1>,
Commutable=1, TargetConstraintType=2>,
SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=Constraint, TargetConstraintType=2>,
SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=1, Constraint=Constraint, TargetConstraintType=2>,
SchedUnary<"WriteVICALUI", "ReadVICALUV", mx, forceMasked=1,
forceMergeOpRead=true>;
}
Expand All @@ -3072,10 +3133,10 @@ multiclass VPseudoVCALUM_VM_XM_IM<string Constraint> {
multiclass VPseudoVCALUM_VM_XM<string Constraint> {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=Constraint, TargetConstraintType=2>,
SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx, forceMasked=1,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=Constraint, TargetConstraintType=2>,
SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx, forceMasked=1,
forceMergeOpRead=true>;
}
Expand All @@ -3085,10 +3146,10 @@ multiclass VPseudoVCALUM_V_X_I<string Constraint> {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=Constraint,
Commutable=1>,
Commutable=1, TargetConstraintType=2>,
SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=Constraint>,
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=Constraint, TargetConstraintType=2>,
SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=0, Constraint=Constraint>,
Expand All @@ -3100,10 +3161,10 @@ multiclass VPseudoVCALUM_V_X_I<string Constraint> {
multiclass VPseudoVCALUM_V_X<string Constraint> {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=Constraint>,
defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=Constraint, TargetConstraintType=2>,
SchedBinary<"WriteVICALUV", "ReadVICALUV", "ReadVICALUV", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=Constraint>,
defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=Constraint, TargetConstraintType=2>,
SchedBinary<"WriteVICALUX", "ReadVICALUV", "ReadVICALUX", mx,
forceMergeOpRead=true>;
}
Expand All @@ -3127,13 +3188,13 @@ multiclass VPseudoVNCLP_WV_WX_WI_RM {
multiclass VPseudoVNSHT_WV_WX_WI {
foreach m = MxListW in {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_WV<m>,
defm "" : VPseudoBinaryV_WV<m, TargetConstraintType=2>,
SchedBinary<"WriteVNShiftV", "ReadVNShiftV", "ReadVNShiftV", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_WX<m>,
defm "" : VPseudoBinaryV_WX<m, TargetConstraintType=2>,
SchedBinary<"WriteVNShiftX", "ReadVNShiftV", "ReadVNShiftX", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_WI<m>,
defm "" : VPseudoBinaryV_WI<m, TargetConstraintType=2>,
SchedUnary<"WriteVNShiftI", "ReadVNShiftV", mx,
forceMergeOpRead=true>;
}
Expand Down Expand Up @@ -3178,11 +3239,12 @@ multiclass VPseudoTernaryWithPolicy<VReg RetClass,
DAGOperand Op2Class,
LMULInfo MInfo,
string Constraint = "",
bit Commutable = 0> {
bit Commutable = 0,
int TargetConstraintType = 1> {
let VLMul = MInfo.value in {
let isCommutable = Commutable in
def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>,
def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint, TargetConstraintType>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint, TargetConstraintType>,
RISCVMaskedPseudo<MaskIdx=3>;
}
}
Expand All @@ -3192,16 +3254,19 @@ multiclass VPseudoTernaryWithPolicyRoundingMode<VReg RetClass,
DAGOperand Op2Class,
LMULInfo MInfo,
string Constraint = "",
bit Commutable = 0> {
bit Commutable = 0,
int TargetConstraintType = 1> {
let VLMul = MInfo.value in {
let isCommutable = Commutable in
def "_" # MInfo.MX :
VPseudoTernaryNoMaskWithPolicyRoundingMode<RetClass, Op1Class,
Op2Class, Constraint>;
Op2Class, Constraint,
TargetConstraintType>;
def "_" # MInfo.MX # "_MASK" :
VPseudoBinaryMaskPolicyRoundingMode<RetClass, Op1Class,
Op2Class, Constraint,
UsesVXRM_=0>,
UsesVXRM_=0,
TargetConstraintType=TargetConstraintType>,
RISCVMaskedPseudo<MaskIdx=3>;
}
}
Expand Down Expand Up @@ -3236,31 +3301,34 @@ multiclass VPseudoTernaryV_VF_AAXA_RM<LMULInfo m, FPR_Info f, string Constraint
multiclass VPseudoTernaryW_VV<LMULInfo m> {
defvar constraint = "@earlyclobber $rd";
defm _VV : VPseudoTernaryWithPolicy<m.wvrclass, m.vrclass, m.vrclass, m,
constraint>;
constraint, /*Commutable*/ 0, TargetConstraintType=3>;
}

multiclass VPseudoTernaryW_VV_RM<LMULInfo m> {
defvar constraint = "@earlyclobber $rd";
defm _VV : VPseudoTernaryWithPolicyRoundingMode<m.wvrclass, m.vrclass, m.vrclass, m,
constraint>;
constraint, /* Commutable */ 0,
TargetConstraintType=3>;
}

multiclass VPseudoTernaryW_VX<LMULInfo m> {
defvar constraint = "@earlyclobber $rd";
defm "_VX" : VPseudoTernaryWithPolicy<m.wvrclass, GPR, m.vrclass, m,
constraint>;
constraint, /*Commutable*/ 0, TargetConstraintType=3>;
}

multiclass VPseudoTernaryW_VF<LMULInfo m, FPR_Info f> {
multiclass VPseudoTernaryW_VF<LMULInfo m, FPR_Info f, int TargetConstraintType = 1> {
defvar constraint = "@earlyclobber $rd";
defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.wvrclass, f.fprclass,
m.vrclass, m, constraint>;
m.vrclass, m, constraint, /*Commutable*/ 0, TargetConstraintType>;
}

multiclass VPseudoTernaryW_VF_RM<LMULInfo m, FPR_Info f> {
defvar constraint = "@earlyclobber $rd";
defm "_V" # f.FX : VPseudoTernaryWithPolicyRoundingMode<m.wvrclass, f.fprclass,
m.vrclass, m, constraint>;
m.vrclass, m, constraint,
/* Commutable */ 0,
TargetConstraintType=3>;
}

multiclass VPseudoVSLDVWithPolicy<VReg RetClass,
Expand Down Expand Up @@ -3395,34 +3463,34 @@ multiclass VPseudoVWMAC_VV_VF_BF_RM {
multiclass VPseudoVCMPM_VV_VX_VI {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryM_VV<m>,
defm "" : VPseudoBinaryM_VV<m, TargetConstraintType=2>,
SchedBinary<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV", mx>;
defm "" : VPseudoBinaryM_VX<m>,
defm "" : VPseudoBinaryM_VX<m, TargetConstraintType=2>,
SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
defm "" : VPseudoBinaryM_VI<m>,
defm "" : VPseudoBinaryM_VI<m, TargetConstraintType=2>,
SchedUnary<"WriteVICmpI", "ReadVICmpV", mx>;
}
}

multiclass VPseudoVCMPM_VV_VX {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryM_VV<m>,
defm "" : VPseudoBinaryM_VV<m, TargetConstraintType=2>,
SchedBinary<"WriteVICmpV", "ReadVICmpV", "ReadVICmpV", mx>;
defm "" : VPseudoBinaryM_VX<m>,
defm "" : VPseudoBinaryM_VX<m, TargetConstraintType=2>,
SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
}
}

multiclass VPseudoVCMPM_VV_VF {
foreach m = MxListF in {
defm "" : VPseudoBinaryM_VV<m>,
defm "" : VPseudoBinaryM_VV<m, TargetConstraintType=2>,
SchedBinary<"WriteVFCmpV", "ReadVFCmpV", "ReadVFCmpV", m.MX>;
}

foreach f = FPList in {
foreach m = f.MxList in {
defm "" : VPseudoBinaryM_VF<m, f>,
defm "" : VPseudoBinaryM_VF<m, f, TargetConstraintType=2>,
SchedBinary<"WriteVFCmpF", "ReadVFCmpV", "ReadVFCmpF", m.MX>;
}
}
Expand All @@ -3431,7 +3499,7 @@ multiclass VPseudoVCMPM_VV_VF {
multiclass VPseudoVCMPM_VF {
foreach f = FPList in {
foreach m = f.MxList in {
defm "" : VPseudoBinaryM_VF<m, f>,
defm "" : VPseudoBinaryM_VF<m, f, TargetConstraintType=2>,
SchedBinary<"WriteVFCmpF", "ReadVFCmpV", "ReadVFCmpF", m.MX>;
}
}
Expand All @@ -3440,9 +3508,9 @@ multiclass VPseudoVCMPM_VF {
multiclass VPseudoVCMPM_VX_VI {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryM_VX<m>,
defm "" : VPseudoBinaryM_VX<m, TargetConstraintType=2>,
SchedBinary<"WriteVICmpX", "ReadVICmpV", "ReadVICmpX", mx>;
defm "" : VPseudoBinaryM_VI<m>,
defm "" : VPseudoBinaryM_VI<m, TargetConstraintType=2>,
SchedUnary<"WriteVICmpI", "ReadVICmpV", mx>;
}
}
Expand Down Expand Up @@ -3537,21 +3605,23 @@ multiclass VPseudoVFWREDO_VS_RM {
multiclass VPseudoConversion<VReg RetClass,
VReg Op1Class,
LMULInfo MInfo,
string Constraint = ""> {
string Constraint = "",
int TargetConstraintType = 1> {
let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint>;
def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint, TargetConstraintType>;
def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask<RetClass, Op1Class,
Constraint>,
Constraint, TargetConstraintType>,
RISCVMaskedPseudo<MaskIdx=2>;
}
}

multiclass VPseudoConversionRoundingMode<VReg RetClass,
VReg Op1Class,
LMULInfo MInfo,
string Constraint = ""> {
string Constraint = "",
int TargetConstraintType = 1> {
let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoUnaryNoMaskRoundingMode<RetClass, Op1Class, Constraint>;
def "_" # MInfo.MX : VPseudoUnaryNoMaskRoundingMode<RetClass, Op1Class, Constraint, TargetConstraintType>;
def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMaskRoundingMode<RetClass, Op1Class,
Constraint>,
RISCVMaskedPseudo<MaskIdx=2>;
Expand Down Expand Up @@ -3632,7 +3702,7 @@ multiclass VPseudoVCVTF_RM_V {
multiclass VPseudoVWCVTI_V {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListFW in {
defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>,
defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, TargetConstraintType=3>,
SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX,
forceMergeOpRead=true>;
}
Expand All @@ -3641,7 +3711,7 @@ multiclass VPseudoVWCVTI_V {
multiclass VPseudoVWCVTI_V_RM {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListFW in {
defm _V : VPseudoConversionRoundingMode<m.wvrclass, m.vrclass, m, constraint>,
defm _V : VPseudoConversionRoundingMode<m.wvrclass, m.vrclass, m, constraint, TargetConstraintType=3>,
SchedUnary<"WriteVFWCvtFToIV", "ReadVFWCvtFToIV", m.MX,
forceMergeOpRead=true>;
}
Expand All @@ -3659,7 +3729,7 @@ multiclass VPseudoVWCVTI_RM_V {
multiclass VPseudoVWCVTF_V {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListW in {
defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>,
defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, TargetConstraintType=3>,
SchedUnary<"WriteVFWCvtIToFV", "ReadVFWCvtIToFV", m.MX,
forceMergeOpRead=true>;
}
Expand All @@ -3668,7 +3738,7 @@ multiclass VPseudoVWCVTF_V {
multiclass VPseudoVWCVTD_V {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListFW in {
defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint>,
defm _V : VPseudoConversion<m.wvrclass, m.vrclass, m, constraint, TargetConstraintType=3>,
SchedUnary<"WriteVFWCvtFToFV", "ReadVFWCvtFToFV", m.MX,
forceMergeOpRead=true>;
}
Expand All @@ -3677,7 +3747,7 @@ multiclass VPseudoVWCVTD_V {
multiclass VPseudoVNCVTI_W {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListW in {
defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint>,
defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>,
SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX,
forceMergeOpRead=true>;
}
Expand All @@ -3686,7 +3756,7 @@ multiclass VPseudoVNCVTI_W {
multiclass VPseudoVNCVTI_W_RM {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListW in {
defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint>,
defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>,
SchedUnary<"WriteVFNCvtFToIV", "ReadVFNCvtFToIV", m.MX,
forceMergeOpRead=true>;
}
Expand All @@ -3704,7 +3774,7 @@ multiclass VPseudoVNCVTI_RM_W {
multiclass VPseudoVNCVTF_W_RM {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListFW in {
defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint>,
defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>,
SchedUnary<"WriteVFNCvtIToFV", "ReadVFNCvtIToFV", m.MX,
forceMergeOpRead=true>;
}
Expand All @@ -3722,7 +3792,7 @@ multiclass VPseudoVNCVTF_RM_W {
multiclass VPseudoVNCVTD_W {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListFW in {
defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint>,
defm _W : VPseudoConversion<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>,
SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX,
forceMergeOpRead=true>;
}
Expand All @@ -3731,7 +3801,7 @@ multiclass VPseudoVNCVTD_W {
multiclass VPseudoVNCVTD_W_RM {
defvar constraint = "@earlyclobber $rd";
foreach m = MxListFW in {
defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint>,
defm _W : VPseudoConversionRoundingMode<m.vrclass, m.wvrclass, m, constraint, TargetConstraintType=2>,
SchedUnary<"WriteVFNCvtFToFV", "ReadVFNCvtFToFV", m.MX,
forceMergeOpRead=true>;
}
Expand Down