395 changes: 196 additions & 199 deletions llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -253,25 +253,25 @@ define amdgpu_kernel void @fp_to_sint_i64 (ptr addrspace(1) %out, float %in) {
; EG-NEXT: ADD_INT * T2.W, PV.W, literal.y,
; EG-NEXT: 8388608(1.175494e-38), -150(nan)
; EG-NEXT: ADD_INT T0.X, T0.W, literal.x,
; EG-NEXT: SUB_INT T0.Y, literal.y, T0.W,
; EG-NEXT: AND_INT T0.Z, PS, literal.z,
; EG-NEXT: AND_INT T0.Y, PS, literal.y,
; EG-NEXT: SUB_INT T0.Z, literal.z, T0.W,
; EG-NEXT: NOT_INT T0.W, PS,
; EG-NEXT: LSHR * T3.W, PV.W, 1,
; EG-NEXT: -127(nan), 150(2.101948e-43)
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: -127(nan), 31(4.344025e-44)
; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,
; EG-NEXT: LSHL T1.Y, T1.W, PV.Z,
; EG-NEXT: AND_INT T0.Z, T2.W, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
; EG-NEXT: AND_INT * T1.W, PV.Y, literal.x,
; EG-NEXT: AND_INT T1.Y, PV.Z, literal.x,
; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, T1.W, PV.Z,
; EG-NEXT: LSHL T0.W, T1.W, PV.Y,
; EG-NEXT: AND_INT * T1.W, T2.W, literal.x,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T1.Z, PV.Z, PV.Y, 0.0,
; EG-NEXT: CNDE_INT T0.W, PV.Z, PV.X, PV.Y,
; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
; EG-NEXT: CNDE_INT T0.W, PS, PV.X, PV.W,
; EG-NEXT: SETGT_INT * T1.W, T0.X, literal.x,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T0.Z, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T0.W, PS, PV.Y, PV.Z,
; EG-NEXT: CNDE_INT T1.Z, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T0.W, PS, PV.Z, PV.Y,
; EG-NEXT: ASHR * T1.W, KC0[2].Z, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: XOR_INT T0.W, PV.W, PS,
Expand Down Expand Up @@ -364,79 +364,78 @@ define amdgpu_kernel void @fp_to_sint_v2i64(ptr addrspace(1) %out, <2 x float> %
;
; EG-LABEL: fp_to_sint_v2i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 75, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 74, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: MOV * T0.W, literal.x,
; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT: BFE_UINT * T1.W, KC0[2].W, literal.x, PV.W,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: AND_INT T0.Z, KC0[2].W, literal.x,
; EG-NEXT: BFE_UINT T0.W, KC0[3].X, literal.y, T0.W,
; EG-NEXT: ADD_INT * T2.W, PV.W, literal.z,
; EG-NEXT: 8388607(1.175494e-38), 23(3.222986e-44)
; EG-NEXT: BFE_UINT T0.Z, KC0[3].X, literal.x, PV.W,
; EG-NEXT: BFE_UINT T0.W, KC0[2].W, literal.x, PV.W,
; EG-NEXT: AND_INT * T1.Z, KC0[2].W, literal.y,
; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
; EG-NEXT: ADD_INT T1.W, PV.W, literal.x,
; EG-NEXT: ADD_INT * T2.W, PV.Z, literal.x,
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: SUB_INT T0.X, literal.x, PV.W,
; EG-NEXT: SUB_INT T0.Y, literal.x, T1.W,
; EG-NEXT: AND_INT T1.Z, PS, literal.y,
; EG-NEXT: OR_INT T3.W, PV.Z, literal.z,
; EG-NEXT: AND_INT T0.X, PS, literal.x,
; EG-NEXT: AND_INT T0.Y, PV.W, literal.x,
; EG-NEXT: OR_INT T1.Z, T1.Z, literal.y,
; EG-NEXT: SUB_INT T3.W, literal.z, T0.W,
; EG-NEXT: AND_INT * T4.W, KC0[3].X, literal.w,
; EG-NEXT: 150(2.101948e-43), 31(4.344025e-44)
; EG-NEXT: 8388608(1.175494e-38), 8388607(1.175494e-38)
; EG-NEXT: 31(4.344025e-44), 8388608(1.175494e-38)
; EG-NEXT: 150(2.101948e-43), 8388607(1.175494e-38)
; EG-NEXT: OR_INT T1.X, PS, literal.x,
; EG-NEXT: LSHL T1.Y, PV.W, PV.Z,
; EG-NEXT: AND_INT T0.Z, T2.W, literal.y,
; EG-NEXT: BIT_ALIGN_INT T4.W, 0.0, PV.W, PV.Y,
; EG-NEXT: AND_INT * T5.W, PV.Y, literal.y,
; EG-NEXT: AND_INT T1.Y, PV.W, literal.y,
; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PV.Z, PV.W,
; EG-NEXT: LSHL T3.W, PV.Z, PV.Y,
; EG-NEXT: AND_INT * T4.W, T1.W, literal.y,
; EG-NEXT: 8388608(1.175494e-38), 32(4.484155e-44)
; EG-NEXT: CNDE_INT T2.X, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T0.Y, PV.Z, PV.Y, 0.0,
; EG-NEXT: ADD_INT T1.Z, T0.W, literal.x,
; EG-NEXT: BIT_ALIGN_INT T4.W, 0.0, PV.X, T0.X,
; EG-NEXT: AND_INT * T5.W, T0.X, literal.y,
; EG-NEXT: -150(nan), 32(4.484155e-44)
; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T2.Z, PV.Y, PV.Z, 0.0,
; EG-NEXT: LSHL T5.W, PV.X, T0.X,
; EG-NEXT: AND_INT * T6.W, T2.W, literal.x,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T0.X, PS, PV.W, 0.0,
; EG-NEXT: NOT_INT T2.Y, T2.W,
; EG-NEXT: AND_INT T2.Z, PV.Z, literal.x,
; EG-NEXT: NOT_INT T2.W, PV.Z,
; EG-NEXT: LSHR * T4.W, T1.X, 1,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: LSHR T3.X, T3.W, 1,
; EG-NEXT: ADD_INT T3.Y, T0.W, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
; EG-NEXT: LSHL T0.W, T1.X, PV.Z,
; EG-NEXT: AND_INT * T2.W, T1.Z, literal.y,
; EG-NEXT: NOT_INT T1.Y, T1.W,
; EG-NEXT: SUB_INT T3.Z, literal.x, T0.Z,
; EG-NEXT: NOT_INT T1.W, T2.W, BS:VEC_120/SCL_212
; EG-NEXT: LSHR * T2.W, T1.X, 1,
; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT: LSHR T2.X, T1.Z, 1,
; EG-NEXT: ADD_INT T2.Y, T0.Z, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, PS, PV.W,
; EG-NEXT: BIT_ALIGN_INT T1.W, 0.0, T1.X, PV.Z,
; EG-NEXT: AND_INT * T2.W, PV.Z, literal.y,
; EG-NEXT: -127(nan), 32(4.484155e-44)
; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T4.Y, PS, PV.Z, PV.W,
; EG-NEXT: SETGT_INT T1.Z, PV.Y, literal.x,
; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, PV.X, T2.Y,
; EG-NEXT: ADD_INT * T1.W, T1.W, literal.y,
; EG-NEXT: CNDE_INT T3.Y, T6.W, PV.Z, T5.W, BS:VEC_021/SCL_122
; EG-NEXT: SETGT_INT T0.Z, PV.Y, literal.x,
; EG-NEXT: BIT_ALIGN_INT T1.W, 0.0, PV.X, T1.Y,
; EG-NEXT: ADD_INT * T0.W, T0.W, literal.y,
; EG-NEXT: 23(3.222986e-44), -127(nan)
; EG-NEXT: CNDE_INT T3.X, T0.Z, PV.W, T1.Y,
; EG-NEXT: CNDE_INT T2.X, T4.W, PV.W, T3.W,
; EG-NEXT: SETGT_INT T1.Y, PS, literal.x,
; EG-NEXT: CNDE_INT T0.Z, PV.Z, 0.0, PV.Y,
; EG-NEXT: CNDE_INT T0.W, PV.Z, T0.X, PV.X,
; EG-NEXT: CNDE_INT T1.Z, PV.Z, 0.0, PV.Y,
; EG-NEXT: CNDE_INT T1.W, PV.Z, PV.X, T0.X,
; EG-NEXT: ASHR * T2.W, KC0[3].X, literal.y,
; EG-NEXT: 23(3.222986e-44), 31(4.344025e-44)
; EG-NEXT: XOR_INT T0.X, PV.W, PS,
; EG-NEXT: XOR_INT T2.Y, PV.Z, PS,
; EG-NEXT: XOR_INT T3.Y, PV.Z, PS,
; EG-NEXT: CNDE_INT T0.Z, PV.Y, 0.0, PV.X,
; EG-NEXT: CNDE_INT T0.W, PV.Y, T2.X, T0.Y,
; EG-NEXT: CNDE_INT T1.W, PV.Y, T2.Z, T0.Y,
; EG-NEXT: ASHR * T3.W, KC0[2].W, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: XOR_INT T0.Y, PV.W, PS,
; EG-NEXT: XOR_INT T0.Z, PV.Z, PS,
; EG-NEXT: SUB_INT T0.W, PV.Y, T2.W,
; EG-NEXT: SUB_INT T1.W, PV.Y, T2.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.X, T2.W,
; EG-NEXT: SUB_INT T1.Y, PV.W, PS,
; EG-NEXT: SETGT_INT T1.Z, 0.0, T3.Y,
; EG-NEXT: SUB_INT T0.W, PV.Z, T3.W,
; EG-NEXT: SETGT_INT T1.Z, 0.0, T2.Y,
; EG-NEXT: SUB_INT T1.W, PV.Z, T3.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T3.W,
; EG-NEXT: SUB_INT T0.Z, PV.W, PS,
; EG-NEXT: SETGT_INT T0.W, 0.0, T1.W,
; EG-NEXT: SETGT_INT T0.W, 0.0, T0.W,
; EG-NEXT: CNDE_INT * T1.W, PV.Z, PV.Y, 0.0,
; EG-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, 0.0,
; EG-NEXT: SUB_INT * T2.W, T0.X, T2.W,
Expand Down Expand Up @@ -567,170 +566,168 @@ define amdgpu_kernel void @fp_to_sint_v4i64(ptr addrspace(1) %out, <4 x float> %
;
; EG-LABEL: fp_to_sint_v4i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 101, @6, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 54, @108, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 0
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T2.X, 1
; EG-NEXT: ALU 99, @6, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 54, @106, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T0.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 6:
; EG-NEXT: MOV * T0.W, literal.x,
; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT: BFE_UINT T1.W, KC0[4].X, literal.x, PV.W,
; EG-NEXT: AND_INT * T2.W, KC0[4].X, literal.y,
; EG-NEXT: BFE_UINT T1.W, KC0[3].Z, literal.x, PV.W,
; EG-NEXT: AND_INT * T2.W, KC0[3].Z, literal.y,
; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
; EG-NEXT: OR_INT T0.Z, PS, literal.x,
; EG-NEXT: BFE_UINT T2.W, KC0[3].Z, literal.y, T0.W,
; EG-NEXT: ADD_INT * T3.W, PV.W, literal.z,
; EG-NEXT: 8388608(1.175494e-38), 23(3.222986e-44)
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: ADD_INT T0.Y, PV.W, literal.x,
; EG-NEXT: AND_INT T1.Z, PS, literal.y,
; EG-NEXT: NOT_INT T4.W, PS,
; EG-NEXT: LSHR * T5.W, PV.Z, 1,
; EG-NEXT: -127(nan), 31(4.344025e-44)
; EG-NEXT: OR_INT T2.W, PS, literal.x,
; EG-NEXT: ADD_INT * T3.W, PV.W, literal.y,
; EG-NEXT: 8388608(1.175494e-38), -150(nan)
; EG-NEXT: ADD_INT T0.X, T1.W, literal.x,
; EG-NEXT: BIT_ALIGN_INT T1.Y, 0.0, PS, PV.W,
; EG-NEXT: AND_INT T2.Z, T3.W, literal.y, BS:VEC_201
; EG-NEXT: LSHL T3.W, T0.Z, PV.Z,
; EG-NEXT: SUB_INT * T1.W, literal.z, T1.W,
; EG-NEXT: -127(nan), 32(4.484155e-44)
; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT: AND_INT T1.X, PS, literal.x,
; EG-NEXT: BIT_ALIGN_INT T2.Y, 0.0, T0.Z, PS,
; EG-NEXT: AND_INT T0.Z, KC0[3].Z, literal.y,
; EG-NEXT: CNDE_INT T1.W, PV.Z, PV.Y, PV.W,
; EG-NEXT: SETGT_INT * T4.W, PV.X, literal.z,
; EG-NEXT: BFE_UINT T0.Y, KC0[4].X, literal.y, T0.W,
; EG-NEXT: AND_INT T0.Z, PS, literal.z,
; EG-NEXT: NOT_INT T4.W, PS,
; EG-NEXT: LSHR * T5.W, PV.W, 1,
; EG-NEXT: -127(nan), 23(3.222986e-44)
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,
; EG-NEXT: AND_INT T1.Y, T3.W, literal.x,
; EG-NEXT: LSHL T0.Z, T2.W, PV.Z, BS:VEC_120/SCL_212
; EG-NEXT: AND_INT T3.W, KC0[4].X, literal.y,
; EG-NEXT: ADD_INT * T4.W, PV.Y, literal.z,
; EG-NEXT: 32(4.484155e-44), 8388607(1.175494e-38)
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: AND_INT T2.Y, PS, literal.x,
; EG-NEXT: OR_INT T1.Z, PV.W, literal.y,
; EG-NEXT: CNDE_INT T3.W, PV.Y, PV.X, PV.Z,
; EG-NEXT: SETGT_INT * T5.W, T0.X, literal.z,
; EG-NEXT: 31(4.344025e-44), 8388608(1.175494e-38)
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T2.X, PS, 0.0, PV.W,
; EG-NEXT: OR_INT T1.Y, PV.Z, literal.x,
; EG-NEXT: ADD_INT T0.Z, T2.W, literal.y,
; EG-NEXT: CNDE_INT T1.W, PV.X, PV.Y, 0.0,
; EG-NEXT: CNDE_INT * T3.W, T2.Z, T3.W, 0.0,
; EG-NEXT: 8388608(1.175494e-38), -150(nan)
; EG-NEXT: CNDE_INT T1.X, T4.W, PV.W, PS,
; EG-NEXT: ASHR T2.Y, KC0[4].X, literal.x,
; EG-NEXT: AND_INT T1.Z, PV.Z, literal.x,
; EG-NEXT: NOT_INT T1.W, PV.Z,
; EG-NEXT: LSHR * T3.W, PV.Y, 1,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
; EG-NEXT: LSHL T3.Y, T1.Y, PV.Z,
; EG-NEXT: XOR_INT T1.Z, PV.X, PV.Y,
; EG-NEXT: XOR_INT T1.W, T2.X, PV.Y,
; EG-NEXT: SUB_INT * T2.W, literal.x, T2.W,
; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT: AND_INT T1.X, T0.Z, literal.x,
; EG-NEXT: AND_INT T4.Y, PS, literal.x,
; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, T1.Y, PS, BS:VEC_021/SCL_122
; EG-NEXT: SUB_INT T1.W, PV.W, T2.Y,
; EG-NEXT: SUBB_UINT * T2.W, PV.Z, T2.Y,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: SUB_INT T2.X, PV.W, PS,
; EG-NEXT: CNDE_INT T1.Y, PV.Y, PV.Z, 0.0,
; EG-NEXT: CNDE_INT T0.Z, PV.X, T3.Y, 0.0,
; EG-NEXT: CNDE_INT T1.W, PV.X, T3.X, T3.Y, BS:VEC_021/SCL_122
; EG-NEXT: SETGT_INT * T2.W, T0.Y, literal.x,
; EG-NEXT: CNDE_INT T3.Y, PS, 0.0, PV.W,
; EG-NEXT: SUB_INT T2.Z, literal.x, T1.W,
; EG-NEXT: LSHL T1.W, PV.Z, PV.Y,
; EG-NEXT: AND_INT * T3.W, T4.W, literal.y,
; EG-NEXT: 150(2.101948e-43), 32(4.484155e-44)
; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,
; EG-NEXT: AND_INT T2.Y, PV.Z, literal.x,
; EG-NEXT: SUB_INT T3.Z, literal.y, T0.Y,
; EG-NEXT: NOT_INT T4.W, T4.W,
; EG-NEXT: LSHR * T6.W, T1.Z, 1,
; EG-NEXT: 32(4.484155e-44), 150(2.101948e-43)
; EG-NEXT: BIT_ALIGN_INT T2.X, 0.0, T2.W, T2.Z,
; EG-NEXT: ADD_INT T0.Y, T0.Y, literal.x,
; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PS, PV.W,
; EG-NEXT: BIT_ALIGN_INT T2.W, 0.0, T1.Z, PV.Z,
; EG-NEXT: AND_INT * T4.W, PV.Z, literal.y,
; EG-NEXT: -127(nan), 32(4.484155e-44)
; EG-NEXT: CNDE_INT T3.X, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T4.Y, T3.W, PV.Z, T1.W,
; EG-NEXT: SETGT_INT T1.Z, PV.Y, literal.x,
; EG-NEXT: CNDE_INT T1.W, T1.Y, T0.Z, 0.0,
; EG-NEXT: CNDE_INT * T2.W, T2.Y, PV.X, 0.0,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: BFE_UINT T1.X, KC0[3].W, literal.x, T0.W,
; EG-NEXT: AND_INT T3.Y, KC0[3].W, literal.y,
; EG-NEXT: CNDE_INT T2.Z, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T1.W, PS, PV.Y, PV.Z,
; EG-NEXT: ASHR * T2.W, KC0[3].Z, literal.z,
; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
; EG-NEXT: CNDE_INT T2.X, T5.W, PS, PV.W,
; EG-NEXT: ASHR T1.Y, KC0[3].Z, literal.x,
; EG-NEXT: CNDE_INT T0.Z, PV.Z, 0.0, PV.Y,
; EG-NEXT: CNDE_INT T1.W, PV.Z, PV.X, T1.X,
; EG-NEXT: ASHR * T2.W, KC0[4].X, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: BFE_UINT T3.X, KC0[3].Y, literal.x, T0.W,
; EG-NEXT: XOR_INT T1.Y, PV.W, PS,
; EG-NEXT: XOR_INT T2.Y, PV.W, PS,
; EG-NEXT: XOR_INT T0.Z, PV.Z, PS,
; EG-NEXT: OR_INT T0.W, PV.Y, literal.y,
; EG-NEXT: SUB_INT * T1.W, literal.z, PV.X,
; EG-NEXT: 23(3.222986e-44), 8388608(1.175494e-38)
; EG-NEXT: XOR_INT T1.W, PV.X, PV.Y,
; EG-NEXT: XOR_INT * T3.W, T3.Y, PV.Y,
; EG-NEXT: SUB_INT T3.Y, PS, T1.Y,
; EG-NEXT: SUBB_UINT T1.Z, PV.W, T1.Y,
; EG-NEXT: SUB_INT T3.W, PV.Z, T2.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T2.W,
; EG-NEXT: SUB_INT T4.Y, PV.W, PS,
; EG-NEXT: SUB_INT T0.Z, PV.Y, PV.Z,
; EG-NEXT: BFE_UINT T3.W, KC0[3].Y, literal.x, T0.W,
; EG-NEXT: AND_INT * T4.W, KC0[3].Y, literal.y,
; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
; EG-NEXT: SETGT_INT T0.X, 0.0, T0.X,
; EG-NEXT: ADD_INT T3.Y, PV.W, literal.x,
; EG-NEXT: OR_INT T1.Z, PS, literal.y,
; EG-NEXT: BFE_UINT T0.W, KC0[3].W, literal.z, T0.W,
; EG-NEXT: ADD_INT * T4.W, PV.W, literal.w,
; EG-NEXT: -127(nan), 8388608(1.175494e-38)
; EG-NEXT: 23(3.222986e-44), -150(nan)
; EG-NEXT: AND_INT T1.X, KC0[3].W, literal.x,
; EG-NEXT: ADD_INT T5.Y, PV.W, literal.y,
; EG-NEXT: SUB_INT T2.Z, literal.z, T3.W,
; EG-NEXT: NOT_INT T3.W, PS,
; EG-NEXT: LSHR * T5.W, PV.Z, 1,
; EG-NEXT: 8388607(1.175494e-38), -150(nan)
; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT: AND_INT T4.X, KC0[3].Y, literal.x,
; EG-NEXT: AND_INT T3.Y, PS, literal.y,
; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PV.W, PS,
; EG-NEXT: SUB_INT T1.W, PV.Z, T2.W,
; EG-NEXT: SUBB_UINT * T3.W, PV.Y, T2.W,
; EG-NEXT: 8388607(1.175494e-38), 32(4.484155e-44)
; EG-NEXT: SUB_INT T5.X, PV.W, PS,
; EG-NEXT: SETGT_INT T0.Y, 0.0, T0.Y,
; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
; EG-NEXT: OR_INT T1.W, PV.X, literal.x,
; EG-NEXT: ADD_INT * T3.W, T3.X, literal.y,
; EG-NEXT: 8388608(1.175494e-38), -150(nan)
; EG-NEXT: ADD_INT T4.X, T3.X, literal.x,
; EG-NEXT: SUB_INT T3.Y, literal.y, T3.X,
; EG-NEXT: AND_INT T2.Z, PS, literal.z,
; EG-NEXT: NOT_INT T4.W, PS,
; EG-NEXT: LSHR * T5.W, PV.W, 1,
; EG-NEXT: -127(nan), 150(2.101948e-43)
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
; EG-NEXT: LSHL T4.Y, T1.W, PV.Z,
; EG-NEXT: AND_INT T2.Z, T3.W, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: BIT_ALIGN_INT T1.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
; EG-NEXT: AND_INT * T3.W, PV.Y, literal.x,
; EG-NEXT: BIT_ALIGN_INT T2.X, 0.0, PS, PV.W,
; EG-NEXT: AND_INT T6.Y, PV.Z, literal.x,
; EG-NEXT: AND_INT T3.Z, PV.Y, literal.y,
; EG-NEXT: OR_INT T3.W, PV.X, literal.z,
; EG-NEXT: AND_INT * T5.W, T4.W, literal.y,
; EG-NEXT: 32(4.484155e-44), 31(4.344025e-44)
; EG-NEXT: 8388608(1.175494e-38), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, T1.Z, T2.Z,
; EG-NEXT: LSHL T7.Y, T1.Z, PS,
; EG-NEXT: AND_INT T1.Z, T4.W, literal.x,
; EG-NEXT: LSHL T4.W, PV.W, PV.Z,
; EG-NEXT: AND_INT * T5.W, T5.Y, literal.x,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: ADD_INT T6.X, T1.X, literal.x,
; EG-NEXT: CNDE_INT T3.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT * T3.Z, PV.Z, PV.Y, 0.0,
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: ALU clause starting at 108:
; EG-NEXT: CNDE_INT T1.W, T2.Z, T3.X, T4.Y,
; EG-NEXT: SETGT_INT * T3.W, T4.X, literal.x,
; EG-NEXT: CNDE_INT T3.X, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T8.Y, PV.Z, PV.Y, 0.0,
; EG-NEXT: CNDE_INT * T2.Z, T6.Y, PV.X, 0.0,
; EG-NEXT: ALU clause starting at 106:
; EG-NEXT: CNDE_INT T6.W, T1.Z, T2.X, T7.Y, BS:VEC_021/SCL_122
; EG-NEXT: SETGT_INT * T7.W, T3.Y, literal.x,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T3.X, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, T3.Z,
; EG-NEXT: AND_INT T2.Z, T6.X, literal.x,
; EG-NEXT: NOT_INT T1.W, T6.X,
; EG-NEXT: LSHR * T3.W, T0.W, 1,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: ASHR T7.X, KC0[3].Y, literal.x,
; EG-NEXT: ADD_INT T4.Y, T1.X, literal.y,
; EG-NEXT: BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
; EG-NEXT: LSHL T0.W, T0.W, PV.Z,
; EG-NEXT: AND_INT * T1.W, T6.X, literal.z,
; EG-NEXT: CNDE_INT T1.X, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T6.Y, PS, T2.Z, T8.Y,
; EG-NEXT: SUB_INT T1.Z, literal.x, T0.W,
; EG-NEXT: NOT_INT T6.W, T5.Y,
; EG-NEXT: LSHR * T7.W, T3.W, 1,
; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT: ASHR T2.X, KC0[3].Y, literal.x,
; EG-NEXT: ADD_INT T5.Y, T0.W, literal.y,
; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PS, PV.W,
; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, T3.W, PV.Z,
; EG-NEXT: AND_INT * T3.W, PV.Z, literal.z,
; EG-NEXT: 31(4.344025e-44), -127(nan)
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T5.Y, PS, PV.Z, PV.W,
; EG-NEXT: SETGT_INT T2.Z, PV.Y, literal.x,
; EG-NEXT: XOR_INT T0.W, T3.Y, PV.X,
; EG-NEXT: XOR_INT * T1.W, T3.X, PV.X,
; EG-NEXT: CNDE_INT T4.X, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T7.Y, T5.W, PV.Z, T4.W,
; EG-NEXT: SETGT_INT T1.Z, PV.Y, literal.x,
; EG-NEXT: XOR_INT T0.W, T6.Y, PV.X,
; EG-NEXT: XOR_INT * T3.W, T1.X, PV.X,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: SUB_INT T3.X, PS, T7.X,
; EG-NEXT: SUBB_UINT T3.Y, PV.W, T7.X,
; EG-NEXT: CNDE_INT T3.Z, PV.Z, 0.0, PV.Y,
; EG-NEXT: CNDE_INT T1.W, PV.Z, T0.Z, PV.X,
; EG-NEXT: ASHR * T3.W, KC0[3].W, literal.x,
; EG-NEXT: SUB_INT T1.X, PS, T2.X,
; EG-NEXT: SUBB_UINT T6.Y, PV.W, T2.X,
; EG-NEXT: CNDE_INT T2.Z, PV.Z, 0.0, PV.Y,
; EG-NEXT: CNDE_INT T3.W, PV.Z, PV.X, T3.X,
; EG-NEXT: ASHR * T4.W, KC0[3].W, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: XOR_INT T1.X, PV.W, PS,
; EG-NEXT: XOR_INT T5.Y, PV.Z, PS,
; EG-NEXT: SUB_INT T0.Z, PV.X, PV.Y,
; EG-NEXT: SETGT_INT T1.W, 0.0, T4.X, BS:VEC_021/SCL_122
; EG-NEXT: CNDE_INT * T6.W, T0.Y, T5.X, 0.0,
; EG-NEXT: SETGT_INT T0.X, 0.0, T0.X,
; EG-NEXT: XOR_INT T3.X, PV.W, PS,
; EG-NEXT: XOR_INT T7.Y, PV.Z, PS,
; EG-NEXT: SUB_INT T1.Z, PV.X, PV.Y,
; EG-NEXT: SETGT_INT T3.W, 0.0, T3.Y,
; EG-NEXT: CNDE_INT * T6.W, T0.X, T0.Z, 0.0,
; EG-NEXT: SETGT_INT T1.X, 0.0, T0.Y,
; EG-NEXT: CNDE_INT T6.Y, PV.W, PV.Z, 0.0,
; EG-NEXT: SUB_INT T0.Z, T1.Y, T2.W, BS:VEC_021/SCL_122
; EG-NEXT: SUB_INT T2.W, PV.Y, T3.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.X, T3.W,
; EG-NEXT: SUB_INT T3.X, PV.W, PS,
; EG-NEXT: SETGT_INT T1.Y, 0.0, T4.Y,
; EG-NEXT: CNDE_INT T6.Z, T0.Y, PV.Z, 0.0,
; EG-NEXT: SUB_INT T0.W, T0.W, T7.X, BS:VEC_021/SCL_122
; EG-NEXT: CNDE_INT * T4.W, PV.X, T2.X, 0.0,
; EG-NEXT: CNDE_INT T6.X, T1.W, PV.W, 0.0,
; EG-NEXT: CNDE_INT T4.Y, PV.Y, PV.X, 0.0,
; EG-NEXT: SUB_INT T0.W, T1.Z, T2.Y,
; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,
; EG-NEXT: SUB_INT T0.Z, T1.W, T1.Y, BS:VEC_021/SCL_122
; EG-NEXT: SUB_INT T1.W, PV.Y, T4.W,
; EG-NEXT: SUBB_UINT * T5.W, PV.X, T4.W,
; EG-NEXT: SUB_INT T4.X, PV.W, PS,
; EG-NEXT: SETGT_INT T0.Y, 0.0, T5.Y, BS:VEC_021/SCL_122
; EG-NEXT: CNDE_INT T6.Z, T0.X, PV.Z, 0.0,
; EG-NEXT: SUB_INT T0.W, T0.W, T2.X,
; EG-NEXT: CNDE_INT * T1.W, PV.X, T4.Y, 0.0,
; EG-NEXT: CNDE_INT T6.X, T3.W, PV.W, 0.0,
; EG-NEXT: CNDE_INT T1.Y, PV.Y, PV.X, 0.0,
; EG-NEXT: SUB_INT T0.W, T2.Y, T2.W,
; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T4.Z, T0.X, PV.W, 0.0,
; EG-NEXT: SUB_INT * T0.W, T1.X, T3.W, BS:VEC_120/SCL_212
; EG-NEXT: CNDE_INT T4.X, T1.Y, PV.W, 0.0,
; EG-NEXT: CNDE_INT T1.Z, T1.X, PV.W, 0.0,
; EG-NEXT: SUB_INT * T0.W, T3.X, T4.W, BS:VEC_120/SCL_212
; EG-NEXT: CNDE_INT T1.X, T0.Y, PV.W, 0.0,
; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
; EG-NEXT: LSHR * T0.X, PV.W, literal.x,
; EG-NEXT: LSHR * T2.X, PV.W, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%conv = fptosi <4 x float> %x to <4 x i64>
store <4 x i64> %conv, ptr addrspace(1) %out
Expand Down
395 changes: 196 additions & 199 deletions llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -200,25 +200,25 @@ define amdgpu_kernel void @fp_to_uint_f32_to_i64(ptr addrspace(1) %out, float %x
; EG-NEXT: ADD_INT * T2.W, PV.W, literal.y,
; EG-NEXT: 8388608(1.175494e-38), -150(nan)
; EG-NEXT: ADD_INT T0.X, T0.W, literal.x,
; EG-NEXT: SUB_INT T0.Y, literal.y, T0.W,
; EG-NEXT: AND_INT T0.Z, PS, literal.z,
; EG-NEXT: AND_INT T0.Y, PS, literal.y,
; EG-NEXT: SUB_INT T0.Z, literal.z, T0.W,
; EG-NEXT: NOT_INT T0.W, PS,
; EG-NEXT: LSHR * T3.W, PV.W, 1,
; EG-NEXT: -127(nan), 150(2.101948e-43)
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: -127(nan), 31(4.344025e-44)
; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,
; EG-NEXT: LSHL T1.Y, T1.W, PV.Z,
; EG-NEXT: AND_INT T0.Z, T2.W, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
; EG-NEXT: AND_INT * T1.W, PV.Y, literal.x,
; EG-NEXT: AND_INT T1.Y, PV.Z, literal.x,
; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, T1.W, PV.Z,
; EG-NEXT: LSHL T0.W, T1.W, PV.Y,
; EG-NEXT: AND_INT * T1.W, T2.W, literal.x,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T1.Z, PV.Z, PV.Y, 0.0,
; EG-NEXT: CNDE_INT T0.W, PV.Z, PV.X, PV.Y,
; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
; EG-NEXT: CNDE_INT T0.W, PS, PV.X, PV.W,
; EG-NEXT: SETGT_INT * T1.W, T0.X, literal.x,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T0.Z, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T0.W, PS, PV.Y, PV.Z,
; EG-NEXT: CNDE_INT T1.Z, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T0.W, PS, PV.Z, PV.Y,
; EG-NEXT: ASHR * T1.W, KC0[2].Z, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: XOR_INT T0.W, PV.W, PS,
Expand Down Expand Up @@ -288,79 +288,78 @@ define amdgpu_kernel void @fp_to_uint_v2f32_to_v2i64(ptr addrspace(1) %out, <2 x
;
; EG-LABEL: fp_to_uint_v2f32_to_v2i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 75, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 74, @4, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T0.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: MOV * T0.W, literal.x,
; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT: BFE_UINT * T1.W, KC0[2].W, literal.x, PV.W,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: AND_INT T0.Z, KC0[2].W, literal.x,
; EG-NEXT: BFE_UINT T0.W, KC0[3].X, literal.y, T0.W,
; EG-NEXT: ADD_INT * T2.W, PV.W, literal.z,
; EG-NEXT: 8388607(1.175494e-38), 23(3.222986e-44)
; EG-NEXT: BFE_UINT T0.Z, KC0[3].X, literal.x, PV.W,
; EG-NEXT: BFE_UINT T0.W, KC0[2].W, literal.x, PV.W,
; EG-NEXT: AND_INT * T1.Z, KC0[2].W, literal.y,
; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
; EG-NEXT: ADD_INT T1.W, PV.W, literal.x,
; EG-NEXT: ADD_INT * T2.W, PV.Z, literal.x,
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: SUB_INT T0.X, literal.x, PV.W,
; EG-NEXT: SUB_INT T0.Y, literal.x, T1.W,
; EG-NEXT: AND_INT T1.Z, PS, literal.y,
; EG-NEXT: OR_INT T3.W, PV.Z, literal.z,
; EG-NEXT: AND_INT T0.X, PS, literal.x,
; EG-NEXT: AND_INT T0.Y, PV.W, literal.x,
; EG-NEXT: OR_INT T1.Z, T1.Z, literal.y,
; EG-NEXT: SUB_INT T3.W, literal.z, T0.W,
; EG-NEXT: AND_INT * T4.W, KC0[3].X, literal.w,
; EG-NEXT: 150(2.101948e-43), 31(4.344025e-44)
; EG-NEXT: 8388608(1.175494e-38), 8388607(1.175494e-38)
; EG-NEXT: 31(4.344025e-44), 8388608(1.175494e-38)
; EG-NEXT: 150(2.101948e-43), 8388607(1.175494e-38)
; EG-NEXT: OR_INT T1.X, PS, literal.x,
; EG-NEXT: LSHL T1.Y, PV.W, PV.Z,
; EG-NEXT: AND_INT T0.Z, T2.W, literal.y,
; EG-NEXT: BIT_ALIGN_INT T4.W, 0.0, PV.W, PV.Y,
; EG-NEXT: AND_INT * T5.W, PV.Y, literal.y,
; EG-NEXT: AND_INT T1.Y, PV.W, literal.y,
; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PV.Z, PV.W,
; EG-NEXT: LSHL T3.W, PV.Z, PV.Y,
; EG-NEXT: AND_INT * T4.W, T1.W, literal.y,
; EG-NEXT: 8388608(1.175494e-38), 32(4.484155e-44)
; EG-NEXT: CNDE_INT T2.X, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T0.Y, PV.Z, PV.Y, 0.0,
; EG-NEXT: ADD_INT T1.Z, T0.W, literal.x,
; EG-NEXT: BIT_ALIGN_INT T4.W, 0.0, PV.X, T0.X,
; EG-NEXT: AND_INT * T5.W, T0.X, literal.y,
; EG-NEXT: -150(nan), 32(4.484155e-44)
; EG-NEXT: CNDE_INT T0.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T2.Z, PV.Y, PV.Z, 0.0,
; EG-NEXT: LSHL T5.W, PV.X, T0.X,
; EG-NEXT: AND_INT * T6.W, T2.W, literal.x,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T0.X, PS, PV.W, 0.0,
; EG-NEXT: NOT_INT T2.Y, T2.W,
; EG-NEXT: AND_INT T2.Z, PV.Z, literal.x,
; EG-NEXT: NOT_INT T2.W, PV.Z,
; EG-NEXT: LSHR * T4.W, T1.X, 1,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: LSHR T3.X, T3.W, 1,
; EG-NEXT: ADD_INT T3.Y, T0.W, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
; EG-NEXT: LSHL T0.W, T1.X, PV.Z,
; EG-NEXT: AND_INT * T2.W, T1.Z, literal.y,
; EG-NEXT: NOT_INT T1.Y, T1.W,
; EG-NEXT: SUB_INT T3.Z, literal.x, T0.Z,
; EG-NEXT: NOT_INT T1.W, T2.W, BS:VEC_120/SCL_212
; EG-NEXT: LSHR * T2.W, T1.X, 1,
; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT: LSHR T2.X, T1.Z, 1,
; EG-NEXT: ADD_INT T2.Y, T0.Z, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, PS, PV.W,
; EG-NEXT: BIT_ALIGN_INT T1.W, 0.0, T1.X, PV.Z,
; EG-NEXT: AND_INT * T2.W, PV.Z, literal.y,
; EG-NEXT: -127(nan), 32(4.484155e-44)
; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T4.Y, PS, PV.Z, PV.W,
; EG-NEXT: SETGT_INT T1.Z, PV.Y, literal.x,
; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, PV.X, T2.Y,
; EG-NEXT: ADD_INT * T1.W, T1.W, literal.y,
; EG-NEXT: CNDE_INT T3.Y, T6.W, PV.Z, T5.W, BS:VEC_021/SCL_122
; EG-NEXT: SETGT_INT T0.Z, PV.Y, literal.x,
; EG-NEXT: BIT_ALIGN_INT T1.W, 0.0, PV.X, T1.Y,
; EG-NEXT: ADD_INT * T0.W, T0.W, literal.y,
; EG-NEXT: 23(3.222986e-44), -127(nan)
; EG-NEXT: CNDE_INT T3.X, T0.Z, PV.W, T1.Y,
; EG-NEXT: CNDE_INT T2.X, T4.W, PV.W, T3.W,
; EG-NEXT: SETGT_INT T1.Y, PS, literal.x,
; EG-NEXT: CNDE_INT T0.Z, PV.Z, 0.0, PV.Y,
; EG-NEXT: CNDE_INT T0.W, PV.Z, T0.X, PV.X,
; EG-NEXT: CNDE_INT T1.Z, PV.Z, 0.0, PV.Y,
; EG-NEXT: CNDE_INT T1.W, PV.Z, PV.X, T0.X,
; EG-NEXT: ASHR * T2.W, KC0[3].X, literal.y,
; EG-NEXT: 23(3.222986e-44), 31(4.344025e-44)
; EG-NEXT: XOR_INT T0.X, PV.W, PS,
; EG-NEXT: XOR_INT T2.Y, PV.Z, PS,
; EG-NEXT: XOR_INT T3.Y, PV.Z, PS,
; EG-NEXT: CNDE_INT T0.Z, PV.Y, 0.0, PV.X,
; EG-NEXT: CNDE_INT T0.W, PV.Y, T2.X, T0.Y,
; EG-NEXT: CNDE_INT T1.W, PV.Y, T2.Z, T0.Y,
; EG-NEXT: ASHR * T3.W, KC0[2].W, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: XOR_INT T0.Y, PV.W, PS,
; EG-NEXT: XOR_INT T0.Z, PV.Z, PS,
; EG-NEXT: SUB_INT T0.W, PV.Y, T2.W,
; EG-NEXT: SUB_INT T1.W, PV.Y, T2.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.X, T2.W,
; EG-NEXT: SUB_INT T1.Y, PV.W, PS,
; EG-NEXT: SETGT_INT T1.Z, 0.0, T3.Y,
; EG-NEXT: SUB_INT T0.W, PV.Z, T3.W,
; EG-NEXT: SETGT_INT T1.Z, 0.0, T2.Y,
; EG-NEXT: SUB_INT T1.W, PV.Z, T3.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T3.W,
; EG-NEXT: SUB_INT T0.Z, PV.W, PS,
; EG-NEXT: SETGT_INT T0.W, 0.0, T1.W,
; EG-NEXT: SETGT_INT T0.W, 0.0, T0.W,
; EG-NEXT: CNDE_INT * T1.W, PV.Z, PV.Y, 0.0,
; EG-NEXT: CNDE_INT T1.Y, PV.W, PV.Z, 0.0,
; EG-NEXT: SUB_INT * T2.W, T0.X, T2.W,
Expand Down Expand Up @@ -449,170 +448,168 @@ define amdgpu_kernel void @fp_to_uint_v4f32_to_v4i64(ptr addrspace(1) %out, <4 x
;
; EG-LABEL: fp_to_uint_v4f32_to_v4i64:
; EG: ; %bb.0:
; EG-NEXT: ALU 101, @6, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 54, @108, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 0
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T2.X, 1
; EG-NEXT: ALU 99, @6, KC0[CB0:0-32], KC1[]
; EG-NEXT: ALU 54, @106, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T6.XYZW, T0.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 6:
; EG-NEXT: MOV * T0.W, literal.x,
; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)
; EG-NEXT: BFE_UINT T1.W, KC0[4].X, literal.x, PV.W,
; EG-NEXT: AND_INT * T2.W, KC0[4].X, literal.y,
; EG-NEXT: BFE_UINT T1.W, KC0[3].Z, literal.x, PV.W,
; EG-NEXT: AND_INT * T2.W, KC0[3].Z, literal.y,
; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
; EG-NEXT: OR_INT T0.Z, PS, literal.x,
; EG-NEXT: BFE_UINT T2.W, KC0[3].Z, literal.y, T0.W,
; EG-NEXT: ADD_INT * T3.W, PV.W, literal.z,
; EG-NEXT: 8388608(1.175494e-38), 23(3.222986e-44)
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: ADD_INT T0.Y, PV.W, literal.x,
; EG-NEXT: AND_INT T1.Z, PS, literal.y,
; EG-NEXT: NOT_INT T4.W, PS,
; EG-NEXT: LSHR * T5.W, PV.Z, 1,
; EG-NEXT: -127(nan), 31(4.344025e-44)
; EG-NEXT: OR_INT T2.W, PS, literal.x,
; EG-NEXT: ADD_INT * T3.W, PV.W, literal.y,
; EG-NEXT: 8388608(1.175494e-38), -150(nan)
; EG-NEXT: ADD_INT T0.X, T1.W, literal.x,
; EG-NEXT: BIT_ALIGN_INT T1.Y, 0.0, PS, PV.W,
; EG-NEXT: AND_INT T2.Z, T3.W, literal.y, BS:VEC_201
; EG-NEXT: LSHL T3.W, T0.Z, PV.Z,
; EG-NEXT: SUB_INT * T1.W, literal.z, T1.W,
; EG-NEXT: -127(nan), 32(4.484155e-44)
; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT: AND_INT T1.X, PS, literal.x,
; EG-NEXT: BIT_ALIGN_INT T2.Y, 0.0, T0.Z, PS,
; EG-NEXT: AND_INT T0.Z, KC0[3].Z, literal.y,
; EG-NEXT: CNDE_INT T1.W, PV.Z, PV.Y, PV.W,
; EG-NEXT: SETGT_INT * T4.W, PV.X, literal.z,
; EG-NEXT: BFE_UINT T0.Y, KC0[4].X, literal.y, T0.W,
; EG-NEXT: AND_INT T0.Z, PS, literal.z,
; EG-NEXT: NOT_INT T4.W, PS,
; EG-NEXT: LSHR * T5.W, PV.W, 1,
; EG-NEXT: -127(nan), 23(3.222986e-44)
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, PS, PV.W,
; EG-NEXT: AND_INT T1.Y, T3.W, literal.x,
; EG-NEXT: LSHL T0.Z, T2.W, PV.Z, BS:VEC_120/SCL_212
; EG-NEXT: AND_INT T3.W, KC0[4].X, literal.y,
; EG-NEXT: ADD_INT * T4.W, PV.Y, literal.z,
; EG-NEXT: 32(4.484155e-44), 8388607(1.175494e-38)
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: AND_INT T2.Y, PS, literal.x,
; EG-NEXT: OR_INT T1.Z, PV.W, literal.y,
; EG-NEXT: CNDE_INT T3.W, PV.Y, PV.X, PV.Z,
; EG-NEXT: SETGT_INT * T5.W, T0.X, literal.z,
; EG-NEXT: 31(4.344025e-44), 8388608(1.175494e-38)
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T2.X, PS, 0.0, PV.W,
; EG-NEXT: OR_INT T1.Y, PV.Z, literal.x,
; EG-NEXT: ADD_INT T0.Z, T2.W, literal.y,
; EG-NEXT: CNDE_INT T1.W, PV.X, PV.Y, 0.0,
; EG-NEXT: CNDE_INT * T3.W, T2.Z, T3.W, 0.0,
; EG-NEXT: 8388608(1.175494e-38), -150(nan)
; EG-NEXT: CNDE_INT T1.X, T4.W, PV.W, PS,
; EG-NEXT: ASHR T2.Y, KC0[4].X, literal.x,
; EG-NEXT: AND_INT T1.Z, PV.Z, literal.x,
; EG-NEXT: NOT_INT T1.W, PV.Z,
; EG-NEXT: LSHR * T3.W, PV.Y, 1,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
; EG-NEXT: LSHL T3.Y, T1.Y, PV.Z,
; EG-NEXT: XOR_INT T1.Z, PV.X, PV.Y,
; EG-NEXT: XOR_INT T1.W, T2.X, PV.Y,
; EG-NEXT: SUB_INT * T2.W, literal.x, T2.W,
; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT: AND_INT T1.X, T0.Z, literal.x,
; EG-NEXT: AND_INT T4.Y, PS, literal.x,
; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, T1.Y, PS, BS:VEC_021/SCL_122
; EG-NEXT: SUB_INT T1.W, PV.W, T2.Y,
; EG-NEXT: SUBB_UINT * T2.W, PV.Z, T2.Y,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: SUB_INT T2.X, PV.W, PS,
; EG-NEXT: CNDE_INT T1.Y, PV.Y, PV.Z, 0.0,
; EG-NEXT: CNDE_INT T0.Z, PV.X, T3.Y, 0.0,
; EG-NEXT: CNDE_INT T1.W, PV.X, T3.X, T3.Y, BS:VEC_021/SCL_122
; EG-NEXT: SETGT_INT * T2.W, T0.Y, literal.x,
; EG-NEXT: CNDE_INT T3.Y, PS, 0.0, PV.W,
; EG-NEXT: SUB_INT T2.Z, literal.x, T1.W,
; EG-NEXT: LSHL T1.W, PV.Z, PV.Y,
; EG-NEXT: AND_INT * T3.W, T4.W, literal.y,
; EG-NEXT: 150(2.101948e-43), 32(4.484155e-44)
; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,
; EG-NEXT: AND_INT T2.Y, PV.Z, literal.x,
; EG-NEXT: SUB_INT T3.Z, literal.y, T0.Y,
; EG-NEXT: NOT_INT T4.W, T4.W,
; EG-NEXT: LSHR * T6.W, T1.Z, 1,
; EG-NEXT: 32(4.484155e-44), 150(2.101948e-43)
; EG-NEXT: BIT_ALIGN_INT T2.X, 0.0, T2.W, T2.Z,
; EG-NEXT: ADD_INT T0.Y, T0.Y, literal.x,
; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PS, PV.W,
; EG-NEXT: BIT_ALIGN_INT T2.W, 0.0, T1.Z, PV.Z,
; EG-NEXT: AND_INT * T4.W, PV.Z, literal.y,
; EG-NEXT: -127(nan), 32(4.484155e-44)
; EG-NEXT: CNDE_INT T3.X, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T4.Y, T3.W, PV.Z, T1.W,
; EG-NEXT: SETGT_INT T1.Z, PV.Y, literal.x,
; EG-NEXT: CNDE_INT T1.W, T1.Y, T0.Z, 0.0,
; EG-NEXT: CNDE_INT * T2.W, T2.Y, PV.X, 0.0,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: BFE_UINT T1.X, KC0[3].W, literal.x, T0.W,
; EG-NEXT: AND_INT T3.Y, KC0[3].W, literal.y,
; EG-NEXT: CNDE_INT T2.Z, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T1.W, PS, PV.Y, PV.Z,
; EG-NEXT: ASHR * T2.W, KC0[3].Z, literal.z,
; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
; EG-NEXT: CNDE_INT T2.X, T5.W, PS, PV.W,
; EG-NEXT: ASHR T1.Y, KC0[3].Z, literal.x,
; EG-NEXT: CNDE_INT T0.Z, PV.Z, 0.0, PV.Y,
; EG-NEXT: CNDE_INT T1.W, PV.Z, PV.X, T1.X,
; EG-NEXT: ASHR * T2.W, KC0[4].X, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: BFE_UINT T3.X, KC0[3].Y, literal.x, T0.W,
; EG-NEXT: XOR_INT T1.Y, PV.W, PS,
; EG-NEXT: XOR_INT T2.Y, PV.W, PS,
; EG-NEXT: XOR_INT T0.Z, PV.Z, PS,
; EG-NEXT: OR_INT T0.W, PV.Y, literal.y,
; EG-NEXT: SUB_INT * T1.W, literal.z, PV.X,
; EG-NEXT: 23(3.222986e-44), 8388608(1.175494e-38)
; EG-NEXT: XOR_INT T1.W, PV.X, PV.Y,
; EG-NEXT: XOR_INT * T3.W, T3.Y, PV.Y,
; EG-NEXT: SUB_INT T3.Y, PS, T1.Y,
; EG-NEXT: SUBB_UINT T1.Z, PV.W, T1.Y,
; EG-NEXT: SUB_INT T3.W, PV.Z, T2.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.Y, T2.W,
; EG-NEXT: SUB_INT T4.Y, PV.W, PS,
; EG-NEXT: SUB_INT T0.Z, PV.Y, PV.Z,
; EG-NEXT: BFE_UINT T3.W, KC0[3].Y, literal.x, T0.W,
; EG-NEXT: AND_INT * T4.W, KC0[3].Y, literal.y,
; EG-NEXT: 23(3.222986e-44), 8388607(1.175494e-38)
; EG-NEXT: SETGT_INT T0.X, 0.0, T0.X,
; EG-NEXT: ADD_INT T3.Y, PV.W, literal.x,
; EG-NEXT: OR_INT T1.Z, PS, literal.y,
; EG-NEXT: BFE_UINT T0.W, KC0[3].W, literal.z, T0.W,
; EG-NEXT: ADD_INT * T4.W, PV.W, literal.w,
; EG-NEXT: -127(nan), 8388608(1.175494e-38)
; EG-NEXT: 23(3.222986e-44), -150(nan)
; EG-NEXT: AND_INT T1.X, KC0[3].W, literal.x,
; EG-NEXT: ADD_INT T5.Y, PV.W, literal.y,
; EG-NEXT: SUB_INT T2.Z, literal.z, T3.W,
; EG-NEXT: NOT_INT T3.W, PS,
; EG-NEXT: LSHR * T5.W, PV.Z, 1,
; EG-NEXT: 8388607(1.175494e-38), -150(nan)
; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT: AND_INT T4.X, KC0[3].Y, literal.x,
; EG-NEXT: AND_INT T3.Y, PS, literal.y,
; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PV.W, PS,
; EG-NEXT: SUB_INT T1.W, PV.Z, T2.W,
; EG-NEXT: SUBB_UINT * T3.W, PV.Y, T2.W,
; EG-NEXT: 8388607(1.175494e-38), 32(4.484155e-44)
; EG-NEXT: SUB_INT T5.X, PV.W, PS,
; EG-NEXT: SETGT_INT T0.Y, 0.0, T0.Y,
; EG-NEXT: CNDE_INT T0.Z, PV.Y, PV.Z, 0.0,
; EG-NEXT: OR_INT T1.W, PV.X, literal.x,
; EG-NEXT: ADD_INT * T3.W, T3.X, literal.y,
; EG-NEXT: 8388608(1.175494e-38), -150(nan)
; EG-NEXT: ADD_INT T4.X, T3.X, literal.x,
; EG-NEXT: SUB_INT T3.Y, literal.y, T3.X,
; EG-NEXT: AND_INT T2.Z, PS, literal.z,
; EG-NEXT: NOT_INT T4.W, PS,
; EG-NEXT: LSHR * T5.W, PV.W, 1,
; EG-NEXT: -127(nan), 150(2.101948e-43)
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T3.X, 0.0, PS, PV.W,
; EG-NEXT: LSHL T4.Y, T1.W, PV.Z,
; EG-NEXT: AND_INT T2.Z, T3.W, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: BIT_ALIGN_INT T1.W, 0.0, T1.W, PV.Y, BS:VEC_021/SCL_122
; EG-NEXT: AND_INT * T3.W, PV.Y, literal.x,
; EG-NEXT: BIT_ALIGN_INT T2.X, 0.0, PS, PV.W,
; EG-NEXT: AND_INT T6.Y, PV.Z, literal.x,
; EG-NEXT: AND_INT T3.Z, PV.Y, literal.y,
; EG-NEXT: OR_INT T3.W, PV.X, literal.z,
; EG-NEXT: AND_INT * T5.W, T4.W, literal.y,
; EG-NEXT: 32(4.484155e-44), 31(4.344025e-44)
; EG-NEXT: 8388608(1.175494e-38), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T1.X, 0.0, T1.Z, T2.Z,
; EG-NEXT: LSHL T7.Y, T1.Z, PS,
; EG-NEXT: AND_INT T1.Z, T4.W, literal.x,
; EG-NEXT: LSHL T4.W, PV.W, PV.Z,
; EG-NEXT: AND_INT * T5.W, T5.Y, literal.x,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: ADD_INT T6.X, T1.X, literal.x,
; EG-NEXT: CNDE_INT T3.Y, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT * T3.Z, PV.Z, PV.Y, 0.0,
; EG-NEXT: -150(nan), 0(0.000000e+00)
; EG-NEXT: ALU clause starting at 108:
; EG-NEXT: CNDE_INT T1.W, T2.Z, T3.X, T4.Y,
; EG-NEXT: SETGT_INT * T3.W, T4.X, literal.x,
; EG-NEXT: CNDE_INT T3.X, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T8.Y, PV.Z, PV.Y, 0.0,
; EG-NEXT: CNDE_INT * T2.Z, T6.Y, PV.X, 0.0,
; EG-NEXT: ALU clause starting at 106:
; EG-NEXT: CNDE_INT T6.W, T1.Z, T2.X, T7.Y, BS:VEC_021/SCL_122
; EG-NEXT: SETGT_INT * T7.W, T3.Y, literal.x,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T3.X, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T3.Y, PS, T3.Y, T3.Z,
; EG-NEXT: AND_INT T2.Z, T6.X, literal.x,
; EG-NEXT: NOT_INT T1.W, T6.X,
; EG-NEXT: LSHR * T3.W, T0.W, 1,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: ASHR T7.X, KC0[3].Y, literal.x,
; EG-NEXT: ADD_INT T4.Y, T1.X, literal.y,
; EG-NEXT: BIT_ALIGN_INT T3.Z, 0.0, PS, PV.W,
; EG-NEXT: LSHL T0.W, T0.W, PV.Z,
; EG-NEXT: AND_INT * T1.W, T6.X, literal.z,
; EG-NEXT: CNDE_INT T1.X, PS, 0.0, PV.W,
; EG-NEXT: CNDE_INT T6.Y, PS, T2.Z, T8.Y,
; EG-NEXT: SUB_INT T1.Z, literal.x, T0.W,
; EG-NEXT: NOT_INT T6.W, T5.Y,
; EG-NEXT: LSHR * T7.W, T3.W, 1,
; EG-NEXT: 150(2.101948e-43), 0(0.000000e+00)
; EG-NEXT: ASHR T2.X, KC0[3].Y, literal.x,
; EG-NEXT: ADD_INT T5.Y, T0.W, literal.y,
; EG-NEXT: BIT_ALIGN_INT T2.Z, 0.0, PS, PV.W,
; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, T3.W, PV.Z,
; EG-NEXT: AND_INT * T3.W, PV.Z, literal.z,
; EG-NEXT: 31(4.344025e-44), -127(nan)
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T1.X, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T5.Y, PS, PV.Z, PV.W,
; EG-NEXT: SETGT_INT T2.Z, PV.Y, literal.x,
; EG-NEXT: XOR_INT T0.W, T3.Y, PV.X,
; EG-NEXT: XOR_INT * T1.W, T3.X, PV.X,
; EG-NEXT: CNDE_INT T4.X, PS, PV.W, 0.0,
; EG-NEXT: CNDE_INT T7.Y, T5.W, PV.Z, T4.W,
; EG-NEXT: SETGT_INT T1.Z, PV.Y, literal.x,
; EG-NEXT: XOR_INT T0.W, T6.Y, PV.X,
; EG-NEXT: XOR_INT * T3.W, T1.X, PV.X,
; EG-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; EG-NEXT: SUB_INT T3.X, PS, T7.X,
; EG-NEXT: SUBB_UINT T3.Y, PV.W, T7.X,
; EG-NEXT: CNDE_INT T3.Z, PV.Z, 0.0, PV.Y,
; EG-NEXT: CNDE_INT T1.W, PV.Z, T0.Z, PV.X,
; EG-NEXT: ASHR * T3.W, KC0[3].W, literal.x,
; EG-NEXT: SUB_INT T1.X, PS, T2.X,
; EG-NEXT: SUBB_UINT T6.Y, PV.W, T2.X,
; EG-NEXT: CNDE_INT T2.Z, PV.Z, 0.0, PV.Y,
; EG-NEXT: CNDE_INT T3.W, PV.Z, PV.X, T3.X,
; EG-NEXT: ASHR * T4.W, KC0[3].W, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: XOR_INT T1.X, PV.W, PS,
; EG-NEXT: XOR_INT T5.Y, PV.Z, PS,
; EG-NEXT: SUB_INT T0.Z, PV.X, PV.Y,
; EG-NEXT: SETGT_INT T1.W, 0.0, T4.X, BS:VEC_021/SCL_122
; EG-NEXT: CNDE_INT * T6.W, T0.Y, T5.X, 0.0,
; EG-NEXT: SETGT_INT T0.X, 0.0, T0.X,
; EG-NEXT: XOR_INT T3.X, PV.W, PS,
; EG-NEXT: XOR_INT T7.Y, PV.Z, PS,
; EG-NEXT: SUB_INT T1.Z, PV.X, PV.Y,
; EG-NEXT: SETGT_INT T3.W, 0.0, T3.Y,
; EG-NEXT: CNDE_INT * T6.W, T0.X, T0.Z, 0.0,
; EG-NEXT: SETGT_INT T1.X, 0.0, T0.Y,
; EG-NEXT: CNDE_INT T6.Y, PV.W, PV.Z, 0.0,
; EG-NEXT: SUB_INT T0.Z, T1.Y, T2.W, BS:VEC_021/SCL_122
; EG-NEXT: SUB_INT T2.W, PV.Y, T3.W,
; EG-NEXT: SUBB_UINT * T4.W, PV.X, T3.W,
; EG-NEXT: SUB_INT T3.X, PV.W, PS,
; EG-NEXT: SETGT_INT T1.Y, 0.0, T4.Y,
; EG-NEXT: CNDE_INT T6.Z, T0.Y, PV.Z, 0.0,
; EG-NEXT: SUB_INT T0.W, T0.W, T7.X, BS:VEC_021/SCL_122
; EG-NEXT: CNDE_INT * T4.W, PV.X, T2.X, 0.0,
; EG-NEXT: CNDE_INT T6.X, T1.W, PV.W, 0.0,
; EG-NEXT: CNDE_INT T4.Y, PV.Y, PV.X, 0.0,
; EG-NEXT: SUB_INT T0.W, T1.Z, T2.Y,
; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,
; EG-NEXT: SUB_INT T0.Z, T1.W, T1.Y, BS:VEC_021/SCL_122
; EG-NEXT: SUB_INT T1.W, PV.Y, T4.W,
; EG-NEXT: SUBB_UINT * T5.W, PV.X, T4.W,
; EG-NEXT: SUB_INT T4.X, PV.W, PS,
; EG-NEXT: SETGT_INT T0.Y, 0.0, T5.Y, BS:VEC_021/SCL_122
; EG-NEXT: CNDE_INT T6.Z, T0.X, PV.Z, 0.0,
; EG-NEXT: SUB_INT T0.W, T0.W, T2.X,
; EG-NEXT: CNDE_INT * T1.W, PV.X, T4.Y, 0.0,
; EG-NEXT: CNDE_INT T6.X, T3.W, PV.W, 0.0,
; EG-NEXT: CNDE_INT T1.Y, PV.Y, PV.X, 0.0,
; EG-NEXT: SUB_INT T0.W, T2.Y, T2.W,
; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T4.Z, T0.X, PV.W, 0.0,
; EG-NEXT: SUB_INT * T0.W, T1.X, T3.W, BS:VEC_120/SCL_212
; EG-NEXT: CNDE_INT T4.X, T1.Y, PV.W, 0.0,
; EG-NEXT: CNDE_INT T1.Z, T1.X, PV.W, 0.0,
; EG-NEXT: SUB_INT * T0.W, T3.X, T4.W, BS:VEC_120/SCL_212
; EG-NEXT: CNDE_INT T1.X, T0.Y, PV.W, 0.0,
; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
; EG-NEXT: LSHR * T0.X, PV.W, literal.x,
; EG-NEXT: LSHR * T2.X, PV.W, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%conv = fptoui <4 x float> %x to <4 x i64>
store <4 x i64> %conv, ptr addrspace(1) %out
Expand Down
1,592 changes: 788 additions & 804 deletions llvm/test/CodeGen/AMDGPU/llvm.exp.ll
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1,592 changes: 788 additions & 804 deletions llvm/test/CodeGen/AMDGPU/llvm.exp10.ll
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216 changes: 109 additions & 107 deletions llvm/test/CodeGen/AMDGPU/shl.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -795,17 +795,17 @@ define amdgpu_kernel void @shl_i64(ptr addrspace(1) %out, ptr addrspace(1) %in)
; EG-NEXT: ALU clause starting at 8:
; EG-NEXT: MOV * T0.X, KC0[2].Z,
; EG-NEXT: ALU clause starting at 9:
; EG-NEXT: AND_INT T1.Y, T0.Z, literal.x,
; EG-NEXT: LSHR T1.Z, T0.Y, 1,
; EG-NEXT: LSHR T1.Y, T0.Y, 1,
; EG-NEXT: NOT_INT T1.Z, T0.Z,
; EG-NEXT: BIT_ALIGN_INT T0.W, T0.Y, T0.X, 1,
; EG-NEXT: NOT_INT * T1.W, T0.Z,
; EG-NEXT: AND_INT * T1.W, T0.Z, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T1.Z, PV.Z, PV.W, PS,
; EG-NEXT: LSHL T0.W, T0.X, PV.Y,
; EG-NEXT: LSHL T2.Z, T0.X, PS,
; EG-NEXT: BIT_ALIGN_INT T0.W, PV.Y, PV.W, PV.Z,
; EG-NEXT: AND_INT * T1.W, T0.Z, literal.x,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT * T0.Y, PS, PV.Z, PV.W,
; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0,
; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, PV.Z,
; EG-NEXT: CNDE_INT T0.X, T1.W, T2.Z, 0.0,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%b_ptr = getelementptr i64, ptr addrspace(1) %in, i64 1
Expand Down Expand Up @@ -858,8 +858,8 @@ define amdgpu_kernel void @shl_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %in
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 1 @6
; EG-NEXT: ALU 22, @11, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T0.X, 1
; EG-NEXT: ALU 23, @11, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 1
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: Fetch clause starting at 6:
Expand All @@ -868,27 +868,28 @@ define amdgpu_kernel void @shl_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %in
; EG-NEXT: ALU clause starting at 10:
; EG-NEXT: MOV * T0.X, KC0[2].Z,
; EG-NEXT: ALU clause starting at 11:
; EG-NEXT: AND_INT T1.Y, T1.Z, literal.x,
; EG-NEXT: AND_INT * T1.W, T1.Z, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: LSHL T2.X, T0.Z, PV.W,
; EG-NEXT: AND_INT T1.Y, T1.Z, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: LSHR T2.Z, T0.W, 1,
; EG-NEXT: BIT_ALIGN_INT T0.W, T0.W, T0.Z, 1,
; EG-NEXT: BIT_ALIGN_INT T0.W, T0.W, T0.Z, 1, BS:VEC_102/SCL_221
; EG-NEXT: NOT_INT * T1.W, T1.Z,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T3.X, PV.Z, PV.W, PS,
; EG-NEXT: LSHR T2.Y, T0.Y, 1,
; EG-NEXT: NOT_INT T0.Z, T1.X,
; EG-NEXT: BIT_ALIGN_INT T0.W, T0.Y, T0.X, 1,
; EG-NEXT: AND_INT * T1.W, T1.X, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T0.W, PV.Z, PV.W, PS,
; EG-NEXT: LSHL * T1.W, T0.Z, PV.Y,
; EG-NEXT: AND_INT T2.X, T1.Z, literal.x,
; EG-NEXT: AND_INT T1.Y, T1.X, literal.y,
; EG-NEXT: LSHR T0.Z, T0.Y, 1,
; EG-NEXT: BIT_ALIGN_INT T2.W, T0.Y, T0.X, 1,
; EG-NEXT: NOT_INT * T3.W, T1.X,
; EG-NEXT: 32(4.484155e-44), 31(4.344025e-44)
; EG-NEXT: BIT_ALIGN_INT T0.Y, PV.Z, PV.W, PS,
; EG-NEXT: LSHL T0.Z, T0.X, PV.Y,
; EG-NEXT: AND_INT T2.W, T1.X, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: CNDE_INT * T3.W, PV.X, T0.W, T1.W,
; EG-NEXT: LSHL T0.Y, T0.X, PS, BS:VEC_120/SCL_212
; EG-NEXT: AND_INT T1.Z, T1.X, literal.x, BS:VEC_201
; EG-NEXT: BIT_ALIGN_INT T0.W, PV.Y, PV.W, PV.Z,
; EG-NEXT: CNDE_INT * T2.W, T1.Y, PV.X, T2.X,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT T3.Y, PV.W, PV.Y, PV.Z,
; EG-NEXT: CNDE_INT * T3.Z, T2.X, T1.W, 0.0,
; EG-NEXT: CNDE_INT T3.X, T2.W, T0.Z, 0.0,
; EG-NEXT: CNDE_INT T2.Y, PV.Z, PV.W, PV.Y,
; EG-NEXT: CNDE_INT * T2.Z, T1.Y, T2.X, 0.0,
; EG-NEXT: CNDE_INT T2.X, T1.Z, T0.Y, 0.0,
; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%b_ptr = getelementptr <2 x i64>, ptr addrspace(1) %in, i64 1
Expand Down Expand Up @@ -955,65 +956,66 @@ define amdgpu_kernel void @shl_v4i64(ptr addrspace(1) %out, ptr addrspace(1) %in
; EG: ; %bb.0:
; EG-NEXT: ALU 0, @14, KC0[CB0:0-32], KC1[]
; EG-NEXT: TEX 3 @6
; EG-NEXT: ALU 47, @15, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.XYZW, T2.X, 0
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T4.XYZW, T0.X, 1
; EG-NEXT: ALU 48, @15, KC0[CB0:0-32], KC1[]
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T0.X, 0
; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XYZW, T1.X, 1
; EG-NEXT: CF_END
; EG-NEXT: Fetch clause starting at 6:
; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 48, #1
; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 0, #1
; EG-NEXT: VTX_READ_128 T3.XYZW, T0.X, 32, #1
; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 16, #1
; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 32, #1
; EG-NEXT: VTX_READ_128 T2.XYZW, T0.X, 48, #1
; EG-NEXT: VTX_READ_128 T3.XYZW, T0.X, 16, #1
; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
; EG-NEXT: ALU clause starting at 14:
; EG-NEXT: MOV * T0.X, KC0[2].Z,
; EG-NEXT: ALU clause starting at 15:
; EG-NEXT: AND_INT T4.Z, T1.Z, literal.x,
; EG-NEXT: LSHR T1.W, T0.W, 1,
; EG-NEXT: NOT_INT * T3.W, T1.Z,
; EG-NEXT: AND_INT * T1.W, T1.Z, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T4.X, T0.W, T0.Z, 1,
; EG-NEXT: AND_INT T1.Y, T3.Z, literal.x, BS:VEC_201
; EG-NEXT: LSHR T5.Z, T2.W, 1, BS:VEC_120/SCL_212
; EG-NEXT: BIT_ALIGN_INT T0.W, T2.W, T2.Z, 1, BS:VEC_102/SCL_221
; EG-NEXT: NOT_INT * T2.W, T3.Z,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T3.Y, PV.Z, PV.W, PS,
; EG-NEXT: LSHL T2.Z, T2.Z, PV.Y,
; EG-NEXT: BIT_ALIGN_INT T0.W, T1.W, PV.X, T3.W,
; EG-NEXT: LSHL * T1.W, T0.Z, T4.Z,
; EG-NEXT: LSHL * T1.W, T0.Z, PV.W,
; EG-NEXT: AND_INT T4.X, T1.Z, literal.x,
; EG-NEXT: AND_INT T1.Y, T1.X, literal.y,
; EG-NEXT: LSHR T0.Z, T0.Y, 1,
; EG-NEXT: BIT_ALIGN_INT T2.W, T0.Y, T0.X, 1,
; EG-NEXT: NOT_INT * T3.W, T1.X,
; EG-NEXT: LSHR T1.Y, T3.W, 1,
; EG-NEXT: NOT_INT T4.Z, T2.Z, BS:VEC_201
; EG-NEXT: BIT_ALIGN_INT T2.W, T3.W, T3.Z, 1,
; EG-NEXT: AND_INT * T3.W, T2.Z, literal.y,
; EG-NEXT: 32(4.484155e-44), 31(4.344025e-44)
; EG-NEXT: AND_INT T5.X, T3.Z, literal.x,
; EG-NEXT: BIT_ALIGN_INT T0.Y, PV.Z, PV.W, PS,
; EG-NEXT: LSHL T0.Z, T0.X, PV.Y,
; EG-NEXT: AND_INT T2.W, T1.X, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: CNDE_INT * T4.W, PV.X, T0.W, T1.W,
; EG-NEXT: LSHL T5.X, T3.Z, PS,
; EG-NEXT: AND_INT T2.Y, T2.Z, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: BIT_ALIGN_INT T2.Z, PV.Y, PV.W, PV.Z,
; EG-NEXT: LSHR T2.W, T3.Y, 1,
; EG-NEXT: NOT_INT * T3.W, T2.X,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T6.X, T3.Y, T3.X, 1,
; EG-NEXT: AND_INT T1.Y, T2.X, literal.x,
; EG-NEXT: LSHR T3.Z, T0.W, 1,
; EG-NEXT: BIT_ALIGN_INT T0.W, T0.W, T0.Z, 1,
; EG-NEXT: NOT_INT * T4.W, T1.Z,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T7.X, PV.Z, PV.W, PS,
; EG-NEXT: LSHL T1.Y, T3.X, PV.Y, BS:VEC_120/SCL_212
; EG-NEXT: AND_INT T0.Z, T2.X, literal.x, BS:VEC_201
; EG-NEXT: BIT_ALIGN_INT T0.W, T2.W, PV.X, T3.W,
; EG-NEXT: CNDE_INT * T3.W, T2.Y, T2.Z, T5.X,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: AND_INT T0.X, T3.X, literal.x,
; EG-NEXT: CNDE_INT T4.Y, PV.W, PV.Y, PV.Z,
; EG-NEXT: LSHR T1.Z, T2.Y, 1,
; EG-NEXT: BIT_ALIGN_INT T0.W, T2.Y, T2.X, 1,
; EG-NEXT: NOT_INT * T3.W, T3.X,
; EG-NEXT: LSHR T2.X, T0.Y, 1,
; EG-NEXT: CNDE_INT T3.Y, PV.Z, PV.W, PV.Y,
; EG-NEXT: NOT_INT T1.Z, T1.X,
; EG-NEXT: BIT_ALIGN_INT T0.W, T0.Y, T0.X, 1,
; EG-NEXT: AND_INT * T2.W, T1.X, literal.x,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: BIT_ALIGN_INT T1.X, PV.Z, PV.W, PS,
; EG-NEXT: LSHL T0.Y, T2.X, PV.X,
; EG-NEXT: CNDE_INT T4.Z, T4.X, T1.W, 0.0, BS:VEC_120/SCL_212
; EG-NEXT: AND_INT * T0.W, T3.X, literal.x, BS:VEC_201
; EG-NEXT: LSHL T0.X, T0.X, PS,
; EG-NEXT: AND_INT T0.Y, T1.X, literal.x, BS:VEC_120/SCL_212
; EG-NEXT: CNDE_INT T3.Z, T2.Y, T5.X, 0.0, BS:VEC_021/SCL_122
; EG-NEXT: BIT_ALIGN_INT * T0.W, PV.X, PV.W, PV.Z,
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT * T1.W, T5.X, T3.Y, T2.Z,
; EG-NEXT: CNDE_INT T4.X, T2.W, T0.Z, 0.0,
; EG-NEXT: CNDE_INT T1.Y, T0.W, T1.X, T0.Y, BS:VEC_120/SCL_212
; EG-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.x,
; EG-NEXT: CNDE_INT * T2.W, T4.X, T7.X, T1.W,
; EG-NEXT: CNDE_INT T3.X, T0.Z, T1.Y, 0.0,
; EG-NEXT: CNDE_INT T2.Y, T0.Y, T0.W, T0.X,
; EG-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.x,
; EG-NEXT: 16(2.242078e-44), 0(0.000000e+00)
; EG-NEXT: LSHR T0.X, PV.W, literal.x,
; EG-NEXT: CNDE_INT T1.Z, T5.X, T2.Z, 0.0,
; EG-NEXT: CNDE_INT * T1.X, T0.W, T0.Y, 0.0,
; EG-NEXT: LSHR T1.X, PV.W, literal.x,
; EG-NEXT: CNDE_INT T2.Z, T4.X, T1.W, 0.0,
; EG-NEXT: CNDE_INT * T2.X, T0.Y, T0.X, 0.0,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,
; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%b_ptr = getelementptr <4 x i64>, ptr addrspace(1) %in, i64 1
%a = load <4 x i64>, ptr addrspace(1) %in
Expand Down Expand Up @@ -1172,17 +1174,17 @@ define amdgpu_kernel void @s_shl_constant_i64(ptr addrspace(1) %out, i64 %a) {
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: AND_INT T0.Z, KC0[2].W, literal.x,
; EG-NEXT: MOV T0.W, literal.y,
; EG-NEXT: NOT_INT * T1.W, KC0[2].W,
; EG-NEXT: 31(4.344025e-44), -1(nan)
; EG-NEXT: BIT_ALIGN_INT T1.Z, literal.x, PV.W, PS,
; EG-NEXT: LSHL T0.W, literal.y, PV.Z,
; EG-NEXT: MOV T0.Z, literal.x,
; EG-NEXT: NOT_INT T0.W, KC0[2].W,
; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,
; EG-NEXT: -1(nan), 31(4.344025e-44)
; EG-NEXT: LSHL T1.Z, literal.x, PS,
; EG-NEXT: BIT_ALIGN_INT T0.W, literal.y, PV.Z, PV.W,
; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.z,
; EG-NEXT: 32767(4.591635e-41), -1(nan)
; EG-NEXT: -1(nan), 32767(4.591635e-41)
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT * T0.Y, PS, PV.Z, PV.W,
; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0,
; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, PV.Z,
; EG-NEXT: CNDE_INT T0.X, T1.W, T1.Z, 0.0,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%shl = shl i64 281474976710655, %a
Expand Down Expand Up @@ -1423,15 +1425,15 @@ define amdgpu_kernel void @s_shl_inline_imm_64_i64(ptr addrspace(1) %out, ptr ad
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: NOT_INT T0.W, KC0[2].W,
; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.x,
; EG-NEXT: AND_INT T0.W, KC0[2].W, literal.x,
; EG-NEXT: NOT_INT * T1.W, KC0[2].W,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: LSHL T0.Z, literal.x, PS,
; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, literal.y, PV.W,
; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,
; EG-NEXT: 64(8.968310e-44), 32(4.484155e-44)
; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, PV.Z,
; EG-NEXT: CNDE_INT T0.X, T1.W, T0.Z, 0.0,
; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, literal.x, PS,
; EG-NEXT: AND_INT T1.W, KC0[2].W, literal.x,
; EG-NEXT: LSHL * T0.W, literal.y, PV.W,
; EG-NEXT: 32(4.484155e-44), 64(8.968310e-44)
; EG-NEXT: CNDE_INT * T0.Y, PV.W, PV.Z, PS,
; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%shl = shl i64 64, %a
Expand Down Expand Up @@ -1903,16 +1905,16 @@ define amdgpu_kernel void @s_shl_inline_imm_f32_4_0_i64(ptr addrspace(1) %out, p
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: NOT_INT T0.W, KC0[2].W,
; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.x,
; EG-NEXT: AND_INT T0.W, KC0[2].W, literal.x,
; EG-NEXT: NOT_INT * T1.W, KC0[2].W,
; EG-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; EG-NEXT: LSHL T0.Z, literal.x, PS,
; EG-NEXT: BIT_ALIGN_INT T0.W, 0.0, literal.y, PV.W,
; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.z,
; EG-NEXT: 1082130432(4.000000e+00), 541065216(1.626303e-19)
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, PV.Z,
; EG-NEXT: CNDE_INT T0.X, T1.W, T0.Z, 0.0,
; EG-NEXT: BIT_ALIGN_INT T0.Z, 0.0, literal.x, PS,
; EG-NEXT: AND_INT T1.W, KC0[2].W, literal.y,
; EG-NEXT: LSHL * T0.W, literal.z, PV.W,
; EG-NEXT: 541065216(1.626303e-19), 32(4.484155e-44)
; EG-NEXT: 1082130432(4.000000e+00), 0(0.000000e+00)
; EG-NEXT: CNDE_INT * T0.Y, PV.W, PV.Z, PS,
; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%shl = shl i64 1082130432, %a
Expand Down Expand Up @@ -1959,17 +1961,17 @@ define amdgpu_kernel void @s_shl_inline_imm_f32_neg_4_0_i64(ptr addrspace(1) %ou
; EG-NEXT: CF_END
; EG-NEXT: PAD
; EG-NEXT: ALU clause starting at 4:
; EG-NEXT: AND_INT T0.Z, KC0[2].W, literal.x,
; EG-NEXT: MOV T0.W, literal.y,
; EG-NEXT: NOT_INT * T1.W, KC0[2].W,
; EG-NEXT: 31(4.344025e-44), -532676608(-5.534023e+19)
; EG-NEXT: BIT_ALIGN_INT T1.Z, literal.x, PV.W, PS,
; EG-NEXT: LSHL T0.W, literal.y, PV.Z,
; EG-NEXT: MOV T0.Z, literal.x,
; EG-NEXT: NOT_INT T0.W, KC0[2].W,
; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.y,
; EG-NEXT: -532676608(-5.534023e+19), 31(4.344025e-44)
; EG-NEXT: LSHL T1.Z, literal.x, PS,
; EG-NEXT: BIT_ALIGN_INT T0.W, literal.y, PV.Z, PV.W,
; EG-NEXT: AND_INT * T1.W, KC0[2].W, literal.z,
; EG-NEXT: 2147483647(nan), -1065353216(-4.000000e+00)
; EG-NEXT: -1065353216(-4.000000e+00), 2147483647(nan)
; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)
; EG-NEXT: CNDE_INT * T0.Y, PS, PV.Z, PV.W,
; EG-NEXT: CNDE_INT T0.X, T1.W, T0.W, 0.0,
; EG-NEXT: CNDE_INT * T0.Y, PS, PV.W, PV.Z,
; EG-NEXT: CNDE_INT T0.X, T1.W, T1.Z, 0.0,
; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%shl = shl i64 -1065353216, %a
Expand Down