116 changes: 56 additions & 60 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2194,7 +2194,7 @@ multiclass VPseudoBinaryEmul<VReg RetClass,
LMULInfo lmul,
LMULInfo emul,
string Constraint = "",
int sew = 0> {
int sew> {
let VLMul = lmul.value, SEW=sew in {
defvar suffix = !if(sew, "_" # lmul.MX # "_E" # sew, "_" # lmul.MX);
def suffix # "_" # emul.MX : VPseudoBinaryNoMaskPolicy<RetClass, Op1Class, Op2Class,
Expand Down Expand Up @@ -2246,14 +2246,13 @@ multiclass VPseudoBinaryV_VV_RM<LMULInfo m, string Constraint = "", bit Commutab
}

// Similar to VPseudoBinaryV_VV, but uses MxListF.
multiclass VPseudoBinaryFV_VV<LMULInfo m, string Constraint = "", int sew = 0> {
defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, Constraint, sew>;
multiclass VPseudoBinaryFV_VV<LMULInfo m, int sew> {
defm _VV : VPseudoBinary<m.vrclass, m.vrclass, m.vrclass, m, "", sew>;
}

multiclass VPseudoBinaryFV_VV_RM<LMULInfo m, string Constraint = "", int sew = 0> {
multiclass VPseudoBinaryFV_VV_RM<LMULInfo m, int sew> {
defm _VV : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m,
Constraint, sew,
UsesVXRM=0>;
"", sew, UsesVXRM=0>;
}

multiclass VPseudoVGTR_EI16_VV<string Constraint = ""> {
Expand Down Expand Up @@ -2295,14 +2294,14 @@ multiclass VPseudoVSLD1_VX<string Constraint = ""> {
}
}

multiclass VPseudoBinaryV_VF<LMULInfo m, FPR_Info f, string Constraint = "", int sew = 0> {
multiclass VPseudoBinaryV_VF<LMULInfo m, FPR_Info f, int sew> {
defm "_V" # f.FX : VPseudoBinary<m.vrclass, m.vrclass,
f.fprclass, m, Constraint, sew>;
f.fprclass, m, "", sew>;
}

multiclass VPseudoBinaryV_VF_RM<LMULInfo m, FPR_Info f, string Constraint = "", int sew = 0> {
multiclass VPseudoBinaryV_VF_RM<LMULInfo m, FPR_Info f, int sew> {
defm "_V" # f.FX : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass,
f.fprclass, m, Constraint, sew,
f.fprclass, m, "", sew,
UsesVXRM=0>;
}

Expand All @@ -2317,11 +2316,11 @@ multiclass VPseudoVSLD1_VF<string Constraint = ""> {
}
}

multiclass VPseudoBinaryV_VI<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
multiclass VPseudoBinaryV_VI<Operand ImmType, LMULInfo m, string Constraint = ""> {
defm _VI : VPseudoBinary<m.vrclass, m.vrclass, ImmType, m, Constraint>;
}

multiclass VPseudoBinaryV_VI_RM<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
multiclass VPseudoBinaryV_VI_RM<Operand ImmType, LMULInfo m, string Constraint = ""> {
defm _VI : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, ImmType, m, Constraint>;
}

Expand All @@ -2348,7 +2347,7 @@ multiclass VPseudoBinaryW_VV<LMULInfo m, bit Commutable = 0> {
Commutable=Commutable>;
}

multiclass VPseudoBinaryW_VV_RM<LMULInfo m, int sew = 0> {
multiclass VPseudoBinaryW_VV_RM<LMULInfo m, int sew> {
defm _VV : VPseudoBinaryRoundingMode<m.wvrclass, m.vrclass, m.vrclass, m,
"@earlyclobber $rd", sew, UsesVXRM=0,
TargetConstraintType=3>;
Expand All @@ -2364,7 +2363,7 @@ multiclass VPseudoBinaryW_VI<Operand ImmType, LMULInfo m> {
"@earlyclobber $rd", TargetConstraintType=3>;
}

multiclass VPseudoBinaryW_VF_RM<LMULInfo m, FPR_Info f, int sew = 0> {
multiclass VPseudoBinaryW_VF_RM<LMULInfo m, FPR_Info f, int sew> {
defm "_V" # f.FX : VPseudoBinaryRoundingMode<m.wvrclass, m.vrclass,
f.fprclass, m,
"@earlyclobber $rd", sew,
Expand All @@ -2379,7 +2378,7 @@ multiclass VPseudoBinaryW_WV<LMULInfo m> {
"@earlyclobber $rd", TargetConstraintType=3>;
}

multiclass VPseudoBinaryW_WV_RM<LMULInfo m, int sew = 0> {
multiclass VPseudoBinaryW_WV_RM<LMULInfo m, int sew> {
defm _WV : VPseudoBinaryRoundingMode<m.wvrclass, m.wvrclass, m.vrclass, m,
"@earlyclobber $rd", sew, UsesVXRM = 0,
TargetConstraintType = 3>;
Expand All @@ -2392,7 +2391,7 @@ multiclass VPseudoBinaryW_WX<LMULInfo m> {
defm "_WX" : VPseudoBinary<m.wvrclass, m.wvrclass, GPR, m, /*Constraint*/ "", TargetConstraintType=3>;
}

multiclass VPseudoBinaryW_WF_RM<LMULInfo m, FPR_Info f, int sew = 0> {
multiclass VPseudoBinaryW_WF_RM<LMULInfo m, FPR_Info f, int sew> {
defm "_W" # f.FX : VPseudoBinaryRoundingMode<m.wvrclass, m.wvrclass,
f.fprclass, m,
Constraint="",
Expand Down Expand Up @@ -2696,13 +2695,13 @@ multiclass VPseudoBinaryM_VI<LMULInfo m, int TargetConstraintType = 1> {
!if(!ge(m.octuple, 16), "@earlyclobber $rd", ""), TargetConstraintType>;
}

multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
multiclass VPseudoVGTR_VV_VX_VI<string Constraint = ""> {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VX<m, Constraint>,
SchedBinary<"WriteVRGatherVX", "ReadVRGatherVX_data",
"ReadVRGatherVX_index", mx, forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
defm "" : VPseudoBinaryV_VI<uimm5, m, Constraint>,
SchedUnary<"WriteVRGatherVI", "ReadVRGatherVI_data", mx,
forceMergeOpRead=true>;

Expand All @@ -2715,8 +2714,7 @@ multiclass VPseudoVGTR_VV_VX_VI<Operand ImmType = simm5, string Constraint = "">
}
}

multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = "",
bit Commutable = 0> {
multiclass VPseudoVSALU_VV_VX_VI<string Constraint = "", bit Commutable = 0> {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VV<m, Constraint, Commutable=Commutable>,
Expand All @@ -2725,13 +2723,13 @@ multiclass VPseudoVSALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""
defm "" : VPseudoBinaryV_VX<m, Constraint>,
SchedBinary<"WriteVSALUX", "ReadVSALUV", "ReadVSALUX", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
defm "" : VPseudoBinaryV_VI<simm5, m, Constraint>,
SchedUnary<"WriteVSALUI", "ReadVSALUV", mx, forceMergeOpRead=true>;
}
}


multiclass VPseudoVSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
multiclass VPseudoVSHT_VV_VX_VI<string Constraint = ""> {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VV<m, Constraint>,
Expand All @@ -2740,12 +2738,12 @@ multiclass VPseudoVSHT_VV_VX_VI<Operand ImmType = simm5, string Constraint = "">
defm "" : VPseudoBinaryV_VX<m, Constraint>,
SchedBinary<"WriteVShiftX", "ReadVShiftV", "ReadVShiftX", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
defm "" : VPseudoBinaryV_VI<uimm5, m, Constraint>,
SchedUnary<"WriteVShiftI", "ReadVShiftV", mx, forceMergeOpRead=true>;
}
}

multiclass VPseudoVSSHT_VV_VX_VI_RM<Operand ImmType = simm5, string Constraint = ""> {
multiclass VPseudoVSSHT_VV_VX_VI_RM<string Constraint = ""> {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VV_RM<m, Constraint>,
Expand All @@ -2754,13 +2752,12 @@ multiclass VPseudoVSSHT_VV_VX_VI_RM<Operand ImmType = simm5, string Constraint =
defm "" : VPseudoBinaryV_VX_RM<m, Constraint>,
SchedBinary<"WriteVSShiftX", "ReadVSShiftV", "ReadVSShiftX", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VI_RM<ImmType, m, Constraint>,
defm "" : VPseudoBinaryV_VI_RM<uimm5, m, Constraint>,
SchedUnary<"WriteVSShiftI", "ReadVSShiftV", mx, forceMergeOpRead=true>;
}
}

multiclass VPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = "",
bit Commutable = 0> {
multiclass VPseudoVALU_VV_VX_VI<string Constraint = "", bit Commutable = 0> {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VV<m, Constraint, Commutable=Commutable>,
Expand All @@ -2769,7 +2766,7 @@ multiclass VPseudoVALU_VV_VX_VI<Operand ImmType = simm5, string Constraint = "",
defm "" : VPseudoBinaryV_VX<m, Constraint>,
SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VI<ImmType, m, Constraint>,
defm "" : VPseudoBinaryV_VI<simm5, m, Constraint>,
SchedUnary<"WriteVIALUI", "ReadVIALUV", mx, forceMergeOpRead=true>;
}
}
Expand Down Expand Up @@ -2846,14 +2843,14 @@ multiclass VPseudoVDIV_VV_VX {
multiclass VPseudoVFMUL_VV_VF_RM {
foreach m = MxListF in {
foreach e = SchedSEWSet<m.MX, isF=1>.val in
defm "" : VPseudoBinaryFV_VV_RM<m, "", sew=e>,
defm "" : VPseudoBinaryFV_VV_RM<m, e>,
SchedBinary<"WriteVFMulV", "ReadVFMulV", "ReadVFMulV", m.MX, e,
forceMergeOpRead=true>;
}

foreach f = FPList in {
foreach m = f.MxList in {
defm "" : VPseudoBinaryV_VF_RM<m, f, "", sew=f.SEW>,
defm "" : VPseudoBinaryV_VF_RM<m, f, f.SEW>,
SchedBinary<"WriteVFMulF", "ReadVFMulV", "ReadVFMulF", m.MX,
f.SEW, forceMergeOpRead=true>;
}
Expand All @@ -2865,15 +2862,15 @@ multiclass VPseudoVFDIV_VV_VF_RM {
defvar mx = m.MX;
defvar sews = SchedSEWSet<mx, isF=1>.val;
foreach e = sews in {
defm "" : VPseudoBinaryFV_VV_RM<m, "", e>,
defm "" : VPseudoBinaryFV_VV_RM<m, e>,
SchedBinary<"WriteVFDivV", "ReadVFDivV", "ReadVFDivV", mx, e,
forceMergeOpRead=true>;
}
}

foreach f = FPList in {
foreach m = f.MxList in {
defm "" : VPseudoBinaryV_VF_RM<m, f, "", f.SEW>,
defm "" : VPseudoBinaryV_VF_RM<m, f, f.SEW>,
SchedBinary<"WriteVFDivF", "ReadVFDivV", "ReadVFDivF", m.MX, f.SEW,
forceMergeOpRead=true>;
}
Expand All @@ -2883,7 +2880,7 @@ multiclass VPseudoVFDIV_VV_VF_RM {
multiclass VPseudoVFRDIV_VF_RM {
foreach f = FPList in {
foreach m = f.MxList in {
defm "" : VPseudoBinaryV_VF_RM<m, f, "", f.SEW>,
defm "" : VPseudoBinaryV_VF_RM<m, f, f.SEW>,
SchedBinary<"WriteVFDivF", "ReadVFDivV", "ReadVFDivF", m.MX, f.SEW,
forceMergeOpRead=true>;
}
Expand Down Expand Up @@ -2938,14 +2935,14 @@ multiclass VPseudoVMAX_VV_VF {
multiclass VPseudoVALU_VV_VF_RM {
foreach m = MxListF in {
foreach e = SchedSEWSet<m.MX, isF=1>.val in
defm "" : VPseudoBinaryFV_VV_RM<m, "", sew=e>,
defm "" : VPseudoBinaryFV_VV_RM<m, e>,
SchedBinary<"WriteVFALUV", "ReadVFALUV", "ReadVFALUV", m.MX, e,
forceMergeOpRead=true>;
}

foreach f = FPList in {
foreach m = f.MxList in {
defm "" : VPseudoBinaryV_VF_RM<m, f, "", sew=f.SEW>,
defm "" : VPseudoBinaryV_VF_RM<m, f, f.SEW>,
SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX,
f.SEW, forceMergeOpRead=true>;
}
Expand All @@ -2955,20 +2952,20 @@ multiclass VPseudoVALU_VV_VF_RM {
multiclass VPseudoVALU_VF_RM {
foreach f = FPList in {
foreach m = f.MxList in {
defm "" : VPseudoBinaryV_VF_RM<m, f, "", sew=f.SEW>,
defm "" : VPseudoBinaryV_VF_RM<m, f, f.SEW>,
SchedBinary<"WriteVFALUF", "ReadVFALUV", "ReadVFALUF", m.MX,
f.SEW, forceMergeOpRead=true>;
}
}
}

multiclass VPseudoVALU_VX_VI<Operand ImmType = simm5> {
multiclass VPseudoVALU_VX_VI {
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoBinaryV_VX<m>,
SchedBinary<"WriteVIALUX", "ReadVIALUV", "ReadVIALUX", mx,
forceMergeOpRead=true>;
defm "" : VPseudoBinaryV_VI<ImmType, m>,
defm "" : VPseudoBinaryV_VI<simm5, m>,
SchedUnary<"WriteVIALUI", "ReadVIALUV", mx, forceMergeOpRead=true>;
}
}
Expand Down Expand Up @@ -3248,8 +3245,8 @@ multiclass VPseudoTernaryWithPolicyRoundingMode<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class,
LMULInfo MInfo,
string Constraint = "",
int sew = 0,
string Constraint,
int sew,
bit Commutable = 0,
int TargetConstraintType = 1> {
let VLMul = MInfo.value in {
Expand All @@ -3273,7 +3270,7 @@ multiclass VPseudoTernaryV_VV_AAXA<LMULInfo m, string Constraint = ""> {
Constraint, Commutable=1>;
}

multiclass VPseudoTernaryV_VV_AAXA_RM<LMULInfo m, string Constraint = "", int sew = 0> {
multiclass VPseudoTernaryV_VV_AAXA_RM<LMULInfo m, string Constraint, int sew> {
defm _VV : VPseudoTernaryWithPolicyRoundingMode<m.vrclass, m.vrclass, m.vrclass, m,
Constraint, sew, Commutable=1>;
}
Expand All @@ -3284,7 +3281,7 @@ multiclass VPseudoTernaryV_VX_AAXA<LMULInfo m, string Constraint = ""> {
}

multiclass VPseudoTernaryV_VF_AAXA_RM<LMULInfo m, FPR_Info f,
string Constraint = "", int sew = 0> {
string Constraint, int sew> {
defm "_V" # f.FX : VPseudoTernaryWithPolicyRoundingMode<m.vrclass, f.fprclass,
m.vrclass, m, Constraint,
sew, Commutable=1>;
Expand All @@ -3296,7 +3293,7 @@ multiclass VPseudoTernaryW_VV<LMULInfo m, bit Commutable = 0> {
constraint, Commutable=Commutable, TargetConstraintType=3>;
}

multiclass VPseudoTernaryW_VV_RM<LMULInfo m, int sew = 0> {
multiclass VPseudoTernaryW_VV_RM<LMULInfo m, int sew> {
defvar constraint = "@earlyclobber $rd";
defm _VV : VPseudoTernaryWithPolicyRoundingMode<m.wvrclass, m.vrclass, m.vrclass, m,
constraint, sew, /* Commutable */ 0,
Expand All @@ -3309,7 +3306,7 @@ multiclass VPseudoTernaryW_VX<LMULInfo m> {
constraint, /*Commutable*/ 0, TargetConstraintType=3>;
}

multiclass VPseudoTernaryW_VF_RM<LMULInfo m, FPR_Info f, int sew = 0> {
multiclass VPseudoTernaryW_VF_RM<LMULInfo m, FPR_Info f, int sew> {
defvar constraint = "@earlyclobber $rd";
defm "_V" # f.FX : VPseudoTernaryWithPolicyRoundingMode<m.wvrclass, f.fprclass,
m.vrclass, m, constraint,
Expand All @@ -3333,8 +3330,8 @@ multiclass VPseudoVSLDV_VX<LMULInfo m, string Constraint = ""> {
defm _VX : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, GPR, m, Constraint>;
}

multiclass VPseudoVSLDV_VI<Operand ImmType = simm5, LMULInfo m, string Constraint = ""> {
defm _VI : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, ImmType, m, Constraint>;
multiclass VPseudoVSLDV_VI<LMULInfo m, string Constraint = ""> {
defm _VI : VPseudoVSLDVWithPolicy<m.vrclass, m.vrclass, uimm5, m, Constraint>;
}

multiclass VPseudoVMAC_VV_VX_AAXA<string Constraint = ""> {
Expand Down Expand Up @@ -3366,15 +3363,14 @@ multiclass VPseudoVMAC_VV_VF_AAXA_RM<string Constraint = ""> {
}
}

multiclass VPseudoVSLD_VX_VI<Operand ImmType = simm5, bit slidesUp = false,
string Constraint = ""> {
multiclass VPseudoVSLD_VX_VI<bit slidesUp = false, string Constraint = ""> {
defvar WriteSlideX = !if(slidesUp, "WriteVSlideUpX", "WriteVSlideDownX");
foreach m = MxList in {
defvar mx = m.MX;
defm "" : VPseudoVSLDV_VX<m, Constraint>,
SchedTernary<WriteSlideX, "ReadVISlideV", "ReadVISlideV",
"ReadVISlideX", mx>;
defm "" : VPseudoVSLDV_VI<ImmType, m, Constraint>,
defm "" : VPseudoVSLDV_VI<m, Constraint>,
SchedBinary<"WriteVSlideI", "ReadVISlideV", "ReadVISlideV", mx>;
}
}
Expand Down Expand Up @@ -5441,7 +5437,7 @@ multiclass VPatBinaryV_VV_VX_VI<string intrinsic, string instruction,
VPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType>;

multiclass VPatBinaryV_VV_VX_VI_RM<string intrinsic, string instruction,
list<VTypeInfo> vtilist, Operand ImmType = simm5>
list<VTypeInfo> vtilist, Operand ImmType>
: VPatBinaryV_VV_RM<intrinsic, instruction, vtilist>,
VPatBinaryV_VX_RM<intrinsic, instruction, vtilist>,
VPatBinaryV_VI_RM<intrinsic, instruction, vtilist, ImmType>;
Expand Down Expand Up @@ -5777,7 +5773,7 @@ multiclass VPatTernaryV_VV_VX_AAXA_RM<string intrinsic, string instruction,
VPatTernaryV_VX_AAXA_RM<intrinsic, instruction, vtilist, isSEWAware>;

multiclass VPatTernaryV_VX_VI<string intrinsic, string instruction,
list<VTypeInfo> vtilist, Operand Imm_type = simm5>
list<VTypeInfo> vtilist, Operand Imm_type>
: VPatTernaryV_VX<intrinsic, instruction, vtilist>,
VPatTernaryV_VI<intrinsic, instruction, vtilist, Imm_type>;

Expand Down Expand Up @@ -5809,7 +5805,7 @@ multiclass VPatBinaryM_VX_VI<string intrinsic, string instruction,
VPatBinaryM_VI<intrinsic, instruction, vtilist>;

multiclass VPatBinaryV_VV_VX_VI_INT<string intrinsic, string instruction,
list<VTypeInfo> vtilist, Operand ImmType = simm5>
list<VTypeInfo> vtilist, Operand ImmType>
: VPatBinaryV_VV_INT<intrinsic#"_vv", instruction, vtilist>,
VPatBinaryV_VX_INT<intrinsic#"_vx", instruction, vtilist>,
VPatBinaryV_VI<intrinsic#"_vx", instruction, vtilist, ImmType>;
Expand Down Expand Up @@ -6329,9 +6325,9 @@ defm PseudoVXOR : VPseudoVALU_VV_VX_VI<Commutable=1>;
//===----------------------------------------------------------------------===//
// 11.6. Vector Single-Width Bit Shift Instructions
//===----------------------------------------------------------------------===//
defm PseudoVSLL : VPseudoVSHT_VV_VX_VI<uimm5>;
defm PseudoVSRL : VPseudoVSHT_VV_VX_VI<uimm5>;
defm PseudoVSRA : VPseudoVSHT_VV_VX_VI<uimm5>;
defm PseudoVSLL : VPseudoVSHT_VV_VX_VI;
defm PseudoVSRL : VPseudoVSHT_VV_VX_VI;
defm PseudoVSRA : VPseudoVSHT_VV_VX_VI;

//===----------------------------------------------------------------------===//
// 11.7. Vector Narrowing Integer Right Shift Instructions
Expand Down Expand Up @@ -6440,8 +6436,8 @@ let Defs = [VXSAT] in {
//===----------------------------------------------------------------------===//
// 12.4. Vector Single-Width Scaling Shift Instructions
//===----------------------------------------------------------------------===//
defm PseudoVSSRL : VPseudoVSSHT_VV_VX_VI_RM<uimm5>;
defm PseudoVSSRA : VPseudoVSSHT_VV_VX_VI_RM<uimm5>;
defm PseudoVSSRL : VPseudoVSSHT_VV_VX_VI_RM;
defm PseudoVSSRA : VPseudoVSSHT_VV_VX_VI_RM;

//===----------------------------------------------------------------------===//
// 12.5. Vector Narrowing Fixed-Point Clip Instructions
Expand Down Expand Up @@ -6826,8 +6822,8 @@ let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
// 16.3. Vector Slide Instructions
//===----------------------------------------------------------------------===//
let Predicates = [HasVInstructions] in {
defm PseudoVSLIDEUP : VPseudoVSLD_VX_VI<uimm5, /*slidesUp=*/true, "@earlyclobber $rd">;
defm PseudoVSLIDEDOWN : VPseudoVSLD_VX_VI<uimm5, /*slidesUp=*/false>;
defm PseudoVSLIDEUP : VPseudoVSLD_VX_VI</*slidesUp=*/true, "@earlyclobber $rd">;
defm PseudoVSLIDEDOWN : VPseudoVSLD_VX_VI</*slidesUp=*/false>;
defm PseudoVSLIDE1UP : VPseudoVSLD1_VX<"@earlyclobber $rd">;
defm PseudoVSLIDE1DOWN : VPseudoVSLD1_VX;
} // Predicates = [HasVInstructions]
Expand All @@ -6841,7 +6837,7 @@ let Predicates = [HasVInstructionsAnyF] in {
// 16.4. Vector Register Gather Instructions
//===----------------------------------------------------------------------===//
let Predicates = [HasVInstructions] in {
defm PseudoVRGATHER : VPseudoVGTR_VV_VX_VI<uimm5, "@earlyclobber $rd">;
defm PseudoVRGATHER : VPseudoVGTR_VV_VX_VI<"@earlyclobber $rd">;
defm PseudoVRGATHEREI16 : VPseudoVGTR_EI16_VV<Constraint = "@earlyclobber $rd">;

//===----------------------------------------------------------------------===//
Expand Down
13 changes: 5 additions & 8 deletions llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
View file
Original file line number Diff line number Diff line change
Expand Up @@ -251,11 +251,9 @@ multiclass VPseudoBinaryNoMaskPolicy_Zvk<VReg RetClass,
VReg Op1Class,
DAGOperand Op2Class,
LMULInfo MInfo,
string Constraint = "",
int sew = 0> {
let VLMul = MInfo.value, SEW=sew in {
defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX);
def suffix : VPseudoBinaryNoMaskPolicy<RetClass, Op1Class, Op2Class,
string Constraint = ""> {
let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoBinaryNoMaskPolicy<RetClass, Op1Class, Op2Class,
Constraint>;
}
}
Expand Down Expand Up @@ -1025,11 +1023,10 @@ multiclass VPatBinaryV_VV_VX_VROL<string intrinsic, string instruction,
VPatBinaryV_VI_VROL<intrinsic, instruction2, vtilist>;

multiclass VPatBinaryV_VV_VX_VI_VROR<string intrinsic, string instruction,
list<VTypeInfo> vtilist,
Operand ImmType = uimm6>
list<VTypeInfo> vtilist>
: VPatBinaryV_VV<intrinsic, instruction, vtilist>,
VPatBinaryV_VX_VROTATE<intrinsic, instruction, vtilist>,
VPatBinaryV_VI<intrinsic, instruction, vtilist, ImmType>;
VPatBinaryV_VI<intrinsic, instruction, vtilist, uimm6>;

multiclass VPatBinaryW_VV_VX_VI_VWSLL<string intrinsic, string instruction,
list<VTypeInfoToWide> vtilist>
Expand Down