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*****************************************************
Support for AArch64 Scalable Matrix Extension in LLVM
*****************************************************

.. contents::
:local:

1. Introduction
===============

The :ref:`AArch64 SME ACLE <aarch64_sme_acle>` provides a number of
attributes for users to control PSTATE.SM and PSTATE.ZA.
The :ref:`AArch64 SME ABI<aarch64_sme_abi>` describes the requirements for
calls between functions when at least one of those functions uses PSTATE.SM or
PSTATE.ZA.

This document describes how the SME ACLE attributes map to LLVM IR
attributes and how LLVM lowers these attributes to implement the rules and
requirements of the ABI.

Below we describe the LLVM IR attributes and their relation to the C/C++
level ACLE attributes:

``aarch64_pstate_sm_enabled``
is used for functions with ``__attribute__((arm_streaming))``

``aarch64_pstate_sm_compatible``
is used for functions with ``__attribute__((arm_streaming_compatible))``

``aarch64_pstate_sm_body``
is used for functions with ``__attribute__((arm_locally_streaming))`` and is
only valid on function definitions (not declarations)

``aarch64_pstate_za_new``
is used for functions with ``__attribute__((arm_new_za))``

``aarch64_pstate_za_shared``
is used for functions with ``__attribute__((arm_shared_za))``

``aarch64_pstate_za_preserved``
is used for functions with ``__attribute__((arm_preserves_za))``

Clang must ensure that the above attributes are added both to the
function's declaration/definition as well as to their call-sites. This is
important for calls to attributed function pointers, where there is no
definition or declaration available.


2. Handling PSTATE.SM
=====================

When changing PSTATE.SM the execution of FP/vector operations may be transferred
to another processing element. This has three important implications:

* The runtime SVE vector length may change.

* The contents of FP/AdvSIMD/SVE registers are zeroed.

* The set of allowable instructions changes.

This leads to certain restrictions on IR and optimizations. For example, it
is undefined behaviour to share vector-length dependent state between functions
that may operate with different values for PSTATE.SM. Front-ends must honour
these restrictions when generating LLVM IR.

Even though the runtime SVE vector length may change, for the purpose of LLVM IR
and almost all parts of CodeGen we can assume that the runtime value for
``vscale`` does not. If we let the compiler insert the appropriate ``smstart``
and ``smstop`` instructions around call boundaries, then the effects on SVE
state can be mitigated. By limiting the state changes to a very brief window
around the call we can control how the operations are scheduled and how live
values remain preserved between state transitions.

In order to control PSTATE.SM at this level of granularity, we use function and
callsite attributes rather than intrinsics.


Restrictions on attributes
--------------------------

* It is undefined behaviour to pass or return (pointers to) scalable vector
objects to/from functions which may use a different SVE vector length.
This includes functions with a non-streaming interface, but marked with
``aarch64_pstate_sm_body``.

* It is not allowed for a function to be decorated with both
``aarch64_pstate_sm_compatible`` and ``aarch64_pstate_sm_enabled``.

* It is not allowed for a function to be decorated with both
``aarch64_pstate_za_new`` and ``aarch64_pstate_za_preserved``.

* It is not allowed for a function to be decorated with both
``aarch64_pstate_za_new`` and ``aarch64_pstate_za_shared``.

These restrictions also apply in the higher level SME ACLE, which means we can
emit diagnostics in Clang to signal users about incorrect behaviour.


Compiler inserted streaming-mode changes
----------------------------------------

The table below describes the transitions in PSTATE.SM the compiler has to
account for when doing calls between functions with different attributes.
In this table, we use the following abbreviations:

``N``
functions with a normal interface (PSTATE.SM=0 on entry, PSTATE.SM=0 on
return)

``S``
functions with a Streaming interface (PSTATE.SM=1 on entry, PSTATE.SM=1
on return)

``SC``
functions with a Streaming-Compatible interface (PSTATE.SM can be
either 0 or 1 on entry, and is unchanged on return).

Functions with ``__attribute__((arm_locally_streaming))`` are excluded from this
table because for the caller the attribute is synonymous to 'streaming', and
for the callee it is merely an implementation detail that is explicitly not
exposed to the caller.

.. table:: Combinations of calls for functions with different attributes

==== ==== =============================== ============================== ==============================
From To Before call After call After exception
==== ==== =============================== ============================== ==============================
N N
N S SMSTART SMSTOP
N SC
S N SMSTOP SMSTART SMSTART
S S SMSTART
S SC SMSTART
SC N If PSTATE.SM before call is 1, If PSTATE.SM before call is 1, If PSTATE.SM before call is 1,
then SMSTOP then SMSTART then SMSTART
SC S If PSTATE.SM before call is 0, If PSTATE.SM before call is 0, If PSTATE.SM before call is 1,
then SMSTART then SMSTOP then SMSTART
SC SC If PSTATE.SM before call is 1,
then SMSTART
==== ==== =============================== ============================== ==============================


Because changing PSTATE.SM zeroes the FP/vector registers, it is best to emit
the ``smstart`` and ``smstop`` instructions before register allocation, so that
the register allocator can spill/reload registers around the mode change.

The compiler should also have sufficient information on which operations are
part of the call/function's arguments/result and which operations are part of
the function's body, so that it can place the mode changes in exactly the right
position. The suitable place to do this seems to be SelectionDAG, where it lowers
the call's arguments/return values to implement the specified calling convention.
SelectionDAG provides Chains and Glue to specify the order of operations and give
preliminary control over the instruction's scheduling.


Example of preserving state
---------------------------

When passing and returning a ``float`` value to/from a function
that has a streaming interface from a function that has a normal interface, the
call-site will need to ensure that the argument/result registers are preserved
and that no other code is scheduled in between the ``smstart/smstop`` and the call.

.. code-block:: llvm
define float @foo(float %f) nounwind {
%res = call float @bar(float %f) "aarch64_pstate_sm_enabled"
ret float %res
}
declare float @bar(float) "aarch64_pstate_sm_enabled"
The program needs to preserve the value of the floating point argument and
return value in register ``s0``:

.. code-block:: none
foo: // @foo
// %bb.0:
stp d15, d14, [sp, #-80]! // 16-byte Folded Spill
stp d13, d12, [sp, #16] // 16-byte Folded Spill
stp d11, d10, [sp, #32] // 16-byte Folded Spill
stp d9, d8, [sp, #48] // 16-byte Folded Spill
str x30, [sp, #64] // 8-byte Folded Spill
str s0, [sp, #76] // 4-byte Folded Spill
smstart sm
ldr s0, [sp, #76] // 4-byte Folded Reload
bl bar
str s0, [sp, #76] // 4-byte Folded Spill
smstop sm
ldp d9, d8, [sp, #48] // 16-byte Folded Reload
ldp d11, d10, [sp, #32] // 16-byte Folded Reload
ldp d13, d12, [sp, #16] // 16-byte Folded Reload
ldr s0, [sp, #76] // 4-byte Folded Reload
ldr x30, [sp, #64] // 8-byte Folded Reload
ldp d15, d14, [sp], #80 // 16-byte Folded Reload
ret
Setting the correct register masks on the ISD nodes and inserting the
``smstart/smstop`` in the right places should ensure this is done correctly.


Instruction Selection Nodes
---------------------------

.. code-block:: none
AArch64ISD::SMSTART Chain, [SM|ZA|Both], CurrentState, ExpectedState[, RegMask]
AArch64ISD::SMSTOP Chain, [SM|ZA|Both], CurrentState, ExpectedState[, RegMask]
The ``SMSTART/SMSTOP`` nodes take ``CurrentState`` and ``ExpectedState`` operand for
the case of a conditional SMSTART/SMSTOP. The instruction will only be executed
if CurrentState != ExpectedState.

When ``CurrentState`` and ``ExpectedState`` can be evaluated at compile-time
(i.e. they are both constants) then an unconditional ``smstart/smstop``
instruction is emitted. Otherwise the node is matched to a Pseudo instruction
which expands to a compare/branch and a ``smstart/smstop``. This is necessary to
implement transitions from ``SC -> N`` and ``SC -> S``.


Unchained Function calls
------------------------
When a function with "``aarch64_pstate_sm_enabled``" calls a function that is not
streaming compatible, the compiler has to insert a SMSTOP before the call and
insert a SMSTOP after the call.

If the function that is called is an intrinsic with no side-effects which in
turn is lowered to a function call (e.g. ``@llvm.cos()``), then the call to
``@llvm.cos()`` is not part of any Chain; it can be scheduled freely.

Lowering of a Callsite creates a small chain of nodes which:

- starts a call sequence

- copies input values from virtual registers to physical registers specified by
the ABI

- executes a branch-and-link

- stops the call sequence

- copies the output values from their physical registers to virtual registers

When the callsite's Chain is not used, only the result value from the chained
sequence is used, but the Chain itself is discarded.

The ``SMSTART`` and ``SMSTOP`` ISD nodes return a Chain, but no real
values, so when the ``SMSTART/SMSTOP`` nodes are part of a Chain that isn't
used, these nodes are not considered for scheduling and are
removed from the DAG. In order to prevent these nodes
from being removed, we need a way to ensure the results from the
``CopyFromReg`` can only be **used after** the ``SMSTART/SMSTOP`` has been
executed.

We can use a CopyToReg -> CopyFromReg sequence for this, which moves the
value to/from a virtual register and chains these nodes with the
SMSTART/SMSTOP to make them part of the expression that calculates
the result value. The resulting COPY nodes are removed by the register
allocator.

The example below shows how this is used in a DAG that does not link
together the result by a Chain, but rather by a value:

.. code-block:: none
t0: ch,glue = AArch64ISD::SMSTOP ...
t1: ch,glue = ISD::CALL ....
t2: res,ch,glue = CopyFromReg t1, ...
t3: ch,glue = AArch64ISD::SMSTART t2:1, .... <- this is now part of the expression that returns the result value.
t4: ch = CopyToReg t3, Register:f64 %vreg, t2
t5: res,ch = CopyFromReg t4, Register:f64 %vreg
t6: res = FADD t5, t9
We also need this for locally streaming functions, where an ``SMSTART`` needs to
be inserted into the DAG at the start of the function.

Functions with __attribute__((arm_locally_streaming))
-----------------------------------------------------

If a function is marked as ``arm_locally_streaming``, then the runtime SVE
vector length in the prologue/epilogue may be different from the vector length
in the function's body. This happens because we invoke smstart after setting up
the stack-frame and similarly invoke smstop before deallocating the stack-frame.

To ensure we use the correct SVE vector length to allocate the locals with, we
can use the streaming vector-length to allocate the stack-slots through the
``ADDSVL`` instruction, even when the CPU is not yet in streaming mode.

This only works for locals and not callee-save slots, since LLVM doesn't support
mixing two different scalable vector lengths in one stack frame. That means that the
case where a function is marked ``arm_locally_streaming`` and needs to spill SVE
callee-saves in the prologue is currently unsupported. However, it is unlikely
for this to happen without user intervention, because ``arm_locally_streaming``
functions cannot take or return vector-length-dependent values. This would otherwise
require forcing both the SVE PCS using '``aarch64_sve_pcs``' combined with using
``arm_locally_streaming`` in order to encounter this problem. This combination
can be prevented in Clang through emitting a diagnostic.


An example of how the prologue/epilogue would look for a function that is
attributed with ``arm_locally_streaming``:

.. code-block:: c++

#define N 64

void __attribute__((arm_streaming_compatible)) some_use(svfloat32_t *);
// Use a float argument type, to check the value isn't clobbered by smstart.
// Use a float return type to check the value isn't clobbered by smstop.
float __attribute__((noinline, arm_locally_streaming)) foo(float arg) {
// Create local for SVE vector to check local is created with correct
// size when not yet in streaming mode (ADDSVL).
float array[N];
svfloat32_t vector;

some_use(&vector);
svst1_f32(svptrue_b32(), &array[0], vector);
return array[N - 1] + arg;
}

should use ADDSVL for allocating the stack space and should avoid clobbering
the return/argument values.

.. code-block:: none
_Z3foof: // @_Z3foof
// %bb.0: // %entry
stp d15, d14, [sp, #-96]! // 16-byte Folded Spill
stp d13, d12, [sp, #16] // 16-byte Folded Spill
stp d11, d10, [sp, #32] // 16-byte Folded Spill
stp d9, d8, [sp, #48] // 16-byte Folded Spill
stp x29, x30, [sp, #64] // 16-byte Folded Spill
add x29, sp, #64
str x28, [sp, #80] // 8-byte Folded Spill
addsvl sp, sp, #-1
sub sp, sp, #256
str s0, [x29, #28] // 4-byte Folded Spill
smstart sm
sub x0, x29, #64
addsvl x0, x0, #-1
bl _Z10some_usePu13__SVFloat32_t
sub x8, x29, #64
ptrue p0.s
ld1w { z0.s }, p0/z, [x8, #-1, mul vl]
ldr s1, [x29, #28] // 4-byte Folded Reload
st1w { z0.s }, p0, [sp]
ldr s0, [sp, #252]
fadd s0, s0, s1
str s0, [x29, #28] // 4-byte Folded Spill
smstop sm
ldr s0, [x29, #28] // 4-byte Folded Reload
addsvl sp, sp, #1
add sp, sp, #256
ldp x29, x30, [sp, #64] // 16-byte Folded Reload
ldp d9, d8, [sp, #48] // 16-byte Folded Reload
ldp d11, d10, [sp, #32] // 16-byte Folded Reload
ldp d13, d12, [sp, #16] // 16-byte Folded Reload
ldr x28, [sp, #80] // 8-byte Folded Reload
ldp d15, d14, [sp], #96 // 16-byte Folded Reload
ret
Preventing the use of illegal instructions in Streaming Mode
------------------------------------------------------------

* When executing a program in streaming-mode (PSTATE.SM=1) a subset of SVE/SVE2
instructions and most AdvSIMD/NEON instructions are invalid.

* When executing a program in normal mode (PSTATE.SM=0), a subset of SME
instructions are invalid.

* Streaming-compatible functions must only use instructions that are valid when
either PSTATE.SM=0 or PSTATE.SM=1.

The value of PSTATE.SM is not controlled by the feature flags, but rather by the
function attributes. This means that we can compile for '``+sme``' and the compiler
will code-generate any instructions, even if they are not legal under the requested
streaming mode. The compiler needs to use the function attributes to ensure the
compiler doesn't do transformations under the assumption that certain operations
are available at runtime.

We made a conscious choice not to model this with feature flags, because we
still want to support inline-asm in either mode (with the user placing
smstart/smstop manually), and this became rather complicated to implement at the
individual instruction level (see `D120261 <https://reviews.llvm.org/D120261>`_
and `D121208 <https://reviews.llvm.org/D121208>`_) because of limitations in
TableGen.

As a first step, this means we'll disable vectorization (LoopVectorize/SLP)
entirely when the a function has either of the ``aarch64_pstate_sm_enabled``,
``aarch64_pstate_sm_body`` or ``aarch64_pstate_sm_compatible`` attributes,
in order to avoid the use of vector instructions.

Later on we'll aim to relax these restrictions to enable scalable
auto-vectorization with a subset of streaming-compatible instructions, but that
requires changes to the CostModel, Legalization and SelectionDAG lowering.

We will also emit diagnostics in Clang to prevent the use of
non-streaming(-compatible) operations, e.g. through ACLE intrinsics, when a
function is decorated with the streaming mode attributes.


Other things to consider
------------------------

* Inlining must be disabled when the call-site needs to toggle PSTATE.SM or
when the callee's function body is executed in a different streaming mode than
its caller. This is needed because function calls are the boundaries for
streaming mode changes.

* Tail call optimization must be disabled when the call-site needs to toggle
PSTATE.SM, such that the caller can restore the original value of PSTATE.SM.


3. Handling PSTATE.ZA
=====================

In contrast to PSTATE.SM, enabling PSTATE.ZA does not affect the SVE vector
length and also doesn't clobber FP/AdvSIMD/SVE registers. This means it is safe
to toggle PSTATE.ZA using intrinsics. This also makes it simpler to setup a
lazy-save mechanism for calls to private-ZA functions (i.e. functions that may
either directly or indirectly clobber ZA state).

For this purpose, we'll introduce a new LLVM IR pass that is run just before
SelectionDAG.

Setting up a lazy-save
----------------------

Committing a lazy-save
----------------------

Exception handling and ZA
-------------------------

4. References
=============

.. _aarch64_sme_acle:

1. `SME ACLE Pull-request <https://github.com/ARM-software/acle/pull/188>`__

.. _aarch64_sme_abi:

2. `SME ABI Pull-request <https://github.com/ARM-software/abi-aa/pull/123>`__
4 changes: 4 additions & 0 deletions llvm/docs/UserGuides.rst
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Expand Up @@ -12,6 +12,7 @@ intermediate LLVM representation.
.. toctree::
:hidden:

AArch64SME
AddingConstrainedIntrinsics
AdvancedBuilds
AliasAnalysis
Expand Down Expand Up @@ -229,6 +230,9 @@ Additional Topics
LLVM's support for generating NEON instructions on big endian ARM targets is
somewhat nonintuitive. This document explains the implementation and rationale.

:doc:`AArch64SME`
LLVM's support for AArch64 SME ACLE and ABI.

:doc:`CompileCudaWithLLVM`
LLVM support for CUDA.

Expand Down
101 changes: 101 additions & 0 deletions llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
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Expand Up @@ -89,6 +89,8 @@ class AArch64ExpandPseudo : public MachineFunctionPass {
bool expandCALL_BTI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI);
bool expandStoreSwiftAsyncContext(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI);
MachineBasicBlock *expandCondSMToggle(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI);
};

} // end anonymous namespace
Expand Down Expand Up @@ -849,6 +851,99 @@ bool AArch64ExpandPseudo::expandStoreSwiftAsyncContext(
return true;
}

MachineBasicBlock *
AArch64ExpandPseudo::expandCondSMToggle(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MBBI) {
MachineInstr &MI = *MBBI;
// In the case of a smstart/smstop before a unreachable, just remove the pseudo.
// Exception handling code generated by Clang may introduce unreachables and it
// seems unnecessary to restore pstate.sm when that happens. Note that it is
// not just an optimisation, the code below expects a successor instruction/block
// in order to split the block at MBBI.
if (std::next(MBBI) == MBB.end() &&
MI.getParent()->successors().begin() ==
MI.getParent()->successors().end()) {
MI.eraseFromParent();
return &MBB;
}

// Expand the pseudo into smstart or smstop instruction. The pseudo has the
// following operands:
//
// MSRpstatePseudo <za|sm|both>, <0|1>, pstate.sm, expectedval, <regmask>
//
// The pseudo is expanded into a conditional smstart/smstop, with a
// check if pstate.sm (register) equals the expected value, and if not,
// invokes the smstart/smstop.
//
// As an example, the following block contains a normal call from a
// streaming-compatible function:
//
// OrigBB:
// MSRpstatePseudo 3, 0, %0, 0, <regmask> <- Conditional SMSTOP
// bl @normal_callee
// MSRpstatePseudo 3, 1, %0, 0, <regmask> <- Conditional SMSTART
//
// ...which will be transformed into:
//
// OrigBB:
// TBNZx %0:gpr64, 0, SMBB
// b EndBB
//
// SMBB:
// MSRpstatesvcrImm1 3, 0, <regmask> <- SMSTOP
//
// EndBB:
// bl @normal_callee
// MSRcond_pstatesvcrImm1 3, 1, <regmask> <- SMSTART
//
DebugLoc DL = MI.getDebugLoc();

// Create the conditional branch based on the third operand of the
// instruction, which tells us if we are wrapping a normal or streaming
// function.
// We test the live value of pstate.sm and toggle pstate.sm if this is not the
// expected value for the callee (0 for a normal callee and 1 for a streaming
// callee).
auto PStateSM = MI.getOperand(2).getReg();
bool IsStreamingCallee = MI.getOperand(3).getImm();
unsigned Opc = IsStreamingCallee ? AArch64::TBZX : AArch64::TBNZX;
MachineInstrBuilder Tbx =
BuildMI(MBB, MBBI, DL, TII->get(Opc)).addReg(PStateSM).addImm(0);

// Split MBB and create two new blocks:
// - MBB now contains all instructions before MSRcond_pstatesvcrImm1.
// - SMBB contains the MSRcond_pstatesvcrImm1 instruction only.
// - EndBB contains all instructions after MSRcond_pstatesvcrImm1.
MachineInstr &PrevMI = *std::prev(MBBI);
MachineBasicBlock *SMBB = MBB.splitAt(PrevMI, /*UpdateLiveIns*/ true);
MachineBasicBlock *EndBB = std::next(MI.getIterator()) == SMBB->end()
? *SMBB->successors().begin()
: SMBB->splitAt(MI, /*UpdateLiveIns*/ true);

// Add the SMBB label to the TB[N]Z instruction & create a branch to EndBB.
Tbx.addMBB(SMBB);
BuildMI(&MBB, DL, TII->get(AArch64::B))
.addMBB(EndBB);
MBB.addSuccessor(EndBB);

// Create the SMSTART/SMSTOP (MSRpstatesvcrImm1) instruction in SMBB.
MachineInstrBuilder MIB = BuildMI(*SMBB, SMBB->begin(), MI.getDebugLoc(),
TII->get(AArch64::MSRpstatesvcrImm1));
// Copy all but the second and third operands of MSRcond_pstatesvcrImm1 (as
// these contain the CopyFromReg for the first argument and the flag to
// indicate whether the callee is streaming or normal).
MIB.add(MI.getOperand(0));
MIB.add(MI.getOperand(1));
for (unsigned i = 4; i < MI.getNumOperands(); ++i)
MIB.add(MI.getOperand(i));

BuildMI(SMBB, DL, TII->get(AArch64::B)).addMBB(EndBB);

MI.eraseFromParent();
return EndBB;
}

/// If MBBI references a pseudo instruction that should be expanded here,
/// do the expansion and return true. Otherwise return false.
bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
Expand Down Expand Up @@ -1276,6 +1371,12 @@ bool AArch64ExpandPseudo::expandMI(MachineBasicBlock &MBB,
return expandCALL_BTI(MBB, MBBI);
case AArch64::StoreSwiftAsyncContext:
return expandStoreSwiftAsyncContext(MBB, MBBI);
case AArch64::MSRpstatePseudo: {
auto *NewMBB = expandCondSMToggle(MBB, MBBI);
if (NewMBB != &MBB)
NextMBBI = MBB.end(); // The NextMBBI iterator is invalidated.
return true;
}
}
return false;
}
Expand Down
1 change: 0 additions & 1 deletion llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
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Expand Up @@ -2536,7 +2536,6 @@ MachineBasicBlock *AArch64TargetLowering::EmitInstrWithCustomInserter(

case AArch64::F128CSEL:
return EmitF128CSEL(MI, BB);

case TargetOpcode::STATEPOINT:
// STATEPOINT is a pseudo instruction which has no implicit defs/uses
// while bl call instruction (where statepoint will be lowered at the end)
Expand Down
21 changes: 21 additions & 0 deletions llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
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Expand Up @@ -147,6 +147,21 @@ def : InstAlias<"smstop sm", (MSRpstatesvcrImm1 0b001, 0b0)>;
def : InstAlias<"smstop za", (MSRpstatesvcrImm1 0b010, 0b0)>;


// Pseudo to match to smstart/smstop. This expands:
//
// pseudonode (pstate_za|pstate_sm), before_call, expected_value
//
// Into:
//
// if (before_call != expected_value)
// node (pstate_za|pstate_sm)
//
// where node can be either 'smstart' or 'smstop'.
def MSRpstatePseudo :
Pseudo<(outs),
(ins svcr_op:$pstatefield, timm0_1:$imm, GPR64:$rtpstate, timm0_1:$expected_pstate, variable_ops), []>,
Sched<[WriteSys]>;

// Scenario A:
//
// %pstate.before.call = 1
Expand Down Expand Up @@ -175,6 +190,12 @@ def : Pat<(AArch64_smstart (i32 svcr_op:$pstate), (i64 0), (i64 1)), // before
def : Pat<(AArch64_smstop (i32 svcr_op:$pstate), (i64 0), (i64 1)), // after call
(MSRpstatesvcrImm1 svcr_op:$pstate, 0b0)>;

// The generic case which gets expanded to a pseudo node.
def : Pat<(AArch64_smstart (i32 svcr_op:$pstate), (i64 GPR64:$rtpstate), (i64 timm0_1:$expected_pstate)),
(MSRpstatePseudo svcr_op:$pstate, 0b1, GPR64:$rtpstate, timm0_1:$expected_pstate)>;
def : Pat<(AArch64_smstop (i32 svcr_op:$pstate), (i64 GPR64:$rtpstate), (i64 timm0_1:$expected_pstate)),
(MSRpstatePseudo svcr_op:$pstate, 0b0, GPR64:$rtpstate, timm0_1:$expected_pstate)>;

// Read and write TPIDR2_EL0
def : Pat<(int_aarch64_sme_set_tpidr2 i64:$val),
(MSR 0xde85, GPR64:$val)>;
Expand Down
402 changes: 402 additions & 0 deletions llvm/test/CodeGen/AArch64/sme-streaming-compatible-interface.ll
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