219 changes: 132 additions & 87 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-and-scalar.mir
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Original file line number Diff line number Diff line change
@@ -1,31 +1,16 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86

--- |
define i1 @test_and_i1() {
%ret = and i1 undef, undef
ret i1 %ret
}

define i8 @test_and_i8() {
%ret = and i8 undef, undef
ret i8 %ret
}

define i16 @test_and_i16() {
%ret = and i16 undef, undef
ret i16 %ret
}

define i32 @test_and_i32() {
%ret = and i32 undef, undef
ret i32 %ret
}

define i64 @test_and_i64() {
%ret = and i64 undef, undef
ret i64 %ret
}
define void @test_and_i1() { ret void}
define void @test_and_i8() { ret void }
define void @test_and_i16() { ret void }
define void @test_and_i27() { ret void }
define void @test_and_i32() { ret void }
define void @test_and_i42() { ret void }
define void @test_and_i64() { ret void }

...
---
Expand All @@ -39,15 +24,14 @@ registers:
- { id: 2, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_and_i1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[TRUNC1]]
; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s8)
; CHECK: $eax = COPY [[ANYEXT]](s32)
; CHECK: RET 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s8)
; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET 0
%0(s32) = COPY $edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_AND %1, %1
Expand All @@ -63,95 +47,156 @@ regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
- { id: 2, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_and_i8
; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[DEF]], [[DEF]]
; CHECK: $al = COPY [[AND]](s8)
; CHECK: RET 0, implicit $al
%0(s8) = IMPLICIT_DEF
%1(s8) = G_AND %0, %0
$al = COPY %1(s8)
RET 0, implicit $al
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s8) = G_AND [[TRUNC]], [[TRUNC]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s8)
; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET 0
%0(s32) = COPY $edx
%1(s8) = G_TRUNC %0(s32)
%2(s8) = G_AND %1, %1
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
name: test_and_i16
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_and_i16
; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
; CHECK: [[AND:%[0-9]+]]:_(s16) = G_AND [[DEF]], [[DEF]]
; CHECK: $ax = COPY [[AND]](s16)
; CHECK: RET 0, implicit $ax
%0(s16) = IMPLICIT_DEF
%1(s16) = G_AND %0, %0
$ax = COPY %1(s16)
RET 0, implicit $ax
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s16) = G_AND [[TRUNC]], [[TRUNC]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[AND]](s16)
; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET 0
%0(s32) = COPY $edx
%1(s16) = G_TRUNC %0(s32)
%2(s16) = G_AND %1, %1
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
name: test_and_i27
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_and_i27
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY]]
; CHECK-NEXT: $eax = COPY [[AND]](s32)
; CHECK-NEXT: RET 0
%0(s32) = COPY $edx
%1(s27) = G_TRUNC %0(s32)
%2(s27) = G_AND %1, %1
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
name: test_and_i32
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_and_i32
; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[DEF]]
; CHECK: $eax = COPY [[AND]](s32)
; CHECK: RET 0, implicit $eax
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[DEF]], [[DEF1]]
; CHECK-NEXT: $eax = COPY [[AND]](s32)
; CHECK-NEXT: RET 0
%0(s32) = IMPLICIT_DEF
%1(s32) = G_AND %0, %0
$eax = COPY %1(s32)
RET 0, implicit $eax
%1(s32) = IMPLICIT_DEF
%2(s32) = G_AND %0, %1
$eax = COPY %2
RET 0
...
---
name: test_and_i42
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_and_i42
; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X64-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[COPY]]
; X64-NEXT: $rax = COPY [[AND]](s64)
; X64-NEXT: RET 0
; X86-LABEL: name: test_and_i42
; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV2]]
; X86-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[UV3]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; X86-NEXT: $rax = COPY [[MV]](s64)
; X86-NEXT: RET 0
%0(s64) = COPY $rdx
%1(s42) = G_TRUNC %0(s64)
%2(s42) = G_AND %1, %1
%3:_(s64) = G_ANYEXT %2
$rax = COPY %3
RET 0
...
---
name: test_and_i64
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_and_i64
; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF]]
; CHECK: $rax = COPY [[AND]](s64)
; CHECK: RET 0, implicit $rax
; X64-LABEL: name: test_and_i64
; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X64-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[DEF1]]
; X64-NEXT: $rax = COPY [[AND]](s64)
; X64-NEXT: RET 0
; X86-LABEL: name: test_and_i64
; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; X86-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[UV]], [[UV2]]
; X86-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[UV1]], [[UV3]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)
; X86-NEXT: $rax = COPY [[MV]](s64)
; X86-NEXT: RET 0
%0(s64) = IMPLICIT_DEF
%1(s64) = G_AND %0, %0
$rax = COPY %1(s64)
RET 0, implicit $rax
%1(s64) = IMPLICIT_DEF
%2(s64) = G_AND %0, %1
$rax = COPY %2
RET 0
...
134 changes: 134 additions & 0 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-and-v128.mir
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,134 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s

--- |
define void @test_and_v16i8() {
%ret = and <16 x i8> undef, undef
ret void
}

define void @test_and_v8i16() {
%ret = and <8 x i16> undef, undef
ret void
}

define void @test_and_v4i32() {
%ret = and <4 x i32> undef, undef
ret void
}

define void @test_and_v2i64() {
%ret = and <2 x i64> undef, undef
ret void
}
...
---
name: test_and_v16i8
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
; CHECK-LABEL: name: test_and_v16i8
; CHECK: liveins: $xmm0, $xmm1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[DEF]], [[DEF1]]
; CHECK-NEXT: $xmm0 = COPY [[AND]](<16 x s8>)
; CHECK-NEXT: RET 0
%0(<16 x s8>) = IMPLICIT_DEF
%1(<16 x s8>) = IMPLICIT_DEF
%2(<16 x s8>) = G_AND %0, %1
$xmm0 = COPY %2
RET 0
...
---
name: test_and_v8i16
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
; CHECK-LABEL: name: test_and_v8i16
; CHECK: liveins: $xmm0, $xmm1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<8 x s16>) = G_AND [[DEF]], [[DEF1]]
; CHECK-NEXT: $xmm0 = COPY [[AND]](<8 x s16>)
; CHECK-NEXT: RET 0
%0(<8 x s16>) = IMPLICIT_DEF
%1(<8 x s16>) = IMPLICIT_DEF
%2(<8 x s16>) = G_AND %0, %1
$xmm0 = COPY %2
RET 0
...
---
name: test_and_v4i32
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
; CHECK-LABEL: name: test_and_v4i32
; CHECK: liveins: $xmm0, $xmm1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[DEF]], [[DEF1]]
; CHECK-NEXT: $xmm0 = COPY [[AND]](<4 x s32>)
; CHECK-NEXT: RET 0
%0(<4 x s32>) = IMPLICIT_DEF
%1(<4 x s32>) = IMPLICIT_DEF
%2(<4 x s32>) = G_AND %0, %1
$xmm0 = COPY %2
RET 0
...
---
name: test_and_v2i64
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
; CHECK-LABEL: name: test_and_v2i64
; CHECK: liveins: $xmm0, $xmm1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
; CHECK-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[DEF]], [[DEF1]]
; CHECK-NEXT: $xmm0 = COPY [[AND]](<2 x s64>)
; CHECK-NEXT: RET 0
%0(<2 x s64>) = IMPLICIT_DEF
%1(<2 x s64>) = IMPLICIT_DEF
%2(<2 x s64>) = G_AND %0, %1
$xmm0 = COPY %2
RET 0
...
182 changes: 182 additions & 0 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-and-v256.mir
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,182 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=SSE
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX

--- |
define void @test_and_v32i8() {
%ret = and <32 x i8> undef, undef
ret void
}

define void @test_and_v16i16() {
%ret = and <16 x i16> undef, undef
ret void
}

define void @test_and_v8i32() {
%ret = and <8 x i32> undef, undef
ret void
}

define void @test_and_v4i64() {
%ret = and <4 x i64> undef, undef
ret void
}
...
---
name: test_and_v32i8
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1
; SSE-LABEL: name: test_and_v32i8
; SSE: liveins: $ymm0, $ymm1
; SSE-NEXT: {{ $}}
; SSE-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
; SSE-NEXT: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x s8>)
; SSE-NEXT: [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<32 x s8>)
; SSE-NEXT: [[AND:%[0-9]+]]:_(<16 x s8>) = G_AND [[UV]], [[UV2]]
; SSE-NEXT: [[AND1:%[0-9]+]]:_(<16 x s8>) = G_AND [[UV1]], [[UV3]]
; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[AND]](<16 x s8>), [[AND1]](<16 x s8>)
; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)
; SSE-NEXT: RET 0
; AVX-LABEL: name: test_and_v32i8
; AVX: liveins: $ymm0, $ymm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
; AVX-NEXT: [[AND:%[0-9]+]]:_(<32 x s8>) = G_AND [[DEF]], [[DEF1]]
; AVX-NEXT: $ymm0 = COPY [[AND]](<32 x s8>)
; AVX-NEXT: RET 0
%0(<32 x s8>) = IMPLICIT_DEF
%1(<32 x s8>) = IMPLICIT_DEF
%2(<32 x s8>) = G_AND %0, %1
$ymm0 = COPY %2
RET 0
...
---
name: test_and_v16i16
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1
; SSE-LABEL: name: test_and_v16i16
; SSE: liveins: $ymm0, $ymm1
; SSE-NEXT: {{ $}}
; SSE-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
; SSE-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x s16>)
; SSE-NEXT: [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<16 x s16>)
; SSE-NEXT: [[AND:%[0-9]+]]:_(<8 x s16>) = G_AND [[UV]], [[UV2]]
; SSE-NEXT: [[AND1:%[0-9]+]]:_(<8 x s16>) = G_AND [[UV1]], [[UV3]]
; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[AND]](<8 x s16>), [[AND1]](<8 x s16>)
; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<16 x s16>)
; SSE-NEXT: RET 0
; AVX-LABEL: name: test_and_v16i16
; AVX: liveins: $ymm0, $ymm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
; AVX-NEXT: [[AND:%[0-9]+]]:_(<16 x s16>) = G_AND [[DEF]], [[DEF1]]
; AVX-NEXT: $ymm0 = COPY [[AND]](<16 x s16>)
; AVX-NEXT: RET 0
%0(<16 x s16>) = IMPLICIT_DEF
%1(<16 x s16>) = IMPLICIT_DEF
%2(<16 x s16>) = G_AND %0, %1
$ymm0 = COPY %2
RET 0
...
---
name: test_and_v8i32
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1
; SSE-LABEL: name: test_and_v8i32
; SSE: liveins: $ymm0, $ymm1
; SSE-NEXT: {{ $}}
; SSE-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
; SSE-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)
; SSE-NEXT: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)
; SSE-NEXT: [[AND:%[0-9]+]]:_(<4 x s32>) = G_AND [[UV]], [[UV2]]
; SSE-NEXT: [[AND1:%[0-9]+]]:_(<4 x s32>) = G_AND [[UV1]], [[UV3]]
; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[AND]](<4 x s32>), [[AND1]](<4 x s32>)
; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<8 x s32>)
; SSE-NEXT: RET 0
; AVX-LABEL: name: test_and_v8i32
; AVX: liveins: $ymm0, $ymm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
; AVX-NEXT: [[AND:%[0-9]+]]:_(<8 x s32>) = G_AND [[DEF]], [[DEF1]]
; AVX-NEXT: $ymm0 = COPY [[AND]](<8 x s32>)
; AVX-NEXT: RET 0
%0(<8 x s32>) = IMPLICIT_DEF
%1(<8 x s32>) = IMPLICIT_DEF
%2(<8 x s32>) = G_AND %0, %1
$ymm0 = COPY %2
RET 0
...
---
name: test_and_v4i64
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1
; SSE-LABEL: name: test_and_v4i64
; SSE: liveins: $ymm0, $ymm1
; SSE-NEXT: {{ $}}
; SSE-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
; SSE-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; SSE-NEXT: [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<4 x s64>)
; SSE-NEXT: [[AND:%[0-9]+]]:_(<2 x s64>) = G_AND [[UV]], [[UV2]]
; SSE-NEXT: [[AND1:%[0-9]+]]:_(<2 x s64>) = G_AND [[UV1]], [[UV3]]
; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[AND]](<2 x s64>), [[AND1]](<2 x s64>)
; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<4 x s64>)
; SSE-NEXT: RET 0
; AVX-LABEL: name: test_and_v4i64
; AVX: liveins: $ymm0, $ymm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
; AVX-NEXT: [[AND:%[0-9]+]]:_(<4 x s64>) = G_AND [[DEF]], [[DEF1]]
; AVX-NEXT: $ymm0 = COPY [[AND]](<4 x s64>)
; AVX-NEXT: RET 0
%0(<4 x s64>) = IMPLICIT_DEF
%1(<4 x s64>) = IMPLICIT_DEF
%2(<4 x s64>) = G_AND %0, %1
$ymm0 = COPY %2
RET 0
...
246 changes: 246 additions & 0 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-and-v512.mir
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,246 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX512
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX512

--- |
define void @test_and_v64i8() {
%ret = and <64 x i8> undef, undef
ret void
}

define void @test_and_v32i16() {
%ret = and <32 x i16> undef, undef
ret void
}

define void @test_and_v16i32() {
%ret = and <16 x i32> undef, undef
ret void
}

define void @test_and_v8i64() {
%ret = and <8 x i64> undef, undef
ret void
}

define <64 x i8> @test_and_v64i8_2(<64 x i8> %arg1, <64 x i8> %arg2) #0 {
%ret = and <64 x i8> %arg1, %arg2
ret <64 x i8> %ret
}
...
---
name: test_and_v64i8
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $zmm1
; AVX-LABEL: name: test_and_v64i8
; AVX: liveins: $zmm0, $zmm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
; AVX-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)
; AVX-NEXT: [[UV2:%[0-9]+]]:_(<32 x s8>), [[UV3:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)
; AVX-NEXT: [[AND:%[0-9]+]]:_(<32 x s8>) = G_AND [[UV]], [[UV2]]
; AVX-NEXT: [[AND1:%[0-9]+]]:_(<32 x s8>) = G_AND [[UV1]], [[UV3]]
; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[AND]](<32 x s8>), [[AND1]](<32 x s8>)
; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)
; AVX-NEXT: RET 0
; AVX512-LABEL: name: test_and_v64i8
; AVX512: liveins: $zmm0, $zmm1
; AVX512-NEXT: {{ $}}
; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
; AVX512-NEXT: [[AND:%[0-9]+]]:_(<64 x s8>) = G_AND [[DEF]], [[DEF1]]
; AVX512-NEXT: $zmm0 = COPY [[AND]](<64 x s8>)
; AVX512-NEXT: RET 0
%0(<64 x s8>) = IMPLICIT_DEF
%1(<64 x s8>) = IMPLICIT_DEF
%2(<64 x s8>) = G_AND %0, %1
$zmm0 = COPY %2
RET 0
...
---
name: test_and_v32i16
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $zmm1
; AVX-LABEL: name: test_and_v32i16
; AVX: liveins: $zmm0, $zmm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
; AVX-NEXT: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)
; AVX-NEXT: [[UV2:%[0-9]+]]:_(<16 x s16>), [[UV3:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)
; AVX-NEXT: [[AND:%[0-9]+]]:_(<16 x s16>) = G_AND [[UV]], [[UV2]]
; AVX-NEXT: [[AND1:%[0-9]+]]:_(<16 x s16>) = G_AND [[UV1]], [[UV3]]
; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[AND]](<16 x s16>), [[AND1]](<16 x s16>)
; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)
; AVX-NEXT: RET 0
; AVX512-LABEL: name: test_and_v32i16
; AVX512: liveins: $zmm0, $zmm1
; AVX512-NEXT: {{ $}}
; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
; AVX512-NEXT: [[AND:%[0-9]+]]:_(<32 x s16>) = G_AND [[DEF]], [[DEF1]]
; AVX512-NEXT: $zmm0 = COPY [[AND]](<32 x s16>)
; AVX512-NEXT: RET 0
%0(<32 x s16>) = IMPLICIT_DEF
%1(<32 x s16>) = IMPLICIT_DEF
%2(<32 x s16>) = G_AND %0, %1
$zmm0 = COPY %2
RET 0
...
---
name: test_and_v16i32
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $zmm1
; AVX-LABEL: name: test_and_v16i32
; AVX: liveins: $zmm0, $zmm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
; AVX-NEXT: [[UV:%[0-9]+]]:_(<8 x s32>), [[UV1:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
; AVX-NEXT: [[UV2:%[0-9]+]]:_(<8 x s32>), [[UV3:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)
; AVX-NEXT: [[AND:%[0-9]+]]:_(<8 x s32>) = G_AND [[UV]], [[UV2]]
; AVX-NEXT: [[AND1:%[0-9]+]]:_(<8 x s32>) = G_AND [[UV1]], [[UV3]]
; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[AND]](<8 x s32>), [[AND1]](<8 x s32>)
; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<16 x s32>)
; AVX-NEXT: RET 0
; AVX512-LABEL: name: test_and_v16i32
; AVX512: liveins: $zmm0, $zmm1
; AVX512-NEXT: {{ $}}
; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
; AVX512-NEXT: [[AND:%[0-9]+]]:_(<16 x s32>) = G_AND [[DEF]], [[DEF1]]
; AVX512-NEXT: $zmm0 = COPY [[AND]](<16 x s32>)
; AVX512-NEXT: RET 0
%0(<16 x s32>) = IMPLICIT_DEF
%1(<16 x s32>) = IMPLICIT_DEF
%2(<16 x s32>) = G_AND %0, %1
$zmm0 = COPY %2
RET 0
...
---
name: test_and_v8i64
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $zmm1
; AVX-LABEL: name: test_and_v8i64
; AVX: liveins: $zmm0, $zmm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
; AVX-NEXT: [[UV:%[0-9]+]]:_(<4 x s64>), [[UV1:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[DEF]](<8 x s64>)
; AVX-NEXT: [[UV2:%[0-9]+]]:_(<4 x s64>), [[UV3:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[DEF1]](<8 x s64>)
; AVX-NEXT: [[AND:%[0-9]+]]:_(<4 x s64>) = G_AND [[UV]], [[UV2]]
; AVX-NEXT: [[AND1:%[0-9]+]]:_(<4 x s64>) = G_AND [[UV1]], [[UV3]]
; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[AND]](<4 x s64>), [[AND1]](<4 x s64>)
; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<8 x s64>)
; AVX-NEXT: RET 0
; AVX512-LABEL: name: test_and_v8i64
; AVX512: liveins: $zmm0, $zmm1
; AVX512-NEXT: {{ $}}
; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
; AVX512-NEXT: [[AND:%[0-9]+]]:_(<8 x s64>) = G_AND [[DEF]], [[DEF1]]
; AVX512-NEXT: $zmm0 = COPY [[AND]](<8 x s64>)
; AVX512-NEXT: RET 0
%0(<8 x s64>) = IMPLICIT_DEF
%1(<8 x s64>) = IMPLICIT_DEF
%2(<8 x s64>) = G_AND %0, %1
$zmm0 = COPY %2
RET 0
...
---
name: test_and_v64i8_2
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
- { id: 6, class: _ }
- { id: 7, class: _ }
- { id: 8, class: _ }
#
#
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1, $ymm2, $ymm3
; AVX-LABEL: name: test_and_v64i8_2
; AVX: liveins: $ymm0, $ymm1, $ymm2, $ymm3
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0
; AVX-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1
; AVX-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2
; AVX-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3
; AVX-NEXT: [[AND:%[0-9]+]]:_(<32 x s8>) = G_AND [[COPY]], [[COPY2]]
; AVX-NEXT: [[AND1:%[0-9]+]]:_(<32 x s8>) = G_AND [[COPY1]], [[COPY3]]
; AVX-NEXT: $ymm0 = COPY [[AND]](<32 x s8>)
; AVX-NEXT: $ymm1 = COPY [[AND1]](<32 x s8>)
; AVX-NEXT: RET 0, implicit $ymm0, implicit $ymm1
; AVX512-LABEL: name: test_and_v64i8_2
; AVX512: liveins: $ymm0, $ymm1, $ymm2, $ymm3
; AVX512-NEXT: {{ $}}
; AVX512-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0
; AVX512-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1
; AVX512-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2
; AVX512-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3
; AVX512-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY]](<32 x s8>), [[COPY1]](<32 x s8>)
; AVX512-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY2]](<32 x s8>), [[COPY3]](<32 x s8>)
; AVX512-NEXT: [[AND:%[0-9]+]]:_(<64 x s8>) = G_AND [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
; AVX512-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[AND]](<64 x s8>)
; AVX512-NEXT: $ymm0 = COPY [[UV]](<32 x s8>)
; AVX512-NEXT: $ymm1 = COPY [[UV1]](<32 x s8>)
; AVX512-NEXT: RET 0, implicit $ymm0, implicit $ymm1
%2(<32 x s8>) = COPY $ymm0
%3(<32 x s8>) = COPY $ymm1
%4(<32 x s8>) = COPY $ymm2
%5(<32 x s8>) = COPY $ymm3
%0(<64 x s8>) = G_CONCAT_VECTORS %2(<32 x s8>), %3(<32 x s8>)
%1(<64 x s8>) = G_CONCAT_VECTORS %4(<32 x s8>), %5(<32 x s8>)
%6(<64 x s8>) = G_AND %0, %1
%7(<32 x s8>), %8(<32 x s8>) = G_UNMERGE_VALUES %6(<64 x s8>)
$ymm0 = COPY %7(<32 x s8>)
$ymm1 = COPY %8(<32 x s8>)
RET 0, implicit $ymm0, implicit $ymm1
...
225 changes: 134 additions & 91 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-or-scalar.mir
View file
Original file line number Diff line number Diff line change
@@ -1,31 +1,16 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86

--- |
define i1 @test_or_i1() {
%ret = or i1 undef, undef
ret i1 %ret
}

define i8 @test_or_i8() {
%ret = or i8 undef, undef
ret i8 %ret
}

define i16 @test_or_i16() {
%ret = or i16 undef, undef
ret i16 %ret
}

define i32 @test_or_i32() {
%ret = or i32 undef, undef
ret i32 %ret
}

define i64 @test_or_i64() {
%ret = or i64 undef, undef
ret i64 %ret
}
define void @test_or_i1() { ret void}
define void @test_or_i8() { ret void }
define void @test_or_i16() { ret void }
define void @test_or_i27() { ret void }
define void @test_or_i32() { ret void }
define void @test_or_i42() { ret void }
define void @test_or_i64() { ret void }

...
---
Expand All @@ -39,22 +24,19 @@ registers:
- { id: 2, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_or_i1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[OR:%[0-9]+]]:_(s8) = G_OR [[TRUNC]], [[TRUNC1]]
; CHECK: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
; CHECK: [[AND:%[0-9]+]]:_(s8) = G_AND [[OR]], [[C]]
; CHECK: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s1))
; CHECK: RET 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s8) = G_OR [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s8)
; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET 0
%0(s32) = COPY $edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_OR %1, %1
%3:_(p0) = G_IMPLICIT_DEF
G_STORE %2, %3 :: (store (s1))
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
Expand All @@ -65,95 +47,156 @@ regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
- { id: 2, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_or_i8
; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
; CHECK: [[OR:%[0-9]+]]:_(s8) = G_OR [[DEF]], [[DEF]]
; CHECK: $al = COPY [[OR]](s8)
; CHECK: RET 0, implicit $al
%0(s8) = IMPLICIT_DEF
%1(s8) = G_OR %0, %0
$al = COPY %1(s8)
RET 0, implicit $al
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s8) = G_OR [[TRUNC]], [[TRUNC]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s8)
; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET 0
%0(s32) = COPY $edx
%1(s8) = G_TRUNC %0(s32)
%2(s8) = G_OR %1, %1
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
name: test_or_i16
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_or_i16
; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
; CHECK: [[OR:%[0-9]+]]:_(s16) = G_OR [[DEF]], [[DEF]]
; CHECK: $ax = COPY [[OR]](s16)
; CHECK: RET 0, implicit $ax
%0(s16) = IMPLICIT_DEF
%1(s16) = G_OR %0, %0
$ax = COPY %1(s16)
RET 0, implicit $ax
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s16) = G_OR [[TRUNC]], [[TRUNC]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[OR]](s16)
; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET 0
%0(s32) = COPY $edx
%1(s16) = G_TRUNC %0(s32)
%2(s16) = G_OR %1, %1
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
name: test_or_i27
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_or_i27
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY]]
; CHECK-NEXT: $eax = COPY [[OR]](s32)
; CHECK-NEXT: RET 0
%0(s32) = COPY $edx
%1(s27) = G_TRUNC %0(s32)
%2(s27) = G_OR %1, %1
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
name: test_or_i32
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_or_i32
; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; CHECK: [[OR:%[0-9]+]]:_(s32) = G_OR [[DEF]], [[DEF]]
; CHECK: $eax = COPY [[OR]](s32)
; CHECK: RET 0, implicit $eax
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[DEF]], [[DEF1]]
; CHECK-NEXT: $eax = COPY [[OR]](s32)
; CHECK-NEXT: RET 0
%0(s32) = IMPLICIT_DEF
%1(s32) = G_OR %0, %0
$eax = COPY %1(s32)
RET 0, implicit $eax
%1(s32) = IMPLICIT_DEF
%2(s32) = G_OR %0, %1
$eax = COPY %2
RET 0
...
---
name: test_or_i42
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_or_i42
; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X64-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[COPY]]
; X64-NEXT: $rax = COPY [[OR]](s64)
; X64-NEXT: RET 0
; X86-LABEL: name: test_or_i42
; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; X86-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[UV2]]
; X86-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV1]], [[UV3]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; X86-NEXT: $rax = COPY [[MV]](s64)
; X86-NEXT: RET 0
%0(s64) = COPY $rdx
%1(s42) = G_TRUNC %0(s64)
%2(s42) = G_OR %1, %1
%3:_(s64) = G_ANYEXT %2
$rax = COPY %3
RET 0
...
---
name: test_or_i64
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_or_i64
; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF]]
; CHECK: $rax = COPY [[OR]](s64)
; CHECK: RET 0, implicit $rax
; X64-LABEL: name: test_or_i64
; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X64-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[DEF]], [[DEF1]]
; X64-NEXT: $rax = COPY [[OR]](s64)
; X64-NEXT: RET 0
; X86-LABEL: name: test_or_i64
; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; X86-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[UV]], [[UV2]]
; X86-NEXT: [[OR1:%[0-9]+]]:_(s32) = G_OR [[UV1]], [[UV3]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[OR]](s32), [[OR1]](s32)
; X86-NEXT: $rax = COPY [[MV]](s64)
; X86-NEXT: RET 0
%0(s64) = IMPLICIT_DEF
%1(s64) = G_OR %0, %0
$rax = COPY %1(s64)
RET 0, implicit $rax
%1(s64) = IMPLICIT_DEF
%2(s64) = G_OR %0, %1
$rax = COPY %2
RET 0
...
134 changes: 134 additions & 0 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-or-v128.mir
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,134 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s

--- |
define void @test_or_v16i8() {
%ret = or <16 x i8> undef, undef
ret void
}

define void @test_or_v8i16() {
%ret = or <8 x i16> undef, undef
ret void
}

define void @test_or_v4i32() {
%ret = or <4 x i32> undef, undef
ret void
}

define void @test_or_v2i64() {
%ret = or <2 x i64> undef, undef
ret void
}
...
---
name: test_or_v16i8
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
; CHECK-LABEL: name: test_or_v16i8
; CHECK: liveins: $xmm0, $xmm1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<16 x s8>) = G_OR [[DEF]], [[DEF1]]
; CHECK-NEXT: $xmm0 = COPY [[OR]](<16 x s8>)
; CHECK-NEXT: RET 0
%0(<16 x s8>) = IMPLICIT_DEF
%1(<16 x s8>) = IMPLICIT_DEF
%2(<16 x s8>) = G_OR %0, %1
$xmm0 = COPY %2
RET 0
...
---
name: test_or_v8i16
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
; CHECK-LABEL: name: test_or_v8i16
; CHECK: liveins: $xmm0, $xmm1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<8 x s16>) = G_OR [[DEF]], [[DEF1]]
; CHECK-NEXT: $xmm0 = COPY [[OR]](<8 x s16>)
; CHECK-NEXT: RET 0
%0(<8 x s16>) = IMPLICIT_DEF
%1(<8 x s16>) = IMPLICIT_DEF
%2(<8 x s16>) = G_OR %0, %1
$xmm0 = COPY %2
RET 0
...
---
name: test_or_v4i32
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
; CHECK-LABEL: name: test_or_v4i32
; CHECK: liveins: $xmm0, $xmm1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[DEF]], [[DEF1]]
; CHECK-NEXT: $xmm0 = COPY [[OR]](<4 x s32>)
; CHECK-NEXT: RET 0
%0(<4 x s32>) = IMPLICIT_DEF
%1(<4 x s32>) = IMPLICIT_DEF
%2(<4 x s32>) = G_OR %0, %1
$xmm0 = COPY %2
RET 0
...
---
name: test_or_v2i64
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
; CHECK-LABEL: name: test_or_v2i64
; CHECK: liveins: $xmm0, $xmm1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
; CHECK-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[DEF]], [[DEF1]]
; CHECK-NEXT: $xmm0 = COPY [[OR]](<2 x s64>)
; CHECK-NEXT: RET 0
%0(<2 x s64>) = IMPLICIT_DEF
%1(<2 x s64>) = IMPLICIT_DEF
%2(<2 x s64>) = G_OR %0, %1
$xmm0 = COPY %2
RET 0
...
182 changes: 182 additions & 0 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-or-v256.mir
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,182 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=SSE
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX

--- |
define void @test_or_v32i8() {
%ret = or <32 x i8> undef, undef
ret void
}

define void @test_or_v16i16() {
%ret = or <16 x i16> undef, undef
ret void
}

define void @test_or_v8i32() {
%ret = or <8 x i32> undef, undef
ret void
}

define void @test_or_v4i64() {
%ret = or <4 x i64> undef, undef
ret void
}
...
---
name: test_or_v32i8
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1
; SSE-LABEL: name: test_or_v32i8
; SSE: liveins: $ymm0, $ymm1
; SSE-NEXT: {{ $}}
; SSE-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
; SSE-NEXT: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x s8>)
; SSE-NEXT: [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<32 x s8>)
; SSE-NEXT: [[OR:%[0-9]+]]:_(<16 x s8>) = G_OR [[UV]], [[UV2]]
; SSE-NEXT: [[OR1:%[0-9]+]]:_(<16 x s8>) = G_OR [[UV1]], [[UV3]]
; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[OR]](<16 x s8>), [[OR1]](<16 x s8>)
; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)
; SSE-NEXT: RET 0
; AVX-LABEL: name: test_or_v32i8
; AVX: liveins: $ymm0, $ymm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
; AVX-NEXT: [[OR:%[0-9]+]]:_(<32 x s8>) = G_OR [[DEF]], [[DEF1]]
; AVX-NEXT: $ymm0 = COPY [[OR]](<32 x s8>)
; AVX-NEXT: RET 0
%0(<32 x s8>) = IMPLICIT_DEF
%1(<32 x s8>) = IMPLICIT_DEF
%2(<32 x s8>) = G_OR %0, %1
$ymm0 = COPY %2
RET 0
...
---
name: test_or_v16i16
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1
; SSE-LABEL: name: test_or_v16i16
; SSE: liveins: $ymm0, $ymm1
; SSE-NEXT: {{ $}}
; SSE-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
; SSE-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x s16>)
; SSE-NEXT: [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<16 x s16>)
; SSE-NEXT: [[OR:%[0-9]+]]:_(<8 x s16>) = G_OR [[UV]], [[UV2]]
; SSE-NEXT: [[OR1:%[0-9]+]]:_(<8 x s16>) = G_OR [[UV1]], [[UV3]]
; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[OR]](<8 x s16>), [[OR1]](<8 x s16>)
; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<16 x s16>)
; SSE-NEXT: RET 0
; AVX-LABEL: name: test_or_v16i16
; AVX: liveins: $ymm0, $ymm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
; AVX-NEXT: [[OR:%[0-9]+]]:_(<16 x s16>) = G_OR [[DEF]], [[DEF1]]
; AVX-NEXT: $ymm0 = COPY [[OR]](<16 x s16>)
; AVX-NEXT: RET 0
%0(<16 x s16>) = IMPLICIT_DEF
%1(<16 x s16>) = IMPLICIT_DEF
%2(<16 x s16>) = G_OR %0, %1
$ymm0 = COPY %2
RET 0
...
---
name: test_or_v8i32
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1
; SSE-LABEL: name: test_or_v8i32
; SSE: liveins: $ymm0, $ymm1
; SSE-NEXT: {{ $}}
; SSE-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
; SSE-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)
; SSE-NEXT: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)
; SSE-NEXT: [[OR:%[0-9]+]]:_(<4 x s32>) = G_OR [[UV]], [[UV2]]
; SSE-NEXT: [[OR1:%[0-9]+]]:_(<4 x s32>) = G_OR [[UV1]], [[UV3]]
; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[OR]](<4 x s32>), [[OR1]](<4 x s32>)
; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<8 x s32>)
; SSE-NEXT: RET 0
; AVX-LABEL: name: test_or_v8i32
; AVX: liveins: $ymm0, $ymm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
; AVX-NEXT: [[OR:%[0-9]+]]:_(<8 x s32>) = G_OR [[DEF]], [[DEF1]]
; AVX-NEXT: $ymm0 = COPY [[OR]](<8 x s32>)
; AVX-NEXT: RET 0
%0(<8 x s32>) = IMPLICIT_DEF
%1(<8 x s32>) = IMPLICIT_DEF
%2(<8 x s32>) = G_OR %0, %1
$ymm0 = COPY %2
RET 0
...
---
name: test_or_v4i64
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1
; SSE-LABEL: name: test_or_v4i64
; SSE: liveins: $ymm0, $ymm1
; SSE-NEXT: {{ $}}
; SSE-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
; SSE-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; SSE-NEXT: [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<4 x s64>)
; SSE-NEXT: [[OR:%[0-9]+]]:_(<2 x s64>) = G_OR [[UV]], [[UV2]]
; SSE-NEXT: [[OR1:%[0-9]+]]:_(<2 x s64>) = G_OR [[UV1]], [[UV3]]
; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[OR]](<2 x s64>), [[OR1]](<2 x s64>)
; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<4 x s64>)
; SSE-NEXT: RET 0
; AVX-LABEL: name: test_or_v4i64
; AVX: liveins: $ymm0, $ymm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
; AVX-NEXT: [[OR:%[0-9]+]]:_(<4 x s64>) = G_OR [[DEF]], [[DEF1]]
; AVX-NEXT: $ymm0 = COPY [[OR]](<4 x s64>)
; AVX-NEXT: RET 0
%0(<4 x s64>) = IMPLICIT_DEF
%1(<4 x s64>) = IMPLICIT_DEF
%2(<4 x s64>) = G_OR %0, %1
$ymm0 = COPY %2
RET 0
...
246 changes: 246 additions & 0 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-or-v512.mir
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,246 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX512
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX512

--- |
define void @test_or_v64i8() {
%ret = or <64 x i8> undef, undef
ret void
}

define void @test_or_v32i16() {
%ret = or <32 x i16> undef, undef
ret void
}

define void @test_or_v16i32() {
%ret = or <16 x i32> undef, undef
ret void
}

define void @test_or_v8i64() {
%ret = or <8 x i64> undef, undef
ret void
}

define <64 x i8> @test_or_v64i8_2(<64 x i8> %arg1, <64 x i8> %arg2) #0 {
%ret = or <64 x i8> %arg1, %arg2
ret <64 x i8> %ret
}
...
---
name: test_or_v64i8
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $zmm1
; AVX-LABEL: name: test_or_v64i8
; AVX: liveins: $zmm0, $zmm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
; AVX-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)
; AVX-NEXT: [[UV2:%[0-9]+]]:_(<32 x s8>), [[UV3:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)
; AVX-NEXT: [[OR:%[0-9]+]]:_(<32 x s8>) = G_OR [[UV]], [[UV2]]
; AVX-NEXT: [[OR1:%[0-9]+]]:_(<32 x s8>) = G_OR [[UV1]], [[UV3]]
; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[OR]](<32 x s8>), [[OR1]](<32 x s8>)
; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)
; AVX-NEXT: RET 0
; AVX512-LABEL: name: test_or_v64i8
; AVX512: liveins: $zmm0, $zmm1
; AVX512-NEXT: {{ $}}
; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
; AVX512-NEXT: [[OR:%[0-9]+]]:_(<64 x s8>) = G_OR [[DEF]], [[DEF1]]
; AVX512-NEXT: $zmm0 = COPY [[OR]](<64 x s8>)
; AVX512-NEXT: RET 0
%0(<64 x s8>) = IMPLICIT_DEF
%1(<64 x s8>) = IMPLICIT_DEF
%2(<64 x s8>) = G_OR %0, %1
$zmm0 = COPY %2
RET 0
...
---
name: test_or_v32i16
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $zmm1
; AVX-LABEL: name: test_or_v32i16
; AVX: liveins: $zmm0, $zmm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
; AVX-NEXT: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)
; AVX-NEXT: [[UV2:%[0-9]+]]:_(<16 x s16>), [[UV3:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)
; AVX-NEXT: [[OR:%[0-9]+]]:_(<16 x s16>) = G_OR [[UV]], [[UV2]]
; AVX-NEXT: [[OR1:%[0-9]+]]:_(<16 x s16>) = G_OR [[UV1]], [[UV3]]
; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[OR]](<16 x s16>), [[OR1]](<16 x s16>)
; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)
; AVX-NEXT: RET 0
; AVX512-LABEL: name: test_or_v32i16
; AVX512: liveins: $zmm0, $zmm1
; AVX512-NEXT: {{ $}}
; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
; AVX512-NEXT: [[OR:%[0-9]+]]:_(<32 x s16>) = G_OR [[DEF]], [[DEF1]]
; AVX512-NEXT: $zmm0 = COPY [[OR]](<32 x s16>)
; AVX512-NEXT: RET 0
%0(<32 x s16>) = IMPLICIT_DEF
%1(<32 x s16>) = IMPLICIT_DEF
%2(<32 x s16>) = G_OR %0, %1
$zmm0 = COPY %2
RET 0
...
---
name: test_or_v16i32
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $zmm1
; AVX-LABEL: name: test_or_v16i32
; AVX: liveins: $zmm0, $zmm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
; AVX-NEXT: [[UV:%[0-9]+]]:_(<8 x s32>), [[UV1:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
; AVX-NEXT: [[UV2:%[0-9]+]]:_(<8 x s32>), [[UV3:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)
; AVX-NEXT: [[OR:%[0-9]+]]:_(<8 x s32>) = G_OR [[UV]], [[UV2]]
; AVX-NEXT: [[OR1:%[0-9]+]]:_(<8 x s32>) = G_OR [[UV1]], [[UV3]]
; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[OR]](<8 x s32>), [[OR1]](<8 x s32>)
; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<16 x s32>)
; AVX-NEXT: RET 0
; AVX512-LABEL: name: test_or_v16i32
; AVX512: liveins: $zmm0, $zmm1
; AVX512-NEXT: {{ $}}
; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
; AVX512-NEXT: [[OR:%[0-9]+]]:_(<16 x s32>) = G_OR [[DEF]], [[DEF1]]
; AVX512-NEXT: $zmm0 = COPY [[OR]](<16 x s32>)
; AVX512-NEXT: RET 0
%0(<16 x s32>) = IMPLICIT_DEF
%1(<16 x s32>) = IMPLICIT_DEF
%2(<16 x s32>) = G_OR %0, %1
$zmm0 = COPY %2
RET 0
...
---
name: test_or_v8i64
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $zmm1
; AVX-LABEL: name: test_or_v8i64
; AVX: liveins: $zmm0, $zmm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
; AVX-NEXT: [[UV:%[0-9]+]]:_(<4 x s64>), [[UV1:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[DEF]](<8 x s64>)
; AVX-NEXT: [[UV2:%[0-9]+]]:_(<4 x s64>), [[UV3:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[DEF1]](<8 x s64>)
; AVX-NEXT: [[OR:%[0-9]+]]:_(<4 x s64>) = G_OR [[UV]], [[UV2]]
; AVX-NEXT: [[OR1:%[0-9]+]]:_(<4 x s64>) = G_OR [[UV1]], [[UV3]]
; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[OR]](<4 x s64>), [[OR1]](<4 x s64>)
; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<8 x s64>)
; AVX-NEXT: RET 0
; AVX512-LABEL: name: test_or_v8i64
; AVX512: liveins: $zmm0, $zmm1
; AVX512-NEXT: {{ $}}
; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
; AVX512-NEXT: [[OR:%[0-9]+]]:_(<8 x s64>) = G_OR [[DEF]], [[DEF1]]
; AVX512-NEXT: $zmm0 = COPY [[OR]](<8 x s64>)
; AVX512-NEXT: RET 0
%0(<8 x s64>) = IMPLICIT_DEF
%1(<8 x s64>) = IMPLICIT_DEF
%2(<8 x s64>) = G_OR %0, %1
$zmm0 = COPY %2
RET 0
...
---
name: test_or_v64i8_2
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
- { id: 6, class: _ }
- { id: 7, class: _ }
- { id: 8, class: _ }
#
#
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1, $ymm2, $ymm3
; AVX-LABEL: name: test_or_v64i8_2
; AVX: liveins: $ymm0, $ymm1, $ymm2, $ymm3
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0
; AVX-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1
; AVX-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2
; AVX-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3
; AVX-NEXT: [[OR:%[0-9]+]]:_(<32 x s8>) = G_OR [[COPY]], [[COPY2]]
; AVX-NEXT: [[OR1:%[0-9]+]]:_(<32 x s8>) = G_OR [[COPY1]], [[COPY3]]
; AVX-NEXT: $ymm0 = COPY [[OR]](<32 x s8>)
; AVX-NEXT: $ymm1 = COPY [[OR1]](<32 x s8>)
; AVX-NEXT: RET 0, implicit $ymm0, implicit $ymm1
; AVX512-LABEL: name: test_or_v64i8_2
; AVX512: liveins: $ymm0, $ymm1, $ymm2, $ymm3
; AVX512-NEXT: {{ $}}
; AVX512-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0
; AVX512-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1
; AVX512-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2
; AVX512-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3
; AVX512-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY]](<32 x s8>), [[COPY1]](<32 x s8>)
; AVX512-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY2]](<32 x s8>), [[COPY3]](<32 x s8>)
; AVX512-NEXT: [[OR:%[0-9]+]]:_(<64 x s8>) = G_OR [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
; AVX512-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[OR]](<64 x s8>)
; AVX512-NEXT: $ymm0 = COPY [[UV]](<32 x s8>)
; AVX512-NEXT: $ymm1 = COPY [[UV1]](<32 x s8>)
; AVX512-NEXT: RET 0, implicit $ymm0, implicit $ymm1
%2(<32 x s8>) = COPY $ymm0
%3(<32 x s8>) = COPY $ymm1
%4(<32 x s8>) = COPY $ymm2
%5(<32 x s8>) = COPY $ymm3
%0(<64 x s8>) = G_CONCAT_VECTORS %2(<32 x s8>), %3(<32 x s8>)
%1(<64 x s8>) = G_CONCAT_VECTORS %4(<32 x s8>), %5(<32 x s8>)
%6(<64 x s8>) = G_OR %0, %1
%7(<32 x s8>), %8(<32 x s8>) = G_UNMERGE_VALUES %6(<64 x s8>)
$ymm0 = COPY %7(<32 x s8>)
$ymm1 = COPY %8(<32 x s8>)
RET 0, implicit $ymm0, implicit $ymm1
...
221 changes: 134 additions & 87 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-xor-scalar.mir
View file
Original file line number Diff line number Diff line change
@@ -1,31 +1,16 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -O0 -mtriple=x86_64-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X64
# RUN: llc -O0 -mtriple=i386-linux-gnu -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=CHECK,X86

--- |
define i1 @test_xor_i1() {
%ret = xor i1 undef, undef
ret i1 %ret
}

define i8 @test_xor_i8() {
%ret = xor i8 undef, undef
ret i8 %ret
}

define i16 @test_xor_i16() {
%ret = xor i16 undef, undef
ret i16 %ret
}

define i32 @test_xor_i32() {
%ret = xor i32 undef, undef
ret i32 %ret
}

define i64 @test_xor_i64() {
%ret = xor i64 undef, undef
ret i64 %ret
}
define void @test_xor_i1() { ret void}
define void @test_xor_i8() { ret void }
define void @test_xor_i16() { ret void }
define void @test_xor_i27() { ret void }
define void @test_xor_i32() { ret void }
define void @test_xor_i42() { ret void }
define void @test_xor_i64() { ret void }

...
---
Expand All @@ -39,18 +24,19 @@ registers:
- { id: 2, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_xor_i1
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; CHECK: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[TRUNC]], [[TRUNC1]]
; CHECK: RET 0
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[TRUNC]], [[TRUNC1]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s8)
; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET 0
%0(s32) = COPY $edx
%1(s1) = G_TRUNC %0(s32)
%2(s1) = G_XOR %1, %1
%3:_(p0) = G_IMPLICIT_DEF
G_STORE %2, %3 ::(store (s1))
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
Expand All @@ -61,95 +47,156 @@ regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
- { id: 2, class: _, preferred-register: '' }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_xor_i8
; CHECK: [[DEF:%[0-9]+]]:_(s8) = IMPLICIT_DEF
; CHECK: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[DEF]], [[DEF]]
; CHECK: $al = COPY [[XOR]](s8)
; CHECK: RET 0, implicit $al
%0(s8) = IMPLICIT_DEF
%1(s8) = G_XOR %0, %0
$al = COPY %1(s8)
RET 0, implicit $al
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s8) = G_XOR [[TRUNC]], [[TRUNC]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s8)
; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET 0
%0(s32) = COPY $edx
%1(s8) = G_TRUNC %0(s32)
%2(s8) = G_XOR %1, %1
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
name: test_xor_i16
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_xor_i16
; CHECK: [[DEF:%[0-9]+]]:_(s16) = IMPLICIT_DEF
; CHECK: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[DEF]], [[DEF]]
; CHECK: $ax = COPY [[XOR]](s16)
; CHECK: RET 0, implicit $ax
%0(s16) = IMPLICIT_DEF
%1(s16) = G_XOR %0, %0
$ax = COPY %1(s16)
RET 0, implicit $ax
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s16) = G_XOR [[TRUNC]], [[TRUNC]]
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[XOR]](s16)
; CHECK-NEXT: $eax = COPY [[ANYEXT]](s32)
; CHECK-NEXT: RET 0
%0(s32) = COPY $edx
%1(s16) = G_TRUNC %0(s32)
%2(s16) = G_XOR %1, %1
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
name: test_xor_i27
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_xor_i27
; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edx
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY]]
; CHECK-NEXT: $eax = COPY [[XOR]](s32)
; CHECK-NEXT: RET 0
%0(s32) = COPY $edx
%1(s27) = G_TRUNC %0(s32)
%2(s27) = G_XOR %1, %1
%3:_(s32) = G_ANYEXT %2
$eax = COPY %3
RET 0
...
---
name: test_xor_i32
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_xor_i32
; CHECK: [[DEF:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; CHECK: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[DEF]], [[DEF]]
; CHECK: $eax = COPY [[XOR]](s32)
; CHECK: RET 0, implicit $eax
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(s32) = IMPLICIT_DEF
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[DEF]], [[DEF1]]
; CHECK-NEXT: $eax = COPY [[XOR]](s32)
; CHECK-NEXT: RET 0
%0(s32) = IMPLICIT_DEF
%1(s32) = G_XOR %0, %0
$eax = COPY %1(s32)
RET 0, implicit $eax
%1(s32) = IMPLICIT_DEF
%2(s32) = G_XOR %0, %1
$eax = COPY %2
RET 0
...
---
name: test_xor_i42
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; X64-LABEL: name: test_xor_i42
; X64: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X64-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[COPY]]
; X64-NEXT: $rax = COPY [[XOR]](s64)
; X64-NEXT: RET 0
; X86-LABEL: name: test_xor_i42
; X86: [[COPY:%[0-9]+]]:_(s64) = COPY $rdx
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](s64)
; X86-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[UV]], [[UV2]]
; X86-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[UV1]], [[UV3]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[XOR]](s32), [[XOR1]](s32)
; X86-NEXT: $rax = COPY [[MV]](s64)
; X86-NEXT: RET 0
%0(s64) = COPY $rdx
%1(s42) = G_TRUNC %0(s64)
%2(s42) = G_XOR %1, %1
%3:_(s64) = G_ANYEXT %2
$rax = COPY %3
RET 0
...
---
name: test_xor_i64
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _, preferred-register: '' }
- { id: 1, class: _, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
; CHECK-LABEL: name: test_xor_i64
; CHECK: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
; CHECK: $rax = COPY [[XOR]](s64)
; CHECK: RET 0, implicit $rax
; X64-LABEL: name: test_xor_i64
; X64: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X64-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X64-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF1]]
; X64-NEXT: $rax = COPY [[XOR]](s64)
; X64-NEXT: RET 0
; X86-LABEL: name: test_xor_i64
; X86: [[DEF:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: [[DEF1:%[0-9]+]]:_(s64) = IMPLICIT_DEF
; X86-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF]](s64)
; X86-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[DEF1]](s64)
; X86-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[UV]], [[UV2]]
; X86-NEXT: [[XOR1:%[0-9]+]]:_(s32) = G_XOR [[UV1]], [[UV3]]
; X86-NEXT: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[XOR]](s32), [[XOR1]](s32)
; X86-NEXT: $rax = COPY [[MV]](s64)
; X86-NEXT: RET 0
%0(s64) = IMPLICIT_DEF
%1(s64) = G_XOR %0, %0
$rax = COPY %1(s64)
RET 0, implicit $rax
%1(s64) = IMPLICIT_DEF
%2(s64) = G_XOR %0, %1
$rax = COPY %2
RET 0
...
134 changes: 134 additions & 0 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-xor-v128.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,134 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s

--- |
define void @test_xor_v16i8() {
%ret = xor <16 x i8> undef, undef
ret void
}

define void @test_xor_v8i16() {
%ret = xor <8 x i16> undef, undef
ret void
}

define void @test_xor_v4i32() {
%ret = xor <4 x i32> undef, undef
ret void
}

define void @test_xor_v2i64() {
%ret = xor <2 x i64> undef, undef
ret void
}
...
---
name: test_xor_v16i8
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
; CHECK-LABEL: name: test_xor_v16i8
; CHECK: liveins: $xmm0, $xmm1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s8>) = IMPLICIT_DEF
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<16 x s8>) = G_XOR [[DEF]], [[DEF1]]
; CHECK-NEXT: $xmm0 = COPY [[XOR]](<16 x s8>)
; CHECK-NEXT: RET 0
%0(<16 x s8>) = IMPLICIT_DEF
%1(<16 x s8>) = IMPLICIT_DEF
%2(<16 x s8>) = G_XOR %0, %1
$xmm0 = COPY %2
RET 0
...
---
name: test_xor_v8i16
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
; CHECK-LABEL: name: test_xor_v8i16
; CHECK: liveins: $xmm0, $xmm1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s16>) = IMPLICIT_DEF
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<8 x s16>) = G_XOR [[DEF]], [[DEF1]]
; CHECK-NEXT: $xmm0 = COPY [[XOR]](<8 x s16>)
; CHECK-NEXT: RET 0
%0(<8 x s16>) = IMPLICIT_DEF
%1(<8 x s16>) = IMPLICIT_DEF
%2(<8 x s16>) = G_XOR %0, %1
$xmm0 = COPY %2
RET 0
...
---
name: test_xor_v4i32
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
; CHECK-LABEL: name: test_xor_v4i32
; CHECK: liveins: $xmm0, $xmm1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s32>) = IMPLICIT_DEF
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR [[DEF]], [[DEF1]]
; CHECK-NEXT: $xmm0 = COPY [[XOR]](<4 x s32>)
; CHECK-NEXT: RET 0
%0(<4 x s32>) = IMPLICIT_DEF
%1(<4 x s32>) = IMPLICIT_DEF
%2(<4 x s32>) = G_XOR %0, %1
$xmm0 = COPY %2
RET 0
...
---
name: test_xor_v2i64
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $xmm0, $xmm1
; CHECK-LABEL: name: test_xor_v2i64
; CHECK: liveins: $xmm0, $xmm1
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
; CHECK-NEXT: [[DEF1:%[0-9]+]]:_(<2 x s64>) = IMPLICIT_DEF
; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[DEF]], [[DEF1]]
; CHECK-NEXT: $xmm0 = COPY [[XOR]](<2 x s64>)
; CHECK-NEXT: RET 0
%0(<2 x s64>) = IMPLICIT_DEF
%1(<2 x s64>) = IMPLICIT_DEF
%2(<2 x s64>) = G_XOR %0, %1
$xmm0 = COPY %2
RET 0
...
182 changes: 182 additions & 0 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-xor-v256.mir
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Original file line number Diff line number Diff line change
@@ -0,0 +1,182 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sse2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=SSE
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX

--- |
define void @test_xor_v32i8() {
%ret = xor <32 x i8> undef, undef
ret void
}

define void @test_xor_v16i16() {
%ret = xor <16 x i16> undef, undef
ret void
}

define void @test_xor_v8i32() {
%ret = xor <8 x i32> undef, undef
ret void
}

define void @test_xor_v4i64() {
%ret = xor <4 x i64> undef, undef
ret void
}
...
---
name: test_xor_v32i8
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1
; SSE-LABEL: name: test_xor_v32i8
; SSE: liveins: $ymm0, $ymm1
; SSE-NEXT: {{ $}}
; SSE-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
; SSE-NEXT: [[UV:%[0-9]+]]:_(<16 x s8>), [[UV1:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF]](<32 x s8>)
; SSE-NEXT: [[UV2:%[0-9]+]]:_(<16 x s8>), [[UV3:%[0-9]+]]:_(<16 x s8>) = G_UNMERGE_VALUES [[DEF1]](<32 x s8>)
; SSE-NEXT: [[XOR:%[0-9]+]]:_(<16 x s8>) = G_XOR [[UV]], [[UV2]]
; SSE-NEXT: [[XOR1:%[0-9]+]]:_(<16 x s8>) = G_XOR [[UV1]], [[UV3]]
; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s8>) = G_CONCAT_VECTORS [[XOR]](<16 x s8>), [[XOR1]](<16 x s8>)
; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<32 x s8>)
; SSE-NEXT: RET 0
; AVX-LABEL: name: test_xor_v32i8
; AVX: liveins: $ymm0, $ymm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s8>) = IMPLICIT_DEF
; AVX-NEXT: [[XOR:%[0-9]+]]:_(<32 x s8>) = G_XOR [[DEF]], [[DEF1]]
; AVX-NEXT: $ymm0 = COPY [[XOR]](<32 x s8>)
; AVX-NEXT: RET 0
%0(<32 x s8>) = IMPLICIT_DEF
%1(<32 x s8>) = IMPLICIT_DEF
%2(<32 x s8>) = G_XOR %0, %1
$ymm0 = COPY %2
RET 0
...
---
name: test_xor_v16i16
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1
; SSE-LABEL: name: test_xor_v16i16
; SSE: liveins: $ymm0, $ymm1
; SSE-NEXT: {{ $}}
; SSE-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
; SSE-NEXT: [[UV:%[0-9]+]]:_(<8 x s16>), [[UV1:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF]](<16 x s16>)
; SSE-NEXT: [[UV2:%[0-9]+]]:_(<8 x s16>), [[UV3:%[0-9]+]]:_(<8 x s16>) = G_UNMERGE_VALUES [[DEF1]](<16 x s16>)
; SSE-NEXT: [[XOR:%[0-9]+]]:_(<8 x s16>) = G_XOR [[UV]], [[UV2]]
; SSE-NEXT: [[XOR1:%[0-9]+]]:_(<8 x s16>) = G_XOR [[UV1]], [[UV3]]
; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s16>) = G_CONCAT_VECTORS [[XOR]](<8 x s16>), [[XOR1]](<8 x s16>)
; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<16 x s16>)
; SSE-NEXT: RET 0
; AVX-LABEL: name: test_xor_v16i16
; AVX: liveins: $ymm0, $ymm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s16>) = IMPLICIT_DEF
; AVX-NEXT: [[XOR:%[0-9]+]]:_(<16 x s16>) = G_XOR [[DEF]], [[DEF1]]
; AVX-NEXT: $ymm0 = COPY [[XOR]](<16 x s16>)
; AVX-NEXT: RET 0
%0(<16 x s16>) = IMPLICIT_DEF
%1(<16 x s16>) = IMPLICIT_DEF
%2(<16 x s16>) = G_XOR %0, %1
$ymm0 = COPY %2
RET 0
...
---
name: test_xor_v8i32
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1
; SSE-LABEL: name: test_xor_v8i32
; SSE: liveins: $ymm0, $ymm1
; SSE-NEXT: {{ $}}
; SSE-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
; SSE-NEXT: [[UV:%[0-9]+]]:_(<4 x s32>), [[UV1:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF]](<8 x s32>)
; SSE-NEXT: [[UV2:%[0-9]+]]:_(<4 x s32>), [[UV3:%[0-9]+]]:_(<4 x s32>) = G_UNMERGE_VALUES [[DEF1]](<8 x s32>)
; SSE-NEXT: [[XOR:%[0-9]+]]:_(<4 x s32>) = G_XOR [[UV]], [[UV2]]
; SSE-NEXT: [[XOR1:%[0-9]+]]:_(<4 x s32>) = G_XOR [[UV1]], [[UV3]]
; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s32>) = G_CONCAT_VECTORS [[XOR]](<4 x s32>), [[XOR1]](<4 x s32>)
; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<8 x s32>)
; SSE-NEXT: RET 0
; AVX-LABEL: name: test_xor_v8i32
; AVX: liveins: $ymm0, $ymm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s32>) = IMPLICIT_DEF
; AVX-NEXT: [[XOR:%[0-9]+]]:_(<8 x s32>) = G_XOR [[DEF]], [[DEF1]]
; AVX-NEXT: $ymm0 = COPY [[XOR]](<8 x s32>)
; AVX-NEXT: RET 0
%0(<8 x s32>) = IMPLICIT_DEF
%1(<8 x s32>) = IMPLICIT_DEF
%2(<8 x s32>) = G_XOR %0, %1
$ymm0 = COPY %2
RET 0
...
---
name: test_xor_v4i64
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1
; SSE-LABEL: name: test_xor_v4i64
; SSE: liveins: $ymm0, $ymm1
; SSE-NEXT: {{ $}}
; SSE-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
; SSE-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
; SSE-NEXT: [[UV:%[0-9]+]]:_(<2 x s64>), [[UV1:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF]](<4 x s64>)
; SSE-NEXT: [[UV2:%[0-9]+]]:_(<2 x s64>), [[UV3:%[0-9]+]]:_(<2 x s64>) = G_UNMERGE_VALUES [[DEF1]](<4 x s64>)
; SSE-NEXT: [[XOR:%[0-9]+]]:_(<2 x s64>) = G_XOR [[UV]], [[UV2]]
; SSE-NEXT: [[XOR1:%[0-9]+]]:_(<2 x s64>) = G_XOR [[UV1]], [[UV3]]
; SSE-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x s64>) = G_CONCAT_VECTORS [[XOR]](<2 x s64>), [[XOR1]](<2 x s64>)
; SSE-NEXT: $ymm0 = COPY [[CONCAT_VECTORS]](<4 x s64>)
; SSE-NEXT: RET 0
; AVX-LABEL: name: test_xor_v4i64
; AVX: liveins: $ymm0, $ymm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<4 x s64>) = IMPLICIT_DEF
; AVX-NEXT: [[XOR:%[0-9]+]]:_(<4 x s64>) = G_XOR [[DEF]], [[DEF1]]
; AVX-NEXT: $ymm0 = COPY [[XOR]](<4 x s64>)
; AVX-NEXT: RET 0
%0(<4 x s64>) = IMPLICIT_DEF
%1(<4 x s64>) = IMPLICIT_DEF
%2(<4 x s64>) = G_XOR %0, %1
$ymm0 = COPY %2
RET 0
...
246 changes: 246 additions & 0 deletions llvm/test/CodeGen/X86/GlobalISel/legalize-xor-v512.mir
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,246 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx2 -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX512
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f,+avx512bw -run-pass=legalizer %s -o - | FileCheck %s --check-prefixes=AVX512

--- |
define void @test_xor_v64i8() {
%ret = xor <64 x i8> undef, undef
ret void
}

define void @test_xor_v32i16() {
%ret = xor <32 x i16> undef, undef
ret void
}

define void @test_xor_v16i32() {
%ret = xor <16 x i32> undef, undef
ret void
}

define void @test_xor_v8i64() {
%ret = xor <8 x i64> undef, undef
ret void
}

define <64 x i8> @test_xor_v64i8_2(<64 x i8> %arg1, <64 x i8> %arg2) #0 {
%ret = xor <64 x i8> %arg1, %arg2
ret <64 x i8> %ret
}
...
---
name: test_xor_v64i8
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $zmm1
; AVX-LABEL: name: test_xor_v64i8
; AVX: liveins: $zmm0, $zmm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
; AVX-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF]](<64 x s8>)
; AVX-NEXT: [[UV2:%[0-9]+]]:_(<32 x s8>), [[UV3:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[DEF1]](<64 x s8>)
; AVX-NEXT: [[XOR:%[0-9]+]]:_(<32 x s8>) = G_XOR [[UV]], [[UV2]]
; AVX-NEXT: [[XOR1:%[0-9]+]]:_(<32 x s8>) = G_XOR [[UV1]], [[UV3]]
; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[XOR]](<32 x s8>), [[XOR1]](<32 x s8>)
; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<64 x s8>)
; AVX-NEXT: RET 0
; AVX512-LABEL: name: test_xor_v64i8
; AVX512: liveins: $zmm0, $zmm1
; AVX512-NEXT: {{ $}}
; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<64 x s8>) = IMPLICIT_DEF
; AVX512-NEXT: [[XOR:%[0-9]+]]:_(<64 x s8>) = G_XOR [[DEF]], [[DEF1]]
; AVX512-NEXT: $zmm0 = COPY [[XOR]](<64 x s8>)
; AVX512-NEXT: RET 0
%0(<64 x s8>) = IMPLICIT_DEF
%1(<64 x s8>) = IMPLICIT_DEF
%2(<64 x s8>) = G_XOR %0, %1
$zmm0 = COPY %2
RET 0
...
---
name: test_xor_v32i16
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $zmm1
; AVX-LABEL: name: test_xor_v32i16
; AVX: liveins: $zmm0, $zmm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
; AVX-NEXT: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF]](<32 x s16>)
; AVX-NEXT: [[UV2:%[0-9]+]]:_(<16 x s16>), [[UV3:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[DEF1]](<32 x s16>)
; AVX-NEXT: [[XOR:%[0-9]+]]:_(<16 x s16>) = G_XOR [[UV]], [[UV2]]
; AVX-NEXT: [[XOR1:%[0-9]+]]:_(<16 x s16>) = G_XOR [[UV1]], [[UV3]]
; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[XOR]](<16 x s16>), [[XOR1]](<16 x s16>)
; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<32 x s16>)
; AVX-NEXT: RET 0
; AVX512-LABEL: name: test_xor_v32i16
; AVX512: liveins: $zmm0, $zmm1
; AVX512-NEXT: {{ $}}
; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<32 x s16>) = IMPLICIT_DEF
; AVX512-NEXT: [[XOR:%[0-9]+]]:_(<32 x s16>) = G_XOR [[DEF]], [[DEF1]]
; AVX512-NEXT: $zmm0 = COPY [[XOR]](<32 x s16>)
; AVX512-NEXT: RET 0
%0(<32 x s16>) = IMPLICIT_DEF
%1(<32 x s16>) = IMPLICIT_DEF
%2(<32 x s16>) = G_XOR %0, %1
$zmm0 = COPY %2
RET 0
...
---
name: test_xor_v16i32
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $zmm1
; AVX-LABEL: name: test_xor_v16i32
; AVX: liveins: $zmm0, $zmm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
; AVX-NEXT: [[UV:%[0-9]+]]:_(<8 x s32>), [[UV1:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF]](<16 x s32>)
; AVX-NEXT: [[UV2:%[0-9]+]]:_(<8 x s32>), [[UV3:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[DEF1]](<16 x s32>)
; AVX-NEXT: [[XOR:%[0-9]+]]:_(<8 x s32>) = G_XOR [[UV]], [[UV2]]
; AVX-NEXT: [[XOR1:%[0-9]+]]:_(<8 x s32>) = G_XOR [[UV1]], [[UV3]]
; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[XOR]](<8 x s32>), [[XOR1]](<8 x s32>)
; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<16 x s32>)
; AVX-NEXT: RET 0
; AVX512-LABEL: name: test_xor_v16i32
; AVX512: liveins: $zmm0, $zmm1
; AVX512-NEXT: {{ $}}
; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<16 x s32>) = IMPLICIT_DEF
; AVX512-NEXT: [[XOR:%[0-9]+]]:_(<16 x s32>) = G_XOR [[DEF]], [[DEF1]]
; AVX512-NEXT: $zmm0 = COPY [[XOR]](<16 x s32>)
; AVX512-NEXT: RET 0
%0(<16 x s32>) = IMPLICIT_DEF
%1(<16 x s32>) = IMPLICIT_DEF
%2(<16 x s32>) = G_XOR %0, %1
$zmm0 = COPY %2
RET 0
...
---
name: test_xor_v8i64
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
body: |
bb.1 (%ir-block.0):
liveins: $zmm0, $zmm1
; AVX-LABEL: name: test_xor_v8i64
; AVX: liveins: $zmm0, $zmm1
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
; AVX-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
; AVX-NEXT: [[UV:%[0-9]+]]:_(<4 x s64>), [[UV1:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[DEF]](<8 x s64>)
; AVX-NEXT: [[UV2:%[0-9]+]]:_(<4 x s64>), [[UV3:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[DEF1]](<8 x s64>)
; AVX-NEXT: [[XOR:%[0-9]+]]:_(<4 x s64>) = G_XOR [[UV]], [[UV2]]
; AVX-NEXT: [[XOR1:%[0-9]+]]:_(<4 x s64>) = G_XOR [[UV1]], [[UV3]]
; AVX-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[XOR]](<4 x s64>), [[XOR1]](<4 x s64>)
; AVX-NEXT: $zmm0 = COPY [[CONCAT_VECTORS]](<8 x s64>)
; AVX-NEXT: RET 0
; AVX512-LABEL: name: test_xor_v8i64
; AVX512: liveins: $zmm0, $zmm1
; AVX512-NEXT: {{ $}}
; AVX512-NEXT: [[DEF:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
; AVX512-NEXT: [[DEF1:%[0-9]+]]:_(<8 x s64>) = IMPLICIT_DEF
; AVX512-NEXT: [[XOR:%[0-9]+]]:_(<8 x s64>) = G_XOR [[DEF]], [[DEF1]]
; AVX512-NEXT: $zmm0 = COPY [[XOR]](<8 x s64>)
; AVX512-NEXT: RET 0
%0(<8 x s64>) = IMPLICIT_DEF
%1(<8 x s64>) = IMPLICIT_DEF
%2(<8 x s64>) = G_XOR %0, %1
$zmm0 = COPY %2
RET 0
...
---
name: test_xor_v64i8_2
alignment: 16
legalized: false
regBankSelected: false
registers:
- { id: 0, class: _ }
- { id: 1, class: _ }
- { id: 2, class: _ }
- { id: 3, class: _ }
- { id: 4, class: _ }
- { id: 5, class: _ }
- { id: 6, class: _ }
- { id: 7, class: _ }
- { id: 8, class: _ }
#
#
body: |
bb.1 (%ir-block.0):
liveins: $ymm0, $ymm1, $ymm2, $ymm3
; AVX-LABEL: name: test_xor_v64i8_2
; AVX: liveins: $ymm0, $ymm1, $ymm2, $ymm3
; AVX-NEXT: {{ $}}
; AVX-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0
; AVX-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1
; AVX-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2
; AVX-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3
; AVX-NEXT: [[XOR:%[0-9]+]]:_(<32 x s8>) = G_XOR [[COPY]], [[COPY2]]
; AVX-NEXT: [[XOR1:%[0-9]+]]:_(<32 x s8>) = G_XOR [[COPY1]], [[COPY3]]
; AVX-NEXT: $ymm0 = COPY [[XOR]](<32 x s8>)
; AVX-NEXT: $ymm1 = COPY [[XOR1]](<32 x s8>)
; AVX-NEXT: RET 0, implicit $ymm0, implicit $ymm1
; AVX512-LABEL: name: test_xor_v64i8_2
; AVX512: liveins: $ymm0, $ymm1, $ymm2, $ymm3
; AVX512-NEXT: {{ $}}
; AVX512-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $ymm0
; AVX512-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $ymm1
; AVX512-NEXT: [[COPY2:%[0-9]+]]:_(<32 x s8>) = COPY $ymm2
; AVX512-NEXT: [[COPY3:%[0-9]+]]:_(<32 x s8>) = COPY $ymm3
; AVX512-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY]](<32 x s8>), [[COPY1]](<32 x s8>)
; AVX512-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY2]](<32 x s8>), [[COPY3]](<32 x s8>)
; AVX512-NEXT: [[XOR:%[0-9]+]]:_(<64 x s8>) = G_XOR [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
; AVX512-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[XOR]](<64 x s8>)
; AVX512-NEXT: $ymm0 = COPY [[UV]](<32 x s8>)
; AVX512-NEXT: $ymm1 = COPY [[UV1]](<32 x s8>)
; AVX512-NEXT: RET 0, implicit $ymm0, implicit $ymm1
%2(<32 x s8>) = COPY $ymm0
%3(<32 x s8>) = COPY $ymm1
%4(<32 x s8>) = COPY $ymm2
%5(<32 x s8>) = COPY $ymm3
%0(<64 x s8>) = G_CONCAT_VECTORS %2(<32 x s8>), %3(<32 x s8>)
%1(<64 x s8>) = G_CONCAT_VECTORS %4(<32 x s8>), %5(<32 x s8>)
%6(<64 x s8>) = G_XOR %0, %1
%7(<32 x s8>), %8(<32 x s8>) = G_UNMERGE_VALUES %6(<64 x s8>)
$ymm0 = COPY %7(<32 x s8>)
$ymm1 = COPY %8(<32 x s8>)
RET 0, implicit $ymm0, implicit $ymm1
...