371 changes: 0 additions & 371 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
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154 changes: 0 additions & 154 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
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Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE

target triple = "aarch64-unknown-linux-gnu"

Expand All @@ -19,11 +18,6 @@ define <8 x i8> @icmp_eq_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_eq_v8i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: cmeq v0.8b, v0.8b, v1.8b
; NONEON-NOSVE-NEXT: ret
%cmp = icmp eq <8 x i8> %op1, %op2
%sext = sext <8 x i1> %cmp to <8 x i8>
ret <8 x i8> %sext
Expand All @@ -39,11 +33,6 @@ define <16 x i8> @icmp_eq_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
; CHECK-NEXT: mov z0.b, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_eq_v16i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: cmeq v0.16b, v0.16b, v1.16b
; NONEON-NOSVE-NEXT: ret
%cmp = icmp eq <16 x i8> %op1, %op2
%sext = sext <16 x i1> %cmp to <16 x i8>
ret <16 x i8> %sext
Expand All @@ -61,15 +50,6 @@ define void @icmp_eq_v32i8(ptr %a, ptr %b) {
; CHECK-NEXT: mov z1.b, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_eq_v32i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q3, [x1]
; NONEON-NOSVE-NEXT: ldp q1, q2, [x0]
; NONEON-NOSVE-NEXT: cmeq v0.16b, v1.16b, v0.16b
; NONEON-NOSVE-NEXT: cmeq v1.16b, v2.16b, v3.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
%op2 = load <32 x i8>, ptr %b
%cmp = icmp eq <32 x i8> %op1, %op2
Expand All @@ -88,11 +68,6 @@ define <4 x i16> @icmp_eq_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_eq_v4i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: cmeq v0.4h, v0.4h, v1.4h
; NONEON-NOSVE-NEXT: ret
%cmp = icmp eq <4 x i16> %op1, %op2
%sext = sext <4 x i1> %cmp to <4 x i16>
ret <4 x i16> %sext
Expand All @@ -108,11 +83,6 @@ define <8 x i16> @icmp_eq_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_eq_v8i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: cmeq v0.8h, v0.8h, v1.8h
; NONEON-NOSVE-NEXT: ret
%cmp = icmp eq <8 x i16> %op1, %op2
%sext = sext <8 x i1> %cmp to <8 x i16>
ret <8 x i16> %sext
Expand All @@ -130,15 +100,6 @@ define void @icmp_eq_v16i16(ptr %a, ptr %b) {
; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_eq_v16i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q3, [x1]
; NONEON-NOSVE-NEXT: ldp q1, q2, [x0]
; NONEON-NOSVE-NEXT: cmeq v0.8h, v1.8h, v0.8h
; NONEON-NOSVE-NEXT: cmeq v1.8h, v2.8h, v3.8h
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
%op2 = load <16 x i16>, ptr %b
%cmp = icmp eq <16 x i16> %op1, %op2
Expand All @@ -157,11 +118,6 @@ define <2 x i32> @icmp_eq_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_eq_v2i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: cmeq v0.2s, v0.2s, v1.2s
; NONEON-NOSVE-NEXT: ret
%cmp = icmp eq <2 x i32> %op1, %op2
%sext = sext <2 x i1> %cmp to <2 x i32>
ret <2 x i32> %sext
Expand All @@ -177,11 +133,6 @@ define <4 x i32> @icmp_eq_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_eq_v4i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: cmeq v0.4s, v0.4s, v1.4s
; NONEON-NOSVE-NEXT: ret
%cmp = icmp eq <4 x i32> %op1, %op2
%sext = sext <4 x i1> %cmp to <4 x i32>
ret <4 x i32> %sext
Expand All @@ -199,15 +150,6 @@ define void @icmp_eq_v8i32(ptr %a, ptr %b) {
; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_eq_v8i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q3, [x1]
; NONEON-NOSVE-NEXT: ldp q1, q2, [x0]
; NONEON-NOSVE-NEXT: cmeq v0.4s, v1.4s, v0.4s
; NONEON-NOSVE-NEXT: cmeq v1.4s, v2.4s, v3.4s
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
%op2 = load <8 x i32>, ptr %b
%cmp = icmp eq <8 x i32> %op1, %op2
Expand All @@ -226,11 +168,6 @@ define <1 x i64> @icmp_eq_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_eq_v1i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: cmeq d0, d0, d1
; NONEON-NOSVE-NEXT: ret
%cmp = icmp eq <1 x i64> %op1, %op2
%sext = sext <1 x i1> %cmp to <1 x i64>
ret <1 x i64> %sext
Expand All @@ -246,11 +183,6 @@ define <2 x i64> @icmp_eq_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_eq_v2i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: cmeq v0.2d, v0.2d, v1.2d
; NONEON-NOSVE-NEXT: ret
%cmp = icmp eq <2 x i64> %op1, %op2
%sext = sext <2 x i1> %cmp to <2 x i64>
ret <2 x i64> %sext
Expand All @@ -268,15 +200,6 @@ define void @icmp_eq_v4i64(ptr %a, ptr %b) {
; CHECK-NEXT: mov z1.d, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_eq_v4i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q3, [x1]
; NONEON-NOSVE-NEXT: ldp q1, q2, [x0]
; NONEON-NOSVE-NEXT: cmeq v0.2d, v1.2d, v0.2d
; NONEON-NOSVE-NEXT: cmeq v1.2d, v2.2d, v3.2d
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
%op2 = load <4 x i64>, ptr %b
%cmp = icmp eq <4 x i64> %op1, %op2
Expand All @@ -301,17 +224,6 @@ define void @icmp_ne_v32i8(ptr %a, ptr %b) {
; CHECK-NEXT: mov z1.b, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_ne_v32i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q3, [x1]
; NONEON-NOSVE-NEXT: ldp q1, q2, [x0]
; NONEON-NOSVE-NEXT: cmeq v0.16b, v1.16b, v0.16b
; NONEON-NOSVE-NEXT: cmeq v1.16b, v2.16b, v3.16b
; NONEON-NOSVE-NEXT: mvn v0.16b, v0.16b
; NONEON-NOSVE-NEXT: mvn v1.16b, v1.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
%op2 = load <32 x i8>, ptr %b
%cmp = icmp ne <32 x i8> %op1, %op2
Expand All @@ -334,14 +246,6 @@ define void @icmp_sge_v8i16(ptr %a, ptr %b) {
; CHECK-NEXT: mov z0.h, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_sge_v8i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ldr q1, [x1]
; NONEON-NOSVE-NEXT: cmge v0.8h, v0.8h, v1.8h
; NONEON-NOSVE-NEXT: str q0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i16>, ptr %a
%op2 = load <8 x i16>, ptr %b
%cmp = icmp sge <8 x i16> %op1, %op2
Expand All @@ -366,15 +270,6 @@ define void @icmp_sgt_v16i16(ptr %a, ptr %b) {
; CHECK-NEXT: mov z1.h, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_sgt_v16i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q3, [x1]
; NONEON-NOSVE-NEXT: ldp q1, q2, [x0]
; NONEON-NOSVE-NEXT: cmgt v0.8h, v1.8h, v0.8h
; NONEON-NOSVE-NEXT: cmgt v1.8h, v2.8h, v3.8h
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
%op2 = load <16 x i16>, ptr %b
%cmp = icmp sgt <16 x i16> %op1, %op2
Expand All @@ -397,14 +292,6 @@ define void @icmp_sle_v4i32(ptr %a, ptr %b) {
; CHECK-NEXT: mov z0.s, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_sle_v4i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ldr q1, [x1]
; NONEON-NOSVE-NEXT: cmge v0.4s, v1.4s, v0.4s
; NONEON-NOSVE-NEXT: str q0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i32>, ptr %a
%op2 = load <4 x i32>, ptr %b
%cmp = icmp sle <4 x i32> %op1, %op2
Expand All @@ -429,15 +316,6 @@ define void @icmp_slt_v8i32(ptr %a, ptr %b) {
; CHECK-NEXT: mov z1.s, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_slt_v8i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q3, [x1]
; NONEON-NOSVE-NEXT: ldp q1, q2, [x0]
; NONEON-NOSVE-NEXT: cmgt v0.4s, v0.4s, v1.4s
; NONEON-NOSVE-NEXT: cmgt v1.4s, v3.4s, v2.4s
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
%op2 = load <8 x i32>, ptr %b
%cmp = icmp slt <8 x i32> %op1, %op2
Expand All @@ -460,14 +338,6 @@ define void @icmp_uge_v2i64(ptr %a, ptr %b) {
; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_uge_v2i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ldr q1, [x1]
; NONEON-NOSVE-NEXT: cmhs v0.2d, v0.2d, v1.2d
; NONEON-NOSVE-NEXT: str q0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <2 x i64>, ptr %a
%op2 = load <2 x i64>, ptr %b
%cmp = icmp uge <2 x i64> %op1, %op2
Expand All @@ -490,14 +360,6 @@ define void @icmp_ugt_v2i64(ptr %a, ptr %b) {
; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_ugt_v2i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ldr q1, [x1]
; NONEON-NOSVE-NEXT: cmhi v0.2d, v0.2d, v1.2d
; NONEON-NOSVE-NEXT: str q0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <2 x i64>, ptr %a
%op2 = load <2 x i64>, ptr %b
%cmp = icmp ugt <2 x i64> %op1, %op2
Expand All @@ -520,14 +382,6 @@ define void @icmp_ule_v2i64(ptr %a, ptr %b) {
; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_ule_v2i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ldr q1, [x1]
; NONEON-NOSVE-NEXT: cmhs v0.2d, v1.2d, v0.2d
; NONEON-NOSVE-NEXT: str q0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <2 x i64>, ptr %a
%op2 = load <2 x i64>, ptr %b
%cmp = icmp ule <2 x i64> %op1, %op2
Expand All @@ -550,14 +404,6 @@ define void @icmp_ult_v2i64(ptr %a, ptr %b) {
; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: icmp_ult_v2i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ldr q1, [x1]
; NONEON-NOSVE-NEXT: cmhi v0.2d, v1.2d, v0.2d
; NONEON-NOSVE-NEXT: str q0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <2 x i64>, ptr %a
%op2 = load <2 x i64>, ptr %b
%cmp = icmp ult <2 x i64> %op1, %op2
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1,145 changes: 0 additions & 1,145 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
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763 changes: 0 additions & 763 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
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546 changes: 0 additions & 546 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
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7 changes: 0 additions & 7 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mla-neon-fa64.ll
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Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sme-fa64 -force-streaming-compatible-sve < %s | FileCheck %s -check-prefix=FA64
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s -check-prefix=NO-FA64
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE

target triple = "aarch64-unknown-linux-gnu"

Expand All @@ -21,12 +20,6 @@ define <8 x i8> @mla8xi8(<8 x i8> %A, <8 x i8> %B, <8 x i8> %C) {
; NO-FA64-NEXT: mad z0.b, p0/m, z1.b, z2.b
; NO-FA64-NEXT: // kill: def $d0 killed $d0 killed $z0
; NO-FA64-NEXT: ret
;
; NONEON-NOSVE-LABEL: mla8xi8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: mla v2.8b, v0.8b, v1.8b
; NONEON-NOSVE-NEXT: fmov d0, d2
; NONEON-NOSVE-NEXT: ret
%tmp1 = mul <8 x i8> %A, %B;
%tmp2 = add <8 x i8> %C, %tmp1;
ret <8 x i8> %tmp2
Expand Down
291 changes: 0 additions & 291 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
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137 changes: 0 additions & 137 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
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Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE

target triple = "aarch64-unknown-linux-gnu"

Expand All @@ -17,14 +16,6 @@ define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, i1 %mask) {
; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v4i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: csetm w8, ne
; NONEON-NOSVE-NEXT: dup v2.4h, w8
; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; NONEON-NOSVE-NEXT: ret
%sel = select i1 %mask, <4 x i8> %op1, <4 x i8> %op2
ret <4 x i8> %sel
}
Expand All @@ -40,14 +31,6 @@ define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, i1 %mask) {
; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v8i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: csetm w8, ne
; NONEON-NOSVE-NEXT: dup v2.8b, w8
; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; NONEON-NOSVE-NEXT: ret
%sel = select i1 %mask, <8 x i8> %op1, <8 x i8> %op2
ret <8 x i8> %sel
}
Expand All @@ -63,14 +46,6 @@ define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, i1 %mask) {
; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v16i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: csetm w8, ne
; NONEON-NOSVE-NEXT: dup v2.16b, w8
; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b
; NONEON-NOSVE-NEXT: ret
%sel = select i1 %mask, <16 x i8> %op1, <16 x i8> %op2
ret <16 x i8> %sel
}
Expand All @@ -89,20 +64,6 @@ define void @select_v32i8(ptr %a, ptr %b, i1 %mask) {
; CHECK-NEXT: sel z1.b, p0, z1.b, z3.b
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v32i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: tst w2, #0x1
; NONEON-NOSVE-NEXT: ldr q1, [x0]
; NONEON-NOSVE-NEXT: ldr q2, [x0, #16]
; NONEON-NOSVE-NEXT: csetm w8, ne
; NONEON-NOSVE-NEXT: ldr q3, [x1]
; NONEON-NOSVE-NEXT: ldr q4, [x1, #16]
; NONEON-NOSVE-NEXT: dup v0.16b, w8
; NONEON-NOSVE-NEXT: bif v1.16b, v3.16b, v0.16b
; NONEON-NOSVE-NEXT: bsl v0.16b, v2.16b, v4.16b
; NONEON-NOSVE-NEXT: stp q1, q0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load volatile <32 x i8>, ptr %a
%op2 = load volatile <32 x i8>, ptr %b
%sel = select i1 %mask, <32 x i8> %op1, <32 x i8> %op2
Expand All @@ -122,14 +83,6 @@ define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, i1 %mask) {
; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v2i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: csetm w8, ne
; NONEON-NOSVE-NEXT: dup v2.2s, w8
; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; NONEON-NOSVE-NEXT: ret
%sel = select i1 %mask, <2 x i16> %op1, <2 x i16> %op2
ret <2 x i16> %sel
}
Expand All @@ -146,14 +99,6 @@ define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, i1 %mask) {
; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v4i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: csetm w8, ne
; NONEON-NOSVE-NEXT: dup v2.4h, w8
; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; NONEON-NOSVE-NEXT: ret
%sel = select i1 %mask, <4 x i16> %op1, <4 x i16> %op2
ret <4 x i16> %sel
}
Expand All @@ -170,14 +115,6 @@ define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, i1 %mask) {
; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v8i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: csetm w8, ne
; NONEON-NOSVE-NEXT: dup v2.8h, w8
; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b
; NONEON-NOSVE-NEXT: ret
%sel = select i1 %mask, <8 x i16> %op1, <8 x i16> %op2
ret <8 x i16> %sel
}
Expand All @@ -197,20 +134,6 @@ define void @select_v16i16(ptr %a, ptr %b, i1 %mask) {
; CHECK-NEXT: sel z1.h, p0, z1.h, z3.h
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v16i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: tst w2, #0x1
; NONEON-NOSVE-NEXT: ldr q1, [x0]
; NONEON-NOSVE-NEXT: ldr q2, [x0, #16]
; NONEON-NOSVE-NEXT: csetm w8, ne
; NONEON-NOSVE-NEXT: ldr q3, [x1]
; NONEON-NOSVE-NEXT: ldr q4, [x1, #16]
; NONEON-NOSVE-NEXT: dup v0.8h, w8
; NONEON-NOSVE-NEXT: bif v1.16b, v3.16b, v0.16b
; NONEON-NOSVE-NEXT: bsl v0.16b, v2.16b, v4.16b
; NONEON-NOSVE-NEXT: stp q1, q0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load volatile <16 x i16>, ptr %a
%op2 = load volatile <16 x i16>, ptr %b
%sel = select i1 %mask, <16 x i16> %op1, <16 x i16> %op2
Expand All @@ -230,14 +153,6 @@ define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, i1 %mask) {
; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v2i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: csetm w8, ne
; NONEON-NOSVE-NEXT: dup v2.2s, w8
; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; NONEON-NOSVE-NEXT: ret
%sel = select i1 %mask, <2 x i32> %op1, <2 x i32> %op2
ret <2 x i32> %sel
}
Expand All @@ -254,14 +169,6 @@ define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, i1 %mask) {
; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v4i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: csetm w8, ne
; NONEON-NOSVE-NEXT: dup v2.4s, w8
; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b
; NONEON-NOSVE-NEXT: ret
%sel = select i1 %mask, <4 x i32> %op1, <4 x i32> %op2
ret <4 x i32> %sel
}
Expand All @@ -281,20 +188,6 @@ define void @select_v8i32(ptr %a, ptr %b, i1 %mask) {
; CHECK-NEXT: sel z1.s, p0, z1.s, z3.s
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v8i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: tst w2, #0x1
; NONEON-NOSVE-NEXT: ldr q1, [x0]
; NONEON-NOSVE-NEXT: ldr q2, [x0, #16]
; NONEON-NOSVE-NEXT: csetm w8, ne
; NONEON-NOSVE-NEXT: ldr q3, [x1]
; NONEON-NOSVE-NEXT: ldr q4, [x1, #16]
; NONEON-NOSVE-NEXT: dup v0.4s, w8
; NONEON-NOSVE-NEXT: bif v1.16b, v3.16b, v0.16b
; NONEON-NOSVE-NEXT: bsl v0.16b, v2.16b, v4.16b
; NONEON-NOSVE-NEXT: stp q1, q0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load volatile <8 x i32>, ptr %a
%op2 = load volatile <8 x i32>, ptr %b
%sel = select i1 %mask, <8 x i32> %op1, <8 x i32> %op2
Expand All @@ -315,14 +208,6 @@ define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, i1 %mask) {
; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v1i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: csetm x8, ne
; NONEON-NOSVE-NEXT: fmov d2, x8
; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; NONEON-NOSVE-NEXT: ret
%sel = select i1 %mask, <1 x i64> %op1, <1 x i64> %op2
ret <1 x i64> %sel
}
Expand All @@ -340,14 +225,6 @@ define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, i1 %mask) {
; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v2i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: csetm x8, ne
; NONEON-NOSVE-NEXT: dup v2.2d, x8
; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b
; NONEON-NOSVE-NEXT: ret
%sel = select i1 %mask, <2 x i64> %op1, <2 x i64> %op2
ret <2 x i64> %sel
}
Expand All @@ -368,20 +245,6 @@ define void @select_v4i64(ptr %a, ptr %b, i1 %mask) {
; CHECK-NEXT: sel z1.d, p0, z1.d, z3.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v4i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: tst w2, #0x1
; NONEON-NOSVE-NEXT: ldr q1, [x0]
; NONEON-NOSVE-NEXT: ldr q2, [x0, #16]
; NONEON-NOSVE-NEXT: csetm x8, ne
; NONEON-NOSVE-NEXT: ldr q3, [x1]
; NONEON-NOSVE-NEXT: ldr q4, [x1, #16]
; NONEON-NOSVE-NEXT: dup v0.2d, x8
; NONEON-NOSVE-NEXT: bif v1.16b, v3.16b, v0.16b
; NONEON-NOSVE-NEXT: bsl v0.16b, v2.16b, v4.16b
; NONEON-NOSVE-NEXT: stp q1, q0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load volatile <4 x i64>, ptr %a
%op2 = load volatile <4 x i64>, ptr %b
%sel = select i1 %mask, <4 x i64> %op1, <4 x i64> %op2
Expand Down
313 changes: 0 additions & 313 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
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822 changes: 0 additions & 822 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
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123 changes: 0 additions & 123 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
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Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE

target triple = "aarch64-unknown-linux-gnu"

Expand All @@ -19,13 +18,6 @@ define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, <4 x i1> %mask) {
; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v4i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: shl v2.4h, v2.4h, #15
; NONEON-NOSVE-NEXT: cmlt v2.4h, v2.4h, #0
; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; NONEON-NOSVE-NEXT: ret
%sel = select <4 x i1> %mask, <4 x i8> %op1, <4 x i8> %op2
ret <4 x i8> %sel
}
Expand All @@ -44,13 +36,6 @@ define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask) {
; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v8i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: shl v2.8b, v2.8b, #7
; NONEON-NOSVE-NEXT: cmlt v2.8b, v2.8b, #0
; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; NONEON-NOSVE-NEXT: ret
%sel = select <8 x i1> %mask, <8 x i8> %op1, <8 x i8> %op2
ret <8 x i8> %sel
}
Expand All @@ -69,13 +54,6 @@ define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask)
; CHECK-NEXT: sel z0.b, p0, z0.b, z1.b
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v16i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: shl v2.16b, v2.16b, #7
; NONEON-NOSVE-NEXT: cmlt v2.16b, v2.16b, #0
; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b
; NONEON-NOSVE-NEXT: ret
%sel = select <16 x i1> %mask, <16 x i8> %op1, <16 x i8> %op2
ret <16 x i8> %sel
}
Expand All @@ -92,18 +70,6 @@ define void @select_v32i8(ptr %a, ptr %b) {
; CHECK-NEXT: sel z1.b, p0, z2.b, z3.b
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v32i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q2, [x0]
; NONEON-NOSVE-NEXT: ldp q1, q3, [x1]
; NONEON-NOSVE-NEXT: cmeq v4.16b, v0.16b, v1.16b
; NONEON-NOSVE-NEXT: cmeq v5.16b, v2.16b, v3.16b
; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v4.16b
; NONEON-NOSVE-NEXT: mov v1.16b, v5.16b
; NONEON-NOSVE-NEXT: bsl v1.16b, v2.16b, v3.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
%op2 = load <32 x i8>, ptr %b
%mask = icmp eq <32 x i8> %op1, %op2
Expand All @@ -126,13 +92,6 @@ define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, <2 x i1> %mask) {
; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v2i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: shl v2.2s, v2.2s, #31
; NONEON-NOSVE-NEXT: cmlt v2.2s, v2.2s, #0
; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; NONEON-NOSVE-NEXT: ret
%sel = select <2 x i1> %mask, <2 x i16> %op1, <2 x i16> %op2
ret <2 x i16> %sel
}
Expand All @@ -151,13 +110,6 @@ define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, <4 x i1> %mask) {
; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v4i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: shl v2.4h, v2.4h, #15
; NONEON-NOSVE-NEXT: cmlt v2.4h, v2.4h, #0
; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; NONEON-NOSVE-NEXT: ret
%sel = select <4 x i1> %mask, <4 x i16> %op1, <4 x i16> %op2
ret <4 x i16> %sel
}
Expand All @@ -177,14 +129,6 @@ define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask) {
; CHECK-NEXT: sel z0.h, p0, z0.h, z1.h
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v8i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ushll v2.8h, v2.8b, #0
; NONEON-NOSVE-NEXT: shl v2.8h, v2.8h, #15
; NONEON-NOSVE-NEXT: cmlt v2.8h, v2.8h, #0
; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b
; NONEON-NOSVE-NEXT: ret
%sel = select <8 x i1> %mask, <8 x i16> %op1, <8 x i16> %op2
ret <8 x i16> %sel
}
Expand All @@ -201,18 +145,6 @@ define void @select_v16i16(ptr %a, ptr %b) {
; CHECK-NEXT: sel z1.h, p0, z2.h, z3.h
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v16i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q2, [x0]
; NONEON-NOSVE-NEXT: ldp q1, q3, [x1]
; NONEON-NOSVE-NEXT: cmeq v4.8h, v0.8h, v1.8h
; NONEON-NOSVE-NEXT: cmeq v5.8h, v2.8h, v3.8h
; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v4.16b
; NONEON-NOSVE-NEXT: mov v1.16b, v5.16b
; NONEON-NOSVE-NEXT: bsl v1.16b, v2.16b, v3.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
%op2 = load <16 x i16>, ptr %b
%mask = icmp eq <16 x i16> %op1, %op2
Expand All @@ -235,13 +167,6 @@ define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, <2 x i1> %mask) {
; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v2i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: shl v2.2s, v2.2s, #31
; NONEON-NOSVE-NEXT: cmlt v2.2s, v2.2s, #0
; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; NONEON-NOSVE-NEXT: ret
%sel = select <2 x i1> %mask, <2 x i32> %op1, <2 x i32> %op2
ret <2 x i32> %sel
}
Expand All @@ -261,14 +186,6 @@ define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) {
; CHECK-NEXT: sel z0.s, p0, z0.s, z1.s
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v4i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ushll v2.4s, v2.4h, #0
; NONEON-NOSVE-NEXT: shl v2.4s, v2.4s, #31
; NONEON-NOSVE-NEXT: cmlt v2.4s, v2.4s, #0
; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b
; NONEON-NOSVE-NEXT: ret
%sel = select <4 x i1> %mask, <4 x i32> %op1, <4 x i32> %op2
ret <4 x i32> %sel
}
Expand All @@ -285,18 +202,6 @@ define void @select_v8i32(ptr %a, ptr %b) {
; CHECK-NEXT: sel z1.s, p0, z2.s, z3.s
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v8i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q2, [x0]
; NONEON-NOSVE-NEXT: ldp q1, q3, [x1]
; NONEON-NOSVE-NEXT: cmeq v4.4s, v0.4s, v1.4s
; NONEON-NOSVE-NEXT: cmeq v5.4s, v2.4s, v3.4s
; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v4.16b
; NONEON-NOSVE-NEXT: mov v1.16b, v5.16b
; NONEON-NOSVE-NEXT: bsl v1.16b, v2.16b, v3.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
%op2 = load <8 x i32>, ptr %b
%mask = icmp eq <8 x i32> %op1, %op2
Expand All @@ -318,14 +223,6 @@ define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, <1 x i1> %mask) {
; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v1i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: tst w0, #0x1
; NONEON-NOSVE-NEXT: csetm x8, ne
; NONEON-NOSVE-NEXT: fmov d2, x8
; NONEON-NOSVE-NEXT: bif v0.8b, v1.8b, v2.8b
; NONEON-NOSVE-NEXT: ret
%sel = select <1 x i1> %mask, <1 x i64> %op1, <1 x i64> %op2
ret <1 x i64> %sel
}
Expand All @@ -345,14 +242,6 @@ define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) {
; CHECK-NEXT: sel z0.d, p0, z0.d, z1.d
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v2i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ushll v2.2d, v2.2s, #0
; NONEON-NOSVE-NEXT: shl v2.2d, v2.2d, #63
; NONEON-NOSVE-NEXT: cmlt v2.2d, v2.2d, #0
; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v2.16b
; NONEON-NOSVE-NEXT: ret
%sel = select <2 x i1> %mask, <2 x i64> %op1, <2 x i64> %op2
ret <2 x i64> %sel
}
Expand All @@ -369,18 +258,6 @@ define void @select_v4i64(ptr %a, ptr %b) {
; CHECK-NEXT: sel z1.d, p0, z2.d, z3.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: select_v4i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q2, [x0]
; NONEON-NOSVE-NEXT: ldp q1, q3, [x1]
; NONEON-NOSVE-NEXT: cmeq v4.2d, v0.2d, v1.2d
; NONEON-NOSVE-NEXT: cmeq v5.2d, v2.2d, v3.2d
; NONEON-NOSVE-NEXT: bif v0.16b, v1.16b, v4.16b
; NONEON-NOSVE-NEXT: mov v1.16b, v5.16b
; NONEON-NOSVE-NEXT: bsl v1.16b, v2.16b, v3.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
%op2 = load <4 x i64>, ptr %b
%mask = icmp eq <4 x i64> %op1, %op2
Expand Down
27 changes: 0 additions & 27 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE

target triple = "aarch64-unknown-linux-gnu"

Expand All @@ -19,19 +18,6 @@ define <4 x i32> @test(ptr %arg1, ptr %arg2) {
; CHECK-NEXT: stp q2, q5, [x0, #32]
; CHECK-NEXT: stp q1, q3, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test:
; NONEON-NOSVE: // %bb.0: // %entry
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0, #32]
; NONEON-NOSVE-NEXT: ldp q3, q4, [x0]
; NONEON-NOSVE-NEXT: add v2.4s, v0.4s, v0.4s
; NONEON-NOSVE-NEXT: add v5.4s, v1.4s, v1.4s
; NONEON-NOSVE-NEXT: dup v0.4s, v1.s[2]
; NONEON-NOSVE-NEXT: add v1.4s, v3.4s, v3.4s
; NONEON-NOSVE-NEXT: add v3.4s, v4.4s, v4.4s
; NONEON-NOSVE-NEXT: stp q2, q5, [x0, #32]
; NONEON-NOSVE-NEXT: stp q1, q3, [x0]
; NONEON-NOSVE-NEXT: ret
entry:
%0 = load <16 x i32>, ptr %arg1, align 256
%1 = load <16 x i32>, ptr %arg2, align 256
Expand All @@ -56,19 +42,6 @@ define <2 x i32> @test2(ptr %arg1, ptr %arg2) {
; CHECK-NEXT: stp q3, q4, [x0]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test2:
; NONEON-NOSVE: // %bb.0: // %entry
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0, #32]
; NONEON-NOSVE-NEXT: ldp q3, q4, [x0]
; NONEON-NOSVE-NEXT: add v2.4s, v0.4s, v0.4s
; NONEON-NOSVE-NEXT: dup v0.2s, v1.s[2]
; NONEON-NOSVE-NEXT: add v1.4s, v1.4s, v1.4s
; NONEON-NOSVE-NEXT: add v3.4s, v3.4s, v3.4s
; NONEON-NOSVE-NEXT: add v4.4s, v4.4s, v4.4s
; NONEON-NOSVE-NEXT: stp q2, q1, [x0, #32]
; NONEON-NOSVE-NEXT: stp q3, q4, [x0]
; NONEON-NOSVE-NEXT: ret
entry:
%0 = load <16 x i32>, ptr %arg1, align 256
%1 = load <16 x i32>, ptr %arg2, align 256
Expand Down
127 changes: 0 additions & 127 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE

target triple = "aarch64-unknown-linux-gnu"

Expand All @@ -12,13 +11,6 @@ define <4 x i8> @load_v4i8(ptr %a) {
; CHECK-NEXT: ld1b { z0.h }, p0/z, [x0]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v4i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr s0, [x0]
; NONEON-NOSVE-NEXT: ushll v0.8h, v0.8b, #0
; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0
; NONEON-NOSVE-NEXT: ret
%load = load <4 x i8>, ptr %a
ret <4 x i8> %load
}
Expand All @@ -28,11 +20,6 @@ define <8 x i8> @load_v8i8(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v8i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <8 x i8>, ptr %a
ret <8 x i8> %load
}
Expand All @@ -42,11 +29,6 @@ define <16 x i8> @load_v16i8(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v16i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <16 x i8>, ptr %a
ret <16 x i8> %load
}
Expand All @@ -56,11 +38,6 @@ define <32 x i8> @load_v32i8(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v32i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <32 x i8>, ptr %a
ret <32 x i8> %load
}
Expand All @@ -72,15 +49,6 @@ define <2 x i16> @load_v2i16(ptr %a) {
; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0]
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v2i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldrh w8, [x0]
; NONEON-NOSVE-NEXT: fmov s0, w8
; NONEON-NOSVE-NEXT: add x8, x0, #2
; NONEON-NOSVE-NEXT: ld1 { v0.h }[2], [x8]
; NONEON-NOSVE-NEXT: // kill: def $d0 killed $d0 killed $q0
; NONEON-NOSVE-NEXT: ret
%load = load <2 x i16>, ptr %a
ret <2 x i16> %load
}
Expand All @@ -90,11 +58,6 @@ define <2 x half> @load_v2f16(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldr s0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v2f16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr s0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <2 x half>, ptr %a
ret <2 x half> %load
}
Expand All @@ -104,11 +67,6 @@ define <4 x i16> @load_v4i16(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v4i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <4 x i16>, ptr %a
ret <4 x i16> %load
}
Expand All @@ -118,11 +76,6 @@ define <4 x half> @load_v4f16(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v4f16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <4 x half>, ptr %a
ret <4 x half> %load
}
Expand All @@ -132,11 +85,6 @@ define <8 x i16> @load_v8i16(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v8i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <8 x i16>, ptr %a
ret <8 x i16> %load
}
Expand All @@ -146,11 +94,6 @@ define <8 x half> @load_v8f16(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v8f16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <8 x half>, ptr %a
ret <8 x half> %load
}
Expand All @@ -160,11 +103,6 @@ define <16 x i16> @load_v16i16(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v16i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <16 x i16>, ptr %a
ret <16 x i16> %load
}
Expand All @@ -174,11 +112,6 @@ define <16 x half> @load_v16f16(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v16f16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <16 x half>, ptr %a
ret <16 x half> %load
}
Expand All @@ -188,11 +121,6 @@ define <2 x i32> @load_v2i32(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v2i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <2 x i32>, ptr %a
ret <2 x i32> %load
}
Expand All @@ -202,11 +130,6 @@ define <2 x float> @load_v2f32(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v2f32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <2 x float>, ptr %a
ret <2 x float> %load
}
Expand All @@ -216,11 +139,6 @@ define <4 x i32> @load_v4i32(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v4i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <4 x i32>, ptr %a
ret <4 x i32> %load
}
Expand All @@ -230,11 +148,6 @@ define <4 x float> @load_v4f32(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v4f32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <4 x float>, ptr %a
ret <4 x float> %load
}
Expand All @@ -244,11 +157,6 @@ define <8 x i32> @load_v8i32(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v8i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <8 x i32>, ptr %a
ret <8 x i32> %load
}
Expand All @@ -258,11 +166,6 @@ define <8 x float> @load_v8f32(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v8f32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <8 x float>, ptr %a
ret <8 x float> %load
}
Expand All @@ -272,11 +175,6 @@ define <1 x i64> @load_v1i64(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v1i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <1 x i64>, ptr %a
ret <1 x i64> %load
}
Expand All @@ -286,11 +184,6 @@ define <1 x double> @load_v1f64(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v1f64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <1 x double>, ptr %a
ret <1 x double> %load
}
Expand All @@ -300,11 +193,6 @@ define <2 x i64> @load_v2i64(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v2i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <2 x i64>, ptr %a
ret <2 x i64> %load
}
Expand All @@ -314,11 +202,6 @@ define <2 x double> @load_v2f64(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v2f64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <2 x double>, ptr %a
ret <2 x double> %load
}
Expand All @@ -328,11 +211,6 @@ define <4 x i64> @load_v4i64(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v4i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <4 x i64>, ptr %a
ret <4 x i64> %load
}
Expand All @@ -342,11 +220,6 @@ define <4 x double> @load_v4f64(ptr %a) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: load_v4f64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%load = load <4 x double>, ptr %a
ret <4 x double> %load
}
Expand Down
436 changes: 0 additions & 436 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll
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954 changes: 0 additions & 954 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
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774 changes: 0 additions & 774 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-store.ll
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216 changes: 0 additions & 216 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE


target triple = "aarch64-unknown-linux-gnu"
Expand All @@ -15,15 +14,6 @@ define void @add_v4i8(ptr %a, ptr %b) {
; CHECK-NEXT: add z0.h, z0.h, z1.h
; CHECK-NEXT: st1b { z0.h }, p0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: add_v4i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr s0, [x0]
; NONEON-NOSVE-NEXT: ldr s1, [x1]
; NONEON-NOSVE-NEXT: uaddl v0.8h, v0.8b, v1.8b
; NONEON-NOSVE-NEXT: uzp1 v0.8b, v0.8b, v0.8b
; NONEON-NOSVE-NEXT: str s0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i8>, ptr %a
%op2 = load <4 x i8>, ptr %b
%res = add <4 x i8> %op1, %op2
Expand All @@ -39,14 +29,6 @@ define void @add_v8i8(ptr %a, ptr %b) {
; CHECK-NEXT: add z0.b, z0.b, z1.b
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: add_v8i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ldr d1, [x1]
; NONEON-NOSVE-NEXT: add v0.8b, v0.8b, v1.8b
; NONEON-NOSVE-NEXT: str d0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i8>, ptr %a
%op2 = load <8 x i8>, ptr %b
%res = add <8 x i8> %op1, %op2
Expand All @@ -62,14 +44,6 @@ define void @add_v16i8(ptr %a, ptr %b) {
; CHECK-NEXT: add z0.b, z0.b, z1.b
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: add_v16i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ldr q1, [x1]
; NONEON-NOSVE-NEXT: add v0.16b, v0.16b, v1.16b
; NONEON-NOSVE-NEXT: str q0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i8>, ptr %a
%op2 = load <16 x i8>, ptr %b
%res = add <16 x i8> %op1, %op2
Expand All @@ -86,15 +60,6 @@ define void @add_v32i8(ptr %a, ptr %b) {
; CHECK-NEXT: add z1.b, z2.b, z3.b
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: add_v32i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q3, [x1]
; NONEON-NOSVE-NEXT: ldp q1, q2, [x0]
; NONEON-NOSVE-NEXT: add v0.16b, v1.16b, v0.16b
; NONEON-NOSVE-NEXT: add v1.16b, v2.16b, v3.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
%op2 = load <32 x i8>, ptr %b
%res = add <32 x i8> %op1, %op2
Expand All @@ -111,23 +76,6 @@ define void @add_v2i16(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: add z0.s, z0.s, z1.s
; CHECK-NEXT: st1h { z0.s }, p0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: add_v2i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldrh w8, [x0]
; NONEON-NOSVE-NEXT: ldrh w9, [x1]
; NONEON-NOSVE-NEXT: fmov s0, w8
; NONEON-NOSVE-NEXT: fmov s1, w9
; NONEON-NOSVE-NEXT: add x8, x0, #2
; NONEON-NOSVE-NEXT: add x9, x1, #2
; NONEON-NOSVE-NEXT: ld1 { v0.h }[2], [x8]
; NONEON-NOSVE-NEXT: ld1 { v1.h }[2], [x9]
; NONEON-NOSVE-NEXT: add v0.2s, v0.2s, v1.2s
; NONEON-NOSVE-NEXT: mov w8, v0.s[1]
; NONEON-NOSVE-NEXT: fmov w9, s0
; NONEON-NOSVE-NEXT: strh w9, [x0]
; NONEON-NOSVE-NEXT: strh w8, [x0, #2]
; NONEON-NOSVE-NEXT: ret
%op1 = load <2 x i16>, ptr %a
%op2 = load <2 x i16>, ptr %b
%res = add <2 x i16> %op1, %op2
Expand All @@ -143,14 +91,6 @@ define void @add_v4i16(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: add z0.h, z0.h, z1.h
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: add_v4i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ldr d1, [x1]
; NONEON-NOSVE-NEXT: add v0.4h, v0.4h, v1.4h
; NONEON-NOSVE-NEXT: str d0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i16>, ptr %a
%op2 = load <4 x i16>, ptr %b
%res = add <4 x i16> %op1, %op2
Expand All @@ -166,14 +106,6 @@ define void @add_v8i16(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: add z0.h, z0.h, z1.h
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: add_v8i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ldr q1, [x1]
; NONEON-NOSVE-NEXT: add v0.8h, v0.8h, v1.8h
; NONEON-NOSVE-NEXT: str q0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i16>, ptr %a
%op2 = load <8 x i16>, ptr %b
%res = add <8 x i16> %op1, %op2
Expand All @@ -190,15 +122,6 @@ define void @add_v16i16(ptr %a, ptr %b, ptr %c) {
; CHECK-NEXT: add z1.h, z2.h, z3.h
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: add_v16i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q3, [x1]
; NONEON-NOSVE-NEXT: ldp q1, q2, [x0]
; NONEON-NOSVE-NEXT: add v0.8h, v1.8h, v0.8h
; NONEON-NOSVE-NEXT: add v1.8h, v2.8h, v3.8h
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
%op2 = load <16 x i16>, ptr %b
%res = add <16 x i16> %op1, %op2
Expand All @@ -214,13 +137,6 @@ define void @abs_v2i32(ptr %a) {
; CHECK-NEXT: abs z0.s, p0/m, z0.s
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: abs_v2i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: abs v0.2s, v0.2s
; NONEON-NOSVE-NEXT: str d0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <2 x i32>, ptr %a
%res = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %op1, i1 false)
store <2 x i32> %res, ptr %a
Expand All @@ -235,13 +151,6 @@ define void @abs_v4i32(ptr %a) {
; CHECK-NEXT: abs z0.s, p0/m, z0.s
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: abs_v4i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: abs v0.4s, v0.4s
; NONEON-NOSVE-NEXT: str q0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i32>, ptr %a
%res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %op1, i1 false)
store <4 x i32> %res, ptr %a
Expand All @@ -257,14 +166,6 @@ define void @abs_v8i32(ptr %a) {
; CHECK-NEXT: abs z1.s, p0/m, z1.s
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: abs_v8i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: abs v0.4s, v0.4s
; NONEON-NOSVE-NEXT: abs v1.4s, v1.4s
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
%res = call <8 x i32> @llvm.abs.v8i32(<8 x i32> %op1, i1 false)
store <8 x i32> %res, ptr %a
Expand All @@ -279,13 +180,6 @@ define void @abs_v2i64(ptr %a) {
; CHECK-NEXT: abs z0.d, p0/m, z0.d
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: abs_v2i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: abs v0.2d, v0.2d
; NONEON-NOSVE-NEXT: str q0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <2 x i64>, ptr %a
%res = call <2 x i64> @llvm.abs.v2i64(<2 x i64> %op1, i1 false)
store <2 x i64> %res, ptr %a
Expand All @@ -301,14 +195,6 @@ define void @abs_v4i64(ptr %a) {
; CHECK-NEXT: abs z1.d, p0/m, z1.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: abs_v4i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: abs v0.2d, v0.2d
; NONEON-NOSVE-NEXT: abs v1.2d, v1.2d
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
%res = call <4 x i64> @llvm.abs.v4i64(<4 x i64> %op1, i1 false)
store <4 x i64> %res, ptr %a
Expand All @@ -325,17 +211,6 @@ define void @fadd_v2f16(ptr %a, ptr %b) {
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: str w8, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: fadd_v2f16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr s0, [x0]
; NONEON-NOSVE-NEXT: ldr s1, [x1]
; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h
; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h
; NONEON-NOSVE-NEXT: fadd v0.4s, v0.4s, v1.4s
; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s
; NONEON-NOSVE-NEXT: str s0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <2 x half>, ptr %a
%op2 = load <2 x half>, ptr %b
%res = fadd <2 x half> %op1, %op2
Expand All @@ -352,17 +227,6 @@ define void @fadd_v4f16(ptr %a, ptr %b) {
; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: fadd_v4f16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ldr d1, [x1]
; NONEON-NOSVE-NEXT: fcvtl v1.4s, v1.4h
; NONEON-NOSVE-NEXT: fcvtl v0.4s, v0.4h
; NONEON-NOSVE-NEXT: fadd v0.4s, v0.4s, v1.4s
; NONEON-NOSVE-NEXT: fcvtn v0.4h, v0.4s
; NONEON-NOSVE-NEXT: str d0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x half>, ptr %a
%op2 = load <4 x half>, ptr %b
%res = fadd <4 x half> %op1, %op2
Expand All @@ -379,21 +243,6 @@ define void @fadd_v8f16(ptr %a, ptr %b) {
; CHECK-NEXT: fadd z0.h, p0/m, z0.h, z1.h
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: fadd_v8f16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ldr q1, [x1]
; NONEON-NOSVE-NEXT: fcvtl v2.4s, v1.4h
; NONEON-NOSVE-NEXT: fcvtl v3.4s, v0.4h
; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h
; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h
; NONEON-NOSVE-NEXT: fadd v2.4s, v3.4s, v2.4s
; NONEON-NOSVE-NEXT: fadd v0.4s, v0.4s, v1.4s
; NONEON-NOSVE-NEXT: fcvtn v1.4h, v2.4s
; NONEON-NOSVE-NEXT: fcvtn2 v1.8h, v0.4s
; NONEON-NOSVE-NEXT: str q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x half>, ptr %a
%op2 = load <8 x half>, ptr %b
%res = fadd <8 x half> %op1, %op2
Expand All @@ -412,29 +261,6 @@ define void @fadd_v16f16(ptr %a, ptr %b) {
; CHECK-NEXT: fadd z1.h, p0/m, z1.h, z3.h
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: fadd_v16f16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q3, [x1]
; NONEON-NOSVE-NEXT: ldp q1, q2, [x0]
; NONEON-NOSVE-NEXT: fcvtl v4.4s, v0.4h
; NONEON-NOSVE-NEXT: fcvtl v6.4s, v3.4h
; NONEON-NOSVE-NEXT: fcvtl2 v0.4s, v0.8h
; NONEON-NOSVE-NEXT: fcvtl v5.4s, v1.4h
; NONEON-NOSVE-NEXT: fcvtl v7.4s, v2.4h
; NONEON-NOSVE-NEXT: fcvtl2 v1.4s, v1.8h
; NONEON-NOSVE-NEXT: fcvtl2 v3.4s, v3.8h
; NONEON-NOSVE-NEXT: fcvtl2 v2.4s, v2.8h
; NONEON-NOSVE-NEXT: fadd v4.4s, v5.4s, v4.4s
; NONEON-NOSVE-NEXT: fadd v5.4s, v7.4s, v6.4s
; NONEON-NOSVE-NEXT: fadd v0.4s, v1.4s, v0.4s
; NONEON-NOSVE-NEXT: fadd v2.4s, v2.4s, v3.4s
; NONEON-NOSVE-NEXT: fcvtn v1.4h, v4.4s
; NONEON-NOSVE-NEXT: fcvtn v3.4h, v5.4s
; NONEON-NOSVE-NEXT: fcvtn2 v1.8h, v0.4s
; NONEON-NOSVE-NEXT: fcvtn2 v3.8h, v2.4s
; NONEON-NOSVE-NEXT: stp q1, q3, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x half>, ptr %a
%op2 = load <16 x half>, ptr %b
%res = fadd <16 x half> %op1, %op2
Expand All @@ -451,14 +277,6 @@ define void @fadd_v2f32(ptr %a, ptr %b) {
; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: str d0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: fadd_v2f32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr d0, [x0]
; NONEON-NOSVE-NEXT: ldr d1, [x1]
; NONEON-NOSVE-NEXT: fadd v0.2s, v0.2s, v1.2s
; NONEON-NOSVE-NEXT: str d0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <2 x float>, ptr %a
%op2 = load <2 x float>, ptr %b
%res = fadd <2 x float> %op1, %op2
Expand All @@ -475,14 +293,6 @@ define void @fadd_v4f32(ptr %a, ptr %b) {
; CHECK-NEXT: fadd z0.s, p0/m, z0.s, z1.s
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: fadd_v4f32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ldr q1, [x1]
; NONEON-NOSVE-NEXT: fadd v0.4s, v0.4s, v1.4s
; NONEON-NOSVE-NEXT: str q0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x float>, ptr %a
%op2 = load <4 x float>, ptr %b
%res = fadd <4 x float> %op1, %op2
Expand All @@ -501,15 +311,6 @@ define void @fadd_v8f32(ptr %a, ptr %b) {
; CHECK-NEXT: fadd z1.s, p0/m, z1.s, z3.s
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: fadd_v8f32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q3, [x1]
; NONEON-NOSVE-NEXT: ldp q1, q2, [x0]
; NONEON-NOSVE-NEXT: fadd v0.4s, v1.4s, v0.4s
; NONEON-NOSVE-NEXT: fadd v1.4s, v2.4s, v3.4s
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x float>, ptr %a
%op2 = load <8 x float>, ptr %b
%res = fadd <8 x float> %op1, %op2
Expand All @@ -526,14 +327,6 @@ define void @fadd_v2f64(ptr %a, ptr %b) {
; CHECK-NEXT: fadd z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT: str q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: fadd_v2f64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: ldr q1, [x1]
; NONEON-NOSVE-NEXT: fadd v0.2d, v0.2d, v1.2d
; NONEON-NOSVE-NEXT: str q0, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <2 x double>, ptr %a
%op2 = load <2 x double>, ptr %b
%res = fadd <2 x double> %op1, %op2
Expand All @@ -552,15 +345,6 @@ define void @fadd_v4f64(ptr %a, ptr %b) {
; CHECK-NEXT: fadd z1.d, p0/m, z1.d, z3.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: fadd_v4f64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q3, [x1]
; NONEON-NOSVE-NEXT: ldp q1, q2, [x0]
; NONEON-NOSVE-NEXT: fadd v0.2d, v1.2d, v0.2d
; NONEON-NOSVE-NEXT: fadd v1.2d, v2.2d, v3.2d
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x double>, ptr %a
%op2 = load <4 x double>, ptr %b
%res = fadd <4 x double> %op1, %op2
Expand Down
127 changes: 0 additions & 127 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-rev.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE


target triple = "aarch64-unknown-linux-gnu"
Expand All @@ -16,14 +15,6 @@ define void @test_revbv16i16(ptr %a) {
; CHECK-NEXT: revb z1.h, p0/m, z1.h
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test_revbv16i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: rev16 v0.16b, v0.16b
; NONEON-NOSVE-NEXT: rev16 v1.16b, v1.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%tmp1 = load <32 x i8>, ptr %a
%tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14, i32 17, i32 16, i32 19, i32 18, i32 21, i32 20, i32 23, i32 22, i32 undef, i32 24, i32 27, i32 undef, i32 29, i32 28, i32 undef, i32 undef>
store <32 x i8> %tmp2, ptr %a
Expand All @@ -40,14 +31,6 @@ define void @test_revbv8i32(ptr %a) {
; CHECK-NEXT: revb z1.s, p0/m, z1.s
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test_revbv8i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: rev32 v0.16b, v0.16b
; NONEON-NOSVE-NEXT: rev32 v1.16b, v1.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%tmp1 = load <32 x i8>, ptr %a
%tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12, i32 19, i32 18, i32 17, i32 16, i32 23, i32 22, i32 21, i32 20, i32 27, i32 undef, i32 undef, i32 undef, i32 31, i32 30, i32 29, i32 undef>
store <32 x i8> %tmp2, ptr %a
Expand All @@ -64,14 +47,6 @@ define void @test_revbv4i64(ptr %a) {
; CHECK-NEXT: revb z1.d, p0/m, z1.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test_revbv4i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: rev64 v0.16b, v0.16b
; NONEON-NOSVE-NEXT: rev64 v1.16b, v1.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%tmp1 = load <32 x i8>, ptr %a
%tmp2 = shufflevector <32 x i8> %tmp1, <32 x i8> undef, <32 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 23, i32 22, i32 21, i32 20, i32 19, i32 18, i32 17, i32 16, i32 31, i32 30, i32 29, i32 undef, i32 27, i32 undef, i32 undef, i32 undef>
store <32 x i8> %tmp2, ptr %a
Expand All @@ -88,14 +63,6 @@ define void @test_revhv8i32(ptr %a) {
; CHECK-NEXT: revh z1.s, p0/m, z1.s
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test_revhv8i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: rev32 v0.8h, v0.8h
; NONEON-NOSVE-NEXT: rev32 v1.8h, v1.8h
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%tmp1 = load <16 x i16>, ptr %a
%tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
store <16 x i16> %tmp2, ptr %a
Expand All @@ -112,14 +79,6 @@ define void @test_revhv8f32(ptr %a) {
; CHECK-NEXT: revh z1.s, p0/m, z1.s
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test_revhv8f32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: rev32 v0.8h, v0.8h
; NONEON-NOSVE-NEXT: rev32 v1.8h, v1.8h
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%tmp1 = load <16 x half>, ptr %a
%tmp2 = shufflevector <16 x half> %tmp1, <16 x half> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
store <16 x half> %tmp2, ptr %a
Expand All @@ -136,14 +95,6 @@ define void @test_revhv4i64(ptr %a) {
; CHECK-NEXT: revh z1.d, p0/m, z1.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test_revhv4i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: rev64 v0.8h, v0.8h
; NONEON-NOSVE-NEXT: rev64 v1.8h, v1.8h
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%tmp1 = load <16 x i16>, ptr %a
%tmp2 = shufflevector <16 x i16> %tmp1, <16 x i16> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
store <16 x i16> %tmp2, ptr %a
Expand All @@ -160,14 +111,6 @@ define void @test_revwv4i64(ptr %a) {
; CHECK-NEXT: revw z1.d, p0/m, z1.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test_revwv4i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: rev64 v0.4s, v0.4s
; NONEON-NOSVE-NEXT: rev64 v1.4s, v1.4s
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%tmp1 = load <8 x i32>, ptr %a
%tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
store <8 x i32> %tmp2, ptr %a
Expand All @@ -184,14 +127,6 @@ define void @test_revwv4f64(ptr %a) {
; CHECK-NEXT: revw z1.d, p0/m, z1.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test_revwv4f64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: rev64 v0.4s, v0.4s
; NONEON-NOSVE-NEXT: rev64 v1.4s, v1.4s
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%tmp1 = load <8 x float>, ptr %a
%tmp2 = shufflevector <8 x float> %tmp1, <8 x float> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
store <8 x float> %tmp2, ptr %a
Expand All @@ -206,12 +141,6 @@ define <16 x i8> @test_revv16i8(ptr %a) {
; CHECK-NEXT: revb z0.d, p0/m, z0.d
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test_revv16i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldr q0, [x0]
; NONEON-NOSVE-NEXT: rev64 v0.16b, v0.16b
; NONEON-NOSVE-NEXT: ret
%tmp1 = load <16 x i8>, ptr %a
%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
ret <16 x i8> %tmp2
Expand All @@ -227,14 +156,6 @@ define void @test_revwv8i32v8i32(ptr %a, ptr %b) {
; CHECK-NEXT: revw z1.d, p0/m, z1.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test_revwv8i32v8i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x1]
; NONEON-NOSVE-NEXT: rev64 v0.4s, v0.4s
; NONEON-NOSVE-NEXT: rev64 v1.4s, v1.4s
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%tmp1 = load <8 x i32>, ptr %a
%tmp2 = load <8 x i32>, ptr %b
%tmp3 = shufflevector <8 x i32> %tmp1, <8 x i32> %tmp2, <8 x i32> <i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
Expand All @@ -255,18 +176,6 @@ define void @test_revhv32i16(ptr %a) {
; CHECK-NEXT: stp q0, q1, [x0, #32]
; CHECK-NEXT: stp q2, q3, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test_revhv32i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0, #32]
; NONEON-NOSVE-NEXT: ldp q2, q3, [x0]
; NONEON-NOSVE-NEXT: rev64 v0.8h, v0.8h
; NONEON-NOSVE-NEXT: rev64 v1.8h, v1.8h
; NONEON-NOSVE-NEXT: rev64 v2.8h, v2.8h
; NONEON-NOSVE-NEXT: rev64 v3.8h, v3.8h
; NONEON-NOSVE-NEXT: stp q0, q1, [x0, #32]
; NONEON-NOSVE-NEXT: stp q2, q3, [x0]
; NONEON-NOSVE-NEXT: ret
%tmp1 = load <32 x i16>, ptr %a
%tmp2 = shufflevector <32 x i16> %tmp1, <32 x i16> undef, <32 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12, i32 19, i32 18, i32 17, i32 16, i32 23, i32 22, i32 21, i32 20, i32 27, i32 undef, i32 undef, i32 undef, i32 31, i32 30, i32 29, i32 undef>
store <32 x i16> %tmp2, ptr %a
Expand All @@ -282,14 +191,6 @@ define void @test_rev_elts_fail(ptr %a) {
; CHECK-NEXT: tbl z0.d, { z2.d }, z0.d
; CHECK-NEXT: stp q1, q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test_rev_elts_fail:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; NONEON-NOSVE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%tmp1 = load <4 x i64>, ptr %a
%tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
store <4 x i64> %tmp2, ptr %a
Expand All @@ -307,15 +208,6 @@ define void @test_revdv4i64_sve2p1(ptr %a) #1 {
; CHECK-NEXT: revd z1.q, p0/m, z1.q
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test_revdv4i64_sve2p1:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ptrue p0.d, vl2
; NONEON-NOSVE-NEXT: revd z0.q, p0/m, z0.q
; NONEON-NOSVE-NEXT: revd z1.q, p0/m, z1.q
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%tmp1 = load <4 x i64>, ptr %a
%tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
store <4 x i64> %tmp2, ptr %a
Expand All @@ -331,15 +223,6 @@ define void @test_revdv4f64_sve2p1(ptr %a) #1 {
; CHECK-NEXT: revd z1.q, p0/m, z1.q
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test_revdv4f64_sve2p1:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ptrue p0.d
; NONEON-NOSVE-NEXT: revd z0.q, p0/m, z0.q
; NONEON-NOSVE-NEXT: revd z1.q, p0/m, z1.q
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%tmp1 = load <4 x double>, ptr %a
%tmp2 = shufflevector <4 x double> %tmp1, <4 x double> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
store <4 x double> %tmp2, ptr %a
Expand All @@ -355,16 +238,6 @@ define void @test_revv8i32(ptr %a) {
; CHECK-NEXT: tbl z0.s, { z2.s }, z0.s
; CHECK-NEXT: stp q1, q0, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: test_revv8i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0]
; NONEON-NOSVE-NEXT: rev64 v0.4s, v0.4s
; NONEON-NOSVE-NEXT: rev64 v1.4s, v1.4s
; NONEON-NOSVE-NEXT: ext v0.16b, v0.16b, v0.16b, #8
; NONEON-NOSVE-NEXT: ext v1.16b, v1.16b, v1.16b, #8
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%tmp1 = load <8 x i32>, ptr %a
%tmp2 = shufflevector <8 x i32> %tmp1, <8 x i32> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
store <8 x i32> %tmp2, ptr %a
Expand Down
320 changes: 0 additions & 320 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-permute-zip-uzp-trn.ll
View file

Large diffs are not rendered by default.

72 changes: 0 additions & 72 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ptest.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE


target triple = "aarch64-unknown-linux-gnu"
Expand Down Expand Up @@ -36,23 +35,6 @@ define i1 @ptest_v16i1(ptr %a, ptr %b) {
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: ptest_v16i1:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q1, q0, [x0, #32]
; NONEON-NOSVE-NEXT: ldp q2, q3, [x0]
; NONEON-NOSVE-NEXT: fcmeq v0.4s, v0.4s, #0.0
; NONEON-NOSVE-NEXT: fcmeq v1.4s, v1.4s, #0.0
; NONEON-NOSVE-NEXT: fcmeq v3.4s, v3.4s, #0.0
; NONEON-NOSVE-NEXT: fcmeq v2.4s, v2.4s, #0.0
; NONEON-NOSVE-NEXT: uzp1 v0.8h, v1.8h, v0.8h
; NONEON-NOSVE-NEXT: uzp1 v1.8h, v2.8h, v3.8h
; NONEON-NOSVE-NEXT: uzp1 v0.16b, v1.16b, v0.16b
; NONEON-NOSVE-NEXT: mvn v0.16b, v0.16b
; NONEON-NOSVE-NEXT: umaxv b0, v0.16b
; NONEON-NOSVE-NEXT: fmov w8, s0
; NONEON-NOSVE-NEXT: and w0, w8, #0x1
; NONEON-NOSVE-NEXT: ret
%v0 = bitcast ptr %a to ptr
%v1 = load <16 x float>, ptr %v0, align 4
%v2 = fcmp une <16 x float> %v1, zeroinitializer
Expand Down Expand Up @@ -110,33 +92,6 @@ define i1 @ptest_or_v16i1(ptr %a, ptr %b) {
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: ptest_or_v16i1:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0, #32]
; NONEON-NOSVE-NEXT: ldp q2, q3, [x0]
; NONEON-NOSVE-NEXT: ldp q5, q4, [x1, #32]
; NONEON-NOSVE-NEXT: fcmeq v1.4s, v1.4s, #0.0
; NONEON-NOSVE-NEXT: fcmeq v0.4s, v0.4s, #0.0
; NONEON-NOSVE-NEXT: fcmeq v3.4s, v3.4s, #0.0
; NONEON-NOSVE-NEXT: fcmeq v2.4s, v2.4s, #0.0
; NONEON-NOSVE-NEXT: ldp q6, q7, [x1]
; NONEON-NOSVE-NEXT: fcmeq v4.4s, v4.4s, #0.0
; NONEON-NOSVE-NEXT: fcmeq v5.4s, v5.4s, #0.0
; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v1.8h
; NONEON-NOSVE-NEXT: fcmeq v7.4s, v7.4s, #0.0
; NONEON-NOSVE-NEXT: fcmeq v6.4s, v6.4s, #0.0
; NONEON-NOSVE-NEXT: uzp1 v1.8h, v2.8h, v3.8h
; NONEON-NOSVE-NEXT: uzp1 v2.8h, v5.8h, v4.8h
; NONEON-NOSVE-NEXT: uzp1 v3.8h, v6.8h, v7.8h
; NONEON-NOSVE-NEXT: uzp1 v0.16b, v1.16b, v0.16b
; NONEON-NOSVE-NEXT: uzp1 v1.16b, v3.16b, v2.16b
; NONEON-NOSVE-NEXT: mvn v0.16b, v0.16b
; NONEON-NOSVE-NEXT: orn v0.16b, v0.16b, v1.16b
; NONEON-NOSVE-NEXT: umaxv b0, v0.16b
; NONEON-NOSVE-NEXT: fmov w8, s0
; NONEON-NOSVE-NEXT: and w0, w8, #0x1
; NONEON-NOSVE-NEXT: ret
%v0 = bitcast ptr %a to ptr
%v1 = load <16 x float>, ptr %v0, align 4
%v2 = fcmp une <16 x float> %v1, zeroinitializer
Expand Down Expand Up @@ -204,33 +159,6 @@ define i1 @ptest_and_v16i1(ptr %a, ptr %b) {
; CHECK-NEXT: fmov w8, s0
; CHECK-NEXT: and w0, w8, #0x1
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: ptest_and_v16i1:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0, #32]
; NONEON-NOSVE-NEXT: ldp q2, q3, [x0]
; NONEON-NOSVE-NEXT: ldp q5, q4, [x1, #32]
; NONEON-NOSVE-NEXT: fcmeq v1.4s, v1.4s, #0.0
; NONEON-NOSVE-NEXT: fcmeq v0.4s, v0.4s, #0.0
; NONEON-NOSVE-NEXT: fcmeq v3.4s, v3.4s, #0.0
; NONEON-NOSVE-NEXT: fcmeq v2.4s, v2.4s, #0.0
; NONEON-NOSVE-NEXT: ldp q6, q7, [x1]
; NONEON-NOSVE-NEXT: fcmeq v4.4s, v4.4s, #0.0
; NONEON-NOSVE-NEXT: fcmeq v5.4s, v5.4s, #0.0
; NONEON-NOSVE-NEXT: uzp1 v0.8h, v0.8h, v1.8h
; NONEON-NOSVE-NEXT: fcmeq v7.4s, v7.4s, #0.0
; NONEON-NOSVE-NEXT: fcmeq v6.4s, v6.4s, #0.0
; NONEON-NOSVE-NEXT: uzp1 v1.8h, v2.8h, v3.8h
; NONEON-NOSVE-NEXT: uzp1 v2.8h, v5.8h, v4.8h
; NONEON-NOSVE-NEXT: uzp1 v3.8h, v6.8h, v7.8h
; NONEON-NOSVE-NEXT: uzp1 v0.16b, v1.16b, v0.16b
; NONEON-NOSVE-NEXT: uzp1 v1.16b, v3.16b, v2.16b
; NONEON-NOSVE-NEXT: mvn v0.16b, v0.16b
; NONEON-NOSVE-NEXT: bic v0.16b, v0.16b, v1.16b
; NONEON-NOSVE-NEXT: uminv b0, v0.16b
; NONEON-NOSVE-NEXT: fmov w8, s0
; NONEON-NOSVE-NEXT: and w0, w8, #0x1
; NONEON-NOSVE-NEXT: ret
%v0 = bitcast ptr %a to ptr
%v1 = load <16 x float>, ptr %v0, align 4
%v2 = fcmp une <16 x float> %v1, zeroinitializer
Expand Down
159 changes: 0 additions & 159 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE


target triple = "aarch64-unknown-linux-gnu"
Expand All @@ -19,13 +18,6 @@ define <4 x i8> @bitreverse_v4i8(<4 x i8> %op) {
; CHECK-NEXT: lsr z0.h, z0.h, #8
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bitreverse_v4i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rev16 v0.8b, v0.8b
; NONEON-NOSVE-NEXT: rbit v0.8b, v0.8b
; NONEON-NOSVE-NEXT: ushr v0.4h, v0.4h, #8
; NONEON-NOSVE-NEXT: ret
%res = call <4 x i8> @llvm.bitreverse.v4i8(<4 x i8> %op)
ret <4 x i8> %res
}
Expand All @@ -38,11 +30,6 @@ define <8 x i8> @bitreverse_v8i8(<8 x i8> %op) {
; CHECK-NEXT: rbit z0.b, p0/m, z0.b
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bitreverse_v8i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rbit v0.8b, v0.8b
; NONEON-NOSVE-NEXT: ret
%res = call <8 x i8> @llvm.bitreverse.v8i8(<8 x i8> %op)
ret <8 x i8> %res
}
Expand All @@ -55,11 +42,6 @@ define <16 x i8> @bitreverse_v16i8(<16 x i8> %op) {
; CHECK-NEXT: rbit z0.b, p0/m, z0.b
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bitreverse_v16i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rbit v0.16b, v0.16b
; NONEON-NOSVE-NEXT: ret
%res = call <16 x i8> @llvm.bitreverse.v16i8(<16 x i8> %op)
ret <16 x i8> %res
}
Expand All @@ -73,14 +55,6 @@ define void @bitreverse_v32i8(ptr %a) {
; CHECK-NEXT: rbit z1.b, p0/m, z1.b
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bitreverse_v32i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: rbit v0.16b, v0.16b
; NONEON-NOSVE-NEXT: rbit v1.16b, v1.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op = load <32 x i8>, ptr %a
%res = call <32 x i8> @llvm.bitreverse.v32i8(<32 x i8> %op)
store <32 x i8> %res, ptr %a
Expand All @@ -96,13 +70,6 @@ define <2 x i16> @bitreverse_v2i16(<2 x i16> %op) {
; CHECK-NEXT: lsr z0.s, z0.s, #16
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bitreverse_v2i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rev32 v0.8b, v0.8b
; NONEON-NOSVE-NEXT: rbit v0.8b, v0.8b
; NONEON-NOSVE-NEXT: ushr v0.2s, v0.2s, #16
; NONEON-NOSVE-NEXT: ret
%res = call <2 x i16> @llvm.bitreverse.v2i16(<2 x i16> %op)
ret <2 x i16> %res
}
Expand All @@ -115,12 +82,6 @@ define <4 x i16> @bitreverse_v4i16(<4 x i16> %op) {
; CHECK-NEXT: rbit z0.h, p0/m, z0.h
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bitreverse_v4i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rev16 v0.8b, v0.8b
; NONEON-NOSVE-NEXT: rbit v0.8b, v0.8b
; NONEON-NOSVE-NEXT: ret
%res = call <4 x i16> @llvm.bitreverse.v4i16(<4 x i16> %op)
ret <4 x i16> %res
}
Expand All @@ -133,12 +94,6 @@ define <8 x i16> @bitreverse_v8i16(<8 x i16> %op) {
; CHECK-NEXT: rbit z0.h, p0/m, z0.h
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bitreverse_v8i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rev16 v0.16b, v0.16b
; NONEON-NOSVE-NEXT: rbit v0.16b, v0.16b
; NONEON-NOSVE-NEXT: ret
%res = call <8 x i16> @llvm.bitreverse.v8i16(<8 x i16> %op)
ret <8 x i16> %res
}
Expand All @@ -152,16 +107,6 @@ define void @bitreverse_v16i16(ptr %a) {
; CHECK-NEXT: rbit z1.h, p0/m, z1.h
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bitreverse_v16i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: rev16 v0.16b, v0.16b
; NONEON-NOSVE-NEXT: rev16 v1.16b, v1.16b
; NONEON-NOSVE-NEXT: rbit v0.16b, v0.16b
; NONEON-NOSVE-NEXT: rbit v1.16b, v1.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op = load <16 x i16>, ptr %a
%res = call <16 x i16> @llvm.bitreverse.v16i16(<16 x i16> %op)
store <16 x i16> %res, ptr %a
Expand All @@ -176,12 +121,6 @@ define <2 x i32> @bitreverse_v2i32(<2 x i32> %op) {
; CHECK-NEXT: rbit z0.s, p0/m, z0.s
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bitreverse_v2i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rev32 v0.8b, v0.8b
; NONEON-NOSVE-NEXT: rbit v0.8b, v0.8b
; NONEON-NOSVE-NEXT: ret
%res = call <2 x i32> @llvm.bitreverse.v2i32(<2 x i32> %op)
ret <2 x i32> %res
}
Expand All @@ -194,12 +133,6 @@ define <4 x i32> @bitreverse_v4i32(<4 x i32> %op) {
; CHECK-NEXT: rbit z0.s, p0/m, z0.s
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bitreverse_v4i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rev32 v0.16b, v0.16b
; NONEON-NOSVE-NEXT: rbit v0.16b, v0.16b
; NONEON-NOSVE-NEXT: ret
%res = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> %op)
ret <4 x i32> %res
}
Expand All @@ -213,16 +146,6 @@ define void @bitreverse_v8i32(ptr %a) {
; CHECK-NEXT: rbit z1.s, p0/m, z1.s
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bitreverse_v8i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: rev32 v0.16b, v0.16b
; NONEON-NOSVE-NEXT: rev32 v1.16b, v1.16b
; NONEON-NOSVE-NEXT: rbit v0.16b, v0.16b
; NONEON-NOSVE-NEXT: rbit v1.16b, v1.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op = load <8 x i32>, ptr %a
%res = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> %op)
store <8 x i32> %res, ptr %a
Expand All @@ -237,12 +160,6 @@ define <1 x i64> @bitreverse_v1i64(<1 x i64> %op) {
; CHECK-NEXT: rbit z0.d, p0/m, z0.d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bitreverse_v1i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rev64 v0.8b, v0.8b
; NONEON-NOSVE-NEXT: rbit v0.8b, v0.8b
; NONEON-NOSVE-NEXT: ret
%res = call <1 x i64> @llvm.bitreverse.v1i64(<1 x i64> %op)
ret <1 x i64> %res
}
Expand All @@ -255,12 +172,6 @@ define <2 x i64> @bitreverse_v2i64(<2 x i64> %op) {
; CHECK-NEXT: rbit z0.d, p0/m, z0.d
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bitreverse_v2i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rev64 v0.16b, v0.16b
; NONEON-NOSVE-NEXT: rbit v0.16b, v0.16b
; NONEON-NOSVE-NEXT: ret
%res = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %op)
ret <2 x i64> %res
}
Expand All @@ -274,16 +185,6 @@ define void @bitreverse_v4i64(ptr %a) {
; CHECK-NEXT: rbit z1.d, p0/m, z1.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bitreverse_v4i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: rev64 v0.16b, v0.16b
; NONEON-NOSVE-NEXT: rev64 v1.16b, v1.16b
; NONEON-NOSVE-NEXT: rbit v0.16b, v0.16b
; NONEON-NOSVE-NEXT: rbit v1.16b, v1.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op = load <4 x i64>, ptr %a
%res = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> %op)
store <4 x i64> %res, ptr %a
Expand All @@ -303,12 +204,6 @@ define <2 x i16> @bswap_v2i16(<2 x i16> %op) {
; CHECK-NEXT: lsr z0.s, z0.s, #16
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bswap_v2i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rev32 v0.8b, v0.8b
; NONEON-NOSVE-NEXT: ushr v0.2s, v0.2s, #16
; NONEON-NOSVE-NEXT: ret
%res = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %op)
ret <2 x i16> %res
}
Expand All @@ -321,11 +216,6 @@ define <4 x i16> @bswap_v4i16(<4 x i16> %op) {
; CHECK-NEXT: revb z0.h, p0/m, z0.h
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bswap_v4i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rev16 v0.8b, v0.8b
; NONEON-NOSVE-NEXT: ret
%res = call <4 x i16> @llvm.bswap.v4i16(<4 x i16> %op)
ret <4 x i16> %res
}
Expand All @@ -338,11 +228,6 @@ define <8 x i16> @bswap_v8i16(<8 x i16> %op) {
; CHECK-NEXT: revb z0.h, p0/m, z0.h
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bswap_v8i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rev16 v0.16b, v0.16b
; NONEON-NOSVE-NEXT: ret
%res = call <8 x i16> @llvm.bswap.v8i16(<8 x i16> %op)
ret <8 x i16> %res
}
Expand All @@ -356,14 +241,6 @@ define void @bswap_v16i16(ptr %a) {
; CHECK-NEXT: revb z1.h, p0/m, z1.h
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bswap_v16i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: rev16 v0.16b, v0.16b
; NONEON-NOSVE-NEXT: rev16 v1.16b, v1.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op = load <16 x i16>, ptr %a
%res = call <16 x i16> @llvm.bswap.v16i16(<16 x i16> %op)
store <16 x i16> %res, ptr %a
Expand All @@ -378,11 +255,6 @@ define <2 x i32> @bswap_v2i32(<2 x i32> %op) {
; CHECK-NEXT: revb z0.s, p0/m, z0.s
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bswap_v2i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rev32 v0.8b, v0.8b
; NONEON-NOSVE-NEXT: ret
%res = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %op)
ret <2 x i32> %res
}
Expand All @@ -395,11 +267,6 @@ define <4 x i32> @bswap_v4i32(<4 x i32> %op) {
; CHECK-NEXT: revb z0.s, p0/m, z0.s
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bswap_v4i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rev32 v0.16b, v0.16b
; NONEON-NOSVE-NEXT: ret
%res = call <4 x i32> @llvm.bswap.v4i32(<4 x i32> %op)
ret <4 x i32> %res
}
Expand All @@ -413,14 +280,6 @@ define void @bswap_v8i32(ptr %a) {
; CHECK-NEXT: revb z1.s, p0/m, z1.s
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bswap_v8i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: rev32 v0.16b, v0.16b
; NONEON-NOSVE-NEXT: rev32 v1.16b, v1.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op = load <8 x i32>, ptr %a
%res = call <8 x i32> @llvm.bswap.v8i32(<8 x i32> %op)
store <8 x i32> %res, ptr %a
Expand All @@ -435,11 +294,6 @@ define <1 x i64> @bswap_v1i64(<1 x i64> %op) {
; CHECK-NEXT: revb z0.d, p0/m, z0.d
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bswap_v1i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rev64 v0.8b, v0.8b
; NONEON-NOSVE-NEXT: ret
%res = call <1 x i64> @llvm.bswap.v1i64(<1 x i64> %op)
ret <1 x i64> %res
}
Expand All @@ -452,11 +306,6 @@ define <2 x i64> @bswap_v2i64(<2 x i64> %op) {
; CHECK-NEXT: revb z0.d, p0/m, z0.d
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bswap_v2i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: rev64 v0.16b, v0.16b
; NONEON-NOSVE-NEXT: ret
%res = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %op)
ret <2 x i64> %res
}
Expand All @@ -470,14 +319,6 @@ define void @bswap_v4i64(ptr %a) {
; CHECK-NEXT: revb z1.d, p0/m, z1.d
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: bswap_v4i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: rev64 v0.16b, v0.16b
; NONEON-NOSVE-NEXT: rev64 v1.16b, v1.16b
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op = load <4 x i64>, ptr %a
%res = call <4 x i64> @llvm.bswap.v4i64(<4 x i64> %op)
store <4 x i64> %res, ptr %a
Expand Down
132 changes: 0 additions & 132 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-sdiv-pow2.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sme -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s --check-prefix=NONEON-NOSVE


target triple = "aarch64-unknown-linux-gnu"
Expand All @@ -15,19 +14,6 @@ define <4 x i8> @sdiv_v4i8(<4 x i8> %op1) {
; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #5
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: sdiv_v4i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: shl v1.4h, v0.4h, #8
; NONEON-NOSVE-NEXT: movi d2, #0xff00ff00ff00ff
; NONEON-NOSVE-NEXT: sshr v1.4h, v1.4h, #8
; NONEON-NOSVE-NEXT: sshr v1.4h, v1.4h, #7
; NONEON-NOSVE-NEXT: and v1.8b, v1.8b, v2.8b
; NONEON-NOSVE-NEXT: usra v0.4h, v1.4h, #3
; NONEON-NOSVE-NEXT: shl v0.4h, v0.4h, #8
; NONEON-NOSVE-NEXT: sshr v0.4h, v0.4h, #8
; NONEON-NOSVE-NEXT: sshr v0.4h, v0.4h, #5
; NONEON-NOSVE-NEXT: ret
%res = sdiv <4 x i8> %op1, shufflevector (<4 x i8> insertelement (<4 x i8> poison, i8 32, i32 0), <4 x i8> poison, <4 x i32> zeroinitializer)
ret <4 x i8> %res
}
Expand All @@ -40,13 +26,6 @@ define <8 x i8> @sdiv_v8i8(<8 x i8> %op1) {
; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #5
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: sdiv_v8i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: cmlt v1.8b, v0.8b, #0
; NONEON-NOSVE-NEXT: usra v0.8b, v1.8b, #3
; NONEON-NOSVE-NEXT: sshr v0.8b, v0.8b, #5
; NONEON-NOSVE-NEXT: ret
%res = sdiv <8 x i8> %op1, shufflevector (<8 x i8> insertelement (<8 x i8> poison, i8 32, i32 0), <8 x i8> poison, <8 x i32> zeroinitializer)
ret <8 x i8> %res
}
Expand All @@ -59,13 +38,6 @@ define <16 x i8> @sdiv_v16i8(<16 x i8> %op1) {
; CHECK-NEXT: asrd z0.b, p0/m, z0.b, #5
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: sdiv_v16i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: cmlt v1.16b, v0.16b, #0
; NONEON-NOSVE-NEXT: usra v0.16b, v1.16b, #3
; NONEON-NOSVE-NEXT: sshr v0.16b, v0.16b, #5
; NONEON-NOSVE-NEXT: ret
%res = sdiv <16 x i8> %op1, shufflevector (<16 x i8> insertelement (<16 x i8> poison, i8 32, i32 0), <16 x i8> poison, <16 x i32> zeroinitializer)
ret <16 x i8> %res
}
Expand All @@ -79,18 +51,6 @@ define void @sdiv_v32i8(ptr %a) {
; CHECK-NEXT: asrd z1.b, p0/m, z1.b, #5
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: sdiv_v32i8:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: cmlt v2.16b, v0.16b, #0
; NONEON-NOSVE-NEXT: cmlt v3.16b, v1.16b, #0
; NONEON-NOSVE-NEXT: usra v0.16b, v2.16b, #3
; NONEON-NOSVE-NEXT: usra v1.16b, v3.16b, #3
; NONEON-NOSVE-NEXT: sshr v0.16b, v0.16b, #5
; NONEON-NOSVE-NEXT: sshr v1.16b, v1.16b, #5
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <32 x i8>, ptr %a
%res = sdiv <32 x i8> %op1, shufflevector (<32 x i8> insertelement (<32 x i8> poison, i8 32, i32 0), <32 x i8> poison, <32 x i32> zeroinitializer)
store <32 x i8> %res, ptr %a
Expand All @@ -106,20 +66,6 @@ define <2 x i16> @sdiv_v2i16(<2 x i16> %op1) {
; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: sdiv_v2i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: shl v1.2s, v0.2s, #16
; NONEON-NOSVE-NEXT: mov w8, #31 // =0x1f
; NONEON-NOSVE-NEXT: dup v2.2s, w8
; NONEON-NOSVE-NEXT: sshr v1.2s, v1.2s, #16
; NONEON-NOSVE-NEXT: ushr v1.2s, v1.2s, #26
; NONEON-NOSVE-NEXT: and v1.8b, v1.8b, v2.8b
; NONEON-NOSVE-NEXT: add v0.2s, v0.2s, v1.2s
; NONEON-NOSVE-NEXT: shl v0.2s, v0.2s, #16
; NONEON-NOSVE-NEXT: sshr v0.2s, v0.2s, #16
; NONEON-NOSVE-NEXT: sshr v0.2s, v0.2s, #5
; NONEON-NOSVE-NEXT: ret
%res = sdiv <2 x i16> %op1, shufflevector (<2 x i16> insertelement (<2 x i16> poison, i16 32, i32 0), <2 x i16> poison, <2 x i32> zeroinitializer)
ret <2 x i16> %res
}
Expand All @@ -132,13 +78,6 @@ define <4 x i16> @sdiv_v4i16(<4 x i16> %op1) {
; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #5
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: sdiv_v4i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: cmlt v1.4h, v0.4h, #0
; NONEON-NOSVE-NEXT: usra v0.4h, v1.4h, #11
; NONEON-NOSVE-NEXT: sshr v0.4h, v0.4h, #5
; NONEON-NOSVE-NEXT: ret
%res = sdiv <4 x i16> %op1, shufflevector (<4 x i16> insertelement (<4 x i16> poison, i16 32, i32 0), <4 x i16> poison, <4 x i32> zeroinitializer)
ret <4 x i16> %res
}
Expand All @@ -151,13 +90,6 @@ define <8 x i16> @sdiv_v8i16(<8 x i16> %op1) {
; CHECK-NEXT: asrd z0.h, p0/m, z0.h, #5
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: sdiv_v8i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: cmlt v1.8h, v0.8h, #0
; NONEON-NOSVE-NEXT: usra v0.8h, v1.8h, #11
; NONEON-NOSVE-NEXT: sshr v0.8h, v0.8h, #5
; NONEON-NOSVE-NEXT: ret
%res = sdiv <8 x i16> %op1, shufflevector (<8 x i16> insertelement (<8 x i16> poison, i16 32, i32 0), <8 x i16> poison, <8 x i32> zeroinitializer)
ret <8 x i16> %res
}
Expand All @@ -171,18 +103,6 @@ define void @sdiv_v16i16(ptr %a) {
; CHECK-NEXT: asrd z1.h, p0/m, z1.h, #5
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: sdiv_v16i16:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: cmlt v2.8h, v0.8h, #0
; NONEON-NOSVE-NEXT: cmlt v3.8h, v1.8h, #0
; NONEON-NOSVE-NEXT: usra v0.8h, v2.8h, #11
; NONEON-NOSVE-NEXT: usra v1.8h, v3.8h, #11
; NONEON-NOSVE-NEXT: sshr v0.8h, v0.8h, #5
; NONEON-NOSVE-NEXT: sshr v1.8h, v1.8h, #5
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <16 x i16>, ptr %a
%res = sdiv <16 x i16> %op1, shufflevector (<16 x i16> insertelement (<16 x i16> poison, i16 32, i32 0), <16 x i16> poison, <16 x i32> zeroinitializer)
store <16 x i16> %res, ptr %a
Expand All @@ -197,13 +117,6 @@ define <2 x i32> @sdiv_v2i32(<2 x i32> %op1) {
; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: sdiv_v2i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: cmlt v1.2s, v0.2s, #0
; NONEON-NOSVE-NEXT: usra v0.2s, v1.2s, #27
; NONEON-NOSVE-NEXT: sshr v0.2s, v0.2s, #5
; NONEON-NOSVE-NEXT: ret
%res = sdiv <2 x i32> %op1, shufflevector (<2 x i32> insertelement (<2 x i32> poison, i32 32, i32 0), <2 x i32> poison, <2 x i32> zeroinitializer)
ret <2 x i32> %res
}
Expand All @@ -216,13 +129,6 @@ define <4 x i32> @sdiv_v4i32(<4 x i32> %op1) {
; CHECK-NEXT: asrd z0.s, p0/m, z0.s, #5
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: sdiv_v4i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: cmlt v1.4s, v0.4s, #0
; NONEON-NOSVE-NEXT: usra v0.4s, v1.4s, #27
; NONEON-NOSVE-NEXT: sshr v0.4s, v0.4s, #5
; NONEON-NOSVE-NEXT: ret
%res = sdiv <4 x i32> %op1, shufflevector (<4 x i32> insertelement (<4 x i32> poison, i32 32, i32 0), <4 x i32> poison, <4 x i32> zeroinitializer)
ret <4 x i32> %res
}
Expand All @@ -236,18 +142,6 @@ define void @sdiv_v8i32(ptr %a) {
; CHECK-NEXT: asrd z1.s, p0/m, z1.s, #5
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: sdiv_v8i32:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: cmlt v2.4s, v0.4s, #0
; NONEON-NOSVE-NEXT: cmlt v3.4s, v1.4s, #0
; NONEON-NOSVE-NEXT: usra v0.4s, v2.4s, #27
; NONEON-NOSVE-NEXT: usra v1.4s, v3.4s, #27
; NONEON-NOSVE-NEXT: sshr v0.4s, v0.4s, #5
; NONEON-NOSVE-NEXT: sshr v1.4s, v1.4s, #5
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <8 x i32>, ptr %a
%res = sdiv <8 x i32> %op1, shufflevector (<8 x i32> insertelement (<8 x i32> poison, i32 32, i32 0), <8 x i32> poison, <8 x i32> zeroinitializer)
store <8 x i32> %res, ptr %a
Expand All @@ -262,13 +156,6 @@ define <1 x i64> @sdiv_v1i64(<1 x i64> %op1) {
; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #5
; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: sdiv_v1i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: cmlt d1, d0, #0
; NONEON-NOSVE-NEXT: usra d0, d1, #59
; NONEON-NOSVE-NEXT: sshr d0, d0, #5
; NONEON-NOSVE-NEXT: ret
%res = sdiv <1 x i64> %op1, shufflevector (<1 x i64> insertelement (<1 x i64> poison, i64 32, i32 0), <1 x i64> poison, <1 x i32> zeroinitializer)
ret <1 x i64> %res
}
Expand All @@ -282,13 +169,6 @@ define <2 x i64> @sdiv_v2i64(<2 x i64> %op1) {
; CHECK-NEXT: asrd z0.d, p0/m, z0.d, #5
; CHECK-NEXT: // kill: def $q0 killed $q0 killed $z0
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: sdiv_v2i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: cmlt v1.2d, v0.2d, #0
; NONEON-NOSVE-NEXT: usra v0.2d, v1.2d, #59
; NONEON-NOSVE-NEXT: sshr v0.2d, v0.2d, #5
; NONEON-NOSVE-NEXT: ret
%res = sdiv <2 x i64> %op1, shufflevector (<2 x i64> insertelement (<2 x i64> poison, i64 32, i32 0), <2 x i64> poison, <2 x i32> zeroinitializer)
ret <2 x i64> %res
}
Expand All @@ -302,18 +182,6 @@ define void @sdiv_v4i64(ptr %a) {
; CHECK-NEXT: asrd z1.d, p0/m, z1.d, #5
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
;
; NONEON-NOSVE-LABEL: sdiv_v4i64:
; NONEON-NOSVE: // %bb.0:
; NONEON-NOSVE-NEXT: ldp q0, q1, [x0]
; NONEON-NOSVE-NEXT: cmlt v2.2d, v0.2d, #0
; NONEON-NOSVE-NEXT: cmlt v3.2d, v1.2d, #0
; NONEON-NOSVE-NEXT: usra v0.2d, v2.2d, #59
; NONEON-NOSVE-NEXT: usra v1.2d, v3.2d, #59
; NONEON-NOSVE-NEXT: sshr v0.2d, v0.2d, #5
; NONEON-NOSVE-NEXT: sshr v1.2d, v1.2d, #5
; NONEON-NOSVE-NEXT: stp q0, q1, [x0]
; NONEON-NOSVE-NEXT: ret
%op1 = load <4 x i64>, ptr %a
%res = sdiv <4 x i64> %op1, shufflevector (<4 x i64> insertelement (<4 x i64> poison, i64 32, i32 0), <4 x i64> poison, <4 x i32> zeroinitializer)
store <4 x i64> %res, ptr %a
Expand Down
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