440 changes: 440 additions & 0 deletions llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll
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72 changes: 72 additions & 0 deletions llvm/test/CodeGen/RISCV/zfh-half-intrinsics.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -5,12 +5,24 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \
; RUN: -verify-machineinstrs -target-abi lp64f | \
; RUN: FileCheck -check-prefix=RV64IZFH %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=zhinx \
; RUN: -verify-machineinstrs -target-abi ilp32 | \
; RUN: FileCheck -check-prefix=RV32IZHINX %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=zhinx \
; RUN: -verify-machineinstrs -target-abi lp64 | \
; RUN: FileCheck -check-prefix=RV64IZHINX %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
; RUN: -mattr=+zfh -verify-machineinstrs -target-abi ilp32d | \
; RUN: FileCheck -check-prefix=RV32IDZFH %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
; RUN: -mattr=+zfh -verify-machineinstrs -target-abi lp64d | \
; RUN: FileCheck -check-prefix=RV64IDZFH %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
; RUN: -mattr=+zhinx -verify-machineinstrs -target-abi ilp32 | \
; RUN: FileCheck -check-prefix=RV32IZDINXZHINX %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
; RUN: -mattr=+zhinx -verify-machineinstrs -target-abi lp64 | \
; RUN: FileCheck -check-prefix=RV64IZDINXZHINX %s

; These intrinsics require half to be a legal type.

Expand All @@ -27,6 +39,16 @@ define iXLen @lrint_f16(half %a) nounwind {
; RV64IZFH-NEXT: fcvt.l.h a0, fa0
; RV64IZFH-NEXT: ret
;
; RV32IZHINX-LABEL: lrint_f16:
; RV32IZHINX: # %bb.0:
; RV32IZHINX-NEXT: fcvt.w.h a0, a0
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: lrint_f16:
; RV64IZHINX: # %bb.0:
; RV64IZHINX-NEXT: fcvt.l.h a0, a0
; RV64IZHINX-NEXT: ret
;
; RV32IDZFH-LABEL: lrint_f16:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: fcvt.w.h a0, fa0
Expand All @@ -36,6 +58,16 @@ define iXLen @lrint_f16(half %a) nounwind {
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.l.h a0, fa0
; RV64IDZFH-NEXT: ret
;
; RV32IZDINXZHINX-LABEL: lrint_f16:
; RV32IZDINXZHINX: # %bb.0:
; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0
; RV32IZDINXZHINX-NEXT: ret
;
; RV64IZDINXZHINX-LABEL: lrint_f16:
; RV64IZDINXZHINX: # %bb.0:
; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0
; RV64IZDINXZHINX-NEXT: ret
%1 = call iXLen @llvm.lrint.iXLen.f16(half %a)
ret iXLen %1
}
Expand All @@ -54,6 +86,16 @@ define iXLen @lround_f16(half %a) nounwind {
; RV64IZFH-NEXT: fcvt.l.h a0, fa0, rmm
; RV64IZFH-NEXT: ret
;
; RV32IZHINX-LABEL: lround_f16:
; RV32IZHINX: # %bb.0:
; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rmm
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: lround_f16:
; RV64IZHINX: # %bb.0:
; RV64IZHINX-NEXT: fcvt.l.h a0, a0, rmm
; RV64IZHINX-NEXT: ret
;
; RV32IDZFH-LABEL: lround_f16:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rmm
Expand All @@ -63,6 +105,16 @@ define iXLen @lround_f16(half %a) nounwind {
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.l.h a0, fa0, rmm
; RV64IDZFH-NEXT: ret
;
; RV32IZDINXZHINX-LABEL: lround_f16:
; RV32IZDINXZHINX: # %bb.0:
; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rmm
; RV32IZDINXZHINX-NEXT: ret
;
; RV64IZDINXZHINX-LABEL: lround_f16:
; RV64IZDINXZHINX: # %bb.0:
; RV64IZDINXZHINX-NEXT: fcvt.l.h a0, a0, rmm
; RV64IZDINXZHINX-NEXT: ret
%1 = call iXLen @llvm.lround.iXLen.f16(half %a)
ret iXLen %1
}
Expand All @@ -78,6 +130,16 @@ define i32 @lround_i32_f16(half %a) nounwind {
; RV64IZFH-NEXT: fcvt.w.h a0, fa0, rmm
; RV64IZFH-NEXT: ret
;
; RV32IZHINX-LABEL: lround_i32_f16:
; RV32IZHINX: # %bb.0:
; RV32IZHINX-NEXT: fcvt.w.h a0, a0, rmm
; RV32IZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: lround_i32_f16:
; RV64IZHINX: # %bb.0:
; RV64IZHINX-NEXT: fcvt.w.h a0, a0, rmm
; RV64IZHINX-NEXT: ret
;
; RV32IDZFH-LABEL: lround_i32_f16:
; RV32IDZFH: # %bb.0:
; RV32IDZFH-NEXT: fcvt.w.h a0, fa0, rmm
Expand All @@ -87,6 +149,16 @@ define i32 @lround_i32_f16(half %a) nounwind {
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fcvt.w.h a0, fa0, rmm
; RV64IDZFH-NEXT: ret
;
; RV32IZDINXZHINX-LABEL: lround_i32_f16:
; RV32IZDINXZHINX: # %bb.0:
; RV32IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rmm
; RV32IZDINXZHINX-NEXT: ret
;
; RV64IZDINXZHINX-LABEL: lround_i32_f16:
; RV64IZDINXZHINX: # %bb.0:
; RV64IZDINXZHINX-NEXT: fcvt.w.h a0, a0, rmm
; RV64IZDINXZHINX-NEXT: ret
%1 = call i32 @llvm.lround.i32.f16(half %a)
ret i32 %1
}
48 changes: 48 additions & 0 deletions llvm/test/CodeGen/RISCV/zfh-imm.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,14 @@
; RUN: | FileCheck --check-prefix=RV64IZFH %s
; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+zfh,+d < %s \
; RUN: | FileCheck --check-prefix=RV64IDZFH %s
; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinx < %s \
; RUN: | FileCheck --check-prefix=RV32IZHINX %s
; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinx,+zdinx < %s \
; RUN: | FileCheck --check-prefix=RV32IZDINXZHINX %s
; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinx < %s \
; RUN: | FileCheck --check-prefix=RV64IZHINX %s
; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinx,+zdinx < %s \
; RUN: | FileCheck --check-prefix=RV64IZDINXZHINX %s

define half @f16_positive_zero(ptr %pf) nounwind {
; RV32IZFH-LABEL: f16_positive_zero:
Expand All @@ -28,6 +36,26 @@ define half @f16_positive_zero(ptr %pf) nounwind {
; RV64IDZFH: # %bb.0:
; RV64IDZFH-NEXT: fmv.h.x fa0, zero
; RV64IDZFH-NEXT: ret
;
; RV32IZHINX-LABEL: f16_positive_zero:
; RV32IZHINX: # %bb.0:
; RV32IZHINX-NEXT: li a0, 0
; RV32IZHINX-NEXT: ret
;
; RV32IZDINXZHINX-LABEL: f16_positive_zero:
; RV32IZDINXZHINX: # %bb.0:
; RV32IZDINXZHINX-NEXT: li a0, 0
; RV32IZDINXZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: f16_positive_zero:
; RV64IZHINX: # %bb.0:
; RV64IZHINX-NEXT: li a0, 0
; RV64IZHINX-NEXT: ret
;
; RV64IZDINXZHINX-LABEL: f16_positive_zero:
; RV64IZDINXZHINX: # %bb.0:
; RV64IZDINXZHINX-NEXT: li a0, 0
; RV64IZDINXZHINX-NEXT: ret
ret half 0.0
}

Expand Down Expand Up @@ -55,5 +83,25 @@ define half @f16_negative_zero(ptr %pf) nounwind {
; RV64IDZFH-NEXT: lui a0, 1048568
; RV64IDZFH-NEXT: fmv.h.x fa0, a0
; RV64IDZFH-NEXT: ret
;
; RV32IZHINX-LABEL: f16_negative_zero:
; RV32IZHINX: # %bb.0:
; RV32IZHINX-NEXT: lui a0, 1048568
; RV32IZHINX-NEXT: ret
;
; RV32IZDINXZHINX-LABEL: f16_negative_zero:
; RV32IZDINXZHINX: # %bb.0:
; RV32IZDINXZHINX-NEXT: lui a0, 1048568
; RV32IZDINXZHINX-NEXT: ret
;
; RV64IZHINX-LABEL: f16_negative_zero:
; RV64IZHINX: # %bb.0:
; RV64IZHINX-NEXT: lui a0, 1048568
; RV64IZHINX-NEXT: ret
;
; RV64IZDINXZHINX-LABEL: f16_negative_zero:
; RV64IZDINXZHINX: # %bb.0:
; RV64IZDINXZHINX-NEXT: lui a0, 1048568
; RV64IZDINXZHINX-NEXT: ret
ret half -0.0
}
460 changes: 460 additions & 0 deletions llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll
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60 changes: 60 additions & 0 deletions llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,18 @@
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
; RUN: -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d | \
; RUN: FileCheck -check-prefix=RV64IDZFHMIN %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zhinxmin \
; RUN: -verify-machineinstrs -target-abi ilp32 | \
; RUN: FileCheck -check-prefix=RV32IZHINXMIN %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zhinxmin \
; RUN: -verify-machineinstrs -target-abi lp64 | \
; RUN: FileCheck -check-prefix=RV64IZHINXMIN %s
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
; RUN: -mattr=+zhinxmin -verify-machineinstrs -target-abi ilp32 | \
; RUN: FileCheck -check-prefix=RV32IZDINXZHINXMIN %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
; RUN: -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64 | \
; RUN: FileCheck -check-prefix=RV64IZDINXZHINXMIN %s

; These intrinsics require half to be a legal type.

Expand Down Expand Up @@ -40,6 +52,30 @@ define iXLen @lrint_f16(half %a) nounwind {
; RV64IDZFHMIN-NEXT: fcvt.s.h fa5, fa0
; RV64IDZFHMIN-NEXT: fcvt.l.s a0, fa5
; RV64IDZFHMIN-NEXT: ret
;
; RV32IZHINXMIN-LABEL: lrint_f16:
; RV32IZHINXMIN: # %bb.0:
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: lrint_f16:
; RV64IZHINXMIN: # %bb.0:
; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0
; RV64IZHINXMIN-NEXT: ret
;
; RV32IZDINXZHINXMIN-LABEL: lrint_f16:
; RV32IZDINXZHINXMIN: # %bb.0:
; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; RV32IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0
; RV32IZDINXZHINXMIN-NEXT: ret
;
; RV64IZDINXZHINXMIN-LABEL: lrint_f16:
; RV64IZDINXZHINXMIN: # %bb.0:
; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; RV64IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0
; RV64IZDINXZHINXMIN-NEXT: ret
%1 = call iXLen @llvm.lrint.iXLen.f16(half %a)
ret iXLen %1
}
Expand Down Expand Up @@ -70,6 +106,30 @@ define iXLen @lround_f16(half %a) nounwind {
; RV64IDZFHMIN-NEXT: fcvt.s.h fa5, fa0
; RV64IDZFHMIN-NEXT: fcvt.l.s a0, fa5, rmm
; RV64IDZFHMIN-NEXT: ret
;
; RV32IZHINXMIN-LABEL: lround_f16:
; RV32IZHINXMIN: # %bb.0:
; RV32IZHINXMIN-NEXT: fcvt.s.h a0, a0
; RV32IZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm
; RV32IZHINXMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: lround_f16:
; RV64IZHINXMIN: # %bb.0:
; RV64IZHINXMIN-NEXT: fcvt.s.h a0, a0
; RV64IZHINXMIN-NEXT: fcvt.l.s a0, a0, rmm
; RV64IZHINXMIN-NEXT: ret
;
; RV32IZDINXZHINXMIN-LABEL: lround_f16:
; RV32IZDINXZHINXMIN: # %bb.0:
; RV32IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; RV32IZDINXZHINXMIN-NEXT: fcvt.w.s a0, a0, rmm
; RV32IZDINXZHINXMIN-NEXT: ret
;
; RV64IZDINXZHINXMIN-LABEL: lround_f16:
; RV64IZDINXZHINXMIN: # %bb.0:
; RV64IZDINXZHINXMIN-NEXT: fcvt.s.h a0, a0
; RV64IZDINXZHINXMIN-NEXT: fcvt.l.s a0, a0, rmm
; RV64IZDINXZHINXMIN-NEXT: ret
%1 = call iXLen @llvm.lround.iXLen.f16(half %a)
ret iXLen %1
}
48 changes: 48 additions & 0 deletions llvm/test/CodeGen/RISCV/zfhmin-imm.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3,10 +3,18 @@
; RUN: | FileCheck --check-prefix=RV32IZFHMIN %s
; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zfhmin,+d < %s \
; RUN: | FileCheck --check-prefix=RV32IDZFHMIN %s
; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinxmin < %s \
; RUN: | FileCheck --check-prefix=RV32IZHINXMIN %s
; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinxmin,+zdinx < %s \
; RUN: | FileCheck --check-prefix=RV32IZDINXZHINXMIN %s
; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfhmin < %s \
; RUN: | FileCheck --check-prefix=RV64IZFHMIN %s
; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+zfhmin,+d < %s \
; RUN: | FileCheck --check-prefix=RV64IDZFHMIN %s
; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinxmin < %s \
; RUN: | FileCheck --check-prefix=RV64IZHINXMIN %s
; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinxmin,+zdinx < %s \
; RUN: | FileCheck --check-prefix=RV64IZDINXZHINXMIN %s

define half @f16_positive_zero(ptr %pf) nounwind {
; RV32IZFHMIN-LABEL: f16_positive_zero:
Expand All @@ -19,6 +27,16 @@ define half @f16_positive_zero(ptr %pf) nounwind {
; RV32IDZFHMIN-NEXT: fmv.h.x fa0, zero
; RV32IDZFHMIN-NEXT: ret
;
; RV32IZHINXMIN-LABEL: f16_positive_zero:
; RV32IZHINXMIN: # %bb.0:
; RV32IZHINXMIN-NEXT: li a0, 0
; RV32IZHINXMIN-NEXT: ret
;
; RV32IZDINXZHINXMIN-LABEL: f16_positive_zero:
; RV32IZDINXZHINXMIN: # %bb.0:
; RV32IZDINXZHINXMIN-NEXT: li a0, 0
; RV32IZDINXZHINXMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: f16_positive_zero:
; RV64IZFHMIN: # %bb.0:
; RV64IZFHMIN-NEXT: fmv.h.x fa0, zero
Expand All @@ -28,6 +46,16 @@ define half @f16_positive_zero(ptr %pf) nounwind {
; RV64IDZFHMIN: # %bb.0:
; RV64IDZFHMIN-NEXT: fmv.h.x fa0, zero
; RV64IDZFHMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: f16_positive_zero:
; RV64IZHINXMIN: # %bb.0:
; RV64IZHINXMIN-NEXT: li a0, 0
; RV64IZHINXMIN-NEXT: ret
;
; RV64IZDINXZHINXMIN-LABEL: f16_positive_zero:
; RV64IZDINXZHINXMIN: # %bb.0:
; RV64IZDINXZHINXMIN-NEXT: li a0, 0
; RV64IZDINXZHINXMIN-NEXT: ret
ret half 0.0
}

Expand All @@ -44,6 +72,16 @@ define half @f16_negative_zero(ptr %pf) nounwind {
; RV32IDZFHMIN-NEXT: fmv.h.x fa0, a0
; RV32IDZFHMIN-NEXT: ret
;
; RV32IZHINXMIN-LABEL: f16_negative_zero:
; RV32IZHINXMIN: # %bb.0:
; RV32IZHINXMIN-NEXT: lui a0, 1048568
; RV32IZHINXMIN-NEXT: ret
;
; RV32IZDINXZHINXMIN-LABEL: f16_negative_zero:
; RV32IZDINXZHINXMIN: # %bb.0:
; RV32IZDINXZHINXMIN-NEXT: lui a0, 1048568
; RV32IZDINXZHINXMIN-NEXT: ret
;
; RV64IZFHMIN-LABEL: f16_negative_zero:
; RV64IZFHMIN: # %bb.0:
; RV64IZFHMIN-NEXT: lui a0, 1048568
Expand All @@ -55,5 +93,15 @@ define half @f16_negative_zero(ptr %pf) nounwind {
; RV64IDZFHMIN-NEXT: lui a0, 1048568
; RV64IDZFHMIN-NEXT: fmv.h.x fa0, a0
; RV64IDZFHMIN-NEXT: ret
;
; RV64IZHINXMIN-LABEL: f16_negative_zero:
; RV64IZHINXMIN: # %bb.0:
; RV64IZHINXMIN-NEXT: lui a0, 1048568
; RV64IZHINXMIN-NEXT: ret
;
; RV64IZDINXZHINXMIN-LABEL: f16_negative_zero:
; RV64IZDINXZHINXMIN: # %bb.0:
; RV64IZDINXZHINXMIN-NEXT: lui a0, 1048568
; RV64IZDINXZHINXMIN-NEXT: ret
ret half -0.0
}