1,542 changes: 771 additions & 771 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-merge-values.mir
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474 changes: 237 additions & 237 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sext.mir
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54 changes: 27 additions & 27 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-constant-32bit.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -10,11 +10,11 @@ body: |
; CI-LABEL: name: test_sextload_constant32bit_s64_s32_align4
; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load (s32), addrspace 6)
; CI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
; CI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; CI-NEXT: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load (s32), addrspace 6)
; CI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p6) = COPY $sgpr0
%1:_(s64) = G_SEXTLOAD %0 :: (load (s32), align 4, addrspace 6)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -28,11 +28,11 @@ body: |
; CI-LABEL: name: test_sextload_constant32bit_s64_s32_align2
; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load (s32), align 2, addrspace 6)
; CI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
; CI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; CI-NEXT: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load (s32), align 2, addrspace 6)
; CI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p6) = COPY $sgpr0
%1:_(s64) = G_SEXTLOAD %0 :: (load (s32), align 2, addrspace 6)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -46,11 +46,11 @@ body: |
; CI-LABEL: name: test_sextload_constant32bit_s64_s32_align1
; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load (s32), align 1, addrspace 6)
; CI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
; CI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; CI-NEXT: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load (s32), align 1, addrspace 6)
; CI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p6) = COPY $sgpr0
%1:_(s64) = G_SEXTLOAD %0 :: (load (s32), align 1, addrspace 6)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -64,10 +64,10 @@ body: |
; CI-LABEL: name: test_sextload_constant32bit_s32_s8_align1
; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[MV]](p4) :: (load (s8), addrspace 6)
; CI: $vgpr0 = COPY [[SEXTLOAD]](s32)
; CI-NEXT: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[MV]](p4) :: (load (s8), addrspace 6)
; CI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
%0:_(p6) = COPY $sgpr0
%1:_(s32) = G_SEXTLOAD %0 :: (load (s8), align 1, addrspace 6)
$vgpr0 = COPY %1
Expand All @@ -81,10 +81,10 @@ body: |
; CI-LABEL: name: test_sextload_constant32bit_s32_s16_align2
; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[MV]](p4) :: (load (s16), addrspace 6)
; CI: $vgpr0 = COPY [[SEXTLOAD]](s32)
; CI-NEXT: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[MV]](p4) :: (load (s16), addrspace 6)
; CI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
%0:_(p6) = COPY $sgpr0
%1:_(s32) = G_SEXTLOAD %0 :: (load (s16), align 2, addrspace 6)
$vgpr0 = COPY %1
Expand All @@ -98,10 +98,10 @@ body: |
; CI-LABEL: name: test_sextload_constant32bit_s32_s16_align1
; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[MV]](p4) :: (load (s16), align 1, addrspace 6)
; CI: $vgpr0 = COPY [[SEXTLOAD]](s32)
; CI-NEXT: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[MV]](p4) :: (load (s16), align 1, addrspace 6)
; CI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
%0:_(p6) = COPY $sgpr0
%1:_(s32) = G_SEXTLOAD %0 :: (load (s16), align 1, addrspace 6)
$vgpr0 = COPY %1
Expand Down
60 changes: 30 additions & 30 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-flat.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -9,12 +9,12 @@ body: |
; SI-LABEL: name: test_sextload_flat_i32_i8
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
; SI: $vgpr0 = COPY [[SEXTLOAD]](s32)
; SI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
; SI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
; VI-LABEL: name: test_sextload_flat_i32_i8
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
; VI: $vgpr0 = COPY [[SEXTLOAD]](s32)
; VI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
; VI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s32) = G_SEXTLOAD %0 :: (load (s8), addrspace 0)
$vgpr0 = COPY %1
Expand All @@ -27,12 +27,12 @@ body: |
; SI-LABEL: name: test_sextload_flat_i32_i16
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
; SI: $vgpr0 = COPY [[SEXTLOAD]](s32)
; SI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
; SI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
; VI-LABEL: name: test_sextload_flat_i32_i16
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
; VI: $vgpr0 = COPY [[SEXTLOAD]](s32)
; VI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
; VI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s32) = G_SEXTLOAD %0 :: (load (s16), addrspace 0)
$vgpr0 = COPY %1
Expand All @@ -45,12 +45,12 @@ body: |
; SI-LABEL: name: test_sextload_flat_i31_i8
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
; SI: $vgpr0 = COPY [[SEXTLOAD]](s32)
; SI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
; SI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
; VI-LABEL: name: test_sextload_flat_i31_i8
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
; VI: $vgpr0 = COPY [[SEXTLOAD]](s32)
; VI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
; VI-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s31) = G_SEXTLOAD %0 :: (load (s8), addrspace 0)
%2:_(s32) = G_ANYEXT %1
Expand All @@ -64,14 +64,14 @@ body: |
; SI-LABEL: name: test_sextload_flat_i64_i8
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; SI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; SI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
; SI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; VI-LABEL: name: test_sextload_flat_i64_i8
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; VI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; VI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s8))
; VI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXTLOAD %0 :: (load (s8), addrspace 0)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -84,14 +84,14 @@ body: |
; SI-LABEL: name: test_sextload_flat_i64_i16
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; SI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; SI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
; SI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; VI-LABEL: name: test_sextload_flat_i64_i16
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; VI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; VI-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p0) :: (load (s16))
; VI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXTLOAD %0 :: (load (s16), addrspace 0)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -104,14 +104,14 @@ body: |
; SI-LABEL: name: test_sextload_flat_i64_i32
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
; SI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
; SI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
; SI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; VI-LABEL: name: test_sextload_flat_i64_i32
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
; VI: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
; VI: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
; VI-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s64) = G_SEXTLOAD %0 :: (load (s32), addrspace 0)
$vgpr0_vgpr1 = COPY %1
Expand Down
232 changes: 116 additions & 116 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-global.mir
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30 changes: 15 additions & 15 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-local.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,8 @@ body: |
; CHECK-LABEL: name: test_sextload_local_i32_i8
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s32) = G_SEXTLOAD %0 :: (load (s8), addrspace 3)
$vgpr0 = COPY %1
Expand All @@ -23,8 +23,8 @@ body: |
; CHECK-LABEL: name: test_sextload_local_i32_i16
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s32) = G_SEXTLOAD %0 :: (load (s16), addrspace 3)
$vgpr0 = COPY %1
Expand All @@ -37,8 +37,8 @@ body: |
; CHECK-LABEL: name: test_sextload_local_i31_i8
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s31) = G_SEXTLOAD %0 :: (load (s8), addrspace 3)
%2:_(s32) = G_ANYEXT %1
Expand All @@ -52,9 +52,9 @@ body: |
; CHECK-LABEL: name: test_sextload_local_i64_i8
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p3) = COPY $vgpr0
%1:_(s64) = G_SEXTLOAD %0 :: (load (s8), addrspace 3)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -67,9 +67,9 @@ body: |
; CHECK-LABEL: name: test_sextload_local_i64_i16
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p3) = COPY $vgpr0
%1:_(s64) = G_SEXTLOAD %0 :: (load (s16), addrspace 3)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -82,9 +82,9 @@ body: |
; CHECK-LABEL: name: test_sextload_local_i64_i32
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p3) = COPY $vgpr0
%1:_(s64) = G_SEXTLOAD %0 :: (load (s32), addrspace 3)
$vgpr0_vgpr1 = COPY %1
Expand Down
30 changes: 15 additions & 15 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-sextload-private.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,8 @@ body: |
; CHECK-LABEL: name: test_sextload_private_i32_i8
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s32) = G_SEXTLOAD %0 :: (load (s8), addrspace 5)
Expand All @@ -25,8 +25,8 @@ body: |
; CHECK-LABEL: name: test_sextload_private_i32_i16
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s32) = G_SEXTLOAD %0 :: (load (s16), addrspace 5)
$vgpr0 = COPY %1
Expand All @@ -39,8 +39,8 @@ body: |
; CHECK-LABEL: name: test_sextload_private_i31_i8
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; CHECK: $vgpr0 = COPY [[SEXTLOAD]](s32)
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[SEXTLOAD]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s31) = G_SEXTLOAD %0 :: (load (s8), addrspace 5)
%2:_(s32) = G_ANYEXT %1
Expand All @@ -54,9 +54,9 @@ body: |
; CHECK-LABEL: name: test_sextload_private_i64_i8
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p5) = COPY $vgpr0
%1:_(s64) = G_SEXTLOAD %0 :: (load (s8), addrspace 5)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -69,9 +69,9 @@ body: |
; CHECK-LABEL: name: test_sextload_private_i64_i16
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[SEXTLOAD]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p5) = COPY $vgpr0
%1:_(s64) = G_SEXTLOAD %0 :: (load (s16), addrspace 5)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -84,9 +84,9 @@ body: |
; CHECK-LABEL: name: test_sextload_private_i64_i32
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; CHECK: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; CHECK-NEXT: [[SEXT:%[0-9]+]]:_(s64) = G_SEXT [[LOAD]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SEXT]](s64)
%0:_(p5) = COPY $vgpr0
%1:_(s64) = G_SEXTLOAD %0 :: (load (s32), addrspace 5)
$vgpr0_vgpr1 = COPY %1
Expand Down
10,824 changes: 5,412 additions & 5,412 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store-global.mir
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1,002 changes: 501 additions & 501 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-store.mir
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712 changes: 356 additions & 356 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir
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516 changes: 258 additions & 258 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir
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616 changes: 308 additions & 308 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zext.mir
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54 changes: 27 additions & 27 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-constant-32bit.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -11,11 +11,11 @@ body: |
; CI-LABEL: name: test_zextload_constant32bit_s64_s32_align4
; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load (s32), addrspace 6)
; CI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
; CI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; CI-NEXT: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load (s32), addrspace 6)
; CI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(p6) = COPY $sgpr0
%1:_(s64) = G_ZEXTLOAD %0 :: (load (s32), align 4, addrspace 6)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -29,11 +29,11 @@ body: |
; CI-LABEL: name: test_zextload_constant32bit_s64_s32_align2
; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load (s32), align 2, addrspace 6)
; CI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
; CI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; CI-NEXT: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load (s32), align 2, addrspace 6)
; CI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(p6) = COPY $sgpr0
%1:_(s64) = G_ZEXTLOAD %0 :: (load (s32), align 2, addrspace 6)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -47,11 +47,11 @@ body: |
; CI-LABEL: name: test_zextload_constant32bit_s64_s32_align1
; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load (s32), align 1, addrspace 6)
; CI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
; CI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; CI-NEXT: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[MV]](p4) :: (load (s32), align 1, addrspace 6)
; CI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
; CI-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(p6) = COPY $sgpr0
%1:_(s64) = G_ZEXTLOAD %0 :: (load (s32), align 1, addrspace 6)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -65,10 +65,10 @@ body: |
; CI-LABEL: name: test_zextload_constant32bit_s32_s8_align1
; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[MV]](p4) :: (load (s8), addrspace 6)
; CI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; CI-NEXT: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[MV]](p4) :: (load (s8), addrspace 6)
; CI-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p6) = COPY $sgpr0
%1:_(s32) = G_ZEXTLOAD %0 :: (load (s8), align 1, addrspace 6)
$vgpr0 = COPY %1
Expand All @@ -82,10 +82,10 @@ body: |
; CI-LABEL: name: test_zextload_constant32bit_s32_s16_align2
; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[MV]](p4) :: (load (s16), addrspace 6)
; CI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; CI-NEXT: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[MV]](p4) :: (load (s16), addrspace 6)
; CI-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p6) = COPY $sgpr0
%1:_(s32) = G_ZEXTLOAD %0 :: (load (s16), align 2, addrspace 6)
$vgpr0 = COPY %1
Expand All @@ -99,10 +99,10 @@ body: |
; CI-LABEL: name: test_zextload_constant32bit_s32_s16_align1
; CI: [[COPY:%[0-9]+]]:_(p6) = COPY $sgpr0
; CI: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[MV]](p4) :: (load (s16), align 1, addrspace 6)
; CI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; CI-NEXT: [[C:%[0-9]+]]:_(p6) = G_CONSTANT i32 0
; CI-NEXT: [[MV:%[0-9]+]]:_(p4) = G_MERGE_VALUES [[COPY]](p6), [[C]](p6)
; CI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[MV]](p4) :: (load (s16), align 1, addrspace 6)
; CI-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p6) = COPY $sgpr0
%1:_(s32) = G_ZEXTLOAD %0 :: (load (s16), align 1, addrspace 6)
$vgpr0 = COPY %1
Expand Down
60 changes: 30 additions & 30 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-flat.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,12 +9,12 @@ body: |
; SI-LABEL: name: test_zextload_flat_i32_i8
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
; SI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; SI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
; SI-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; VI-LABEL: name: test_zextload_flat_i32_i8
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
; VI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; VI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
; VI-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s32) = G_ZEXTLOAD %0 :: (load (s8), addrspace 0)
$vgpr0 = COPY %1
Expand All @@ -27,12 +27,12 @@ body: |
; SI-LABEL: name: test_zextload_flat_i32_i16
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
; SI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; SI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
; SI-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; VI-LABEL: name: test_zextload_flat_i32_i16
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
; VI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; VI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
; VI-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s32) = G_ZEXTLOAD %0 :: (load (s16), addrspace 0)
$vgpr0 = COPY %1
Expand All @@ -45,12 +45,12 @@ body: |
; SI-LABEL: name: test_zextload_flat_i31_i8
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
; SI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; SI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
; SI-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; VI-LABEL: name: test_zextload_flat_i31_i8
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
; VI: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; VI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
; VI-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s31) = G_ZEXTLOAD %0 :: (load (s8), addrspace 0)
%2:_(s32) = G_ANYEXT %1
Expand All @@ -64,14 +64,14 @@ body: |
; SI-LABEL: name: test_zextload_flat_i64_i8
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; SI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
; SI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; VI-LABEL: name: test_zextload_flat_i64_i8
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; VI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s8))
; VI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s64) = G_ZEXTLOAD %0 :: (load (s8), addrspace 0)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -84,14 +84,14 @@ body: |
; SI-LABEL: name: test_zextload_flat_i64_i16
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; SI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
; SI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; VI-LABEL: name: test_zextload_flat_i64_i16
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; VI-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p0) :: (load (s16))
; VI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s64) = G_ZEXTLOAD %0 :: (load (s16), addrspace 0)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -104,14 +104,14 @@ body: |
; SI-LABEL: name: test_zextload_flat_i64_i32
; SI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; SI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
; SI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
; SI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; SI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
; SI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
; SI-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; VI-LABEL: name: test_zextload_flat_i64_i32
; VI: [[COPY:%[0-9]+]]:_(p0) = COPY $vgpr0_vgpr1
; VI: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
; VI: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
; VI: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; VI-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p0) :: (load (s32))
; VI-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
; VI-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(p0) = COPY $vgpr0_vgpr1
%1:_(s64) = G_ZEXTLOAD %0 :: (load (s32), addrspace 0)
$vgpr0_vgpr1 = COPY %1
Expand Down
232 changes: 116 additions & 116 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-global.mir
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30 changes: 15 additions & 15 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-local.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -9,8 +9,8 @@ body: |
; CHECK-LABEL: name: test_zextload_local_i32_i8
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s32) = G_ZEXTLOAD %0 :: (load (s8), addrspace 3)
$vgpr0 = COPY %1
Expand All @@ -23,8 +23,8 @@ body: |
; CHECK-LABEL: name: test_zextload_local_i32_i16
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s32) = G_ZEXTLOAD %0 :: (load (s16), addrspace 3)
$vgpr0 = COPY %1
Expand All @@ -37,8 +37,8 @@ body: |
; CHECK-LABEL: name: test_zextload_local_i31_i8
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p3) = COPY $vgpr0
%1:_(s31) = G_ZEXTLOAD %0 :: (load (s8), addrspace 3)
%2:_(s32) = G_ANYEXT %1
Expand All @@ -52,9 +52,9 @@ body: |
; CHECK-LABEL: name: test_zextload_local_i64_i8
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load (s8), addrspace 3)
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(p3) = COPY $vgpr0
%1:_(s64) = G_ZEXTLOAD %0 :: (load (s8), addrspace 3)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -67,9 +67,9 @@ body: |
; CHECK-LABEL: name: test_zextload_local_i64_i16
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p3) :: (load (s16), addrspace 3)
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(p3) = COPY $vgpr0
%1:_(s64) = G_ZEXTLOAD %0 :: (load (s16), addrspace 3)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -82,9 +82,9 @@ body: |
; CHECK-LABEL: name: test_zextload_local_i64_i32
; CHECK: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p3) :: (load (s32), addrspace 3)
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(p3) = COPY $vgpr0
%1:_(s64) = G_ZEXTLOAD %0 :: (load (s32), addrspace 3)
$vgpr0_vgpr1 = COPY %1
Expand Down
30 changes: 15 additions & 15 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-zextload-private.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,8 @@ body: |
; CHECK-LABEL: name: test_zextload_private_i32_i8
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s32) = G_ZEXTLOAD %0 :: (load (s8), addrspace 5)
$vgpr0 = COPY %1
Expand All @@ -24,8 +24,8 @@ body: |
; CHECK-LABEL: name: test_zextload_private_i32_i16
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s32) = G_ZEXTLOAD %0 :: (load (s16), addrspace 5)
$vgpr0 = COPY %1
Expand All @@ -38,8 +38,8 @@ body: |
; CHECK-LABEL: name: test_zextload_private_i31_i8
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; CHECK: $vgpr0 = COPY [[ZEXTLOAD]](s32)
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p5) = COPY $vgpr0
%1:_(s31) = G_ZEXTLOAD %0 :: (load (s8), addrspace 5)
%2:_(s32) = G_ANYEXT %1
Expand All @@ -53,9 +53,9 @@ body: |
; CHECK-LABEL: name: test_zextload_private_i64_i8
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load (s8), addrspace 5)
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(p5) = COPY $vgpr0
%1:_(s64) = G_ZEXTLOAD %0 :: (load (s8), addrspace 5)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -68,9 +68,9 @@ body: |
; CHECK-LABEL: name: test_zextload_private_i64_i16
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p5) :: (load (s16), addrspace 5)
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[ZEXTLOAD]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(p5) = COPY $vgpr0
%1:_(s64) = G_ZEXTLOAD %0 :: (load (s16), addrspace 5)
$vgpr0_vgpr1 = COPY %1
Expand All @@ -83,9 +83,9 @@ body: |
; CHECK-LABEL: name: test_zextload_private_i64_i32
; CHECK: [[COPY:%[0-9]+]]:_(p5) = COPY $vgpr0
; CHECK: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
; CHECK: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p5) :: (load (s32), addrspace 5)
; CHECK-NEXT: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[LOAD]](s32)
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ZEXT]](s64)
%0:_(p5) = COPY $vgpr0
%1:_(s64) = G_ZEXTLOAD %0 :: (load (s32), addrspace 5)
$vgpr0_vgpr1 = COPY %1
Expand Down
9 changes: 5 additions & 4 deletions llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-sextload-from-sextinreg.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,10 +11,11 @@ body: |
liveins: $vgpr0_vgpr1
; CHECK-LABEL: name: sextload_from_inreg
; CHECK: liveins: $vgpr0_vgpr1
; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
; CHECK: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[LOAD]], 8
; CHECK: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
; CHECK-NEXT: [[SEXT_INREG:%[0-9]+]]:_(s64) = G_SEXT_INREG [[LOAD]], 8
; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](s64)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s64) = G_LOAD %0 :: (load (s64), align 8, addrspace 1)
%2:_(s64) = G_SEXT_INREG %1, 8
Expand Down