465 changes: 290 additions & 175 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-arith.ll
View file

Large diffs are not rendered by default.

46 changes: 22 additions & 24 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-compares.ll
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s

target triple = "aarch64-unknown-linux-gnu"

;
; ICMP EQ
;

define <8 x i8> @icmp_eq_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
define <8 x i8> @icmp_eq_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
; CHECK-LABEL: icmp_eq_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b, vl8
Expand All @@ -22,7 +22,7 @@ define <8 x i8> @icmp_eq_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
ret <8 x i8> %sext
}

define <16 x i8> @icmp_eq_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
define <16 x i8> @icmp_eq_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
; CHECK-LABEL: icmp_eq_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.b, vl16
Expand All @@ -37,7 +37,7 @@ define <16 x i8> @icmp_eq_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
ret <16 x i8> %sext
}

define void @icmp_eq_v32i8(ptr %a, ptr %b) #0 {
define void @icmp_eq_v32i8(ptr %a, ptr %b) {
; CHECK-LABEL: icmp_eq_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -57,7 +57,7 @@ define void @icmp_eq_v32i8(ptr %a, ptr %b) #0 {
ret void
}

define <4 x i16> @icmp_eq_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
define <4 x i16> @icmp_eq_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
; CHECK-LABEL: icmp_eq_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl4
Expand All @@ -72,7 +72,7 @@ define <4 x i16> @icmp_eq_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
ret <4 x i16> %sext
}

define <8 x i16> @icmp_eq_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
define <8 x i16> @icmp_eq_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
; CHECK-LABEL: icmp_eq_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl8
Expand All @@ -87,7 +87,7 @@ define <8 x i16> @icmp_eq_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
ret <8 x i16> %sext
}

define void @icmp_eq_v16i16(ptr %a, ptr %b) #0 {
define void @icmp_eq_v16i16(ptr %a, ptr %b) {
; CHECK-LABEL: icmp_eq_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -107,7 +107,7 @@ define void @icmp_eq_v16i16(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i32> @icmp_eq_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
define <2 x i32> @icmp_eq_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
; CHECK-LABEL: icmp_eq_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl2
Expand All @@ -122,7 +122,7 @@ define <2 x i32> @icmp_eq_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
ret <2 x i32> %sext
}

define <4 x i32> @icmp_eq_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
define <4 x i32> @icmp_eq_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
; CHECK-LABEL: icmp_eq_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.s, vl4
Expand All @@ -137,7 +137,7 @@ define <4 x i32> @icmp_eq_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
ret <4 x i32> %sext
}

define void @icmp_eq_v8i32(ptr %a, ptr %b) #0 {
define void @icmp_eq_v8i32(ptr %a, ptr %b) {
; CHECK-LABEL: icmp_eq_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -157,7 +157,7 @@ define void @icmp_eq_v8i32(ptr %a, ptr %b) #0 {
ret void
}

define <1 x i64> @icmp_eq_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
define <1 x i64> @icmp_eq_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; CHECK-LABEL: icmp_eq_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl1
Expand All @@ -172,7 +172,7 @@ define <1 x i64> @icmp_eq_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
ret <1 x i64> %sext
}

define <2 x i64> @icmp_eq_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
define <2 x i64> @icmp_eq_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
; CHECK-LABEL: icmp_eq_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.d, vl2
Expand All @@ -187,7 +187,7 @@ define <2 x i64> @icmp_eq_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
ret <2 x i64> %sext
}

define void @icmp_eq_v4i64(ptr %a, ptr %b) #0 {
define void @icmp_eq_v4i64(ptr %a, ptr %b) {
; CHECK-LABEL: icmp_eq_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -211,7 +211,7 @@ define void @icmp_eq_v4i64(ptr %a, ptr %b) #0 {
; ICMP NE
;

define void @icmp_ne_v32i8(ptr %a, ptr %b) #0 {
define void @icmp_ne_v32i8(ptr %a, ptr %b) {
; CHECK-LABEL: icmp_ne_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -235,7 +235,7 @@ define void @icmp_ne_v32i8(ptr %a, ptr %b) #0 {
; ICMP SGE
;

define void @icmp_sge_v8i16(ptr %a, ptr %b) #0 {
define void @icmp_sge_v8i16(ptr %a, ptr %b) {
; CHECK-LABEL: icmp_sge_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
Expand All @@ -257,7 +257,7 @@ define void @icmp_sge_v8i16(ptr %a, ptr %b) #0 {
; ICMP SGT
;

define void @icmp_sgt_v16i16(ptr %a, ptr %b) #0 {
define void @icmp_sgt_v16i16(ptr %a, ptr %b) {
; CHECK-LABEL: icmp_sgt_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -281,7 +281,7 @@ define void @icmp_sgt_v16i16(ptr %a, ptr %b) #0 {
; ICMP SLE
;

define void @icmp_sle_v4i32(ptr %a, ptr %b) #0 {
define void @icmp_sle_v4i32(ptr %a, ptr %b) {
; CHECK-LABEL: icmp_sle_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
Expand All @@ -303,7 +303,7 @@ define void @icmp_sle_v4i32(ptr %a, ptr %b) #0 {
; ICMP SLT
;

define void @icmp_slt_v8i32(ptr %a, ptr %b) #0 {
define void @icmp_slt_v8i32(ptr %a, ptr %b) {
; CHECK-LABEL: icmp_slt_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -327,7 +327,7 @@ define void @icmp_slt_v8i32(ptr %a, ptr %b) #0 {
; ICMP UGE
;

define void @icmp_uge_v2i64(ptr %a, ptr %b) #0 {
define void @icmp_uge_v2i64(ptr %a, ptr %b) {
; CHECK-LABEL: icmp_uge_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
Expand All @@ -349,7 +349,7 @@ define void @icmp_uge_v2i64(ptr %a, ptr %b) #0 {
; ICMP UGT
;

define void @icmp_ugt_v2i64(ptr %a, ptr %b) #0 {
define void @icmp_ugt_v2i64(ptr %a, ptr %b) {
; CHECK-LABEL: icmp_ugt_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
Expand All @@ -371,7 +371,7 @@ define void @icmp_ugt_v2i64(ptr %a, ptr %b) #0 {
; ICMP ULE
;

define void @icmp_ule_v2i64(ptr %a, ptr %b) #0 {
define void @icmp_ule_v2i64(ptr %a, ptr %b) {
; CHECK-LABEL: icmp_ule_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
Expand All @@ -393,7 +393,7 @@ define void @icmp_ule_v2i64(ptr %a, ptr %b) #0 {
; ICMP ULT
;

define void @icmp_ult_v2i64(ptr %a, ptr %b) #0 {
define void @icmp_ult_v2i64(ptr %a, ptr %b) {
; CHECK-LABEL: icmp_ult_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
Expand All @@ -410,5 +410,3 @@ define void @icmp_ult_v2i64(ptr %a, ptr %b) #0 {
store <2 x i64> %sext, ptr %a
ret void
}

attributes #0 = { "target-features"="+sve" }
120 changes: 68 additions & 52 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE
; RUN: llc -mattr=+sve2 -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE2

target triple = "aarch64-unknown-linux-gnu"

;
; SDIV
;

define <4 x i8> @sdiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
define <4 x i8> @sdiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
; CHECK-LABEL: sdiv_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -26,7 +27,7 @@ define <4 x i8> @sdiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
ret <4 x i8> %res
}

define <8 x i8> @sdiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
define <8 x i8> @sdiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
; CHECK-LABEL: sdiv_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -53,7 +54,7 @@ define <8 x i8> @sdiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
ret <8 x i8> %res
}

define <16 x i8> @sdiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
define <16 x i8> @sdiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
; CHECK-LABEL: sdiv_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
Expand Down Expand Up @@ -101,7 +102,7 @@ define <16 x i8> @sdiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
ret <16 x i8> %res
}

define void @sdiv_v32i8(ptr %a, ptr %b) #0 {
define void @sdiv_v32i8(ptr %a, ptr %b) {
; CHECK-LABEL: sdiv_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q2, [x0]
Expand Down Expand Up @@ -182,7 +183,7 @@ define void @sdiv_v32i8(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i16> @sdiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
define <2 x i16> @sdiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) {
; CHECK-LABEL: sdiv_v2i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -197,7 +198,7 @@ define <2 x i16> @sdiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
ret <2 x i16> %res
}

define <4 x i16> @sdiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
define <4 x i16> @sdiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
; CHECK-LABEL: sdiv_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -213,7 +214,7 @@ define <4 x i16> @sdiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
ret <4 x i16> %res
}

define <8 x i16> @sdiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
define <8 x i16> @sdiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
; CHECK-LABEL: sdiv_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
Expand All @@ -239,7 +240,7 @@ define <8 x i16> @sdiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
ret <8 x i16> %res
}

define void @sdiv_v16i16(ptr %a, ptr %b) #0 {
define void @sdiv_v16i16(ptr %a, ptr %b) {
; CHECK-LABEL: sdiv_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q3, q0, [x1]
Expand Down Expand Up @@ -278,7 +279,7 @@ define void @sdiv_v16i16(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i32> @sdiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
define <2 x i32> @sdiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
; CHECK-LABEL: sdiv_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -291,7 +292,7 @@ define <2 x i32> @sdiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
ret <2 x i32> %res
}

define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
; CHECK-LABEL: sdiv_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -304,7 +305,7 @@ define <4 x i32> @sdiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
ret <4 x i32> %res
}

define void @sdiv_v8i32(ptr %a, ptr %b) #0 {
define void @sdiv_v8i32(ptr %a, ptr %b) {
; CHECK-LABEL: sdiv_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -321,7 +322,7 @@ define void @sdiv_v8i32(ptr %a, ptr %b) #0 {
ret void
}

define <1 x i64> @sdiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
define <1 x i64> @sdiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; CHECK-LABEL: sdiv_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -334,7 +335,7 @@ define <1 x i64> @sdiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
ret <1 x i64> %res
}

define <2 x i64> @sdiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
define <2 x i64> @sdiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
; CHECK-LABEL: sdiv_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -347,7 +348,7 @@ define <2 x i64> @sdiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
ret <2 x i64> %res
}

define void @sdiv_v4i64(ptr %a, ptr %b) #0 {
define void @sdiv_v4i64(ptr %a, ptr %b) {
; CHECK-LABEL: sdiv_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -368,7 +369,7 @@ define void @sdiv_v4i64(ptr %a, ptr %b) #0 {
; UDIV
;

define <4 x i8> @udiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
define <4 x i8> @udiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
; CHECK-LABEL: udiv_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -386,7 +387,7 @@ define <4 x i8> @udiv_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
ret <4 x i8> %res
}

define <8 x i8> @udiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
define <8 x i8> @udiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
; CHECK-LABEL: udiv_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -413,7 +414,7 @@ define <8 x i8> @udiv_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
ret <8 x i8> %res
}

define <16 x i8> @udiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
define <16 x i8> @udiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
; CHECK-LABEL: udiv_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
Expand Down Expand Up @@ -461,7 +462,7 @@ define <16 x i8> @udiv_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
ret <16 x i8> %res
}

define void @udiv_v32i8(ptr %a, ptr %b) #0 {
define void @udiv_v32i8(ptr %a, ptr %b) {
; CHECK-LABEL: udiv_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q2, [x0]
Expand Down Expand Up @@ -542,7 +543,7 @@ define void @udiv_v32i8(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i16> @udiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
define <2 x i16> @udiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) {
; CHECK-LABEL: udiv_v2i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -557,7 +558,7 @@ define <2 x i16> @udiv_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
ret <2 x i16> %res
}

define <4 x i16> @udiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
define <4 x i16> @udiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
; CHECK-LABEL: udiv_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -573,7 +574,7 @@ define <4 x i16> @udiv_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
ret <4 x i16> %res
}

define <8 x i16> @udiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
define <8 x i16> @udiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
; CHECK-LABEL: udiv_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
Expand All @@ -599,7 +600,7 @@ define <8 x i16> @udiv_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
ret <8 x i16> %res
}

define void @udiv_v16i16(ptr %a, ptr %b) #0 {
define void @udiv_v16i16(ptr %a, ptr %b) {
; CHECK-LABEL: udiv_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q3, q0, [x1]
Expand Down Expand Up @@ -638,7 +639,7 @@ define void @udiv_v16i16(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i32> @udiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
define <2 x i32> @udiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
; CHECK-LABEL: udiv_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -651,7 +652,7 @@ define <2 x i32> @udiv_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
ret <2 x i32> %res
}

define <4 x i32> @udiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
define <4 x i32> @udiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
; CHECK-LABEL: udiv_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -664,7 +665,7 @@ define <4 x i32> @udiv_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
ret <4 x i32> %res
}

define void @udiv_v8i32(ptr %a, ptr %b) #0 {
define void @udiv_v8i32(ptr %a, ptr %b) {
; CHECK-LABEL: udiv_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -681,7 +682,7 @@ define void @udiv_v8i32(ptr %a, ptr %b) #0 {
ret void
}

define <1 x i64> @udiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
define <1 x i64> @udiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; CHECK-LABEL: udiv_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -694,7 +695,7 @@ define <1 x i64> @udiv_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
ret <1 x i64> %res
}

define <2 x i64> @udiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
define <2 x i64> @udiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
; CHECK-LABEL: udiv_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -707,7 +708,7 @@ define <2 x i64> @udiv_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
ret <2 x i64> %res
}

define void @udiv_v4i64(ptr %a, ptr %b) #0 {
define void @udiv_v4i64(ptr %a, ptr %b) {
; CHECK-LABEL: udiv_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -724,31 +725,46 @@ define void @udiv_v4i64(ptr %a, ptr %b) #0 {
ret void
}

define void @udiv_constantsplat_v8i32(ptr %a) #0 {
; CHECK-LABEL: udiv_constantsplat_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
; CHECK-NEXT: mov w8, #8969 // =0x2309
; CHECK-NEXT: ptrue p0.s, vl4
; CHECK-NEXT: movk w8, #22765, lsl #16
; CHECK-NEXT: mov z2.s, w8
; CHECK-NEXT: movprfx z3, z0
; CHECK-NEXT: umulh z3.s, p0/m, z3.s, z2.s
; CHECK-NEXT: umulh z2.s, p0/m, z2.s, z1.s
; CHECK-NEXT: sub z0.s, z0.s, z3.s
; CHECK-NEXT: sub z1.s, z1.s, z2.s
; CHECK-NEXT: lsr z0.s, z0.s, #1
; CHECK-NEXT: lsr z1.s, z1.s, #1
; CHECK-NEXT: add z0.s, z0.s, z3.s
; CHECK-NEXT: add z1.s, z1.s, z2.s
; CHECK-NEXT: lsr z0.s, z0.s, #6
; CHECK-NEXT: lsr z1.s, z1.s, #6
; CHECK-NEXT: stp q0, q1, [x0]
; CHECK-NEXT: ret
define void @udiv_constantsplat_v8i32(ptr %a) {
; SVE-LABEL: udiv_constantsplat_v8i32:
; SVE: // %bb.0:
; SVE-NEXT: ldp q0, q1, [x0]
; SVE-NEXT: mov w8, #8969 // =0x2309
; SVE-NEXT: ptrue p0.s, vl4
; SVE-NEXT: movk w8, #22765, lsl #16
; SVE-NEXT: mov z2.s, w8
; SVE-NEXT: movprfx z3, z0
; SVE-NEXT: umulh z3.s, p0/m, z3.s, z2.s
; SVE-NEXT: umulh z2.s, p0/m, z2.s, z1.s
; SVE-NEXT: sub z0.s, z0.s, z3.s
; SVE-NEXT: sub z1.s, z1.s, z2.s
; SVE-NEXT: lsr z0.s, z0.s, #1
; SVE-NEXT: lsr z1.s, z1.s, #1
; SVE-NEXT: add z0.s, z0.s, z3.s
; SVE-NEXT: add z1.s, z1.s, z2.s
; SVE-NEXT: lsr z0.s, z0.s, #6
; SVE-NEXT: lsr z1.s, z1.s, #6
; SVE-NEXT: stp q0, q1, [x0]
; SVE-NEXT: ret
;
; SVE2-LABEL: udiv_constantsplat_v8i32:
; SVE2: // %bb.0:
; SVE2-NEXT: ldp q0, q1, [x0]
; SVE2-NEXT: mov w8, #8969 // =0x2309
; SVE2-NEXT: movk w8, #22765, lsl #16
; SVE2-NEXT: mov z2.s, w8
; SVE2-NEXT: umulh z3.s, z0.s, z2.s
; SVE2-NEXT: umulh z2.s, z1.s, z2.s
; SVE2-NEXT: sub z0.s, z0.s, z3.s
; SVE2-NEXT: sub z1.s, z1.s, z2.s
; SVE2-NEXT: usra z3.s, z0.s, #1
; SVE2-NEXT: usra z2.s, z1.s, #1
; SVE2-NEXT: lsr z0.s, z3.s, #6
; SVE2-NEXT: lsr z1.s, z2.s, #6
; SVE2-NEXT: stp q0, q1, [x0]
; SVE2-NEXT: ret
%op1 = load <8 x i32>, ptr %a
%res = udiv <8 x i32> %op1, <i32 95, i32 95, i32 95, i32 95, i32 95, i32 95, i32 95, i32 95>
store <8 x i32> %res, ptr %a
ret void
}

attributes #0 = { "target-features"="+sve" }
104 changes: 56 additions & 48 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE
; RUN: llc -mattr=+sve2 -force-streaming-compatible-sve < %s | FileCheck %s --check-prefixes=CHECK,SVE2

target triple = "aarch64-unknown-linux-gnu"

Expand All @@ -10,7 +11,7 @@ target triple = "aarch64-unknown-linux-gnu"
; NOTE: Covers the scenario where a SIGN_EXTEND_INREG is required, whose inreg
; type's element type is not byte based and thus cannot be lowered directly to
; an SVE instruction.
define void @sext_v8i1_v8i32(<8 x i1> %a, ptr %out) #0 {
define void @sext_v8i1_v8i32(<8 x i1> %a, ptr %out) {
; CHECK-LABEL: sext_v8i1_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -36,7 +37,7 @@ define void @sext_v8i1_v8i32(<8 x i1> %a, ptr %out) #0 {
; NOTE: Covers the scenario where a SIGN_EXTEND_INREG is required, whose inreg
; type's element type is not power-of-2 based and thus cannot be lowered
; directly to an SVE instruction.
define void @sext_v4i3_v4i64(<4 x i3> %a, ptr %out) #0 {
define void @sext_v4i3_v4i64(<4 x i3> %a, ptr %out) {
; CHECK-LABEL: sext_v4i3_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -59,7 +60,7 @@ define void @sext_v4i3_v4i64(<4 x i3> %a, ptr %out) #0 {
; sext i8 -> i16
;

define void @sext_v16i8_v16i16(<16 x i8> %a, ptr %out) #0 {
define void @sext_v16i8_v16i16(<16 x i8> %a, ptr %out) {
; CHECK-LABEL: sext_v16i8_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -74,7 +75,7 @@ define void @sext_v16i8_v16i16(<16 x i8> %a, ptr %out) #0 {
}

; NOTE: Extra 'add' is to prevent the extend being combined with the load.
define void @sext_v32i8_v32i16(ptr %in, ptr %out) #0 {
define void @sext_v32i8_v32i16(ptr %in, ptr %out) {
; CHECK-LABEL: sext_v32i8_v32i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -100,7 +101,7 @@ define void @sext_v32i8_v32i16(ptr %in, ptr %out) #0 {
; sext i8 -> i32
;

define void @sext_v8i8_v8i32(<8 x i8> %a, ptr %out) #0 {
define void @sext_v8i8_v8i32(<8 x i8> %a, ptr %out) {
; CHECK-LABEL: sext_v8i8_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -115,7 +116,7 @@ define void @sext_v8i8_v8i32(<8 x i8> %a, ptr %out) #0 {
ret void
}

define void @sext_v16i8_v16i32(<16 x i8> %a, ptr %out) #0 {
define void @sext_v16i8_v16i32(<16 x i8> %a, ptr %out) {
; CHECK-LABEL: sext_v16i8_v16i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -136,7 +137,7 @@ define void @sext_v16i8_v16i32(<16 x i8> %a, ptr %out) #0 {
ret void
}

define void @sext_v32i8_v32i32(ptr %in, ptr %out) #0 {
define void @sext_v32i8_v32i32(ptr %in, ptr %out) {
; CHECK-LABEL: sext_v32i8_v32i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand Down Expand Up @@ -179,7 +180,7 @@ define void @sext_v32i8_v32i32(ptr %in, ptr %out) #0 {
; NOTE: v4i8 is an unpacked typed stored within a v4i16 container. The sign
; extend is a two step process where the container is any_extend'd with the
; result feeding an inreg sign extend.
define void @sext_v4i8_v4i64(<4 x i8> %a, ptr %out) #0 {
define void @sext_v4i8_v4i64(<4 x i8> %a, ptr %out) {
; CHECK-LABEL: sext_v4i8_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -197,7 +198,7 @@ define void @sext_v4i8_v4i64(<4 x i8> %a, ptr %out) #0 {
ret void
}

define void @sext_v8i8_v8i64(<8 x i8> %a, ptr %out) #0 {
define void @sext_v8i8_v8i64(<8 x i8> %a, ptr %out) {
; CHECK-LABEL: sext_v8i8_v8i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -219,7 +220,7 @@ define void @sext_v8i8_v8i64(<8 x i8> %a, ptr %out) #0 {
ret void
}

define void @sext_v16i8_v16i64(<16 x i8> %a, ptr %out) #0 {
define void @sext_v16i8_v16i64(<16 x i8> %a, ptr %out) {
; CHECK-LABEL: sext_v16i8_v16i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand Down Expand Up @@ -254,7 +255,7 @@ define void @sext_v16i8_v16i64(<16 x i8> %a, ptr %out) #0 {
ret void
}

define void @sext_v32i8_v32i64(ptr %in, ptr %out) #0 {
define void @sext_v32i8_v32i64(ptr %in, ptr %out) {
; CHECK-LABEL: sext_v32i8_v32i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand Down Expand Up @@ -322,7 +323,7 @@ define void @sext_v32i8_v32i64(ptr %in, ptr %out) #0 {
; sext i16 -> i32
;

define void @sext_v8i16_v8i32(<8 x i16> %a, ptr %out) #0 {
define void @sext_v8i16_v8i32(<8 x i16> %a, ptr %out) {
; CHECK-LABEL: sext_v8i16_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -336,7 +337,7 @@ define void @sext_v8i16_v8i32(<8 x i16> %a, ptr %out) #0 {
ret void
}

define void @sext_v16i16_v16i32(ptr %in, ptr %out) #0 {
define void @sext_v16i16_v16i32(ptr %in, ptr %out) {
; CHECK-LABEL: sext_v16i16_v16i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -362,7 +363,7 @@ define void @sext_v16i16_v16i32(ptr %in, ptr %out) #0 {
; sext i16 -> i64
;

define void @sext_v4i16_v4i64(<4 x i16> %a, ptr %out) #0 {
define void @sext_v4i16_v4i64(<4 x i16> %a, ptr %out) {
; CHECK-LABEL: sext_v4i16_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -377,7 +378,7 @@ define void @sext_v4i16_v4i64(<4 x i16> %a, ptr %out) #0 {
ret void
}

define void @sext_v8i16_v8i64(<8 x i16> %a, ptr %out) #0 {
define void @sext_v8i16_v8i64(<8 x i16> %a, ptr %out) {
; CHECK-LABEL: sext_v8i16_v8i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -398,7 +399,7 @@ define void @sext_v8i16_v8i64(<8 x i16> %a, ptr %out) #0 {
ret void
}

define void @sext_v16i16_v16i64(ptr %in, ptr %out) #0 {
define void @sext_v16i16_v16i64(ptr %in, ptr %out) {
; CHECK-LABEL: sext_v16i16_v16i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand Down Expand Up @@ -438,7 +439,7 @@ define void @sext_v16i16_v16i64(ptr %in, ptr %out) #0 {
; sext i32 -> i64
;

define void @sext_v4i32_v4i64(<4 x i32> %a, ptr %out) #0 {
define void @sext_v4i32_v4i64(<4 x i32> %a, ptr %out) {
; CHECK-LABEL: sext_v4i32_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -452,7 +453,7 @@ define void @sext_v4i32_v4i64(<4 x i32> %a, ptr %out) #0 {
ret void
}

define void @sext_v8i32_v8i64(ptr %in, ptr %out) #0 {
define void @sext_v8i32_v8i64(ptr %in, ptr %out) {
; CHECK-LABEL: sext_v8i32_v8i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -478,7 +479,7 @@ define void @sext_v8i32_v8i64(ptr %in, ptr %out) #0 {
; zext i8 -> i16
;

define void @zext_v16i8_v16i16(<16 x i8> %a, ptr %out) #0 {
define void @zext_v16i8_v16i16(<16 x i8> %a, ptr %out) {
; CHECK-LABEL: zext_v16i8_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -493,7 +494,7 @@ define void @zext_v16i8_v16i16(<16 x i8> %a, ptr %out) #0 {
}

; NOTE: Extra 'add' is to prevent the extend being combined with the load.
define void @zext_v32i8_v32i16(ptr %in, ptr %out) #0 {
define void @zext_v32i8_v32i16(ptr %in, ptr %out) {
; CHECK-LABEL: zext_v32i8_v32i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -519,7 +520,7 @@ define void @zext_v32i8_v32i16(ptr %in, ptr %out) #0 {
; zext i8 -> i32
;

define void @zext_v8i8_v8i32(<8 x i8> %a, ptr %out) #0 {
define void @zext_v8i8_v8i32(<8 x i8> %a, ptr %out) {
; CHECK-LABEL: zext_v8i8_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -534,7 +535,7 @@ define void @zext_v8i8_v8i32(<8 x i8> %a, ptr %out) #0 {
ret void
}

define void @zext_v16i8_v16i32(<16 x i8> %a, ptr %out) #0 {
define void @zext_v16i8_v16i32(<16 x i8> %a, ptr %out) {
; CHECK-LABEL: zext_v16i8_v16i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -555,7 +556,7 @@ define void @zext_v16i8_v16i32(<16 x i8> %a, ptr %out) #0 {
ret void
}

define void @zext_v32i8_v32i32(ptr %in, ptr %out) #0 {
define void @zext_v32i8_v32i32(ptr %in, ptr %out) {
; CHECK-LABEL: zext_v32i8_v32i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand Down Expand Up @@ -598,7 +599,7 @@ define void @zext_v32i8_v32i32(ptr %in, ptr %out) #0 {
; NOTE: v4i8 is an unpacked typed stored within a v4i16 container. The zero
; extend is a two step process where the container is zero_extend_inreg'd with
; the result feeding a normal zero extend from halfs to doublewords.
define void @zext_v4i8_v4i64(<4 x i8> %a, ptr %out) #0 {
define void @zext_v4i8_v4i64(<4 x i8> %a, ptr %out) {
; CHECK-LABEL: zext_v4i8_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -614,7 +615,7 @@ define void @zext_v4i8_v4i64(<4 x i8> %a, ptr %out) #0 {
ret void
}

define void @zext_v8i8_v8i64(<8 x i8> %a, ptr %out) #0 {
define void @zext_v8i8_v8i64(<8 x i8> %a, ptr %out) {
; CHECK-LABEL: zext_v8i8_v8i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -636,7 +637,7 @@ define void @zext_v8i8_v8i64(<8 x i8> %a, ptr %out) #0 {
ret void
}

define void @zext_v16i8_v16i64(<16 x i8> %a, ptr %out) #0 {
define void @zext_v16i8_v16i64(<16 x i8> %a, ptr %out) {
; CHECK-LABEL: zext_v16i8_v16i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand Down Expand Up @@ -671,7 +672,7 @@ define void @zext_v16i8_v16i64(<16 x i8> %a, ptr %out) #0 {
ret void
}

define void @zext_v32i8_v32i64(ptr %in, ptr %out) #0 {
define void @zext_v32i8_v32i64(ptr %in, ptr %out) {
; CHECK-LABEL: zext_v32i8_v32i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand Down Expand Up @@ -739,7 +740,7 @@ define void @zext_v32i8_v32i64(ptr %in, ptr %out) #0 {
; zext i16 -> i32
;

define void @zext_v8i16_v8i32(<8 x i16> %a, ptr %out) #0 {
define void @zext_v8i16_v8i32(<8 x i16> %a, ptr %out) {
; CHECK-LABEL: zext_v8i16_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -753,7 +754,7 @@ define void @zext_v8i16_v8i32(<8 x i16> %a, ptr %out) #0 {
ret void
}

define void @zext_v16i16_v16i32(ptr %in, ptr %out) #0 {
define void @zext_v16i16_v16i32(ptr %in, ptr %out) {
; CHECK-LABEL: zext_v16i16_v16i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -779,7 +780,7 @@ define void @zext_v16i16_v16i32(ptr %in, ptr %out) #0 {
; zext i16 -> i64
;

define void @zext_v4i16_v4i64(<4 x i16> %a, ptr %out) #0 {
define void @zext_v4i16_v4i64(<4 x i16> %a, ptr %out) {
; CHECK-LABEL: zext_v4i16_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -794,7 +795,7 @@ define void @zext_v4i16_v4i64(<4 x i16> %a, ptr %out) #0 {
ret void
}

define void @zext_v8i16_v8i64(<8 x i16> %a, ptr %out) #0 {
define void @zext_v8i16_v8i64(<8 x i16> %a, ptr %out) {
; CHECK-LABEL: zext_v8i16_v8i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -815,7 +816,7 @@ define void @zext_v8i16_v8i64(<8 x i16> %a, ptr %out) #0 {
ret void
}

define void @zext_v16i16_v16i64(ptr %in, ptr %out) #0 {
define void @zext_v16i16_v16i64(ptr %in, ptr %out) {
; CHECK-LABEL: zext_v16i16_v16i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand Down Expand Up @@ -855,7 +856,7 @@ define void @zext_v16i16_v16i64(ptr %in, ptr %out) #0 {
; zext i32 -> i64
;

define void @zext_v4i32_v4i64(<4 x i32> %a, ptr %out) #0 {
define void @zext_v4i32_v4i64(<4 x i32> %a, ptr %out) {
; CHECK-LABEL: zext_v4i32_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -869,7 +870,7 @@ define void @zext_v4i32_v4i64(<4 x i32> %a, ptr %out) #0 {
ret void
}

define void @zext_v8i32_v8i64(ptr %in, ptr %out) #0 {
define void @zext_v8i32_v8i64(ptr %in, ptr %out) {
; CHECK-LABEL: zext_v8i32_v8i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -891,16 +892,25 @@ define void @zext_v8i32_v8i64(ptr %in, ptr %out) #0 {
ret void
}

define void @extend_and_mul(i32 %0, <2 x i64> %1, ptr %2) #0 {
; CHECK-LABEL: extend_and_mul:
; CHECK: // %bb.0:
; CHECK-NEXT: mov z1.s, w0
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
; CHECK-NEXT: ptrue p0.d, vl2
; CHECK-NEXT: uunpklo z1.d, z1.s
; CHECK-NEXT: mul z0.d, p0/m, z0.d, z1.d
; CHECK-NEXT: str q0, [x1]
; CHECK-NEXT: ret
define void @extend_and_mul(i32 %0, <2 x i64> %1, ptr %2) {
; SVE-LABEL: extend_and_mul:
; SVE: // %bb.0:
; SVE-NEXT: mov z1.s, w0
; SVE-NEXT: // kill: def $q0 killed $q0 def $z0
; SVE-NEXT: ptrue p0.d, vl2
; SVE-NEXT: uunpklo z1.d, z1.s
; SVE-NEXT: mul z0.d, p0/m, z0.d, z1.d
; SVE-NEXT: str q0, [x1]
; SVE-NEXT: ret
;
; SVE2-LABEL: extend_and_mul:
; SVE2: // %bb.0:
; SVE2-NEXT: mov z1.s, w0
; SVE2-NEXT: // kill: def $q0 killed $q0 def $z0
; SVE2-NEXT: uunpklo z1.d, z1.s
; SVE2-NEXT: mul z0.d, z1.d, z0.d
; SVE2-NEXT: str q0, [x1]
; SVE2-NEXT: ret
%broadcast.splatinsert2 = insertelement <2 x i32> poison, i32 %0, i64 0
%broadcast.splat3 = shufflevector <2 x i32> %broadcast.splatinsert2, <2 x i32> poison, <2 x i32> zeroinitializer
%4 = zext <2 x i32> %broadcast.splat3 to <2 x i64>
Expand All @@ -909,7 +919,7 @@ define void @extend_and_mul(i32 %0, <2 x i64> %1, ptr %2) #0 {
ret void
}

define void @extend_no_mul(i32 %0, <2 x i64> %1, ptr %2) #0 {
define void @extend_no_mul(i32 %0, <2 x i64> %1, ptr %2) {
; CHECK-LABEL: extend_no_mul:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: mov w8, w0
Expand All @@ -923,5 +933,3 @@ entry:
store <2 x i64> %3, ptr %2, align 2
ret void
}

attributes #0 = { nounwind "target-features"="+sve" }
116 changes: 57 additions & 59 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-immediates.ll
View file

Large diffs are not rendered by default.

76 changes: 37 additions & 39 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-log.ll
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s

target triple = "aarch64-unknown-linux-gnu"

;
; AND
;

define <8 x i8> @and_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
define <8 x i8> @and_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
; CHECK-LABEL: and_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -19,7 +19,7 @@ define <8 x i8> @and_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
ret <8 x i8> %res
}

define <16 x i8> @and_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
define <16 x i8> @and_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
; CHECK-LABEL: and_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -31,7 +31,7 @@ define <16 x i8> @and_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
ret <16 x i8> %res
}

define void @and_v32i8(ptr %a, ptr %b) #0 {
define void @and_v32i8(ptr %a, ptr %b) {
; CHECK-LABEL: and_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -47,7 +47,7 @@ define void @and_v32i8(ptr %a, ptr %b) #0 {
ret void
}

define <4 x i16> @and_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
define <4 x i16> @and_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
; CHECK-LABEL: and_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -59,7 +59,7 @@ define <4 x i16> @and_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
ret <4 x i16> %res
}

define <8 x i16> @and_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
define <8 x i16> @and_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
; CHECK-LABEL: and_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -71,7 +71,7 @@ define <8 x i16> @and_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
ret <8 x i16> %res
}

define void @and_v16i16(ptr %a, ptr %b) #0 {
define void @and_v16i16(ptr %a, ptr %b) {
; CHECK-LABEL: and_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -87,7 +87,7 @@ define void @and_v16i16(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i32> @and_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
define <2 x i32> @and_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
; CHECK-LABEL: and_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -99,7 +99,7 @@ define <2 x i32> @and_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
ret <2 x i32> %res
}

define <4 x i32> @and_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
define <4 x i32> @and_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
; CHECK-LABEL: and_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -111,7 +111,7 @@ define <4 x i32> @and_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
ret <4 x i32> %res
}

define void @and_v8i32(ptr %a, ptr %b) #0 {
define void @and_v8i32(ptr %a, ptr %b) {
; CHECK-LABEL: and_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -127,7 +127,7 @@ define void @and_v8i32(ptr %a, ptr %b) #0 {
ret void
}

define <1 x i64> @and_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
define <1 x i64> @and_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; CHECK-LABEL: and_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -139,7 +139,7 @@ define <1 x i64> @and_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
ret <1 x i64> %res
}

define <2 x i64> @and_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
define <2 x i64> @and_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
; CHECK-LABEL: and_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -151,7 +151,7 @@ define <2 x i64> @and_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
ret <2 x i64> %res
}

define void @and_v4i64(ptr %a, ptr %b) #0 {
define void @and_v4i64(ptr %a, ptr %b) {
; CHECK-LABEL: and_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -171,7 +171,7 @@ define void @and_v4i64(ptr %a, ptr %b) #0 {
; OR
;

define <8 x i8> @or_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
define <8 x i8> @or_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
; CHECK-LABEL: or_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -183,7 +183,7 @@ define <8 x i8> @or_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
ret <8 x i8> %res
}

define <16 x i8> @or_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
define <16 x i8> @or_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
; CHECK-LABEL: or_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -195,7 +195,7 @@ define <16 x i8> @or_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
ret <16 x i8> %res
}

define void @or_v32i8(ptr %a, ptr %b) #0 {
define void @or_v32i8(ptr %a, ptr %b) {
; CHECK-LABEL: or_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -211,7 +211,7 @@ define void @or_v32i8(ptr %a, ptr %b) #0 {
ret void
}

define <4 x i16> @or_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
define <4 x i16> @or_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
; CHECK-LABEL: or_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -223,7 +223,7 @@ define <4 x i16> @or_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
ret <4 x i16> %res
}

define <8 x i16> @or_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
define <8 x i16> @or_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
; CHECK-LABEL: or_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -235,7 +235,7 @@ define <8 x i16> @or_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
ret <8 x i16> %res
}

define void @or_v16i16(ptr %a, ptr %b) #0 {
define void @or_v16i16(ptr %a, ptr %b) {
; CHECK-LABEL: or_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -251,7 +251,7 @@ define void @or_v16i16(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i32> @or_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
define <2 x i32> @or_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
; CHECK-LABEL: or_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -263,7 +263,7 @@ define <2 x i32> @or_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
ret <2 x i32> %res
}

define <4 x i32> @or_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
define <4 x i32> @or_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
; CHECK-LABEL: or_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -275,7 +275,7 @@ define <4 x i32> @or_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
ret <4 x i32> %res
}

define void @or_v8i32(ptr %a, ptr %b) #0 {
define void @or_v8i32(ptr %a, ptr %b) {
; CHECK-LABEL: or_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -291,7 +291,7 @@ define void @or_v8i32(ptr %a, ptr %b) #0 {
ret void
}

define <1 x i64> @or_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
define <1 x i64> @or_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; CHECK-LABEL: or_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -303,7 +303,7 @@ define <1 x i64> @or_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
ret <1 x i64> %res
}

define <2 x i64> @or_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
define <2 x i64> @or_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
; CHECK-LABEL: or_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -315,7 +315,7 @@ define <2 x i64> @or_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
ret <2 x i64> %res
}

define void @or_v4i64(ptr %a, ptr %b) #0 {
define void @or_v4i64(ptr %a, ptr %b) {
; CHECK-LABEL: or_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -335,7 +335,7 @@ define void @or_v4i64(ptr %a, ptr %b) #0 {
; XOR
;

define <8 x i8> @xor_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
define <8 x i8> @xor_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
; CHECK-LABEL: xor_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -347,7 +347,7 @@ define <8 x i8> @xor_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
ret <8 x i8> %res
}

define <16 x i8> @xor_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
define <16 x i8> @xor_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
; CHECK-LABEL: xor_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -359,7 +359,7 @@ define <16 x i8> @xor_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
ret <16 x i8> %res
}

define void @xor_v32i8(ptr %a, ptr %b) #0 {
define void @xor_v32i8(ptr %a, ptr %b) {
; CHECK-LABEL: xor_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -375,7 +375,7 @@ define void @xor_v32i8(ptr %a, ptr %b) #0 {
ret void
}

define <4 x i16> @xor_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
define <4 x i16> @xor_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
; CHECK-LABEL: xor_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -387,7 +387,7 @@ define <4 x i16> @xor_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
ret <4 x i16> %res
}

define <8 x i16> @xor_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
define <8 x i16> @xor_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
; CHECK-LABEL: xor_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -399,7 +399,7 @@ define <8 x i16> @xor_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
ret <8 x i16> %res
}

define void @xor_v16i16(ptr %a, ptr %b) #0 {
define void @xor_v16i16(ptr %a, ptr %b) {
; CHECK-LABEL: xor_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -415,7 +415,7 @@ define void @xor_v16i16(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i32> @xor_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
define <2 x i32> @xor_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
; CHECK-LABEL: xor_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -427,7 +427,7 @@ define <2 x i32> @xor_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
ret <2 x i32> %res
}

define <4 x i32> @xor_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
define <4 x i32> @xor_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
; CHECK-LABEL: xor_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -439,7 +439,7 @@ define <4 x i32> @xor_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
ret <4 x i32> %res
}

define void @xor_v8i32(ptr %a, ptr %b) #0 {
define void @xor_v8i32(ptr %a, ptr %b) {
; CHECK-LABEL: xor_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -455,7 +455,7 @@ define void @xor_v8i32(ptr %a, ptr %b) #0 {
ret void
}

define <1 x i64> @xor_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
define <1 x i64> @xor_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; CHECK-LABEL: xor_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -467,7 +467,7 @@ define <1 x i64> @xor_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
ret <1 x i64> %res
}

define <2 x i64> @xor_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
define <2 x i64> @xor_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
; CHECK-LABEL: xor_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -479,7 +479,7 @@ define <2 x i64> @xor_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
ret <2 x i64> %res
}

define void @xor_v4i64(ptr %a, ptr %b) #0 {
define void @xor_v4i64(ptr %a, ptr %b) {
; CHECK-LABEL: xor_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -494,5 +494,3 @@ define void @xor_v4i64(ptr %a, ptr %b) #0 {
store <4 x i64> %res, ptr %a
ret void
}

attributes #0 = { "target-features"="+sve" }
100 changes: 49 additions & 51 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-minmax.ll
View file

Large diffs are not rendered by default.

797 changes: 522 additions & 275 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-mulh.ll
View file

Large diffs are not rendered by default.

114 changes: 56 additions & 58 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-reduce.ll
View file

Large diffs are not rendered by default.

56 changes: 27 additions & 29 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s

target triple = "aarch64-unknown-linux-gnu"

;
; SREM
;

define <4 x i8> @srem_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
define <4 x i8> @srem_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
; CHECK-LABEL: srem_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -27,7 +27,7 @@ define <4 x i8> @srem_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
ret <4 x i8> %res
}

define <8 x i8> @srem_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
define <8 x i8> @srem_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
; CHECK-LABEL: srem_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand Down Expand Up @@ -56,7 +56,7 @@ define <8 x i8> @srem_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
ret <8 x i8> %res
}

define <16 x i8> @srem_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
define <16 x i8> @srem_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
; CHECK-LABEL: srem_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
Expand Down Expand Up @@ -106,7 +106,7 @@ define <16 x i8> @srem_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
ret <16 x i8> %res
}

define void @srem_v32i8(ptr %a, ptr %b) #0 {
define void @srem_v32i8(ptr %a, ptr %b) {
; CHECK-LABEL: srem_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q2, q0, [x0]
Expand Down Expand Up @@ -192,7 +192,7 @@ define void @srem_v32i8(ptr %a, ptr %b) #0 {
ret void
}

define <4 x i16> @srem_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
define <4 x i16> @srem_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
; CHECK-LABEL: srem_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -210,7 +210,7 @@ define <4 x i16> @srem_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
ret <4 x i16> %res
}

define <8 x i16> @srem_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
define <8 x i16> @srem_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
; CHECK-LABEL: srem_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
Expand Down Expand Up @@ -238,7 +238,7 @@ define <8 x i16> @srem_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
ret <8 x i16> %res
}

define void @srem_v16i16(ptr %a, ptr %b) #0 {
define void @srem_v16i16(ptr %a, ptr %b) {
; CHECK-LABEL: srem_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q2, q0, [x0]
Expand Down Expand Up @@ -284,7 +284,7 @@ define void @srem_v16i16(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i32> @srem_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
define <2 x i32> @srem_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
; CHECK-LABEL: srem_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -299,7 +299,7 @@ define <2 x i32> @srem_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
ret <2 x i32> %res
}

define <4 x i32> @srem_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
define <4 x i32> @srem_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
; CHECK-LABEL: srem_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -314,7 +314,7 @@ define <4 x i32> @srem_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
ret <4 x i32> %res
}

define void @srem_v8i32(ptr %a, ptr %b) #0 {
define void @srem_v8i32(ptr %a, ptr %b) {
; CHECK-LABEL: srem_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -335,7 +335,7 @@ define void @srem_v8i32(ptr %a, ptr %b) #0 {
ret void
}

define <1 x i64> @srem_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
define <1 x i64> @srem_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; CHECK-LABEL: srem_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -350,7 +350,7 @@ define <1 x i64> @srem_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
ret <1 x i64> %res
}

define <2 x i64> @srem_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
define <2 x i64> @srem_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
; CHECK-LABEL: srem_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -365,7 +365,7 @@ define <2 x i64> @srem_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
ret <2 x i64> %res
}

define void @srem_v4i64(ptr %a, ptr %b) #0 {
define void @srem_v4i64(ptr %a, ptr %b) {
; CHECK-LABEL: srem_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -390,7 +390,7 @@ define void @srem_v4i64(ptr %a, ptr %b) #0 {
; UREM
;

define <4 x i8> @urem_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
define <4 x i8> @urem_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
; CHECK-LABEL: urem_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -410,7 +410,7 @@ define <4 x i8> @urem_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
ret <4 x i8> %res
}

define <8 x i8> @urem_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
define <8 x i8> @urem_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
; CHECK-LABEL: urem_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand Down Expand Up @@ -439,7 +439,7 @@ define <8 x i8> @urem_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
ret <8 x i8> %res
}

define <16 x i8> @urem_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
define <16 x i8> @urem_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
; CHECK-LABEL: urem_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
Expand Down Expand Up @@ -489,7 +489,7 @@ define <16 x i8> @urem_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
ret <16 x i8> %res
}

define void @urem_v32i8(ptr %a, ptr %b) #0 {
define void @urem_v32i8(ptr %a, ptr %b) {
; CHECK-LABEL: urem_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q2, q0, [x0]
Expand Down Expand Up @@ -575,7 +575,7 @@ define void @urem_v32i8(ptr %a, ptr %b) #0 {
ret void
}

define <4 x i16> @urem_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
define <4 x i16> @urem_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
; CHECK-LABEL: urem_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -593,7 +593,7 @@ define <4 x i16> @urem_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
ret <4 x i16> %res
}

define <8 x i16> @urem_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
define <8 x i16> @urem_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
; CHECK-LABEL: urem_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q1 killed $q1 def $z1
Expand Down Expand Up @@ -621,7 +621,7 @@ define <8 x i16> @urem_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
ret <8 x i16> %res
}

define void @urem_v16i16(ptr %a, ptr %b) #0 {
define void @urem_v16i16(ptr %a, ptr %b) {
; CHECK-LABEL: urem_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q2, q0, [x0]
Expand Down Expand Up @@ -667,7 +667,7 @@ define void @urem_v16i16(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i32> @urem_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
define <2 x i32> @urem_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
; CHECK-LABEL: urem_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -682,7 +682,7 @@ define <2 x i32> @urem_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
ret <2 x i32> %res
}

define <4 x i32> @urem_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
define <4 x i32> @urem_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
; CHECK-LABEL: urem_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -697,7 +697,7 @@ define <4 x i32> @urem_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
ret <4 x i32> %res
}

define void @urem_v8i32(ptr %a, ptr %b) #0 {
define void @urem_v8i32(ptr %a, ptr %b) {
; CHECK-LABEL: urem_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -718,7 +718,7 @@ define void @urem_v8i32(ptr %a, ptr %b) #0 {
ret void
}

define <1 x i64> @urem_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
define <1 x i64> @urem_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; CHECK-LABEL: urem_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -733,7 +733,7 @@ define <1 x i64> @urem_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
ret <1 x i64> %res
}

define <2 x i64> @urem_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
define <2 x i64> @urem_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
; CHECK-LABEL: urem_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -748,7 +748,7 @@ define <2 x i64> @urem_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
ret <2 x i64> %res
}

define void @urem_v4i64(ptr %a, ptr %b) #0 {
define void @urem_v4i64(ptr %a, ptr %b) {
; CHECK-LABEL: urem_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -768,5 +768,3 @@ define void @urem_v4i64(ptr %a, ptr %b) #0 {
store <4 x i64> %res, ptr %a
ret void
}

attributes #0 = { "target-features"="+sve" }
32 changes: 15 additions & 17 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-select.ll
View file
Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s

target triple = "aarch64-unknown-linux-gnu"

define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, i1 %mask) #0 {
define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, i1 %mask) {
; CHECK-LABEL: select_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x1
Expand All @@ -19,7 +19,7 @@ define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, i1 %mask) #0 {
ret <4 x i8> %sel
}

define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, i1 %mask) #0 {
define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, i1 %mask) {
; CHECK-LABEL: select_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x1
Expand All @@ -35,7 +35,7 @@ define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, i1 %mask) #0 {
ret <8 x i8> %sel
}

define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, i1 %mask) #0 {
define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, i1 %mask) {
; CHECK-LABEL: select_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x1
Expand All @@ -51,7 +51,7 @@ define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, i1 %mask) #0 {
ret <16 x i8> %sel
}

define void @select_v32i8(ptr %a, ptr %b, i1 %mask) #0 {
define void @select_v32i8(ptr %a, ptr %b, i1 %mask) {
; CHECK-LABEL: select_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w2, #0x1
Expand All @@ -73,7 +73,7 @@ define void @select_v32i8(ptr %a, ptr %b, i1 %mask) #0 {
ret void
}

define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, i1 %mask) #0 {
define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, i1 %mask) {
; CHECK-LABEL: select_v2i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x1
Expand All @@ -89,7 +89,7 @@ define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, i1 %mask) #0 {
ret <2 x i16> %sel
}

define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, i1 %mask) #0 {
define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, i1 %mask) {
; CHECK-LABEL: select_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x1
Expand All @@ -105,7 +105,7 @@ define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, i1 %mask) #0 {
ret <4 x i16> %sel
}

define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, i1 %mask) #0 {
define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, i1 %mask) {
; CHECK-LABEL: select_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x1
Expand All @@ -121,7 +121,7 @@ define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, i1 %mask) #0 {
ret <8 x i16> %sel
}

define void @select_v16i16(ptr %a, ptr %b, i1 %mask) #0 {
define void @select_v16i16(ptr %a, ptr %b, i1 %mask) {
; CHECK-LABEL: select_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w2, #0x1
Expand All @@ -143,7 +143,7 @@ define void @select_v16i16(ptr %a, ptr %b, i1 %mask) #0 {
ret void
}

define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, i1 %mask) #0 {
define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, i1 %mask) {
; CHECK-LABEL: select_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x1
Expand All @@ -159,7 +159,7 @@ define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, i1 %mask) #0 {
ret <2 x i32> %sel
}

define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, i1 %mask) #0 {
define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, i1 %mask) {
; CHECK-LABEL: select_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w0, #0x1
Expand All @@ -175,7 +175,7 @@ define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, i1 %mask) #0 {
ret <4 x i32> %sel
}

define void @select_v8i32(ptr %a, ptr %b, i1 %mask) #0 {
define void @select_v8i32(ptr %a, ptr %b, i1 %mask) {
; CHECK-LABEL: select_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: and w8, w2, #0x1
Expand All @@ -197,7 +197,7 @@ define void @select_v8i32(ptr %a, ptr %b, i1 %mask) #0 {
ret void
}

define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, i1 %mask) #0 {
define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, i1 %mask) {
; CHECK-LABEL: select_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
Expand All @@ -214,7 +214,7 @@ define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, i1 %mask) #0 {
ret <1 x i64> %sel
}

define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, i1 %mask) #0 {
define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, i1 %mask) {
; CHECK-LABEL: select_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
Expand All @@ -231,7 +231,7 @@ define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, i1 %mask) #0 {
ret <2 x i64> %sel
}

define void @select_v4i64(ptr %a, ptr %b, i1 %mask) #0 {
define void @select_v4i64(ptr %a, ptr %b, i1 %mask) {
; CHECK-LABEL: select_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w2 killed $w2 def $x2
Expand All @@ -253,5 +253,3 @@ define void @select_v4i64(ptr %a, ptr %b, i1 %mask) #0 {
store <4 x i64> %sel, ptr %a
ret void
}

attributes #0 = { "target-features"="+sve" }
88 changes: 43 additions & 45 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-shifts.ll
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,13 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s

target triple = "aarch64-unknown-linux-gnu"

;
; ASHR
;

define <4 x i8> @ashr_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
define <4 x i8> @ashr_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
; CHECK-LABEL: ashr_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -22,7 +22,7 @@ define <4 x i8> @ashr_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
ret <4 x i8> %res
}

define <8 x i8> @ashr_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
define <8 x i8> @ashr_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
; CHECK-LABEL: ashr_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -35,7 +35,7 @@ define <8 x i8> @ashr_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
ret <8 x i8> %res
}

define <16 x i8> @ashr_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
define <16 x i8> @ashr_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
; CHECK-LABEL: ashr_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -48,7 +48,7 @@ define <16 x i8> @ashr_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
ret <16 x i8> %res
}

define void @ashr_v32i8(ptr %a, ptr %b) #0 {
define void @ashr_v32i8(ptr %a, ptr %b) {
; CHECK-LABEL: ashr_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -65,7 +65,7 @@ define void @ashr_v32i8(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i16> @ashr_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
define <2 x i16> @ashr_v2i16(<2 x i16> %op1, <2 x i16> %op2) {
; CHECK-LABEL: ashr_v2i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -80,7 +80,7 @@ define <2 x i16> @ashr_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
ret <2 x i16> %res
}

define <4 x i16> @ashr_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
define <4 x i16> @ashr_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
; CHECK-LABEL: ashr_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -93,7 +93,7 @@ define <4 x i16> @ashr_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
ret <4 x i16> %res
}

define <8 x i16> @ashr_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
define <8 x i16> @ashr_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
; CHECK-LABEL: ashr_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -106,7 +106,7 @@ define <8 x i16> @ashr_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
ret <8 x i16> %res
}

define void @ashr_v16i16(ptr %a, ptr %b) #0 {
define void @ashr_v16i16(ptr %a, ptr %b) {
; CHECK-LABEL: ashr_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -123,7 +123,7 @@ define void @ashr_v16i16(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i32> @ashr_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
define <2 x i32> @ashr_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
; CHECK-LABEL: ashr_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -136,7 +136,7 @@ define <2 x i32> @ashr_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
ret <2 x i32> %res
}

define <4 x i32> @ashr_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
define <4 x i32> @ashr_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
; CHECK-LABEL: ashr_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -149,7 +149,7 @@ define <4 x i32> @ashr_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
ret <4 x i32> %res
}

define void @ashr_v8i32(ptr %a, ptr %b) #0 {
define void @ashr_v8i32(ptr %a, ptr %b) {
; CHECK-LABEL: ashr_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -166,7 +166,7 @@ define void @ashr_v8i32(ptr %a, ptr %b) #0 {
ret void
}

define <1 x i64> @ashr_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
define <1 x i64> @ashr_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; CHECK-LABEL: ashr_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -179,7 +179,7 @@ define <1 x i64> @ashr_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
ret <1 x i64> %res
}

define <2 x i64> @ashr_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
define <2 x i64> @ashr_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
; CHECK-LABEL: ashr_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -192,7 +192,7 @@ define <2 x i64> @ashr_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
ret <2 x i64> %res
}

define void @ashr_v4i64(ptr %a, ptr %b) #0 {
define void @ashr_v4i64(ptr %a, ptr %b) {
; CHECK-LABEL: ashr_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -213,7 +213,7 @@ define void @ashr_v4i64(ptr %a, ptr %b) #0 {
; LSHR
;

define <4 x i8> @lshr_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
define <4 x i8> @lshr_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
; CHECK-LABEL: lshr_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -228,7 +228,7 @@ define <4 x i8> @lshr_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
ret <4 x i8> %res
}

define <8 x i8> @lshr_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
define <8 x i8> @lshr_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
; CHECK-LABEL: lshr_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -241,7 +241,7 @@ define <8 x i8> @lshr_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
ret <8 x i8> %res
}

define <16 x i8> @lshr_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
define <16 x i8> @lshr_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
; CHECK-LABEL: lshr_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -254,7 +254,7 @@ define <16 x i8> @lshr_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
ret <16 x i8> %res
}

define void @lshr_v32i8(ptr %a, ptr %b) #0 {
define void @lshr_v32i8(ptr %a, ptr %b) {
; CHECK-LABEL: lshr_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -271,7 +271,7 @@ define void @lshr_v32i8(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i16> @lshr_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
define <2 x i16> @lshr_v2i16(<2 x i16> %op1, <2 x i16> %op2) {
; CHECK-LABEL: lshr_v2i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -286,7 +286,7 @@ define <2 x i16> @lshr_v2i16(<2 x i16> %op1, <2 x i16> %op2) #0 {
ret <2 x i16> %res
}

define <4 x i16> @lshr_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
define <4 x i16> @lshr_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
; CHECK-LABEL: lshr_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -299,7 +299,7 @@ define <4 x i16> @lshr_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
ret <4 x i16> %res
}

define <8 x i16> @lshr_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
define <8 x i16> @lshr_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
; CHECK-LABEL: lshr_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -312,7 +312,7 @@ define <8 x i16> @lshr_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
ret <8 x i16> %res
}

define void @lshr_v16i16(ptr %a, ptr %b) #0 {
define void @lshr_v16i16(ptr %a, ptr %b) {
; CHECK-LABEL: lshr_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -329,7 +329,7 @@ define void @lshr_v16i16(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i32> @lshr_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
define <2 x i32> @lshr_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
; CHECK-LABEL: lshr_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -342,7 +342,7 @@ define <2 x i32> @lshr_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
ret <2 x i32> %res
}

define <4 x i32> @lshr_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
define <4 x i32> @lshr_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
; CHECK-LABEL: lshr_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -355,7 +355,7 @@ define <4 x i32> @lshr_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
ret <4 x i32> %res
}

define void @lshr_v8i32(ptr %a, ptr %b) #0 {
define void @lshr_v8i32(ptr %a, ptr %b) {
; CHECK-LABEL: lshr_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -372,7 +372,7 @@ define void @lshr_v8i32(ptr %a, ptr %b) #0 {
ret void
}

define <1 x i64> @lshr_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
define <1 x i64> @lshr_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; CHECK-LABEL: lshr_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -385,7 +385,7 @@ define <1 x i64> @lshr_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
ret <1 x i64> %res
}

define <2 x i64> @lshr_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
define <2 x i64> @lshr_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
; CHECK-LABEL: lshr_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -398,7 +398,7 @@ define <2 x i64> @lshr_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
ret <2 x i64> %res
}

define void @lshr_v4i64(ptr %a, ptr %b) #0 {
define void @lshr_v4i64(ptr %a, ptr %b) {
; CHECK-LABEL: lshr_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -419,7 +419,7 @@ define void @lshr_v4i64(ptr %a, ptr %b) #0 {
; SHL
;

define <2 x i8> @shl_v2i8(<2 x i8> %op1, <2 x i8> %op2) #0 {
define <2 x i8> @shl_v2i8(<2 x i8> %op1, <2 x i8> %op2) {
; CHECK-LABEL: shl_v2i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -433,7 +433,7 @@ define <2 x i8> @shl_v2i8(<2 x i8> %op1, <2 x i8> %op2) #0 {
ret <2 x i8> %res
}

define <4 x i8> @shl_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
define <4 x i8> @shl_v4i8(<4 x i8> %op1, <4 x i8> %op2) {
; CHECK-LABEL: shl_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1
Expand All @@ -447,7 +447,7 @@ define <4 x i8> @shl_v4i8(<4 x i8> %op1, <4 x i8> %op2) #0 {
ret <4 x i8> %res
}

define <8 x i8> @shl_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
define <8 x i8> @shl_v8i8(<8 x i8> %op1, <8 x i8> %op2) {
; CHECK-LABEL: shl_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -460,7 +460,7 @@ define <8 x i8> @shl_v8i8(<8 x i8> %op1, <8 x i8> %op2) #0 {
ret <8 x i8> %res
}

define <16 x i8> @shl_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
define <16 x i8> @shl_v16i8(<16 x i8> %op1, <16 x i8> %op2) {
; CHECK-LABEL: shl_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -473,7 +473,7 @@ define <16 x i8> @shl_v16i8(<16 x i8> %op1, <16 x i8> %op2) #0 {
ret <16 x i8> %res
}

define void @shl_v32i8(ptr %a, ptr %b) #0 {
define void @shl_v32i8(ptr %a, ptr %b) {
; CHECK-LABEL: shl_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -490,7 +490,7 @@ define void @shl_v32i8(ptr %a, ptr %b) #0 {
ret void
}

define <4 x i16> @shl_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
define <4 x i16> @shl_v4i16(<4 x i16> %op1, <4 x i16> %op2) {
; CHECK-LABEL: shl_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -503,7 +503,7 @@ define <4 x i16> @shl_v4i16(<4 x i16> %op1, <4 x i16> %op2) #0 {
ret <4 x i16> %res
}

define <8 x i16> @shl_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
define <8 x i16> @shl_v8i16(<8 x i16> %op1, <8 x i16> %op2) {
; CHECK-LABEL: shl_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -516,7 +516,7 @@ define <8 x i16> @shl_v8i16(<8 x i16> %op1, <8 x i16> %op2) #0 {
ret <8 x i16> %res
}

define void @shl_v16i16(ptr %a, ptr %b) #0 {
define void @shl_v16i16(ptr %a, ptr %b) {
; CHECK-LABEL: shl_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -533,7 +533,7 @@ define void @shl_v16i16(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i32> @shl_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
define <2 x i32> @shl_v2i32(<2 x i32> %op1, <2 x i32> %op2) {
; CHECK-LABEL: shl_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -546,7 +546,7 @@ define <2 x i32> @shl_v2i32(<2 x i32> %op1, <2 x i32> %op2) #0 {
ret <2 x i32> %res
}

define <4 x i32> @shl_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
define <4 x i32> @shl_v4i32(<4 x i32> %op1, <4 x i32> %op2) {
; CHECK-LABEL: shl_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -559,7 +559,7 @@ define <4 x i32> @shl_v4i32(<4 x i32> %op1, <4 x i32> %op2) #0 {
ret <4 x i32> %res
}

define void @shl_v8i32(ptr %a, ptr %b) #0 {
define void @shl_v8i32(ptr %a, ptr %b) {
; CHECK-LABEL: shl_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -576,7 +576,7 @@ define void @shl_v8i32(ptr %a, ptr %b) #0 {
ret void
}

define <1 x i64> @shl_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
define <1 x i64> @shl_v1i64(<1 x i64> %op1, <1 x i64> %op2) {
; CHECK-LABEL: shl_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -589,7 +589,7 @@ define <1 x i64> @shl_v1i64(<1 x i64> %op1, <1 x i64> %op2) #0 {
ret <1 x i64> %res
}

define <2 x i64> @shl_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
define <2 x i64> @shl_v2i64(<2 x i64> %op1, <2 x i64> %op2) {
; CHECK-LABEL: shl_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -602,7 +602,7 @@ define <2 x i64> @shl_v2i64(<2 x i64> %op1, <2 x i64> %op2) #0 {
ret <2 x i64> %res
}

define void @shl_v4i64(ptr %a, ptr %b) #0 {
define void @shl_v4i64(ptr %a, ptr %b) {
; CHECK-LABEL: shl_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -618,5 +618,3 @@ define void @shl_v4i64(ptr %a, ptr %b) #0 {
store <4 x i64> %res, ptr %a
ret void
}

attributes #0 = { "target-features"="+sve" }
118 changes: 58 additions & 60 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
View file

Large diffs are not rendered by default.

32 changes: 15 additions & 17 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-vselect.ll
View file
Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s

target triple = "aarch64-unknown-linux-gnu"

define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, <4 x i1> %mask) #0 {
define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, <4 x i1> %mask) {
; CHECK-LABEL: select_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
Expand All @@ -21,7 +21,7 @@ define <4 x i8> @select_v4i8(<4 x i8> %op1, <4 x i8> %op2, <4 x i1> %mask) #0 {
ret <4 x i8> %sel
}

define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask) #0 {
define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask) {
; CHECK-LABEL: select_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
Expand All @@ -39,7 +39,7 @@ define <8 x i8> @select_v8i8(<8 x i8> %op1, <8 x i8> %op2, <8 x i1> %mask) #0 {
ret <8 x i8> %sel
}

define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask) #0 {
define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask) {
; CHECK-LABEL: select_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q2 killed $q2 def $z2
Expand All @@ -57,7 +57,7 @@ define <16 x i8> @select_v16i8(<16 x i8> %op1, <16 x i8> %op2, <16 x i1> %mask)
ret <16 x i8> %sel
}

define void @select_v32i8(ptr %a, ptr %b) #0 {
define void @select_v32i8(ptr %a, ptr %b) {
; CHECK-LABEL: select_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
Expand All @@ -77,7 +77,7 @@ define void @select_v32i8(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, <2 x i1> %mask) #0 {
define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, <2 x i1> %mask) {
; CHECK-LABEL: select_v2i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
Expand All @@ -95,7 +95,7 @@ define <2 x i16> @select_v2i16(<2 x i16> %op1, <2 x i16> %op2, <2 x i1> %mask) #
ret <2 x i16> %sel
}

define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, <4 x i1> %mask) #0 {
define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, <4 x i1> %mask) {
; CHECK-LABEL: select_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
Expand All @@ -113,7 +113,7 @@ define <4 x i16> @select_v4i16(<4 x i16> %op1, <4 x i16> %op2, <4 x i1> %mask) #
ret <4 x i16> %sel
}

define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask) #0 {
define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask) {
; CHECK-LABEL: select_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
Expand All @@ -132,7 +132,7 @@ define <8 x i16> @select_v8i16(<8 x i16> %op1, <8 x i16> %op2, <8 x i1> %mask) #
ret <8 x i16> %sel
}

define void @select_v16i16(ptr %a, ptr %b) #0 {
define void @select_v16i16(ptr %a, ptr %b) {
; CHECK-LABEL: select_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
Expand All @@ -152,7 +152,7 @@ define void @select_v16i16(ptr %a, ptr %b) #0 {
ret void
}

define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, <2 x i1> %mask) #0 {
define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, <2 x i1> %mask) {
; CHECK-LABEL: select_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
Expand All @@ -170,7 +170,7 @@ define <2 x i32> @select_v2i32(<2 x i32> %op1, <2 x i32> %op2, <2 x i1> %mask) #
ret <2 x i32> %sel
}

define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) #0 {
define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) {
; CHECK-LABEL: select_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
Expand All @@ -189,7 +189,7 @@ define <4 x i32> @select_v4i32(<4 x i32> %op1, <4 x i32> %op2, <4 x i1> %mask) #
ret <4 x i32> %sel
}

define void @select_v8i32(ptr %a, ptr %b) #0 {
define void @select_v8i32(ptr %a, ptr %b) {
; CHECK-LABEL: select_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
Expand All @@ -209,7 +209,7 @@ define void @select_v8i32(ptr %a, ptr %b) #0 {
ret void
}

define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, <1 x i1> %mask) #0 {
define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, <1 x i1> %mask) {
; CHECK-LABEL: select_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0
Expand All @@ -226,7 +226,7 @@ define <1 x i64> @select_v1i64(<1 x i64> %op1, <1 x i64> %op2, <1 x i1> %mask) #
ret <1 x i64> %sel
}

define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) #0 {
define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) {
; CHECK-LABEL: select_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2
Expand All @@ -245,7 +245,7 @@ define <2 x i64> @select_v2i64(<2 x i64> %op1, <2 x i64> %op2, <2 x i1> %mask) #
ret <2 x i64> %sel
}

define void @select_v4i64(ptr %a, ptr %b) #0 {
define void @select_v4i64(ptr %a, ptr %b) {
; CHECK-LABEL: select_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
Expand All @@ -264,5 +264,3 @@ define void @select_v4i64(ptr %a, ptr %b) #0 {
store <4 x i64> %sel, ptr %a
ret void
}

attributes #0 = { "target-features"="+sve" uwtable }
12 changes: 5 additions & 7 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll
View file
Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s

target triple = "aarch64-unknown-linux-gnu"

declare void @def(ptr)

define void @alloc_v4i8(ptr %st_ptr) #0 {
define void @alloc_v4i8(ptr %st_ptr) nounwind {
; CHECK-LABEL: alloc_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
Expand Down Expand Up @@ -36,7 +36,7 @@ define void @alloc_v4i8(ptr %st_ptr) #0 {
ret void
}

define void @alloc_v6i8(ptr %st_ptr) #0 {
define void @alloc_v6i8(ptr %st_ptr) nounwind {
; CHECK-LABEL: alloc_v6i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #48
Expand Down Expand Up @@ -78,7 +78,7 @@ define void @alloc_v6i8(ptr %st_ptr) #0 {
ret void
}

define void @alloc_v32i8(ptr %st_ptr) #0 {
define void @alloc_v32i8(ptr %st_ptr) nounwind {
; CHECK-LABEL: alloc_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #64
Expand Down Expand Up @@ -127,7 +127,7 @@ define void @alloc_v32i8(ptr %st_ptr) #0 {
}


define void @alloc_v8f64(ptr %st_ptr) #0 {
define void @alloc_v8f64(ptr %st_ptr) nounwind {
; CHECK-LABEL: alloc_v8f64:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #96
Expand All @@ -153,5 +153,3 @@ define void @alloc_v8f64(ptr %st_ptr) #0 {
store <4 x double> %strided.vec, ptr %st_ptr
ret void
}

attributes #0 = { "target-features"="+sve" nounwind}
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-limit-duplane.ll
View file
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s

target triple = "aarch64-unknown-linux-gnu"

Expand Down
52 changes: 25 additions & 27 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll
View file
Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s

target triple = "aarch64-unknown-linux-gnu"

define <4 x i8> @load_v4i8(ptr %a) #0 {
define <4 x i8> @load_v4i8(ptr %a) {
; CHECK-LABEL: load_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ptrue p0.h, vl4
Expand All @@ -14,7 +14,7 @@ define <4 x i8> @load_v4i8(ptr %a) #0 {
ret <4 x i8> %load
}

define <8 x i8> @load_v8i8(ptr %a) #0 {
define <8 x i8> @load_v8i8(ptr %a) {
; CHECK-LABEL: load_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
Expand All @@ -23,7 +23,7 @@ define <8 x i8> @load_v8i8(ptr %a) #0 {
ret <8 x i8> %load
}

define <16 x i8> @load_v16i8(ptr %a) #0 {
define <16 x i8> @load_v16i8(ptr %a) {
; CHECK-LABEL: load_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
Expand All @@ -32,7 +32,7 @@ define <16 x i8> @load_v16i8(ptr %a) #0 {
ret <16 x i8> %load
}

define <32 x i8> @load_v32i8(ptr %a) #0 {
define <32 x i8> @load_v32i8(ptr %a) {
; CHECK-LABEL: load_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -41,7 +41,7 @@ define <32 x i8> @load_v32i8(ptr %a) #0 {
ret <32 x i8> %load
}

define <2 x i16> @load_v2i16(ptr %a) #0 {
define <2 x i16> @load_v2i16(ptr %a) {
; CHECK-LABEL: load_v2i16:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #16
Expand All @@ -57,7 +57,7 @@ define <2 x i16> @load_v2i16(ptr %a) #0 {
ret <2 x i16> %load
}

define <2 x half> @load_v2f16(ptr %a) #0 {
define <2 x half> @load_v2f16(ptr %a) {
; CHECK-LABEL: load_v2f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr s0, [x0]
Expand All @@ -66,7 +66,7 @@ define <2 x half> @load_v2f16(ptr %a) #0 {
ret <2 x half> %load
}

define <4 x i16> @load_v4i16(ptr %a) #0 {
define <4 x i16> @load_v4i16(ptr %a) {
; CHECK-LABEL: load_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
Expand All @@ -75,7 +75,7 @@ define <4 x i16> @load_v4i16(ptr %a) #0 {
ret <4 x i16> %load
}

define <4 x half> @load_v4f16(ptr %a) #0 {
define <4 x half> @load_v4f16(ptr %a) {
; CHECK-LABEL: load_v4f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
Expand All @@ -84,7 +84,7 @@ define <4 x half> @load_v4f16(ptr %a) #0 {
ret <4 x half> %load
}

define <8 x i16> @load_v8i16(ptr %a) #0 {
define <8 x i16> @load_v8i16(ptr %a) {
; CHECK-LABEL: load_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
Expand All @@ -93,7 +93,7 @@ define <8 x i16> @load_v8i16(ptr %a) #0 {
ret <8 x i16> %load
}

define <8 x half> @load_v8f16(ptr %a) #0 {
define <8 x half> @load_v8f16(ptr %a) {
; CHECK-LABEL: load_v8f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
Expand All @@ -102,7 +102,7 @@ define <8 x half> @load_v8f16(ptr %a) #0 {
ret <8 x half> %load
}

define <16 x i16> @load_v16i16(ptr %a) #0 {
define <16 x i16> @load_v16i16(ptr %a) {
; CHECK-LABEL: load_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -111,7 +111,7 @@ define <16 x i16> @load_v16i16(ptr %a) #0 {
ret <16 x i16> %load
}

define <16 x half> @load_v16f16(ptr %a) #0 {
define <16 x half> @load_v16f16(ptr %a) {
; CHECK-LABEL: load_v16f16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -120,7 +120,7 @@ define <16 x half> @load_v16f16(ptr %a) #0 {
ret <16 x half> %load
}

define <2 x i32> @load_v2i32(ptr %a) #0 {
define <2 x i32> @load_v2i32(ptr %a) {
; CHECK-LABEL: load_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
Expand All @@ -129,7 +129,7 @@ define <2 x i32> @load_v2i32(ptr %a) #0 {
ret <2 x i32> %load
}

define <2 x float> @load_v2f32(ptr %a) #0 {
define <2 x float> @load_v2f32(ptr %a) {
; CHECK-LABEL: load_v2f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
Expand All @@ -138,7 +138,7 @@ define <2 x float> @load_v2f32(ptr %a) #0 {
ret <2 x float> %load
}

define <4 x i32> @load_v4i32(ptr %a) #0 {
define <4 x i32> @load_v4i32(ptr %a) {
; CHECK-LABEL: load_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
Expand All @@ -147,7 +147,7 @@ define <4 x i32> @load_v4i32(ptr %a) #0 {
ret <4 x i32> %load
}

define <4 x float> @load_v4f32(ptr %a) #0 {
define <4 x float> @load_v4f32(ptr %a) {
; CHECK-LABEL: load_v4f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
Expand All @@ -156,7 +156,7 @@ define <4 x float> @load_v4f32(ptr %a) #0 {
ret <4 x float> %load
}

define <8 x i32> @load_v8i32(ptr %a) #0 {
define <8 x i32> @load_v8i32(ptr %a) {
; CHECK-LABEL: load_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -165,7 +165,7 @@ define <8 x i32> @load_v8i32(ptr %a) #0 {
ret <8 x i32> %load
}

define <8 x float> @load_v8f32(ptr %a) #0 {
define <8 x float> @load_v8f32(ptr %a) {
; CHECK-LABEL: load_v8f32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -174,7 +174,7 @@ define <8 x float> @load_v8f32(ptr %a) #0 {
ret <8 x float> %load
}

define <1 x i64> @load_v1i64(ptr %a) #0 {
define <1 x i64> @load_v1i64(ptr %a) {
; CHECK-LABEL: load_v1i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
Expand All @@ -183,7 +183,7 @@ define <1 x i64> @load_v1i64(ptr %a) #0 {
ret <1 x i64> %load
}

define <1 x double> @load_v1f64(ptr %a) #0 {
define <1 x double> @load_v1f64(ptr %a) {
; CHECK-LABEL: load_v1f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0]
Expand All @@ -192,7 +192,7 @@ define <1 x double> @load_v1f64(ptr %a) #0 {
ret <1 x double> %load
}

define <2 x i64> @load_v2i64(ptr %a) #0 {
define <2 x i64> @load_v2i64(ptr %a) {
; CHECK-LABEL: load_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
Expand All @@ -201,7 +201,7 @@ define <2 x i64> @load_v2i64(ptr %a) #0 {
ret <2 x i64> %load
}

define <2 x double> @load_v2f64(ptr %a) #0 {
define <2 x double> @load_v2f64(ptr %a) {
; CHECK-LABEL: load_v2f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
Expand All @@ -210,7 +210,7 @@ define <2 x double> @load_v2f64(ptr %a) #0 {
ret <2 x double> %load
}

define <4 x i64> @load_v4i64(ptr %a) #0 {
define <4 x i64> @load_v4i64(ptr %a) {
; CHECK-LABEL: load_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -219,7 +219,7 @@ define <4 x i64> @load_v4i64(ptr %a) #0 {
ret <4 x i64> %load
}

define <4 x double> @load_v4f64(ptr %a) #0 {
define <4 x double> @load_v4f64(ptr %a) {
; CHECK-LABEL: load_v4f64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q0, q1, [x0]
Expand All @@ -228,5 +228,3 @@ define <4 x double> @load_v4f64(ptr %a) #0 {
ret <4 x double> %load
}


attributes #0 = { "target-features"="+sve" }
83 changes: 41 additions & 42 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-log-reduce.ll
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s


target triple = "aarch64-unknown-linux-gnu"

;
; ANDV
;

define i8 @andv_v4i8(<4 x i8> %a) #0 {
define i8 @andv_v4i8(<4 x i8> %a) {
; CHECK-LABEL: andv_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -19,7 +20,7 @@ define i8 @andv_v4i8(<4 x i8> %a) #0 {
ret i8 %res
}

define i8 @andv_v8i8(<8 x i8> %a) #0 {
define i8 @andv_v8i8(<8 x i8> %a) {
; CHECK-LABEL: andv_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -31,7 +32,7 @@ define i8 @andv_v8i8(<8 x i8> %a) #0 {
ret i8 %res
}

define i8 @andv_v16i8(<16 x i8> %a) #0 {
define i8 @andv_v16i8(<16 x i8> %a) {
; CHECK-LABEL: andv_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -43,7 +44,7 @@ define i8 @andv_v16i8(<16 x i8> %a) #0 {
ret i8 %res
}

define i8 @andv_v32i8(ptr %a) #0 {
define i8 @andv_v32i8(ptr %a) {
; CHECK-LABEL: andv_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
Expand All @@ -57,7 +58,7 @@ define i8 @andv_v32i8(ptr %a) #0 {
ret i8 %res
}

define i16 @andv_v2i16(<2 x i16> %a) #0 {
define i16 @andv_v2i16(<2 x i16> %a) {
; CHECK-LABEL: andv_v2i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -69,7 +70,7 @@ define i16 @andv_v2i16(<2 x i16> %a) #0 {
ret i16 %res
}

define i16 @andv_v4i16(<4 x i16> %a) #0 {
define i16 @andv_v4i16(<4 x i16> %a) {
; CHECK-LABEL: andv_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -81,7 +82,7 @@ define i16 @andv_v4i16(<4 x i16> %a) #0 {
ret i16 %res
}

define i16 @andv_v8i16(<8 x i16> %a) #0 {
define i16 @andv_v8i16(<8 x i16> %a) {
; CHECK-LABEL: andv_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -93,7 +94,7 @@ define i16 @andv_v8i16(<8 x i16> %a) #0 {
ret i16 %res
}

define i16 @andv_v16i16(ptr %a) #0 {
define i16 @andv_v16i16(ptr %a) {
; CHECK-LABEL: andv_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
Expand All @@ -107,7 +108,7 @@ define i16 @andv_v16i16(ptr %a) #0 {
ret i16 %res
}

define i32 @andv_v2i32(<2 x i32> %a) #0 {
define i32 @andv_v2i32(<2 x i32> %a) {
; CHECK-LABEL: andv_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -119,7 +120,7 @@ define i32 @andv_v2i32(<2 x i32> %a) #0 {
ret i32 %res
}

define i32 @andv_v4i32(<4 x i32> %a) #0 {
define i32 @andv_v4i32(<4 x i32> %a) {
; CHECK-LABEL: andv_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -131,7 +132,7 @@ define i32 @andv_v4i32(<4 x i32> %a) #0 {
ret i32 %res
}

define i32 @andv_v8i32(ptr %a) #0 {
define i32 @andv_v8i32(ptr %a) {
; CHECK-LABEL: andv_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
Expand All @@ -145,7 +146,7 @@ define i32 @andv_v8i32(ptr %a) #0 {
ret i32 %res
}

define i64 @andv_v2i64(<2 x i64> %a) #0 {
define i64 @andv_v2i64(<2 x i64> %a) {
; CHECK-LABEL: andv_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -157,7 +158,7 @@ define i64 @andv_v2i64(<2 x i64> %a) #0 {
ret i64 %res
}

define i64 @andv_v4i64(ptr %a) #0 {
define i64 @andv_v4i64(ptr %a) {
; CHECK-LABEL: andv_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
Expand All @@ -175,7 +176,7 @@ define i64 @andv_v4i64(ptr %a) #0 {
; EORV
;

define i8 @eorv_v4i8(<4 x i8> %a) #0 {
define i8 @eorv_v4i8(<4 x i8> %a) {
; CHECK-LABEL: eorv_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -187,7 +188,7 @@ define i8 @eorv_v4i8(<4 x i8> %a) #0 {
ret i8 %res
}

define i8 @eorv_v8i8(<8 x i8> %a) #0 {
define i8 @eorv_v8i8(<8 x i8> %a) {
; CHECK-LABEL: eorv_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -199,7 +200,7 @@ define i8 @eorv_v8i8(<8 x i8> %a) #0 {
ret i8 %res
}

define i8 @eorv_v16i8(<16 x i8> %a) #0 {
define i8 @eorv_v16i8(<16 x i8> %a) {
; CHECK-LABEL: eorv_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -211,7 +212,7 @@ define i8 @eorv_v16i8(<16 x i8> %a) #0 {
ret i8 %res
}

define i8 @eorv_v32i8(ptr %a) #0 {
define i8 @eorv_v32i8(ptr %a) {
; CHECK-LABEL: eorv_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
Expand All @@ -225,7 +226,7 @@ define i8 @eorv_v32i8(ptr %a) #0 {
ret i8 %res
}

define i16 @eorv_v2i16(<2 x i16> %a) #0 {
define i16 @eorv_v2i16(<2 x i16> %a) {
; CHECK-LABEL: eorv_v2i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -237,7 +238,7 @@ define i16 @eorv_v2i16(<2 x i16> %a) #0 {
ret i16 %res
}

define i16 @eorv_v4i16(<4 x i16> %a) #0 {
define i16 @eorv_v4i16(<4 x i16> %a) {
; CHECK-LABEL: eorv_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -249,7 +250,7 @@ define i16 @eorv_v4i16(<4 x i16> %a) #0 {
ret i16 %res
}

define i16 @eorv_v8i16(<8 x i16> %a) #0 {
define i16 @eorv_v8i16(<8 x i16> %a) {
; CHECK-LABEL: eorv_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -261,7 +262,7 @@ define i16 @eorv_v8i16(<8 x i16> %a) #0 {
ret i16 %res
}

define i16 @eorv_v16i16(ptr %a) #0 {
define i16 @eorv_v16i16(ptr %a) {
; CHECK-LABEL: eorv_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
Expand All @@ -275,7 +276,7 @@ define i16 @eorv_v16i16(ptr %a) #0 {
ret i16 %res
}

define i32 @eorv_v2i32(<2 x i32> %a) #0 {
define i32 @eorv_v2i32(<2 x i32> %a) {
; CHECK-LABEL: eorv_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -287,7 +288,7 @@ define i32 @eorv_v2i32(<2 x i32> %a) #0 {
ret i32 %res
}

define i32 @eorv_v4i32(<4 x i32> %a) #0 {
define i32 @eorv_v4i32(<4 x i32> %a) {
; CHECK-LABEL: eorv_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -299,7 +300,7 @@ define i32 @eorv_v4i32(<4 x i32> %a) #0 {
ret i32 %res
}

define i32 @eorv_v8i32(ptr %a) #0 {
define i32 @eorv_v8i32(ptr %a) {
; CHECK-LABEL: eorv_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
Expand All @@ -313,7 +314,7 @@ define i32 @eorv_v8i32(ptr %a) #0 {
ret i32 %res
}

define i64 @eorv_v2i64(<2 x i64> %a) #0 {
define i64 @eorv_v2i64(<2 x i64> %a) {
; CHECK-LABEL: eorv_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -325,7 +326,7 @@ define i64 @eorv_v2i64(<2 x i64> %a) #0 {
ret i64 %res
}

define i64 @eorv_v4i64(ptr %a) #0 {
define i64 @eorv_v4i64(ptr %a) {
; CHECK-LABEL: eorv_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
Expand All @@ -343,7 +344,7 @@ define i64 @eorv_v4i64(ptr %a) #0 {
; ORV
;

define i8 @orv_v4i8(<4 x i8> %a) #0 {
define i8 @orv_v4i8(<4 x i8> %a) {
; CHECK-LABEL: orv_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -355,7 +356,7 @@ define i8 @orv_v4i8(<4 x i8> %a) #0 {
ret i8 %res
}

define i8 @orv_v8i8(<8 x i8> %a) #0 {
define i8 @orv_v8i8(<8 x i8> %a) {
; CHECK-LABEL: orv_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -367,7 +368,7 @@ define i8 @orv_v8i8(<8 x i8> %a) #0 {
ret i8 %res
}

define i8 @orv_v16i8(<16 x i8> %a) #0 {
define i8 @orv_v16i8(<16 x i8> %a) {
; CHECK-LABEL: orv_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -379,7 +380,7 @@ define i8 @orv_v16i8(<16 x i8> %a) #0 {
ret i8 %res
}

define i8 @orv_v32i8(ptr %a) #0 {
define i8 @orv_v32i8(ptr %a) {
; CHECK-LABEL: orv_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
Expand All @@ -393,7 +394,7 @@ define i8 @orv_v32i8(ptr %a) #0 {
ret i8 %res
}

define i16 @orv_v2i16(<2 x i16> %a) #0 {
define i16 @orv_v2i16(<2 x i16> %a) {
; CHECK-LABEL: orv_v2i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -405,7 +406,7 @@ define i16 @orv_v2i16(<2 x i16> %a) #0 {
ret i16 %res
}

define i16 @orv_v4i16(<4 x i16> %a) #0 {
define i16 @orv_v4i16(<4 x i16> %a) {
; CHECK-LABEL: orv_v4i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -417,7 +418,7 @@ define i16 @orv_v4i16(<4 x i16> %a) #0 {
ret i16 %res
}

define i16 @orv_v8i16(<8 x i16> %a) #0 {
define i16 @orv_v8i16(<8 x i16> %a) {
; CHECK-LABEL: orv_v8i16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -429,7 +430,7 @@ define i16 @orv_v8i16(<8 x i16> %a) #0 {
ret i16 %res
}

define i16 @orv_v16i16(ptr %a) #0 {
define i16 @orv_v16i16(ptr %a) {
; CHECK-LABEL: orv_v16i16:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
Expand All @@ -443,7 +444,7 @@ define i16 @orv_v16i16(ptr %a) #0 {
ret i16 %res
}

define i32 @orv_v2i32(<2 x i32> %a) #0 {
define i32 @orv_v2i32(<2 x i32> %a) {
; CHECK-LABEL: orv_v2i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -455,7 +456,7 @@ define i32 @orv_v2i32(<2 x i32> %a) #0 {
ret i32 %res
}

define i32 @orv_v4i32(<4 x i32> %a) #0 {
define i32 @orv_v4i32(<4 x i32> %a) {
; CHECK-LABEL: orv_v4i32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -467,7 +468,7 @@ define i32 @orv_v4i32(<4 x i32> %a) #0 {
ret i32 %res
}

define i32 @orv_v8i32(ptr %a) #0 {
define i32 @orv_v8i32(ptr %a) {
; CHECK-LABEL: orv_v8i32:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
Expand All @@ -481,7 +482,7 @@ define i32 @orv_v8i32(ptr %a) #0 {
ret i32 %res
}

define i64 @orv_v2i64(<2 x i64> %a) #0 {
define i64 @orv_v2i64(<2 x i64> %a) {
; CHECK-LABEL: orv_v2i64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -493,7 +494,7 @@ define i64 @orv_v2i64(<2 x i64> %a) #0 {
ret i64 %res
}

define i64 @orv_v4i64(ptr %a) #0 {
define i64 @orv_v4i64(ptr %a) {
; CHECK-LABEL: orv_v4i64:
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
Expand All @@ -507,8 +508,6 @@ define i64 @orv_v4i64(ptr %a) #0 {
ret i64 %res
}

attributes #0 = { "target-features"="+sve" }

declare i8 @llvm.vector.reduce.and.v4i8(<4 x i8>)
declare i8 @llvm.vector.reduce.and.v8i8(<8 x i8>)
declare i8 @llvm.vector.reduce.and.v16i8(<16 x i8>)
Expand Down
31 changes: 15 additions & 16 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-masked-load.ll
View file
Original file line number Diff line number Diff line change
@@ -1,13 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -force-streaming-compatible-sve < %s | FileCheck %s
; RUN: llc -mattr=+sve -force-streaming-compatible-sve < %s | FileCheck %s


target triple = "aarch64-unknown-linux-gnu"

;
; Masked Load
;

define <4 x i8> @masked_load_v4i8(ptr %src, <4 x i1> %mask) #0 {
define <4 x i8> @masked_load_v4i8(ptr %src, <4 x i1> %mask) {
; CHECK-LABEL: masked_load_v4i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -22,7 +23,7 @@ define <4 x i8> @masked_load_v4i8(ptr %src, <4 x i1> %mask) #0 {
ret <4 x i8> %load
}

define <8 x i8> @masked_load_v8i8(ptr %src, <8 x i1> %mask) #0 {
define <8 x i8> @masked_load_v8i8(ptr %src, <8 x i1> %mask) {
; CHECK-LABEL: masked_load_v8i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -37,7 +38,7 @@ define <8 x i8> @masked_load_v8i8(ptr %src, <8 x i1> %mask) #0 {
ret <8 x i8> %load
}

define <16 x i8> @masked_load_v16i8(ptr %src, <16 x i1> %mask) #0 {
define <16 x i8> @masked_load_v16i8(ptr %src, <16 x i1> %mask) {
; CHECK-LABEL: masked_load_v16i8:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -52,7 +53,7 @@ define <16 x i8> @masked_load_v16i8(ptr %src, <16 x i1> %mask) #0 {
ret <16 x i8> %load
}

define <32 x i8> @masked_load_v32i8(ptr %src, <32 x i1> %mask) #0 {
define <32 x i8> @masked_load_v32i8(ptr %src, <32 x i1> %mask) {
; CHECK-LABEL: masked_load_v32i8:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #32
Expand Down Expand Up @@ -133,7 +134,7 @@ define <32 x i8> @masked_load_v32i8(ptr %src, <32 x i1> %mask) #0 {
ret <32 x i8> %load
}

define <2 x half> @masked_load_v2f16(ptr %src, <2 x i1> %mask) #0 {
define <2 x half> @masked_load_v2f16(ptr %src, <2 x i1> %mask) {
; CHECK-LABEL: masked_load_v2f16:
; CHECK: // %bb.0:
; CHECK-NEXT: sub sp, sp, #16
Expand All @@ -158,7 +159,7 @@ define <2 x half> @masked_load_v2f16(ptr %src, <2 x i1> %mask) #0 {
ret <2 x half> %load
}

define <4 x half> @masked_load_v4f16(ptr %src, <4 x i1> %mask) #0 {
define <4 x half> @masked_load_v4f16(ptr %src, <4 x i1> %mask) {
; CHECK-LABEL: masked_load_v4f16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -173,7 +174,7 @@ define <4 x half> @masked_load_v4f16(ptr %src, <4 x i1> %mask) #0 {
ret <4 x half> %load
}

define <8 x half> @masked_load_v8f16(ptr %src, <8 x i1> %mask) #0 {
define <8 x half> @masked_load_v8f16(ptr %src, <8 x i1> %mask) {
; CHECK-LABEL: masked_load_v8f16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -189,7 +190,7 @@ define <8 x half> @masked_load_v8f16(ptr %src, <8 x i1> %mask) #0 {
ret <8 x half> %load
}

define <16 x half> @masked_load_v16f16(ptr %src, <16 x i1> %mask) #0 {
define <16 x half> @masked_load_v16f16(ptr %src, <16 x i1> %mask) {
; CHECK-LABEL: masked_load_v16f16:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $q0 killed $q0 def $z0
Expand All @@ -213,7 +214,7 @@ define <16 x half> @masked_load_v16f16(ptr %src, <16 x i1> %mask) #0 {
ret <16 x half> %load
}

define <2 x float> @masked_load_v2f32(ptr %src, <2 x i1> %mask) #0 {
define <2 x float> @masked_load_v2f32(ptr %src, <2 x i1> %mask) {
; CHECK-LABEL: masked_load_v2f32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -228,7 +229,7 @@ define <2 x float> @masked_load_v2f32(ptr %src, <2 x i1> %mask) #0 {
ret <2 x float> %load
}

define <4 x float> @masked_load_v4f32(ptr %src, <4 x i1> %mask) #0 {
define <4 x float> @masked_load_v4f32(ptr %src, <4 x i1> %mask) {
; CHECK-LABEL: masked_load_v4f32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -244,7 +245,7 @@ define <4 x float> @masked_load_v4f32(ptr %src, <4 x i1> %mask) #0 {
ret <4 x float> %load
}

define <8 x float> @masked_load_v8f32(ptr %src, <8 x i1> %mask) #0 {
define <8 x float> @masked_load_v8f32(ptr %src, <8 x i1> %mask) {
; CHECK-LABEL: masked_load_v8f32:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand Down Expand Up @@ -293,7 +294,7 @@ define <8 x float> @masked_load_v8f32(ptr %src, <8 x i1> %mask) #0 {
ret <8 x float> %load
}

define <2 x double> @masked_load_v2f64(ptr %src, <2 x i1> %mask) #0 {
define <2 x double> @masked_load_v2f64(ptr %src, <2 x i1> %mask) {
; CHECK-LABEL: masked_load_v2f64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand All @@ -309,7 +310,7 @@ define <2 x double> @masked_load_v2f64(ptr %src, <2 x i1> %mask) #0 {
ret <2 x double> %load
}

define <4 x double> @masked_load_v4f64(ptr %src, <4 x i1> %mask) #0 {
define <4 x double> @masked_load_v4f64(ptr %src, <4 x i1> %mask) {
; CHECK-LABEL: masked_load_v4f64:
; CHECK: // %bb.0:
; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0
Expand Down Expand Up @@ -350,5 +351,3 @@ declare <8 x float> @llvm.masked.load.v8f32(ptr, i32, <8 x i1>, <8 x float>)

declare <2 x double> @llvm.masked.load.v2f64(ptr, i32, <2 x i1>, <2 x double>)
declare <4 x double> @llvm.masked.load.v4f64(ptr, i32, <4 x i1>, <4 x double>)

attributes #0 = { "target-features"="+sve" }
Loading