118 changes: 64 additions & 54 deletions llvm/test/CodeGen/X86/GlobalISel/x86_64-select-zext.mir
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Original file line number Diff line number Diff line change
Expand Up @@ -72,11 +72,12 @@ body: |
; CHECK-LABEL: name: zext_i1_to_i8
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; CHECK: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def $eflags
; CHECK: $al = COPY [[AND8ri]]
; CHECK: RET 0, implicit $al
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; CHECK-NEXT: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def dead $eflags
; CHECK-NEXT: $al = COPY [[AND8ri]]
; CHECK-NEXT: RET 0, implicit $al
%1:gpr(s32) = COPY $edi
%3:gpr(s8) = G_CONSTANT i8 1
%4:gpr(s8) = G_TRUNC %1(s32)
Expand All @@ -103,11 +104,12 @@ body: |
; CHECK-LABEL: name: zext_i1_to_i16
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
; CHECK: [[AND16ri_:%[0-9]+]]:gr16 = AND16ri [[COPY1]], 1, implicit-def $eflags
; CHECK: $ax = COPY [[AND16ri_]]
; CHECK: RET 0, implicit $ax
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
; CHECK-NEXT: [[AND16ri:%[0-9]+]]:gr16 = AND16ri [[COPY1]], 1, implicit-def dead $eflags
; CHECK-NEXT: $ax = COPY [[AND16ri]]
; CHECK-NEXT: RET 0, implicit $ax
%1:gpr(s32) = COPY $edi
%3:gpr(s16) = G_CONSTANT i16 1
%4:gpr(s16) = G_TRUNC %1(s32)
Expand All @@ -134,10 +136,11 @@ body: |
; CHECK-LABEL: name: zext_i1_to_i32
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[AND32ri_:%[0-9]+]]:gr32 = AND32ri [[COPY]], 1, implicit-def $eflags
; CHECK: $eax = COPY [[AND32ri_]]
; CHECK: RET 0, implicit $eax
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK-NEXT: [[AND32ri:%[0-9]+]]:gr32 = AND32ri [[COPY]], 1, implicit-def dead $eflags
; CHECK-NEXT: $eax = COPY [[AND32ri]]
; CHECK-NEXT: RET 0, implicit $eax
%1:gpr(s32) = COPY $edi
%3:gpr(s32) = G_CONSTANT i32 1
%4:gpr(s32) = COPY %1(s32)
Expand All @@ -164,12 +167,13 @@ body: |
; CHECK-LABEL: name: zext_i1_to_i64
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 1, implicit-def $eflags
; CHECK: $rax = COPY [[AND64ri32_]]
; CHECK: RET 0, implicit $rax
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
; CHECK-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 1, implicit-def dead $eflags
; CHECK-NEXT: $rax = COPY [[AND64ri32_]]
; CHECK-NEXT: RET 0, implicit $rax
%1:gpr(s32) = COPY $edi
%3:gpr(s64) = G_CONSTANT i64 1
%4:gpr(s64) = G_ANYEXT %1(s32)
Expand All @@ -196,13 +200,14 @@ body: |
; CHECK-LABEL: name: zext_i8_to_i16
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
; CHECK: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]
; CHECK: [[COPY3:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit
; CHECK: $ax = COPY [[COPY3]]
; CHECK: RET 0, implicit $ax
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY2]]
; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr16 = COPY [[MOVZX32rr8_]].sub_16bit
; CHECK-NEXT: $ax = COPY [[COPY3]]
; CHECK-NEXT: RET 0, implicit $ax
%1:gpr(s32) = COPY $edi
%3:gpr(s16) = G_CONSTANT i16 255
%4:gpr(s16) = G_TRUNC %1(s32)
Expand All @@ -229,11 +234,12 @@ body: |
; CHECK-LABEL: name: zext_i8_to_i32
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
; CHECK: $eax = COPY [[MOVZX32rr8_]]
; CHECK: RET 0, implicit $eax
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; CHECK-NEXT: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[COPY1]]
; CHECK-NEXT: $eax = COPY [[MOVZX32rr8_]]
; CHECK-NEXT: RET 0, implicit $eax
%1:gpr(s32) = COPY $edi
%3:gpr(s32) = G_CONSTANT i32 255
%4:gpr(s32) = COPY %1(s32)
Expand All @@ -260,12 +266,13 @@ body: |
; CHECK-LABEL: name: zext_i8_to_i64
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 255, implicit-def $eflags
; CHECK: $rax = COPY [[AND64ri32_]]
; CHECK: RET 0, implicit $rax
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
; CHECK-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 255, implicit-def dead $eflags
; CHECK-NEXT: $rax = COPY [[AND64ri32_]]
; CHECK-NEXT: RET 0, implicit $rax
%1:gpr(s32) = COPY $edi
%3:gpr(s64) = G_CONSTANT i64 255
%4:gpr(s64) = G_ANYEXT %1(s32)
Expand All @@ -292,11 +299,12 @@ body: |
; CHECK-LABEL: name: zext_i16_to_i32
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
; CHECK: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]]
; CHECK: $eax = COPY [[MOVZX32rr16_]]
; CHECK: RET 0, implicit $eax
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY [[COPY]].sub_16bit
; CHECK-NEXT: [[MOVZX32rr16_:%[0-9]+]]:gr32 = MOVZX32rr16 [[COPY1]]
; CHECK-NEXT: $eax = COPY [[MOVZX32rr16_]]
; CHECK-NEXT: RET 0, implicit $eax
%1:gpr(s32) = COPY $edi
%3:gpr(s32) = G_CONSTANT i32 65535
%4:gpr(s32) = COPY %1(s32)
Expand All @@ -323,12 +331,13 @@ body: |
; CHECK-LABEL: name: zext_i16_to_i64
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
; CHECK: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 65535, implicit-def $eflags
; CHECK: $rax = COPY [[AND64ri32_]]
; CHECK: RET 0, implicit $rax
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK-NEXT: [[DEF:%[0-9]+]]:gr64 = IMPLICIT_DEF
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:gr64 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.sub_32bit
; CHECK-NEXT: [[AND64ri32_:%[0-9]+]]:gr64 = AND64ri32 [[INSERT_SUBREG]], 65535, implicit-def dead $eflags
; CHECK-NEXT: $rax = COPY [[AND64ri32_]]
; CHECK-NEXT: RET 0, implicit $rax
%1:gpr(s32) = COPY $edi
%3:gpr(s64) = G_CONSTANT i64 65535
%4:gpr(s64) = G_ANYEXT %1(s32)
Expand All @@ -352,11 +361,12 @@ body: |
; CHECK-LABEL: name: zext_i32_to_i64
; CHECK: liveins: $edi
; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK: [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[COPY]]
; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32rr]], %subreg.sub_32bit
; CHECK: $rax = COPY [[SUBREG_TO_REG]]
; CHECK: RET 0, implicit $rax
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK-NEXT: [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[COPY]]
; CHECK-NEXT: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[MOV32rr]], %subreg.sub_32bit
; CHECK-NEXT: $rax = COPY [[SUBREG_TO_REG]]
; CHECK-NEXT: RET 0, implicit $rax
%0:gpr(s32) = COPY $edi
%1:gpr(s64) = G_ZEXT %0(s32)
$rax = COPY %1(s64)
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/X86/switch-bit-test-unreachable-default.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -39,17 +39,17 @@ define i32 @baz(i32 %0) {
; CHECK-GISEL: liveins: $edi
; CHECK-GISEL: %0:gr32 = COPY $edi
; CHECK-GISEL: %10:gr32 = MOV32ri 1
; CHECK-GISEL: %11:gr32 = MOV32r0 implicit-def $eflags
; CHECK-GISEL: %2:gr32 = SUB32ri %0:gr32(tied-def 0), 0, implicit-def $eflags
; CHECK-GISEL: %11:gr32 = MOV32r0 implicit-def dead $eflags
; CHECK-GISEL: %2:gr32 = SUB32ri %0:gr32(tied-def 0), 0, implicit-def dead $eflags
; CHECK-GISEL: bb.5 (%ir-block.1):
; CHECK-GISEL: ; predecessors: %bb.1
; CHECK-GISEL: successors: %bb.4(0x55555555), %bb.2(0x2aaaaaab); %bb.4(66.67%), %bb.2(33.33%)
; CHECK-GISEL: %3:gr32 = MOV32ri 1
; CHECK-GISEL: %13:gr8 = COPY %2.sub_8bit:gr32
; CHECK-GISEL: $cl = COPY %13:gr8
; CHECK-GISEL: %4:gr32 = SHL32rCL %3:gr32(tied-def 0), implicit-def $eflags, implicit $cl
; CHECK-GISEL: %6:gr32 = AND32ri %4:gr32(tied-def 0), 13056, implicit-def $eflags
; CHECK-GISEL: %7:gr32 = MOV32r0 implicit-def $eflags
; CHECK-GISEL: %4:gr32 = SHL32rCL %3:gr32(tied-def 0), implicit-def dead $eflags, implicit $cl
; CHECK-GISEL: %6:gr32 = AND32ri %4:gr32(tied-def 0), 13056, implicit-def dead $eflags
; CHECK-GISEL: %7:gr32 = MOV32r0 implicit-def dead $eflags
; CHECK-GISEL: CMP32rr %6:gr32, %7:gr32, implicit-def $eflags
; CHECK-GISEL: %12:gr8 = SETCCr 5, implicit $eflags
; CHECK-GISEL: TEST8ri %12:gr8, 1, implicit-def $eflags
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/tools/UpdateTestChecks/update_mir_test_checks/Inputs/x86-condbr.mir.expected
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Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ body: |
; CHECK-NEXT: liveins: $edi
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def $eflags
; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1
; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
; CHECK-NEXT: TEST8ri [[COPY1]], 1, implicit-def $eflags
Expand Down
13 changes: 13 additions & 0 deletions llvm/utils/TableGen/GlobalISelMatchTable.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1966,6 +1966,19 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table,
for (const auto &Renderer : OperandRenderers)
Renderer->emitRenderOpcodes(Table, Rule);

for (auto [OpIdx, Def] : enumerate(I->ImplicitDefs)) {
auto Namespace =
Def->getValue("Namespace") ? Def->getValueAsString("Namespace") : "";
if (DeadImplicitDefs.contains(Def)) {
Table
<< MatchTable::Opcode("GIR_SetImplicitDefDead")
<< MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID)
<< MatchTable::Comment(
("OpIdx for " + Namespace + "::" + Def->getName() + "").str())
<< MatchTable::IntValue(OpIdx) << MatchTable::LineBreak;
}
}

if (I->mayLoad || I->mayStore) {
Table << MatchTable::Opcode("GIR_MergeMemOperands")
<< MatchTable::Comment("InsnID") << MatchTable::IntValue(InsnID)
Expand Down