diff --git a/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll b/llvm/test/CodeGen/PowerPC/f128-truncateNconv.ll
diff --git a/llvm/test/CodeGen/PowerPC/fma-aggr-FMF.ll b/llvm/test/CodeGen/PowerPC/fma-aggr-FMF.ll
@@ -22,10 +22,10 @@ define float @can_fma_with_fewer_uses(float %f1, float %f2, float %f3, float %f4
 define float @no_fma_with_fewer_uses(float %f1, float %f2, float %f3, float %f4) {
 ; CHECK-LABEL: no_fma_with_fewer_uses:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    xsmulsp 0, 3, 4
-; CHECK-NEXT:    xsmulsp 3, 1, 2
-; CHECK-NEXT:    xsmaddasp 0, 1, 2
-; CHECK-NEXT:    xsdivsp 1, 3, 0
+; CHECK-NEXT:    xsmulsp 3, 3, 4
+; CHECK-NEXT:    xsmulsp 0, 1, 2
+; CHECK-NEXT:    xsmaddasp 3, 1, 2
+; CHECK-NEXT:    xsdivsp 1, 0, 3
 ; CHECK-NEXT:    blr
   %mul1 = fmul contract float %f1, %f2
   %mul2 = fmul float %f3, %f4

diff --git a/llvm/test/CodeGen/PowerPC/fma-combine.ll b/llvm/test/CodeGen/PowerPC/fma-combine.ll
@@ -60,36 +60,34 @@ define dso_local double @fma_combine_two_uses(double %a, double %b, double %c) {
 ; CHECK-FAST:       # %bb.0: # %entry
 ; CHECK-FAST-NEXT:    xsnegdp 0, 1
 ; CHECK-FAST-NEXT:    addis 3, 2, v@toc@ha
-; CHECK-FAST-NEXT:    addis 4, 2, z@toc@ha
 ; CHECK-FAST-NEXT:    xsnmaddadp 1, 3, 2
-; CHECK-FAST-NEXT:    xsnegdp 2, 3
 ; CHECK-FAST-NEXT:    stfd 0, v@toc@l(3)
-; CHECK-FAST-NEXT:    stfd 2, z@toc@l(4)
+; CHECK-FAST-NEXT:    xsnegdp 0, 3
+; CHECK-FAST-NEXT:    addis 3, 2, z@toc@ha
+; CHECK-FAST-NEXT:    stfd 0, z@toc@l(3)
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: fma_combine_two_uses:
 ; CHECK-FAST-NOVSX:       # %bb.0: # %entry
-; CHECK-FAST-NOVSX-NEXT:    fnmadd 0, 3, 2, 1
-; CHECK-FAST-NOVSX-NEXT:    fneg 2, 1
+; CHECK-FAST-NOVSX-NEXT:    fneg 0, 1
 ; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, v@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    addis 4, 2, z@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    fneg 3, 3
-; CHECK-FAST-NOVSX-NEXT:    fmr 1, 0
-; CHECK-FAST-NOVSX-NEXT:    stfd 2, v@toc@l(3)
-; CHECK-FAST-NOVSX-NEXT:    stfd 3, z@toc@l(4)
+; CHECK-FAST-NOVSX-NEXT:    fnmadd 1, 3, 2, 1
+; CHECK-FAST-NOVSX-NEXT:    stfd 0, v@toc@l(3)
+; CHECK-FAST-NOVSX-NEXT:    fneg 0, 3
+; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, z@toc@ha
+; CHECK-FAST-NOVSX-NEXT:    stfd 0, z@toc@l(3)
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: fma_combine_two_uses:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xsnegdp 3, 3
+; CHECK-NEXT:    xsnegdp 0, 1
 ; CHECK-NEXT:    addis 3, 2, v@toc@ha
-; CHECK-NEXT:    addis 4, 2, z@toc@ha
-; CHECK-NEXT:    xsmuldp 0, 3, 2
-; CHECK-NEXT:    stfd 3, z@toc@l(4)
-; CHECK-NEXT:    xsnegdp 2, 1
-; CHECK-NEXT:    xssubdp 0, 0, 1
-; CHECK-NEXT:    stfd 2, v@toc@l(3)
-; CHECK-NEXT:    fmr 1, 0
+; CHECK-NEXT:    stfd 0, v@toc@l(3)
+; CHECK-NEXT:    xsnegdp 0, 3
+; CHECK-NEXT:    addis 3, 2, z@toc@ha
+; CHECK-NEXT:    stfd 0, z@toc@l(3)
+; CHECK-NEXT:    xsmuldp 0, 0, 2
+; CHECK-NEXT:    xssubdp 1, 0, 1
 ; CHECK-NEXT:    blr
 entry:
   %fneg = fneg double %a
@@ -105,29 +103,27 @@ define dso_local double @fma_combine_one_use(double %a, double %b, double %c) {
 ; CHECK-FAST-LABEL: fma_combine_one_use:
 ; CHECK-FAST:       # %bb.0: # %entry
 ; CHECK-FAST-NEXT:    xsnegdp 0, 1
-; CHECK-FAST-NEXT:    addis 3, 2, v@toc@ha
 ; CHECK-FAST-NEXT:    xsnmaddadp 1, 3, 2
+; CHECK-FAST-NEXT:    addis 3, 2, v@toc@ha
 ; CHECK-FAST-NEXT:    stfd 0, v@toc@l(3)
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: fma_combine_one_use:
 ; CHECK-FAST-NOVSX:       # %bb.0: # %entry
-; CHECK-FAST-NOVSX-NEXT:    fnmadd 0, 3, 2, 1
-; CHECK-FAST-NOVSX-NEXT:    fneg 2, 1
+; CHECK-FAST-NOVSX-NEXT:    fneg 0, 1
+; CHECK-FAST-NOVSX-NEXT:    fnmadd 1, 3, 2, 1
 ; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, v@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    fmr 1, 0
-; CHECK-FAST-NOVSX-NEXT:    stfd 2, v@toc@l(3)
+; CHECK-FAST-NOVSX-NEXT:    stfd 0, v@toc@l(3)
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: fma_combine_one_use:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    xsnegdp 0, 3
+; CHECK-NEXT:    xsnegdp 0, 1
 ; CHECK-NEXT:    addis 3, 2, v@toc@ha
+; CHECK-NEXT:    stfd 0, v@toc@l(3)
+; CHECK-NEXT:    xsnegdp 0, 3
 ; CHECK-NEXT:    xsmuldp 0, 0, 2
-; CHECK-NEXT:    xsnegdp 2, 1
-; CHECK-NEXT:    xssubdp 0, 0, 1
-; CHECK-NEXT:    stfd 2, v@toc@l(3)
-; CHECK-NEXT:    fmr 1, 0
+; CHECK-NEXT:    xssubdp 1, 0, 1
 ; CHECK-NEXT:    blr
 entry:
   %fneg = fneg double %a
@@ -143,43 +139,43 @@ define dso_local float @fma_combine_no_ice() {
 ; CHECK-FAST:       # %bb.0:
 ; CHECK-FAST-NEXT:    vspltisw 2, 1
 ; CHECK-FAST-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
+; CHECK-FAST-NEXT:    xvcvsxwdp 3, 34
+; CHECK-FAST-NEXT:    lfs 0, .LCPI4_0@toc@l(3)
 ; CHECK-FAST-NEXT:    lfs 2, 0(3)
-; CHECK-FAST-NEXT:    lfs 1, .LCPI4_0@toc@l(3)
 ; CHECK-FAST-NEXT:    addis 3, 2, .LCPI4_1@toc@ha
-; CHECK-FAST-NEXT:    xvcvsxwdp 0, 34
-; CHECK-FAST-NEXT:    xsmaddasp 0, 2, 1
 ; CHECK-FAST-NEXT:    lfs 1, .LCPI4_1@toc@l(3)
-; CHECK-FAST-NEXT:    xsmaddasp 1, 2, 0
-; CHECK-FAST-NEXT:    xsnmsubasp 1, 0, 2
+; CHECK-FAST-NEXT:    xsmaddasp 3, 2, 0
+; CHECK-FAST-NEXT:    xsmaddasp 1, 2, 3
+; CHECK-FAST-NEXT:    xsnmsubasp 1, 3, 2
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: fma_combine_no_ice:
 ; CHECK-FAST-NOVSX:       # %bb.0:
+; CHECK-FAST-NOVSX-NEXT:    lfs 0, 0(3)
 ; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    lfs 0, .LCPI4_0@toc@l(3)
+; CHECK-FAST-NOVSX-NEXT:    lfs 1, .LCPI4_0@toc@l(3)
 ; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI4_1@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    lfs 1, 0(3)
 ; CHECK-FAST-NOVSX-NEXT:    lfs 2, .LCPI4_1@toc@l(3)
 ; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI4_2@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    fmadds 0, 1, 2, 0
+; CHECK-FAST-NOVSX-NEXT:    fmadds 1, 0, 2, 1
 ; CHECK-FAST-NOVSX-NEXT:    lfs 2, .LCPI4_2@toc@l(3)
-; CHECK-FAST-NOVSX-NEXT:    fmadds 2, 1, 0, 2
-; CHECK-FAST-NOVSX-NEXT:    fnmsubs 1, 0, 1, 2
+; CHECK-FAST-NOVSX-NEXT:    fmadds 2, 0, 1, 2
+; CHECK-FAST-NOVSX-NEXT:    fnmsubs 1, 1, 0, 2
 ; CHECK-FAST-NOVSX-NEXT:    blr
 ;
 ; CHECK-LABEL: fma_combine_no_ice:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 2, 1
 ; CHECK-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
+; CHECK-NEXT:    xvcvsxwdp 3, 34
+; CHECK-NEXT:    lfs 0, .LCPI4_0@toc@l(3)
 ; CHECK-NEXT:    lfs 2, 0(3)
-; CHECK-NEXT:    lfs 3, .LCPI4_0@toc@l(3)
 ; CHECK-NEXT:    addis 3, 2, .LCPI4_1@toc@ha
 ; CHECK-NEXT:    lfs 1, .LCPI4_1@toc@l(3)
-; CHECK-NEXT:    xvcvsxwdp 0, 34
-; CHECK-NEXT:    fmr 4, 0
-; CHECK-NEXT:    xsmaddasp 0, 2, 3
-; CHECK-NEXT:    xsnmaddasp 4, 2, 3
-; CHECK-NEXT:    xsmaddasp 1, 2, 0
+; CHECK-NEXT:    fmr 4, 3
+; CHECK-NEXT:    xsmaddasp 3, 2, 0
+; CHECK-NEXT:    xsnmaddasp 4, 2, 0
+; CHECK-NEXT:    xsmaddasp 1, 2, 3
 ; CHECK-NEXT:    xsmaddasp 1, 4, 2
 ; CHECK-NEXT:    blr
   %tmp = load float, ptr undef, align 4
@@ -203,21 +199,21 @@ define dso_local double @getNegatedExpression_crash(double %x, double %y) {
 ; CHECK-FAST:       # %bb.0:
 ; CHECK-FAST-NEXT:    vspltisw 2, -1
 ; CHECK-FAST-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; CHECK-FAST-NEXT:    lfs 4, .LCPI5_0@toc@l(3)
-; CHECK-FAST-NEXT:    xvcvsxwdp 3, 34
-; CHECK-FAST-NEXT:    xssubdp 0, 1, 3
-; CHECK-FAST-NEXT:    # kill: def $f3 killed $f3 killed $vsl3
-; CHECK-FAST-NEXT:    xsmaddadp 3, 1, 4
-; CHECK-FAST-NEXT:    xsmaddadp 0, 3, 2
+; CHECK-FAST-NEXT:    xvcvsxwdp 4, 34
+; CHECK-FAST-NEXT:    lfs 3, .LCPI5_0@toc@l(3)
+; CHECK-FAST-NEXT:    xssubdp 0, 1, 4
+; CHECK-FAST-NEXT:    # kill: def $f4 killed $f4 killed $vsl4
+; CHECK-FAST-NEXT:    xsmaddadp 4, 1, 3
+; CHECK-FAST-NEXT:    xsmaddadp 0, 4, 2
 ; CHECK-FAST-NEXT:    fmr 1, 0
 ; CHECK-FAST-NEXT:    blr
 ;
 ; CHECK-FAST-NOVSX-LABEL: getNegatedExpression_crash:
 ; CHECK-FAST-NOVSX:       # %bb.0:
 ; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; CHECK-FAST-NOVSX-NEXT:    addis 4, 2, .LCPI5_1@toc@ha
 ; CHECK-FAST-NOVSX-NEXT:    lfs 0, .LCPI5_0@toc@l(3)
-; CHECK-FAST-NOVSX-NEXT:    lfs 3, .LCPI5_1@toc@l(4)
+; CHECK-FAST-NOVSX-NEXT:    addis 3, 2, .LCPI5_1@toc@ha
+; CHECK-FAST-NOVSX-NEXT:    lfs 3, .LCPI5_1@toc@l(3)
 ; CHECK-FAST-NOVSX-NEXT:    fmadd 3, 1, 3, 0
 ; CHECK-FAST-NOVSX-NEXT:    fsub 0, 1, 0
 ; CHECK-FAST-NOVSX-NEXT:    fmadd 1, 3, 2, 0
@@ -227,12 +223,12 @@ define dso_local double @getNegatedExpression_crash(double %x, double %y) {
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vspltisw 2, -1
 ; CHECK-NEXT:    addis 3, 2, .LCPI5_0@toc@ha
-; CHECK-NEXT:    lfs 4, .LCPI5_0@toc@l(3)
-; CHECK-NEXT:    xvcvsxwdp 3, 34
-; CHECK-NEXT:    xssubdp 0, 1, 3
-; CHECK-NEXT:    # kill: def $f3 killed $f3 killed $vsl3
-; CHECK-NEXT:    xsmaddadp 3, 1, 4
-; CHECK-NEXT:    xsmaddadp 0, 3, 2
+; CHECK-NEXT:    xvcvsxwdp 4, 34
+; CHECK-NEXT:    lfs 3, .LCPI5_0@toc@l(3)
+; CHECK-NEXT:    xssubdp 0, 1, 4
+; CHECK-NEXT:    # kill: def $f4 killed $f4 killed $vsl4
+; CHECK-NEXT:    xsmaddadp 4, 1, 3
+; CHECK-NEXT:    xsmaddadp 0, 4, 2
 ; CHECK-NEXT:    fmr 1, 0
 ; CHECK-NEXT:    blr
   %neg = fneg reassoc double %x
@@ -334,10 +330,10 @@ define dso_local double @fma_combine_const(double %a, double %b) {
 ; CHECK-NEXT:    addis 3, 2, .LCPI9_0@toc@ha
 ; CHECK-NEXT:    lfd 0, .LCPI9_0@toc@l(3)
 ; CHECK-NEXT:    addis 3, 2, .LCPI9_1@toc@ha
-; CHECK-NEXT:    lfd 3, .LCPI9_1@toc@l(3)
 ; CHECK-NEXT:    xsmuldp 0, 1, 0
+; CHECK-NEXT:    lfd 1, .LCPI9_1@toc@l(3)
+; CHECK-NEXT:    xsmaddadp 2, 0, 1
 ; CHECK-NEXT:    fmr 1, 2
-; CHECK-NEXT:    xsmaddadp 1, 0, 3
 ; CHECK-NEXT:    blr
 entry:
   %0 = fmul double %a, 1.1

diff --git a/llvm/test/CodeGen/PowerPC/fmf-propagation.ll b/llvm/test/CodeGen/PowerPC/fmf-propagation.ll
@@ -302,31 +302,31 @@ define float @fmul_fma_fast2(float %x) {
 define float @sqrt_afn_ieee(float %x) #0 {
 ; FMF-LABEL: sqrt_afn_ieee:
 ; FMF:       # %bb.0:
-; FMF-NEXT:    xsabsdp 0, 1
 ; FMF-NEXT:    addis 3, 2, .LCPI11_1@toc@ha
+; FMF-NEXT:    xsabsdp 0, 1
 ; FMF-NEXT:    lfs 2, .LCPI11_1@toc@l(3)
 ; FMF-NEXT:    fcmpu 0, 0, 2
 ; FMF-NEXT:    xxlxor 0, 0, 0
 ; FMF-NEXT:    blt 0, .LBB11_2
 ; FMF-NEXT:  # %bb.1:
-; FMF-NEXT:    xsrsqrtesp 0, 1
-; FMF-NEXT:    vspltisw 2, -3
+; FMF-NEXT:    xsrsqrtesp 2, 1
 ; FMF-NEXT:    addis 3, 2, .LCPI11_0@toc@ha
-; FMF-NEXT:    lfs 3, .LCPI11_0@toc@l(3)
-; FMF-NEXT:    xvcvsxwdp 2, 34
-; FMF-NEXT:    xsmulsp 1, 1, 0
-; FMF-NEXT:    xsmulsp 0, 1, 0
-; FMF-NEXT:    xsmulsp 1, 1, 3
-; FMF-NEXT:    xsaddsp 0, 0, 2
+; FMF-NEXT:    vspltisw 2, -3
+; FMF-NEXT:    lfs 0, .LCPI11_0@toc@l(3)
+; FMF-NEXT:    xsmulsp 1, 1, 2
 ; FMF-NEXT:    xsmulsp 0, 1, 0
+; FMF-NEXT:    xsmulsp 1, 1, 2
+; FMF-NEXT:    xvcvsxwdp 2, 34
+; FMF-NEXT:    xsaddsp 1, 1, 2
+; FMF-NEXT:    xsmulsp 0, 0, 1
 ; FMF-NEXT:  .LBB11_2:
 ; FMF-NEXT:    fmr 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: sqrt_afn_ieee:
 ; GLOBAL:       # %bb.0:
-; GLOBAL-NEXT:    xsabsdp 0, 1
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI11_1@toc@ha
+; GLOBAL-NEXT:    xsabsdp 0, 1
 ; GLOBAL-NEXT:    lfs 2, .LCPI11_1@toc@l(3)
 ; GLOBAL-NEXT:    fcmpu 0, 0, 2
 ; GLOBAL-NEXT:    xxlxor 0, 0, 0
@@ -335,11 +335,11 @@ define float @sqrt_afn_ieee(float %x) #0 {
 ; GLOBAL-NEXT:    xsrsqrtesp 0, 1
 ; GLOBAL-NEXT:    vspltisw 2, -3
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI11_0@toc@ha
-; GLOBAL-NEXT:    lfs 3, .LCPI11_0@toc@l(3)
 ; GLOBAL-NEXT:    xvcvsxwdp 2, 34
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
-; GLOBAL-NEXT:    xsmulsp 0, 1, 3
+; GLOBAL-NEXT:    lfs 0, .LCPI11_0@toc@l(3)
+; GLOBAL-NEXT:    xsmulsp 0, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB11_2:
 ; GLOBAL-NEXT:    fmr 1, 0
@@ -378,15 +378,15 @@ define float @sqrt_afn_preserve_sign(float %x) #1 {
 ; FMF-NEXT:    beq 0, .LBB13_2
 ; FMF-NEXT:  # %bb.1:
 ; FMF-NEXT:    xsrsqrtesp 0, 1
-; FMF-NEXT:    vspltisw 2, -3
 ; FMF-NEXT:    addis 3, 2, .LCPI13_0@toc@ha
-; FMF-NEXT:    lfs 3, .LCPI13_0@toc@l(3)
-; FMF-NEXT:    xvcvsxwdp 2, 34
+; FMF-NEXT:    vspltisw 2, -3
+; FMF-NEXT:    lfs 2, .LCPI13_0@toc@l(3)
 ; FMF-NEXT:    xsmulsp 1, 1, 0
+; FMF-NEXT:    xsmulsp 2, 1, 2
 ; FMF-NEXT:    xsmulsp 0, 1, 0
-; FMF-NEXT:    xsmulsp 1, 1, 3
-; FMF-NEXT:    xsaddsp 0, 0, 2
-; FMF-NEXT:    xsmulsp 0, 1, 0
+; FMF-NEXT:    xvcvsxwdp 1, 34
+; FMF-NEXT:    xsaddsp 0, 0, 1
+; FMF-NEXT:    xsmulsp 0, 2, 0
 ; FMF-NEXT:  .LBB13_2:
 ; FMF-NEXT:    fmr 1, 0
 ; FMF-NEXT:    blr
@@ -400,11 +400,11 @@ define float @sqrt_afn_preserve_sign(float %x) #1 {
 ; GLOBAL-NEXT:    xsrsqrtesp 0, 1
 ; GLOBAL-NEXT:    vspltisw 2, -3
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI13_0@toc@ha
-; GLOBAL-NEXT:    lfs 3, .LCPI13_0@toc@l(3)
 ; GLOBAL-NEXT:    xvcvsxwdp 2, 34
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
-; GLOBAL-NEXT:    xsmulsp 0, 1, 3
+; GLOBAL-NEXT:    lfs 0, .LCPI13_0@toc@l(3)
+; GLOBAL-NEXT:    xsmulsp 0, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB13_2:
 ; GLOBAL-NEXT:    fmr 1, 0
@@ -440,8 +440,8 @@ define float @sqrt_afn_preserve_sign_inf(float %x) #1 {
 define float @sqrt_fast_ieee(float %x) #0 {
 ; FMF-LABEL: sqrt_fast_ieee:
 ; FMF:       # %bb.0:
-; FMF-NEXT:    xsabsdp 0, 1
 ; FMF-NEXT:    addis 3, 2, .LCPI15_1@toc@ha
+; FMF-NEXT:    xsabsdp 0, 1
 ; FMF-NEXT:    lfs 2, .LCPI15_1@toc@l(3)
 ; FMF-NEXT:    fcmpu 0, 0, 2
 ; FMF-NEXT:    xxlxor 0, 0, 0
@@ -450,20 +450,20 @@ define float @sqrt_fast_ieee(float %x) #0 {
 ; FMF-NEXT:    xsrsqrtesp 0, 1
 ; FMF-NEXT:    vspltisw 2, -3
 ; FMF-NEXT:    addis 3, 2, .LCPI15_0@toc@ha
-; FMF-NEXT:    lfs 3, .LCPI15_0@toc@l(3)
 ; FMF-NEXT:    xvcvsxwdp 2, 34
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    xsmaddasp 2, 1, 0
-; FMF-NEXT:    xsmulsp 0, 1, 3
+; FMF-NEXT:    lfs 0, .LCPI15_0@toc@l(3)
+; FMF-NEXT:    xsmulsp 0, 1, 0
 ; FMF-NEXT:    xsmulsp 0, 0, 2
 ; FMF-NEXT:  .LBB15_2:
 ; FMF-NEXT:    fmr 1, 0
 ; FMF-NEXT:    blr
 ;
 ; GLOBAL-LABEL: sqrt_fast_ieee:
 ; GLOBAL:       # %bb.0:
-; GLOBAL-NEXT:    xsabsdp 0, 1
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI15_1@toc@ha
+; GLOBAL-NEXT:    xsabsdp 0, 1
 ; GLOBAL-NEXT:    lfs 2, .LCPI15_1@toc@l(3)
 ; GLOBAL-NEXT:    fcmpu 0, 0, 2
 ; GLOBAL-NEXT:    xxlxor 0, 0, 0
@@ -472,11 +472,11 @@ define float @sqrt_fast_ieee(float %x) #0 {
 ; GLOBAL-NEXT:    xsrsqrtesp 0, 1
 ; GLOBAL-NEXT:    vspltisw 2, -3
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI15_0@toc@ha
-; GLOBAL-NEXT:    lfs 3, .LCPI15_0@toc@l(3)
 ; GLOBAL-NEXT:    xvcvsxwdp 2, 34
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
-; GLOBAL-NEXT:    xsmulsp 0, 1, 3
+; GLOBAL-NEXT:    lfs 0, .LCPI15_0@toc@l(3)
+; GLOBAL-NEXT:    xsmulsp 0, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB15_2:
 ; GLOBAL-NEXT:    fmr 1, 0
@@ -505,11 +505,11 @@ define float @sqrt_fast_preserve_sign(float %x) #1 {
 ; FMF-NEXT:    xsrsqrtesp 0, 1
 ; FMF-NEXT:    vspltisw 2, -3
 ; FMF-NEXT:    addis 3, 2, .LCPI16_0@toc@ha
-; FMF-NEXT:    lfs 3, .LCPI16_0@toc@l(3)
 ; FMF-NEXT:    xvcvsxwdp 2, 34
 ; FMF-NEXT:    xsmulsp 1, 1, 0
 ; FMF-NEXT:    xsmaddasp 2, 1, 0
-; FMF-NEXT:    xsmulsp 0, 1, 3
+; FMF-NEXT:    lfs 0, .LCPI16_0@toc@l(3)
+; FMF-NEXT:    xsmulsp 0, 1, 0
 ; FMF-NEXT:    xsmulsp 0, 0, 2
 ; FMF-NEXT:  .LBB16_2:
 ; FMF-NEXT:    fmr 1, 0
@@ -524,11 +524,11 @@ define float @sqrt_fast_preserve_sign(float %x) #1 {
 ; GLOBAL-NEXT:    xsrsqrtesp 0, 1
 ; GLOBAL-NEXT:    vspltisw 2, -3
 ; GLOBAL-NEXT:    addis 3, 2, .LCPI16_0@toc@ha
-; GLOBAL-NEXT:    lfs 3, .LCPI16_0@toc@l(3)
 ; GLOBAL-NEXT:    xvcvsxwdp 2, 34
 ; GLOBAL-NEXT:    xsmulsp 1, 1, 0
 ; GLOBAL-NEXT:    xsmaddasp 2, 1, 0
-; GLOBAL-NEXT:    xsmulsp 0, 1, 3
+; GLOBAL-NEXT:    lfs 0, .LCPI16_0@toc@l(3)
+; GLOBAL-NEXT:    xsmulsp 0, 1, 0
 ; GLOBAL-NEXT:    xsmulsp 0, 0, 2
 ; GLOBAL-NEXT:  .LBB16_2:
 ; GLOBAL-NEXT:    fmr 1, 0

diff --git a/llvm/test/CodeGen/PowerPC/fold-rlwinm-1.ll b/llvm/test/CodeGen/PowerPC/fold-rlwinm-1.ll
@@ -26,13 +26,13 @@ define void @foo_multiple_use(i32 signext %var1) {
 ; CHECK-LABEL: foo_multiple_use:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    xori r3, r3, 1
-; CHECK-NEXT:    addis r4, r2, res2@toc@ha
-; CHECK-NEXT:    addis r6, r2, res@toc@ha
+; CHECK-NEXT:    addis r5, r2, res2@toc@ha
 ; CHECK-NEXT:    cntlzw r3, r3
-; CHECK-NEXT:    srwi r5, r3, 5
+; CHECK-NEXT:    srwi r4, r3, 5
 ; CHECK-NEXT:    rlwinm r3, r3, 14, 0, 12
-; CHECK-NEXT:    stw r5, res2@toc@l(r4)
-; CHECK-NEXT:    stw r3, res@toc@l(r6)
+; CHECK-NEXT:    stw r4, res2@toc@l(r5)
+; CHECK-NEXT:    addis r4, r2, res@toc@ha
+; CHECK-NEXT:    stw r3, res@toc@l(r4)
 ; CHECK-NEXT:    blr
 entry:
   %cmp = icmp eq i32 %var1, 1

diff --git a/llvm/test/CodeGen/PowerPC/fp-classify.ll b/llvm/test/CodeGen/PowerPC/fp-classify.ll
@@ -7,8 +7,8 @@
 define zeroext i1 @abs_isinff(float %x) {
 ; P8-LABEL: abs_isinff:
 ; P8:       # %bb.0: # %entry
-; P8-NEXT:    xsabsdp 0, 1
 ; P8-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
+; P8-NEXT:    xsabsdp 0, 1
 ; P8-NEXT:    li 4, 1
 ; P8-NEXT:    lfs 1, .LCPI0_0@toc@l(3)
 ; P8-NEXT:    li 3, 0
@@ -35,8 +35,8 @@ entry:
 define zeroext i1 @abs_isinf(double %x) {
 ; P8-LABEL: abs_isinf:
 ; P8:       # %bb.0: # %entry
-; P8-NEXT:    xsabsdp 0, 1
 ; P8-NEXT:    addis 3, 2, .LCPI1_0@toc@ha
+; P8-NEXT:    xsabsdp 0, 1
 ; P8-NEXT:    li 4, 1
 ; P8-NEXT:    lfs 1, .LCPI1_0@toc@l(3)
 ; P8-NEXT:    li 3, 0
@@ -109,8 +109,8 @@ entry:
 define <4 x i1> @abs_isinfv4f32(<4 x float> %x) {
 ; P8-LABEL: abs_isinfv4f32:
 ; P8:       # %bb.0: # %entry
-; P8-NEXT:    xvabssp 0, 34
 ; P8-NEXT:    addis 3, 2, .LCPI3_0@toc@ha
+; P8-NEXT:    xvabssp 0, 34
 ; P8-NEXT:    addi 3, 3, .LCPI3_0@toc@l
 ; P8-NEXT:    lxvd2x 1, 0, 3
 ; P8-NEXT:    xvcmpeqsp 34, 0, 1
@@ -133,8 +133,8 @@ entry:
 define <2 x i1> @abs_isinfv2f64(<2 x double> %x) {
 ; P8-LABEL: abs_isinfv2f64:
 ; P8:       # %bb.0: # %entry
-; P8-NEXT:    xvabsdp 0, 34
 ; P8-NEXT:    addis 3, 2, .LCPI4_0@toc@ha
+; P8-NEXT:    xvabsdp 0, 34
 ; P8-NEXT:    addi 3, 3, .LCPI4_0@toc@l
 ; P8-NEXT:    lxvd2x 1, 0, 3
 ; P8-NEXT:    xvcmpeqdp 34, 0, 1

diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll b/llvm/test/CodeGen/PowerPC/fp-strict-conv-f128.ll
@@ -496,8 +496,8 @@ define signext i32 @ppcq_to_i32(ppc_fp128 %m) #0 {
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    mffs f0
 ; NOVSX-NEXT:    mtfsb1 31
-; NOVSX-NEXT:    addi r3, r1, -4
 ; NOVSX-NEXT:    mtfsb0 30
+; NOVSX-NEXT:    addi r3, r1, -4
 ; NOVSX-NEXT:    fadd f1, f2, f1
 ; NOVSX-NEXT:    mtfsf 1, f0
 ; NOVSX-NEXT:    fctiwz f0, f1
@@ -616,11 +616,11 @@ define zeroext i32 @ppcq_to_u32(ppc_fp128 %m) #0 {
 ; P8-NEXT:    xxlxor f3, f3, f3
 ; P8-NEXT:    std r30, 112(r1) # 8-byte Folded Spill
 ; P8-NEXT:    lfs f0, .LCPI13_0@toc@l(r3)
+; P8-NEXT:    fcmpo cr1, f2, f3
 ; P8-NEXT:    lis r3, -32768
-; P8-NEXT:    fcmpo cr0, f2, f3
-; P8-NEXT:    fcmpo cr1, f1, f0
-; P8-NEXT:    crand 4*cr5+lt, 4*cr1+eq, lt
-; P8-NEXT:    crandc 4*cr5+gt, 4*cr1+lt, 4*cr1+eq
+; P8-NEXT:    fcmpo cr0, f1, f0
+; P8-NEXT:    crand 4*cr5+lt, eq, 4*cr1+lt
+; P8-NEXT:    crandc 4*cr5+gt, lt, eq
 ; P8-NEXT:    cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
 ; P8-NEXT:    isel r30, 0, r3, 4*cr5+lt
 ; P8-NEXT:    bc 12, 4*cr5+lt, .LBB13_2
@@ -689,22 +689,22 @@ define zeroext i32 @ppcq_to_u32(ppc_fp128 %m) #0 {
 ; NOVSX-LABEL: ppcq_to_u32:
 ; NOVSX:       # %bb.0: # %entry
 ; NOVSX-NEXT:    mfocrf r12, 32
-; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    stw r12, 8(r1)
+; NOVSX-NEXT:    mflr r0
 ; NOVSX-NEXT:    stdu r1, -48(r1)
 ; NOVSX-NEXT:    std r0, 64(r1)
 ; NOVSX-NEXT:    .cfi_def_cfa_offset 48
 ; NOVSX-NEXT:    .cfi_offset lr, 16
 ; NOVSX-NEXT:    .cfi_offset cr2, 8
 ; NOVSX-NEXT:    addis r3, r2, .LCPI13_0@toc@ha
-; NOVSX-NEXT:    addis r4, r2, .LCPI13_1@toc@ha
 ; NOVSX-NEXT:    lfs f0, .LCPI13_0@toc@l(r3)
-; NOVSX-NEXT:    lfs f4, .LCPI13_1@toc@l(r4)
+; NOVSX-NEXT:    addis r3, r2, .LCPI13_1@toc@ha
+; NOVSX-NEXT:    lfs f4, .LCPI13_1@toc@l(r3)
 ; NOVSX-NEXT:    fcmpo cr0, f1, f0
 ; NOVSX-NEXT:    fcmpo cr1, f2, f4
 ; NOVSX-NEXT:    fmr f3, f4
-; NOVSX-NEXT:    crand 4*cr5+lt, eq, 4*cr1+lt
 ; NOVSX-NEXT:    crandc 4*cr5+gt, lt, eq
+; NOVSX-NEXT:    crand 4*cr5+lt, eq, 4*cr1+lt
 ; NOVSX-NEXT:    cror 4*cr2+lt, 4*cr5+gt, 4*cr5+lt
 ; NOVSX-NEXT:    bc 12, 4*cr2+lt, .LBB13_2
 ; NOVSX-NEXT:  # %bb.1: # %entry
@@ -714,8 +714,8 @@ define zeroext i32 @ppcq_to_u32(ppc_fp128 %m) #0 {
 ; NOVSX-NEXT:    nop
 ; NOVSX-NEXT:    mffs f0
 ; NOVSX-NEXT:    mtfsb1 31
-; NOVSX-NEXT:    addi r3, r1, 44
 ; NOVSX-NEXT:    mtfsb0 30
+; NOVSX-NEXT:    addi r3, r1, 44
 ; NOVSX-NEXT:    fadd f1, f2, f1
 ; NOVSX-NEXT:    mtfsf 1, f0
 ; NOVSX-NEXT:    fctiwz f0, f1
@@ -728,8 +728,8 @@ define zeroext i32 @ppcq_to_u32(ppc_fp128 %m) #0 {
 ; NOVSX-NEXT:    addi r1, r1, 48
 ; NOVSX-NEXT:    ld r0, 16(r1)
 ; NOVSX-NEXT:    lwz r12, 8(r1)
-; NOVSX-NEXT:    mtocrf 32, r12
 ; NOVSX-NEXT:    mtlr r0
+; NOVSX-NEXT:    mtocrf 32, r12
 ; NOVSX-NEXT:    blr
 entry:
   %conv = tail call i32 @llvm.experimental.constrained.fptoui.i32.ppcf128(ppc_fp128 %m, metadata !"fpexcept.strict") #0
@@ -831,10 +831,10 @@ define ppc_fp128 @i1_to_ppcq(i1 signext %m) #0 {
 ;
 ; NOVSX-LABEL: i1_to_ppcq:
 ; NOVSX:       # %bb.0: # %entry
-; NOVSX-NEXT:    addi r4, r1, -4
 ; NOVSX-NEXT:    stw r3, -4(r1)
+; NOVSX-NEXT:    addi r3, r1, -4
+; NOVSX-NEXT:    lfiwax f0, 0, r3
 ; NOVSX-NEXT:    addis r3, r2, .LCPI16_0@toc@ha
-; NOVSX-NEXT:    lfiwax f0, 0, r4
 ; NOVSX-NEXT:    lfs f2, .LCPI16_0@toc@l(r3)
 ; NOVSX-NEXT:    fcfid f1, f0
 ; NOVSX-NEXT:    blr
@@ -860,10 +860,10 @@ define ppc_fp128 @u1_to_ppcq(i1 zeroext %m) #0 {
 ;
 ; NOVSX-LABEL: u1_to_ppcq:
 ; NOVSX:       # %bb.0: # %entry
-; NOVSX-NEXT:    addi r4, r1, -4
 ; NOVSX-NEXT:    stw r3, -4(r1)
+; NOVSX-NEXT:    addi r3, r1, -4
+; NOVSX-NEXT:    lfiwax f0, 0, r3
 ; NOVSX-NEXT:    addis r3, r2, .LCPI17_0@toc@ha
-; NOVSX-NEXT:    lfiwax f0, 0, r4
 ; NOVSX-NEXT:    lfs f2, .LCPI17_0@toc@l(r3)
 ; NOVSX-NEXT:    fcfid f1, f0
 ; NOVSX-NEXT:    blr

diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-conv.ll b/llvm/test/CodeGen/PowerPC/fp-strict-conv.ll
@@ -189,9 +189,9 @@ define double @i32_to_d(i32 signext %m) #0 {
 ;
 ; NOVSX-LABEL: i32_to_d:
 ; NOVSX:       # %bb.0: # %entry
-; NOVSX-NEXT:    addi r4, r1, -4
 ; NOVSX-NEXT:    stw r3, -4(r1)
-; NOVSX-NEXT:    lfiwax f0, 0, r4
+; NOVSX-NEXT:    addi r3, r1, -4
+; NOVSX-NEXT:    lfiwax f0, 0, r3
 ; NOVSX-NEXT:    fcfid f1, f0
 ; NOVSX-NEXT:    blr
 entry:
@@ -226,9 +226,9 @@ define double @u32_to_d(i32 zeroext %m) #0 {
 ;
 ; NOVSX-LABEL: u32_to_d:
 ; NOVSX:       # %bb.0: # %entry
-; NOVSX-NEXT:    addi r4, r1, -4
 ; NOVSX-NEXT:    stw r3, -4(r1)
-; NOVSX-NEXT:    lfiwzx f0, 0, r4
+; NOVSX-NEXT:    addi r3, r1, -4
+; NOVSX-NEXT:    lfiwzx f0, 0, r3
 ; NOVSX-NEXT:    fcfidu f1, f0
 ; NOVSX-NEXT:    blr
 entry:
@@ -263,9 +263,9 @@ define float @i32_to_f(i32 signext %m) #0 {
 ;
 ; NOVSX-LABEL: i32_to_f:
 ; NOVSX:       # %bb.0: # %entry
-; NOVSX-NEXT:    addi r4, r1, -4
 ; NOVSX-NEXT:    stw r3, -4(r1)
-; NOVSX-NEXT:    lfiwax f0, 0, r4
+; NOVSX-NEXT:    addi r3, r1, -4
+; NOVSX-NEXT:    lfiwax f0, 0, r3
 ; NOVSX-NEXT:    fcfids f1, f0
 ; NOVSX-NEXT:    blr
 entry:
@@ -300,9 +300,9 @@ define float @u32_to_f(i32 zeroext %m) #0 {
 ;
 ; NOVSX-LABEL: u32_to_f:
 ; NOVSX:       # %bb.0: # %entry
-; NOVSX-NEXT:    addi r4, r1, -4
 ; NOVSX-NEXT:    stw r3, -4(r1)
-; NOVSX-NEXT:    lfiwzx f0, 0, r4
+; NOVSX-NEXT:    addi r3, r1, -4
+; NOVSX-NEXT:    lfiwzx f0, 0, r3
 ; NOVSX-NEXT:    fcfidus f1, f0
 ; NOVSX-NEXT:    blr
 entry:

diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll b/llvm/test/CodeGen/PowerPC/fp-strict-fcmp.ll
diff --git a/llvm/test/CodeGen/PowerPC/fp-strict-round.ll b/llvm/test/CodeGen/PowerPC/fp-strict-round.ll
@@ -215,11 +215,11 @@ define <4 x float> @nearbyint_v4f32(<4 x float> %vf1, <4 x float> %vf2) strictfp
 ; P8-NEXT:    .cfi_offset v31, -16
 ; P8-NEXT:    xxsldwi vs0, v2, v2, 3
 ; P8-NEXT:    li r3, 128
+; P8-NEXT:    xscvspdpn f1, vs0
 ; P8-NEXT:    stxvd2x v29, r1, r3 # 16-byte Folded Spill
 ; P8-NEXT:    li r3, 144
 ; P8-NEXT:    stxvd2x v30, r1, r3 # 16-byte Folded Spill
 ; P8-NEXT:    li r3, 160
-; P8-NEXT:    xscvspdpn f1, vs0
 ; P8-NEXT:    stxvd2x v31, r1, r3 # 16-byte Folded Spill
 ; P8-NEXT:    vmr v31, v2
 ; P8-NEXT:    bl nearbyintf
@@ -243,11 +243,11 @@ define <4 x float> @nearbyint_v4f32(<4 x float> %vf1, <4 x float> %vf2) strictfp
 ; P8-NEXT:    # kill: def $f1 killed $f1 def $vsl1
 ; P8-NEXT:    xxmrghd vs0, v30, vs1
 ; P8-NEXT:    li r3, 160
+; P8-NEXT:    xvcvdpsp v2, vs0
 ; P8-NEXT:    lxvd2x v31, r1, r3 # 16-byte Folded Reload
 ; P8-NEXT:    li r3, 144
 ; P8-NEXT:    lxvd2x v30, r1, r3 # 16-byte Folded Reload
 ; P8-NEXT:    li r3, 128
-; P8-NEXT:    xvcvdpsp v2, vs0
 ; P8-NEXT:    vmrgew v2, v2, v29
 ; P8-NEXT:    lxvd2x v29, r1, r3 # 16-byte Folded Reload
 ; P8-NEXT:    addi r1, r1, 176
@@ -380,14 +380,14 @@ define <4 x double> @fpext_v4f64_v4f32(<4 x float> %vf1) strictfp {
 ; P8-LABEL: fpext_v4f64_v4f32:
 ; P8:       # %bb.0:
 ; P8-NEXT:    xxsldwi vs0, v2, v2, 1
+; P8-NEXT:    xscvspdpn f3, v2
 ; P8-NEXT:    xxsldwi vs1, v2, v2, 3
-; P8-NEXT:    xxswapd vs3, v2
-; P8-NEXT:    xscvspdpn f2, v2
+; P8-NEXT:    xxswapd vs2, v2
 ; P8-NEXT:    xscvspdpn f0, vs0
-; P8-NEXT:    xscvspdpn f1, vs1
-; P8-NEXT:    xscvspdpn f3, vs3
-; P8-NEXT:    xxmrghd v2, vs2, vs0
-; P8-NEXT:    xxmrghd v3, vs3, vs1
+; P8-NEXT:    xxmrghd v2, vs3, vs0
+; P8-NEXT:    xscvspdpn f0, vs1
+; P8-NEXT:    xscvspdpn f1, vs2
+; P8-NEXT:    xxmrghd v3, vs1, vs0
 ; P8-NEXT:    blr
 ;
 ; P9-LABEL: fpext_v4f64_v4f32:

diff --git a/llvm/test/CodeGen/PowerPC/fp-strict.ll b/llvm/test/CodeGen/PowerPC/fp-strict.ll
@@ -90,9 +90,9 @@ define <4 x float> @fadd_v4f32(<4 x float> %vf1, <4 x float> %vf2) #0 {
 ; NOVSX-LABEL: fadd_v4f32:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    addi r3, r1, -32
-; NOVSX-NEXT:    addi r4, r1, -48
 ; NOVSX-NEXT:    stvx v3, 0, r3
-; NOVSX-NEXT:    stvx v2, 0, r4
+; NOVSX-NEXT:    addi r3, r1, -48
+; NOVSX-NEXT:    stvx v2, 0, r3
 ; NOVSX-NEXT:    addi r3, r1, -16
 ; NOVSX-NEXT:    lfs f0, -20(r1)
 ; NOVSX-NEXT:    lfs f1, -36(r1)
@@ -216,9 +216,9 @@ define <4 x float> @fsub_v4f32(<4 x float> %vf1, <4 x float> %vf2) #0 {
 ; NOVSX-LABEL: fsub_v4f32:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    addi r3, r1, -32
-; NOVSX-NEXT:    addi r4, r1, -48
 ; NOVSX-NEXT:    stvx v3, 0, r3
-; NOVSX-NEXT:    stvx v2, 0, r4
+; NOVSX-NEXT:    addi r3, r1, -48
+; NOVSX-NEXT:    stvx v2, 0, r3
 ; NOVSX-NEXT:    addi r3, r1, -16
 ; NOVSX-NEXT:    lfs f0, -20(r1)
 ; NOVSX-NEXT:    lfs f1, -36(r1)
@@ -342,9 +342,9 @@ define <4 x float> @fmul_v4f32(<4 x float> %vf1, <4 x float> %vf2) #0 {
 ; NOVSX-LABEL: fmul_v4f32:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    addi r3, r1, -32
-; NOVSX-NEXT:    addi r4, r1, -48
 ; NOVSX-NEXT:    stvx v3, 0, r3
-; NOVSX-NEXT:    stvx v2, 0, r4
+; NOVSX-NEXT:    addi r3, r1, -48
+; NOVSX-NEXT:    stvx v2, 0, r3
 ; NOVSX-NEXT:    addi r3, r1, -16
 ; NOVSX-NEXT:    lfs f0, -20(r1)
 ; NOVSX-NEXT:    lfs f1, -36(r1)
@@ -468,9 +468,9 @@ define <4 x float> @fdiv_v4f32(<4 x float> %vf1, <4 x float> %vf2) #0 {
 ; NOVSX-LABEL: fdiv_v4f32:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    addi r3, r1, -32
-; NOVSX-NEXT:    addi r4, r1, -48
 ; NOVSX-NEXT:    stvx v3, 0, r3
-; NOVSX-NEXT:    stvx v2, 0, r4
+; NOVSX-NEXT:    addi r3, r1, -48
+; NOVSX-NEXT:    stvx v2, 0, r3
 ; NOVSX-NEXT:    addi r3, r1, -16
 ; NOVSX-NEXT:    lfs f0, -20(r1)
 ; NOVSX-NEXT:    lfs f1, -36(r1)
@@ -649,10 +649,10 @@ define <4 x float> @fmadd_v4f32(<4 x float> %vf0, <4 x float> %vf1, <4 x float>
 ; NOVSX-LABEL: fmadd_v4f32:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    addi r3, r1, -32
-; NOVSX-NEXT:    addi r4, r1, -48
 ; NOVSX-NEXT:    stvx v4, 0, r3
+; NOVSX-NEXT:    addi r3, r1, -48
+; NOVSX-NEXT:    stvx v3, 0, r3
 ; NOVSX-NEXT:    addi r3, r1, -64
-; NOVSX-NEXT:    stvx v3, 0, r4
 ; NOVSX-NEXT:    stvx v2, 0, r3
 ; NOVSX-NEXT:    addi r3, r1, -16
 ; NOVSX-NEXT:    lfs f0, -20(r1)
@@ -912,12 +912,12 @@ define <4 x float> @fmsub_v4f32(<4 x float> %vf0, <4 x float> %vf1, <4 x float>
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    vspltisb v5, -1
 ; NOVSX-NEXT:    addi r3, r1, -48
-; NOVSX-NEXT:    addi r4, r1, -64
-; NOVSX-NEXT:    stvx v3, 0, r3
-; NOVSX-NEXT:    addi r3, r1, -32
-; NOVSX-NEXT:    stvx v2, 0, r4
 ; NOVSX-NEXT:    vslw v5, v5, v5
+; NOVSX-NEXT:    stvx v3, 0, r3
+; NOVSX-NEXT:    addi r3, r1, -64
 ; NOVSX-NEXT:    vsubfp v4, v5, v4
+; NOVSX-NEXT:    stvx v2, 0, r3
+; NOVSX-NEXT:    addi r3, r1, -32
 ; NOVSX-NEXT:    stvx v4, 0, r3
 ; NOVSX-NEXT:    addi r3, r1, -16
 ; NOVSX-NEXT:    lfs f0, -36(r1)
@@ -1184,17 +1184,17 @@ define <4 x float> @fnmadd_v4f32(<4 x float> %vf0, <4 x float> %vf1, <4 x float>
 ; NOVSX-LABEL: fnmadd_v4f32:
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    addi r3, r1, -32
-; NOVSX-NEXT:    addi r4, r1, -48
+; NOVSX-NEXT:    vspltisb v5, -1
 ; NOVSX-NEXT:    stvx v4, 0, r3
+; NOVSX-NEXT:    addi r3, r1, -48
+; NOVSX-NEXT:    stvx v3, 0, r3
 ; NOVSX-NEXT:    addi r3, r1, -64
-; NOVSX-NEXT:    stvx v3, 0, r4
+; NOVSX-NEXT:    vslw v3, v5, v5
 ; NOVSX-NEXT:    stvx v2, 0, r3
-; NOVSX-NEXT:    vspltisb v2, -1
 ; NOVSX-NEXT:    addi r3, r1, -16
 ; NOVSX-NEXT:    lfs f0, -20(r1)
 ; NOVSX-NEXT:    lfs f1, -36(r1)
 ; NOVSX-NEXT:    lfs f2, -52(r1)
-; NOVSX-NEXT:    vslw v2, v2, v2
 ; NOVSX-NEXT:    fmadds f0, f2, f1, f0
 ; NOVSX-NEXT:    lfs f1, -40(r1)
 ; NOVSX-NEXT:    lfs f2, -56(r1)
@@ -1212,8 +1212,8 @@ define <4 x float> @fnmadd_v4f32(<4 x float> %vf0, <4 x float> %vf1, <4 x float>
 ; NOVSX-NEXT:    lfs f0, -32(r1)
 ; NOVSX-NEXT:    fmadds f0, f2, f1, f0
 ; NOVSX-NEXT:    stfs f0, -16(r1)
-; NOVSX-NEXT:    lvx v3, 0, r3
-; NOVSX-NEXT:    vsubfp v2, v2, v3
+; NOVSX-NEXT:    lvx v2, 0, r3
+; NOVSX-NEXT:    vsubfp v2, v3, v2
 ; NOVSX-NEXT:    blr
 ;
 ; SPE-LABEL: fnmadd_v4f32:
@@ -1459,12 +1459,12 @@ define <4 x float> @fnmsub_v4f32(<4 x float> %vf0, <4 x float> %vf1, <4 x float>
 ; NOVSX:       # %bb.0:
 ; NOVSX-NEXT:    vspltisb v5, -1
 ; NOVSX-NEXT:    addi r3, r1, -48
-; NOVSX-NEXT:    addi r4, r1, -64
-; NOVSX-NEXT:    stvx v3, 0, r3
-; NOVSX-NEXT:    addi r3, r1, -32
-; NOVSX-NEXT:    stvx v2, 0, r4
 ; NOVSX-NEXT:    vslw v5, v5, v5
+; NOVSX-NEXT:    stvx v3, 0, r3
+; NOVSX-NEXT:    addi r3, r1, -64
 ; NOVSX-NEXT:    vsubfp v4, v5, v4
+; NOVSX-NEXT:    stvx v2, 0, r3
+; NOVSX-NEXT:    addi r3, r1, -32
 ; NOVSX-NEXT:    stvx v4, 0, r3
 ; NOVSX-NEXT:    addi r3, r1, -16
 ; NOVSX-NEXT:    lfs f0, -36(r1)

diff --git a/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll b/llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll
@@ -49,12 +49,12 @@ entry:
 define i128 @test_neg(ppc_fp128 %x) nounwind  {
 ; PPC64-P8-LABEL: test_neg:
 ; PPC64-P8:       # %bb.0: # %entry
-; PPC64-P8-NEXT:    li 3, 1
 ; PPC64-P8-NEXT:    mffprd 4, 2
-; PPC64-P8-NEXT:    mffprd 5, 1
-; PPC64-P8-NEXT:    rldic 6, 3, 63, 0
-; PPC64-P8-NEXT:    xor 4, 4, 6
-; PPC64-P8-NEXT:    xor 3, 5, 6
+; PPC64-P8-NEXT:    mffprd 3, 1
+; PPC64-P8-NEXT:    li 5, 1
+; PPC64-P8-NEXT:    rldic 5, 5, 63, 0
+; PPC64-P8-NEXT:    xor 3, 3, 5
+; PPC64-P8-NEXT:    xor 4, 4, 5
 ; PPC64-P8-NEXT:    blr
 ;
 ; PPC64-LABEL: test_neg:
@@ -199,13 +199,13 @@ define i128 @test_copysign_const(ppc_fp128 %x) nounwind  {
 ; PPC64-P8-LABEL: test_copysign_const:
 ; PPC64-P8:       # %bb.0: # %entry
 ; PPC64-P8-NEXT:    mffprd 3, 1
-; PPC64-P8-NEXT:    li 4, 16399
 ; PPC64-P8-NEXT:    li 5, 3019
-; PPC64-P8-NEXT:    rldicr 6, 3, 0, 0
-; PPC64-P8-NEXT:    rldic 3, 4, 48, 1
-; PPC64-P8-NEXT:    rldic 4, 5, 52, 0
-; PPC64-P8-NEXT:    or 3, 6, 3
-; PPC64-P8-NEXT:    xor 4, 6, 4
+; PPC64-P8-NEXT:    rldic 5, 5, 52, 0
+; PPC64-P8-NEXT:    rldicr 4, 3, 0, 0
+; PPC64-P8-NEXT:    li 3, 16399
+; PPC64-P8-NEXT:    rldic 3, 3, 48, 1
+; PPC64-P8-NEXT:    or 3, 4, 3
+; PPC64-P8-NEXT:    xor 4, 4, 5
 ; PPC64-P8-NEXT:    blr
 ;
 ; PPC64-LABEL: test_copysign_const:

diff --git a/llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll b/llvm/test/CodeGen/PowerPC/fpscr-intrinsics.ll
@@ -65,9 +65,9 @@ define dso_local void @callmtfsf(i32 zeroext %a) local_unnamed_addr {
 ;
 ; CHECK-AIX32-LABEL: callmtfsf:
 ; CHECK-AIX32:       # %bb.0: # %entry
-; CHECK-AIX32-NEXT:    addi 4, 1, -4
 ; CHECK-AIX32-NEXT:    stw 3, -4(1)
-; CHECK-AIX32-NEXT:    lfiwzx 0, 0, 4
+; CHECK-AIX32-NEXT:    addi 3, 1, -4
+; CHECK-AIX32-NEXT:    lfiwzx 0, 0, 3
 ; CHECK-AIX32-NEXT:    xscvuxddp 0, 0
 ; CHECK-AIX32-NEXT:    mtfsf 7, 0
 ; CHECK-AIX32-NEXT:    blr

diff --git a/llvm/test/CodeGen/PowerPC/frounds.ll b/llvm/test/CodeGen/PowerPC/frounds.ll
@@ -43,10 +43,10 @@ define i32 @foo() {
 ; PPC64LE-NEXT:    mffs 0
 ; PPC64LE-NEXT:    stfd 0, -16(1)
 ; PPC64LE-NEXT:    lwz 3, -16(1)
-; PPC64LE-NEXT:    not 4, 3
-; PPC64LE-NEXT:    clrlwi 3, 3, 30
-; PPC64LE-NEXT:    rlwinm 4, 4, 31, 31, 31
-; PPC64LE-NEXT:    xor 3, 3, 4
+; PPC64LE-NEXT:    clrlwi 4, 3, 30
+; PPC64LE-NEXT:    not 3, 3
+; PPC64LE-NEXT:    rlwinm 3, 3, 31, 31, 31
+; PPC64LE-NEXT:    xor 3, 4, 3
 ; PPC64LE-NEXT:    stw 3, -8(1)
 ; PPC64LE-NEXT:    stw 3, -4(1)
 ; PPC64LE-NEXT:    blr
@@ -55,10 +55,10 @@ define i32 @foo() {
 ; DM:       # %bb.0: # %entry
 ; DM-NEXT:    mffs 0
 ; DM-NEXT:    mffprd 3, 0
-; DM-NEXT:    not 4, 3
-; DM-NEXT:    clrlwi 3, 3, 30
-; DM-NEXT:    rlwinm 4, 4, 31, 31, 31
-; DM-NEXT:    xor 3, 3, 4
+; DM-NEXT:    clrlwi 4, 3, 30
+; DM-NEXT:    not 3, 3
+; DM-NEXT:    rlwinm 3, 3, 31, 31, 31
+; DM-NEXT:    xor 3, 4, 3
 ; DM-NEXT:    stw 3, -8(1)
 ; DM-NEXT:    stw 3, -4(1)
 ; DM-NEXT:    blr

diff --git a/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll b/llvm/test/CodeGen/PowerPC/funnel-shift-rot.ll
@@ -50,27 +50,16 @@ define i64 @rotl_i64_const_shift(i64 %x) {
 ; When first 2 operands match, it's a rotate (by variable amount).
 
 define i16 @rotl_i16(i16 %x, i16 %z) {
-; CHECK32-LABEL: rotl_i16:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    clrlwi 6, 4, 28
-; CHECK32-NEXT:    neg 4, 4
-; CHECK32-NEXT:    clrlwi 5, 3, 16
-; CHECK32-NEXT:    clrlwi 4, 4, 28
-; CHECK32-NEXT:    slw 3, 3, 6
-; CHECK32-NEXT:    srw 4, 5, 4
-; CHECK32-NEXT:    or 3, 3, 4
-; CHECK32-NEXT:    blr
-;
-; CHECK64-LABEL: rotl_i16:
-; CHECK64:       # %bb.0:
-; CHECK64-NEXT:    neg 5, 4
-; CHECK64-NEXT:    clrlwi 6, 3, 16
-; CHECK64-NEXT:    clrlwi 4, 4, 28
-; CHECK64-NEXT:    clrlwi 5, 5, 28
-; CHECK64-NEXT:    slw 3, 3, 4
-; CHECK64-NEXT:    srw 4, 6, 5
-; CHECK64-NEXT:    or 3, 3, 4
-; CHECK64-NEXT:    blr
+; CHECK-LABEL: rotl_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    clrlwi 6, 4, 28
+; CHECK-NEXT:    neg 4, 4
+; CHECK-NEXT:    clrlwi 5, 3, 16
+; CHECK-NEXT:    clrlwi 4, 4, 28
+; CHECK-NEXT:    slw 3, 3, 6
+; CHECK-NEXT:    srw 4, 5, 4
+; CHECK-NEXT:    or 3, 3, 4
+; CHECK-NEXT:    blr
   %f = call i16 @llvm.fshl.i16(i16 %x, i16 %x, i16 %z)
   ret i16 %f
 }
@@ -210,27 +199,16 @@ define i32 @rotr_i32_const_shift(i32 %x) {
 ; When first 2 operands match, it's a rotate (by variable amount).
 
 define i16 @rotr_i16(i16 %x, i16 %z) {
-; CHECK32-LABEL: rotr_i16:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    clrlwi 6, 4, 28
-; CHECK32-NEXT:    neg 4, 4
-; CHECK32-NEXT:    clrlwi 5, 3, 16
-; CHECK32-NEXT:    clrlwi 4, 4, 28
-; CHECK32-NEXT:    srw 5, 5, 6
-; CHECK32-NEXT:    slw 3, 3, 4
-; CHECK32-NEXT:    or 3, 5, 3
-; CHECK32-NEXT:    blr
-;
-; CHECK64-LABEL: rotr_i16:
-; CHECK64:       # %bb.0:
-; CHECK64-NEXT:    neg 5, 4
-; CHECK64-NEXT:    clrlwi 6, 3, 16
-; CHECK64-NEXT:    clrlwi 4, 4, 28
-; CHECK64-NEXT:    clrlwi 5, 5, 28
-; CHECK64-NEXT:    srw 4, 6, 4
-; CHECK64-NEXT:    slw 3, 3, 5
-; CHECK64-NEXT:    or 3, 4, 3
-; CHECK64-NEXT:    blr
+; CHECK-LABEL: rotr_i16:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    clrlwi 6, 4, 28
+; CHECK-NEXT:    neg 4, 4
+; CHECK-NEXT:    clrlwi 5, 3, 16
+; CHECK-NEXT:    clrlwi 4, 4, 28
+; CHECK-NEXT:    srw 5, 5, 6
+; CHECK-NEXT:    slw 3, 3, 4
+; CHECK-NEXT:    or 3, 5, 3
+; CHECK-NEXT:    blr
   %f = call i16 @llvm.fshr.i16(i16 %x, i16 %x, i16 %z)
   ret i16 %f
 }

diff --git a/llvm/test/CodeGen/PowerPC/funnel-shift.ll b/llvm/test/CodeGen/PowerPC/funnel-shift.ll
@@ -19,23 +19,14 @@ declare <4 x i32> @llvm.fshr.v4i32(<4 x i32>, <4 x i32>, <4 x i32>)
 ; General case - all operands can be variables.
 
 define i32 @fshl_i32(i32 %x, i32 %y, i32 %z) {
-; CHECK32-LABEL: fshl_i32:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    clrlwi 5, 5, 27
-; CHECK32-NEXT:    slw 3, 3, 5
-; CHECK32-NEXT:    subfic 5, 5, 32
-; CHECK32-NEXT:    srw 4, 4, 5
-; CHECK32-NEXT:    or 3, 3, 4
-; CHECK32-NEXT:    blr
-;
-; CHECK64-LABEL: fshl_i32:
-; CHECK64:       # %bb.0:
-; CHECK64-NEXT:    clrlwi 5, 5, 27
-; CHECK64-NEXT:    subfic 6, 5, 32
-; CHECK64-NEXT:    slw 3, 3, 5
-; CHECK64-NEXT:    srw 4, 4, 6
-; CHECK64-NEXT:    or 3, 3, 4
-; CHECK64-NEXT:    blr
+; CHECK-LABEL: fshl_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    clrlwi 5, 5, 27
+; CHECK-NEXT:    slw 3, 3, 5
+; CHECK-NEXT:    subfic 5, 5, 32
+; CHECK-NEXT:    srw 4, 4, 5
+; CHECK-NEXT:    or 3, 3, 4
+; CHECK-NEXT:    blr
   %f = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
   ret i32 %f
 }
@@ -89,9 +80,9 @@ define i64 @fshl_i64(i64 %x, i64 %y, i64 %z) {
 ; CHECK64-LABEL: fshl_i64:
 ; CHECK64:       # %bb.0:
 ; CHECK64-NEXT:    clrlwi 5, 5, 26
-; CHECK64-NEXT:    subfic 6, 5, 64
 ; CHECK64-NEXT:    sld 3, 3, 5
-; CHECK64-NEXT:    srd 4, 4, 6
+; CHECK64-NEXT:    subfic 5, 5, 64
+; CHECK64-NEXT:    srd 4, 4, 5
 ; CHECK64-NEXT:    or 3, 3, 4
 ; CHECK64-NEXT:    blr
   %f = call i64 @llvm.fshl.i64(i64 %x, i64 %y, i64 %z)
@@ -213,16 +204,17 @@ define i128 @fshl_i128(i128 %x, i128 %y, i128 %z) nounwind {
 ; CHECK64:       # %bb.0:
 ; CHECK64-NEXT:    andi. 8, 7, 64
 ; CHECK64-NEXT:    clrlwi 7, 7, 26
-; CHECK64-NEXT:    iseleq 5, 6, 5
 ; CHECK64-NEXT:    subfic 8, 7, 64
+; CHECK64-NEXT:    iseleq 5, 6, 5
 ; CHECK64-NEXT:    iseleq 6, 3, 6
 ; CHECK64-NEXT:    iseleq 3, 4, 3
-; CHECK64-NEXT:    srd 4, 5, 8
-; CHECK64-NEXT:    sld 5, 6, 7
+; CHECK64-NEXT:    srd 5, 5, 8
+; CHECK64-NEXT:    sld 9, 6, 7
 ; CHECK64-NEXT:    srd 6, 6, 8
-; CHECK64-NEXT:    sld 7, 3, 7
-; CHECK64-NEXT:    or 3, 5, 4
-; CHECK64-NEXT:    or 4, 7, 6
+; CHECK64-NEXT:    sld 3, 3, 7
+; CHECK64-NEXT:    or 5, 9, 5
+; CHECK64-NEXT:    or 4, 3, 6
+; CHECK64-NEXT:    mr 3, 5
 ; CHECK64-NEXT:    blr
   %f = call i128 @llvm.fshl.i128(i128 %x, i128 %y, i128 %z)
   ret i128 %f
@@ -352,20 +344,20 @@ define i37 @fshl_i37(i37 %x, i37 %y, i37 %z) {
 ;
 ; CHECK64-LABEL: fshl_i37:
 ; CHECK64:       # %bb.0:
-; CHECK64-NEXT:    lis 6, 1771
-; CHECK64-NEXT:    clrldi 7, 5, 27
-; CHECK64-NEXT:    ori 6, 6, 15941
+; CHECK64-NEXT:    lis 7, 1771
+; CHECK64-NEXT:    clrldi 6, 5, 27
 ; CHECK64-NEXT:    sldi 4, 4, 27
-; CHECK64-NEXT:    rldic 6, 6, 32, 5
-; CHECK64-NEXT:    oris 6, 6, 12398
-; CHECK64-NEXT:    ori 6, 6, 46053
-; CHECK64-NEXT:    mulhdu 6, 7, 6
+; CHECK64-NEXT:    ori 7, 7, 15941
+; CHECK64-NEXT:    rldic 7, 7, 32, 5
+; CHECK64-NEXT:    oris 7, 7, 12398
+; CHECK64-NEXT:    ori 7, 7, 46053
+; CHECK64-NEXT:    mulhdu 6, 6, 7
 ; CHECK64-NEXT:    mulli 6, 6, 37
 ; CHECK64-NEXT:    sub 5, 5, 6
 ; CHECK64-NEXT:    clrlwi 5, 5, 26
-; CHECK64-NEXT:    subfic 6, 5, 64
 ; CHECK64-NEXT:    sld 3, 3, 5
-; CHECK64-NEXT:    srd 4, 4, 6
+; CHECK64-NEXT:    subfic 5, 5, 64
+; CHECK64-NEXT:    srd 4, 4, 5
 ; CHECK64-NEXT:    or 3, 3, 4
 ; CHECK64-NEXT:    blr
   %f = call i37 @llvm.fshl.i37(i37 %x, i37 %y, i37 %z)
@@ -448,23 +440,14 @@ define i8 @fshl_i8_const_fold() {
 ; General case - all operands can be variables.
 
 define i32 @fshr_i32(i32 %x, i32 %y, i32 %z) {
-; CHECK32-LABEL: fshr_i32:
-; CHECK32:       # %bb.0:
-; CHECK32-NEXT:    clrlwi 5, 5, 27
-; CHECK32-NEXT:    srw 4, 4, 5
-; CHECK32-NEXT:    subfic 5, 5, 32
-; CHECK32-NEXT:    slw 3, 3, 5
-; CHECK32-NEXT:    or 3, 3, 4
-; CHECK32-NEXT:    blr
-;
-; CHECK64-LABEL: fshr_i32:
-; CHECK64:       # %bb.0:
-; CHECK64-NEXT:    clrlwi 5, 5, 27
-; CHECK64-NEXT:    subfic 6, 5, 32
-; CHECK64-NEXT:    srw 4, 4, 5
-; CHECK64-NEXT:    slw 3, 3, 6
-; CHECK64-NEXT:    or 3, 3, 4
-; CHECK64-NEXT:    blr
+; CHECK-LABEL: fshr_i32:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    clrlwi 5, 5, 27
+; CHECK-NEXT:    srw 4, 4, 5
+; CHECK-NEXT:    subfic 5, 5, 32
+; CHECK-NEXT:    slw 3, 3, 5
+; CHECK-NEXT:    or 3, 3, 4
+; CHECK-NEXT:    blr
   %f = call i32 @llvm.fshr.i32(i32 %x, i32 %y, i32 %z)
   ret i32 %f
 }
@@ -518,9 +501,9 @@ define i64 @fshr_i64(i64 %x, i64 %y, i64 %z) {
 ; CHECK64-LABEL: fshr_i64:
 ; CHECK64:       # %bb.0:
 ; CHECK64-NEXT:    clrlwi 5, 5, 26
-; CHECK64-NEXT:    subfic 6, 5, 64
 ; CHECK64-NEXT:    srd 4, 4, 5
-; CHECK64-NEXT:    sld 3, 3, 6
+; CHECK64-NEXT:    subfic 5, 5, 64
+; CHECK64-NEXT:    sld 3, 3, 5
 ; CHECK64-NEXT:    or 3, 3, 4
 ; CHECK64-NEXT:    blr
   %f = call i64 @llvm.fshr.i64(i64 %x, i64 %y, i64 %z)
@@ -648,21 +631,21 @@ define i37 @fshr_i37(i37 %x, i37 %y, i37 %z) {
 ;
 ; CHECK64-LABEL: fshr_i37:
 ; CHECK64:       # %bb.0:
-; CHECK64-NEXT:    lis 6, 1771
-; CHECK64-NEXT:    clrldi 7, 5, 27
-; CHECK64-NEXT:    ori 6, 6, 15941
+; CHECK64-NEXT:    lis 7, 1771
+; CHECK64-NEXT:    clrldi 6, 5, 27
 ; CHECK64-NEXT:    sldi 4, 4, 27
-; CHECK64-NEXT:    rldic 6, 6, 32, 5
-; CHECK64-NEXT:    oris 6, 6, 12398
-; CHECK64-NEXT:    ori 6, 6, 46053
-; CHECK64-NEXT:    mulhdu 6, 7, 6
+; CHECK64-NEXT:    ori 7, 7, 15941
+; CHECK64-NEXT:    rldic 7, 7, 32, 5
+; CHECK64-NEXT:    oris 7, 7, 12398
+; CHECK64-NEXT:    ori 7, 7, 46053
+; CHECK64-NEXT:    mulhdu 6, 6, 7
 ; CHECK64-NEXT:    mulli 6, 6, 37
 ; CHECK64-NEXT:    sub 5, 5, 6
 ; CHECK64-NEXT:    addi 5, 5, 27
 ; CHECK64-NEXT:    clrlwi 5, 5, 26
-; CHECK64-NEXT:    subfic 6, 5, 64
 ; CHECK64-NEXT:    srd 4, 4, 5
-; CHECK64-NEXT:    sld 3, 3, 6
+; CHECK64-NEXT:    subfic 5, 5, 64
+; CHECK64-NEXT:    sld 3, 3, 5
 ; CHECK64-NEXT:    or 3, 3, 4
 ; CHECK64-NEXT:    blr
   %f = call i37 @llvm.fshr.i37(i37 %x, i37 %y, i37 %z)

diff --git a/llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll b/llvm/test/CodeGen/PowerPC/handle-f16-storage-type.ll
@@ -641,8 +641,8 @@ define <4 x float> @test_extend32_vec4(ptr %p) #0 {
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    stdu r1, -112(r1)
-; P8-NEXT:    std r0, 128(r1)
 ; P8-NEXT:    li r4, 48
+; P8-NEXT:    std r0, 128(r1)
 ; P8-NEXT:    std r30, 96(r1) # 8-byte Folded Spill
 ; P8-NEXT:    mr r30, r3
 ; P8-NEXT:    lhz r3, 6(r3)
@@ -665,19 +665,19 @@ define <4 x float> @test_extend32_vec4(ptr %p) #0 {
 ; P8-NEXT:    xxlor vs61, f1, f1
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
-; P8-NEXT:    # kill: def $f1 killed $f1 def $vsl1
-; P8-NEXT:    xxmrghd vs0, vs63, vs62
 ; P8-NEXT:    li r3, 80
+; P8-NEXT:    # kill: def $f1 killed $f1 def $vsl1
+; P8-NEXT:    xxmrghd vs0, vs61, vs1
+; P8-NEXT:    xxmrghd vs1, vs63, vs62
 ; P8-NEXT:    ld r30, 96(r1) # 8-byte Folded Reload
-; P8-NEXT:    xxmrghd vs1, vs61, vs1
 ; P8-NEXT:    lxvd2x vs63, r1, r3 # 16-byte Folded Reload
 ; P8-NEXT:    li r3, 64
+; P8-NEXT:    xvcvdpsp vs34, vs0
+; P8-NEXT:    xvcvdpsp vs35, vs1
 ; P8-NEXT:    lxvd2x vs62, r1, r3 # 16-byte Folded Reload
 ; P8-NEXT:    li r3, 48
-; P8-NEXT:    xvcvdpsp vs34, vs0
 ; P8-NEXT:    lxvd2x vs61, r1, r3 # 16-byte Folded Reload
-; P8-NEXT:    xvcvdpsp vs35, vs1
-; P8-NEXT:    vmrgew v2, v2, v3
+; P8-NEXT:    vmrgew v2, v3, v2
 ; P8-NEXT:    addi r1, r1, 112
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0
@@ -750,8 +750,8 @@ define <4 x double> @test_extend64_vec4(ptr %p) #0 {
 ; P8:       # %bb.0:
 ; P8-NEXT:    mflr r0
 ; P8-NEXT:    stdu r1, -112(r1)
-; P8-NEXT:    std r0, 128(r1)
 ; P8-NEXT:    li r4, 48
+; P8-NEXT:    std r0, 128(r1)
 ; P8-NEXT:    std r30, 96(r1) # 8-byte Folded Spill
 ; P8-NEXT:    mr r30, r3
 ; P8-NEXT:    lhz r3, 6(r3)
@@ -1005,22 +1005,22 @@ define void @test_trunc64_vec4(<4 x double> %a, ptr %p) #0 {
 ; P8-NEXT:    stdu r1, -128(r1)
 ; P8-NEXT:    li r3, 48
 ; P8-NEXT:    std r0, 144(r1)
-; P8-NEXT:    xxswapd vs1, vs34
 ; P8-NEXT:    std r27, 88(r1) # 8-byte Folded Spill
+; P8-NEXT:    xxswapd vs1, vs34
 ; P8-NEXT:    std r28, 96(r1) # 8-byte Folded Spill
 ; P8-NEXT:    std r29, 104(r1) # 8-byte Folded Spill
 ; P8-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
-; P8-NEXT:    stxvd2x vs62, r1, r3 # 16-byte Folded Spill
-; P8-NEXT:    li r3, 64
 ; P8-NEXT:    std r30, 112(r1) # 8-byte Folded Spill
 ; P8-NEXT:    mr r30, r7
+; P8-NEXT:    stxvd2x vs62, r1, r3 # 16-byte Folded Spill
+; P8-NEXT:    li r3, 64
 ; P8-NEXT:    vmr v30, v2
 ; P8-NEXT:    stxvd2x vs63, r1, r3 # 16-byte Folded Spill
 ; P8-NEXT:    vmr v31, v3
 ; P8-NEXT:    bl __truncdfhf2
 ; P8-NEXT:    nop
-; P8-NEXT:    xxswapd vs1, vs63
 ; P8-NEXT:    mr r29, r3
+; P8-NEXT:    xxswapd vs1, vs63
 ; P8-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; P8-NEXT:    bl __truncdfhf2
 ; P8-NEXT:    nop
@@ -1230,14 +1230,15 @@ define half @PR40273(half) #0 {
 ; P8-NEXT:    clrldi r3, r3, 48
 ; P8-NEXT:    bl __gnu_h2f_ieee
 ; P8-NEXT:    nop
-; P8-NEXT:    xxlxor f0, f0, f0
-; P8-NEXT:    fcmpu cr0, f1, f0
+; P8-NEXT:    fmr f0, f1
+; P8-NEXT:    xxlxor f1, f1, f1
+; P8-NEXT:    fcmpu cr0, f0, f1
 ; P8-NEXT:    beq cr0, .LBB20_2
 ; P8-NEXT:  # %bb.1:
 ; P8-NEXT:    vspltisw v2, 1
-; P8-NEXT:    xvcvsxwdp vs0, vs34
+; P8-NEXT:    xvcvsxwdp vs1, vs34
 ; P8-NEXT:  .LBB20_2:
-; P8-NEXT:    fmr f1, f0
+; P8-NEXT:    # kill: def $f1 killed $f1 killed $vsl1
 ; P8-NEXT:    addi r1, r1, 32
 ; P8-NEXT:    ld r0, 16(r1)
 ; P8-NEXT:    mtlr r0

diff --git a/llvm/test/CodeGen/PowerPC/huge-frame-call.ll b/llvm/test/CodeGen/PowerPC/huge-frame-call.ll
@@ -28,14 +28,14 @@ define dso_local signext i32 @main() nounwind {
 ; CHECK-LE-NEXT:    bl pluto
 ; CHECK-LE-NEXT:    nop
 ; CHECK-LE-NEXT:    addis 3, 2, global.1@toc@ha
-; CHECK-LE-NEXT:    li 4, 0
+; CHECK-LE-NEXT:    li 4, 257
 ; CHECK-LE-NEXT:    li 7, 0
 ; CHECK-LE-NEXT:    li 8, 0
 ; CHECK-LE-NEXT:    li 9, 0
 ; CHECK-LE-NEXT:    addi 5, 3, global.1@toc@l
-; CHECK-LE-NEXT:    ori 6, 4, 32768
+; CHECK-LE-NEXT:    li 3, 0
+; CHECK-LE-NEXT:    ori 6, 3, 32768
 ; CHECK-LE-NEXT:    li 3, 6
-; CHECK-LE-NEXT:    li 4, 257
 ; CHECK-LE-NEXT:    bl snork
 ; CHECK-LE-NEXT:    nop
 ; CHECK-LE-NEXT:    mr 30, 3

diff --git a/llvm/test/CodeGen/PowerPC/huge-frame-size.ll b/llvm/test/CodeGen/PowerPC/huge-frame-size.ll
@@ -20,13 +20,13 @@ define void @foo(i8 %x) {
 ; CHECK-LE-NEXT:    stdux 1, 1, 0
 ; CHECK-LE-NEXT:    .cfi_def_cfa_offset 32
 ; CHECK-LE-NEXT:    li 4, 1
-; CHECK-LE-NEXT:    li 5, -1
-; CHECK-LE-NEXT:    addi 6, 1, 32
+; CHECK-LE-NEXT:    addi 5, 1, 32
 ; CHECK-LE-NEXT:    stb 3, 32(1)
 ; CHECK-LE-NEXT:    rldic 4, 4, 31, 32
-; CHECK-LE-NEXT:    rldic 5, 5, 0, 32
-; CHECK-LE-NEXT:    stbx 3, 6, 4
-; CHECK-LE-NEXT:    stbx 3, 6, 5
+; CHECK-LE-NEXT:    stbx 3, 5, 4
+; CHECK-LE-NEXT:    li 4, -1
+; CHECK-LE-NEXT:    rldic 4, 4, 0, 32
+; CHECK-LE-NEXT:    stbx 3, 5, 4
 ; CHECK-LE-NEXT:    ld 1, 0(1)
 ; CHECK-LE-NEXT:    blr
 ;

diff --git a/llvm/test/CodeGen/PowerPC/int128_ldst.ll b/llvm/test/CodeGen/PowerPC/int128_ldst.ll
diff --git a/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll b/llvm/test/CodeGen/PowerPC/legalize-vaarg.ll
@@ -25,15 +25,15 @@ define <8 x i32> @test_large_vec_vaarg(i32 %n, ...) {
 ; LE-NEXT:    rldicr 3, 3, 0, 59
 ; LE-NEXT:    addi 4, 3, 16
 ; LE-NEXT:    std 4, -8(1)
-; LE-NEXT:    ld 4, -8(1)
 ; LE-NEXT:    lxvd2x 0, 0, 3
-; LE-NEXT:    addi 4, 4, 15
-; LE-NEXT:    rldicr 4, 4, 0, 59
+; LE-NEXT:    ld 3, -8(1)
+; LE-NEXT:    addi 3, 3, 15
+; LE-NEXT:    rldicr 3, 3, 0, 59
+; LE-NEXT:    addi 4, 3, 16
+; LE-NEXT:    std 4, -8(1)
 ; LE-NEXT:    xxswapd 34, 0
-; LE-NEXT:    addi 5, 4, 16
-; LE-NEXT:    std 5, -8(1)
-; LE-NEXT:    lxvd2x 1, 0, 4
-; LE-NEXT:    xxswapd 35, 1
+; LE-NEXT:    lxvd2x 0, 0, 3
+; LE-NEXT:    xxswapd 35, 0
 ; LE-NEXT:    blr
   %args = alloca ptr, align 4
   %x = va_arg ptr %args, <8 x i32>

diff --git a/llvm/test/CodeGen/PowerPC/licm-remat.ll b/llvm/test/CodeGen/PowerPC/licm-remat.ll
@@ -20,8 +20,8 @@ declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture reado
 define linkonce_odr void @ZN6snappyDecompressor_(ptr %this, ptr %writer) {
 ; CHECK-LABEL: ZN6snappyDecompressor_:
 ; CHECK:       # %bb.0: # %entry
-; CHECK:       addis 3, 2, .L__ModuleStringPool@toc@ha
-; CHECK:       addi 25, 3, .L__ModuleStringPool@toc@l
+; CHECK:       addis 4, 2, .L__ModuleStringPool@toc@ha
+; CHECK:       addi 25, 4, .L__ModuleStringPool@toc@l
 ; CHECK:       .LBB0_2: # %for.cond
 ; CHECK-NOT:   addis {{[0-9]+}}, 2, .L__ModuleStringPool@toc@ha
 ; CHECK:       bctrl

diff --git a/llvm/test/CodeGen/PowerPC/licm-tocReg.ll b/llvm/test/CodeGen/PowerPC/licm-tocReg.ll
@@ -67,35 +67,34 @@
 define signext i32 @test(ptr nocapture %FP) local_unnamed_addr #0 {
 ; CHECKLX-LABEL: test:
 ; CHECKLX:       # %bb.0: # %entry
-; CHECKLX-NEXT:    addis 4, 2, .LC0@toc@ha
-; CHECKLX-NEXT:    addis 5, 2, .LC1@toc@ha
 ; CHECKLX-NEXT:    mr 12, 3
-; CHECKLX-NEXT:    ld 4, .LC0@toc@l(4)
-; CHECKLX-NEXT:    ld 5, .LC1@toc@l(5)
-; CHECKLX-NEXT:    lwz 6, 0(4)
-; CHECKLX-NEXT:    lwz 7, 0(5)
-; CHECKLX-NEXT:    cmpw 6, 7
-; CHECKLX-NEXT:    lwz 6, 0(4)
-; CHECKLX-NEXT:    bgt 0, .LBB0_2
+; CHECKLX-NEXT:    addis 3, 2, .LC0@toc@ha
+; CHECKLX-NEXT:    addis 4, 2, .LC1@toc@ha
+; CHECKLX-NEXT:    ld 3, .LC0@toc@l(3)
+; CHECKLX-NEXT:    ld 5, .LC1@toc@l(4)
+; CHECKLX-NEXT:    lwz 6, 0(3)
 ; CHECKLX-NEXT:    .p2align 5
 ; CHECKLX-NEXT:  .LBB0_1: # %if.end
 ; CHECKLX-NEXT:    #
-; CHECKLX-NEXT:    addi 3, 6, 1
-; CHECKLX-NEXT:    stw 3, 0(4)
-; CHECKLX-NEXT:    lwz 3, 0(4)
-; CHECKLX-NEXT:    lwz 6, 0(5)
-; CHECKLX-NEXT:    cmpw 3, 6
-; CHECKLX-NEXT:    lwz 6, 0(4)
-; CHECKLX-NEXT:    ble 0, .LBB0_1
-; CHECKLX-NEXT:  .LBB0_2: # %if.then
+; CHECKLX-NEXT:    lwz 7, 0(5)
+; CHECKLX-NEXT:    lwz 4, 0(3)
+; CHECKLX-NEXT:    cmpw 6, 7
+; CHECKLX-NEXT:    bgt 0, .LBB0_3
+; CHECKLX-NEXT:  # %bb.2: # %if.end
+; CHECKLX-NEXT:    #
+; CHECKLX-NEXT:    addi 4, 4, 1
+; CHECKLX-NEXT:    stw 4, 0(3)
+; CHECKLX-NEXT:    lwz 6, 0(3)
+; CHECKLX-NEXT:    b .LBB0_1
+; CHECKLX-NEXT:  .LBB0_3: # %if.then
 ; CHECKLX-NEXT:    mflr 0
 ; CHECKLX-NEXT:    stdu 1, -32(1)
 ; CHECKLX-NEXT:    std 2, 24(1)
 ; CHECKLX-NEXT:    std 0, 48(1)
 ; CHECKLX-NEXT:    .cfi_def_cfa_offset 32
 ; CHECKLX-NEXT:    .cfi_offset lr, 16
-; CHECKLX-NEXT:    extsw 3, 6
 ; CHECKLX-NEXT:    mtctr 12
+; CHECKLX-NEXT:    extsw 3, 4
 ; CHECKLX-NEXT:    bctrl
 ; CHECKLX-NEXT:    ld 2, 24(1)
 ; CHECKLX-NEXT:    addi 1, 1, 32

diff --git a/llvm/test/CodeGen/PowerPC/load-and-splat.ll b/llvm/test/CodeGen/PowerPC/load-and-splat.ll
@@ -222,16 +222,16 @@ define dso_local void @test4(ptr nocapture %c, ptr nocapture readonly %a) local_
 ;
 ; P8-AIX32-LABEL: test4:
 ; P8-AIX32:       # %bb.0: # %entry
-; P8-AIX32-NEXT:    lwz r5, L..C0(r2) # %const.0
-; P8-AIX32-NEXT:    lwz r6, 28(r4)
-; P8-AIX32-NEXT:    lwz r4, 24(r4)
-; P8-AIX32-NEXT:    stw r6, -16(r1)
-; P8-AIX32-NEXT:    stw r4, -32(r1)
+; P8-AIX32-NEXT:    lwz r5, 24(r4)
+; P8-AIX32-NEXT:    lwz r4, 28(r4)
+; P8-AIX32-NEXT:    stw r4, -16(r1)
+; P8-AIX32-NEXT:    lwz r4, L..C0(r2) # %const.0
+; P8-AIX32-NEXT:    stw r5, -32(r1)
+; P8-AIX32-NEXT:    lxvw4x v2, 0, r4
 ; P8-AIX32-NEXT:    addi r4, r1, -16
-; P8-AIX32-NEXT:    lxvw4x v2, 0, r5
-; P8-AIX32-NEXT:    addi r5, r1, -32
 ; P8-AIX32-NEXT:    lxvw4x v3, 0, r4
-; P8-AIX32-NEXT:    lxvw4x v4, 0, r5
+; P8-AIX32-NEXT:    addi r4, r1, -32
+; P8-AIX32-NEXT:    lxvw4x v4, 0, r4
 ; P8-AIX32-NEXT:    vperm v2, v4, v3, v2
 ; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
 ; P8-AIX32-NEXT:    blr
@@ -299,16 +299,16 @@ define void @test5(ptr %a, ptr %in) {
 ;
 ; P8-AIX32-LABEL: test5:
 ; P8-AIX32:       # %bb.0: # %entry
-; P8-AIX32-NEXT:    lwz r5, L..C1(r2) # %const.0
 ; P8-AIX32-NEXT:    lwz r4, 0(r4)
+; P8-AIX32-NEXT:    srawi r5, r4, 31
 ; P8-AIX32-NEXT:    stw r4, -16(r1)
-; P8-AIX32-NEXT:    srawi r4, r4, 31
-; P8-AIX32-NEXT:    stw r4, -32(r1)
-; P8-AIX32-NEXT:    lxvw4x v2, 0, r5
+; P8-AIX32-NEXT:    lwz r4, L..C1(r2) # %const.0
+; P8-AIX32-NEXT:    stw r5, -32(r1)
+; P8-AIX32-NEXT:    lxvw4x v2, 0, r4
 ; P8-AIX32-NEXT:    addi r4, r1, -16
-; P8-AIX32-NEXT:    addi r5, r1, -32
 ; P8-AIX32-NEXT:    lxvw4x v3, 0, r4
-; P8-AIX32-NEXT:    lxvw4x v4, 0, r5
+; P8-AIX32-NEXT:    addi r4, r1, -32
+; P8-AIX32-NEXT:    lxvw4x v4, 0, r4
 ; P8-AIX32-NEXT:    vperm v2, v4, v3, v2
 ; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
 ; P8-AIX32-NEXT:    blr
@@ -376,16 +376,16 @@ define void @test6(ptr %a, ptr %in) {
 ;
 ; P8-AIX32-LABEL: test6:
 ; P8-AIX32:       # %bb.0: # %entry
-; P8-AIX32-NEXT:    lwz r6, L..C2(r2) # %const.0
 ; P8-AIX32-NEXT:    lwz r4, 0(r4)
 ; P8-AIX32-NEXT:    li r5, 0
 ; P8-AIX32-NEXT:    stw r5, -32(r1)
-; P8-AIX32-NEXT:    addi r5, r1, -16
 ; P8-AIX32-NEXT:    stw r4, -16(r1)
+; P8-AIX32-NEXT:    lwz r4, L..C2(r2) # %const.0
+; P8-AIX32-NEXT:    lxvw4x v2, 0, r4
 ; P8-AIX32-NEXT:    addi r4, r1, -32
-; P8-AIX32-NEXT:    lxvw4x v2, 0, r6
 ; P8-AIX32-NEXT:    lxvw4x v3, 0, r4
-; P8-AIX32-NEXT:    lxvw4x v4, 0, r5
+; P8-AIX32-NEXT:    addi r4, r1, -16
+; P8-AIX32-NEXT:    lxvw4x v4, 0, r4
 ; P8-AIX32-NEXT:    vperm v2, v3, v4, v2
 ; P8-AIX32-NEXT:    stxvw4x v2, 0, r3
 ; P8-AIX32-NEXT:    blr
@@ -823,12 +823,12 @@ define <16 x i8> @unadjusted_lxvdsx(ptr %s, ptr %t) {
 ; P8-AIX32:       # %bb.0: # %entry
 ; P8-AIX32-NEXT:    lwz r4, 4(r3)
 ; P8-AIX32-NEXT:    stw r4, -16(r1)
-; P8-AIX32-NEXT:    addi r4, r1, -32
 ; P8-AIX32-NEXT:    lwz r3, 0(r3)
 ; P8-AIX32-NEXT:    stw r3, -32(r1)
 ; P8-AIX32-NEXT:    addi r3, r1, -16
 ; P8-AIX32-NEXT:    lxvw4x vs0, 0, r3
-; P8-AIX32-NEXT:    lxvw4x vs1, 0, r4
+; P8-AIX32-NEXT:    addi r3, r1, -32
+; P8-AIX32-NEXT:    lxvw4x vs1, 0, r3
 ; P8-AIX32-NEXT:    xxmrghw vs0, vs1, vs0
 ; P8-AIX32-NEXT:    xxmrghd v2, vs0, vs0
 ; P8-AIX32-NEXT:    blr
@@ -1250,11 +1250,11 @@ define <2 x double> @test_v2f64_multiple_use(ptr nocapture readonly %a, ptr noca
 ; P8-NEXT:    lfs f0, 0(r3)
 ; P8-NEXT:    lfd f1, 0(r4)
 ; P8-NEXT:    xsadddp f1, f1, f0
-; P8-NEXT:    xxspltd v2, vs0, 0
 ; P8-NEXT:    stfd f1, 0(r4)
 ; P8-NEXT:    lfd f1, 0(r5)
-; P8-NEXT:    xsadddp f1, f1, f0
-; P8-NEXT:    stfd f1, 0(r5)
+; P8-NEXT:    xxspltd v2, vs0, 0
+; P8-NEXT:    xsadddp f0, f1, f0
+; P8-NEXT:    stfd f0, 0(r5)
 ; P8-NEXT:    blr
 ;
 ; P7-LABEL: test_v2f64_multiple_use:
@@ -1286,11 +1286,11 @@ define <2 x double> @test_v2f64_multiple_use(ptr nocapture readonly %a, ptr noca
 ; P8-AIX32-NEXT:    lfs f0, 0(r3)
 ; P8-AIX32-NEXT:    lfd f1, 0(r4)
 ; P8-AIX32-NEXT:    xsadddp f1, f1, f0
-; P8-AIX32-NEXT:    xxmrghd v2, vs0, vs0
 ; P8-AIX32-NEXT:    stfd f1, 0(r4)
 ; P8-AIX32-NEXT:    lfd f1, 0(r5)
-; P8-AIX32-NEXT:    xsadddp f1, f1, f0
-; P8-AIX32-NEXT:    stfd f1, 0(r5)
+; P8-AIX32-NEXT:    xxmrghd v2, vs0, vs0
+; P8-AIX32-NEXT:    xsadddp f0, f1, f0
+; P8-AIX32-NEXT:    stfd f0, 0(r5)
 ; P8-AIX32-NEXT:    blr
 ;
 ; P7-AIX32-LABEL: test_v2f64_multiple_use:

diff --git a/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll b/llvm/test/CodeGen/PowerPC/load-shuffle-and-shuffle-store.ll
@@ -70,12 +70,12 @@ define <2 x i64> @load_swap01(ptr %vp1, ptr %vp2) {
 define <4 x i32> @load_swap10(ptr %vp1, ptr %vp2) {
 ; CHECK-P8-LABEL: load_swap10:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI2_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x vs1, 0, r4
+; CHECK-P8-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
+; CHECK-P8-NEXT:    addi r3, r3, .LCPI2_0@toc@l
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxswapd v3, vs1
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
@@ -86,10 +86,10 @@ define <4 x i32> @load_swap10(ptr %vp1, ptr %vp2) {
 ;
 ; CHECK-P8-BE-LABEL: load_swap10:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r4, r2, .LCPI2_0@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
-; CHECK-P8-BE-NEXT:    addi r4, r4, .LCPI2_0@toc@l
-; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r4
+; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI2_0@toc@ha
+; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI2_0@toc@l
+; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
@@ -110,12 +110,12 @@ define <4 x i32> @load_swap10(ptr %vp1, ptr %vp2) {
 define <4 x i32> @load_swap11(ptr %vp1, ptr %vp2) {
 ; CHECK-P8-LABEL: load_swap11:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
+; CHECK-P8-NEXT:    addis r3, r2, .LCPI3_0@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI3_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x vs1, 0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxswapd v3, vs1
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
@@ -150,12 +150,12 @@ define <4 x i32> @load_swap11(ptr %vp1, ptr %vp2) {
 define <8 x i16> @load_swap20(ptr %vp1, ptr %vp2){
 ; CHECK-P8-LABEL: load_swap20:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI4_0@toc@ha
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI4_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x vs1, 0, r4
+; CHECK-P8-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
+; CHECK-P8-NEXT:    addi r3, r3, .LCPI4_0@toc@l
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxswapd v3, vs1
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
@@ -166,10 +166,10 @@ define <8 x i16> @load_swap20(ptr %vp1, ptr %vp2){
 ;
 ; CHECK-P8-BE-LABEL: load_swap20:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r4, r2, .LCPI4_0@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
-; CHECK-P8-BE-NEXT:    addi r4, r4, .LCPI4_0@toc@l
-; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r4
+; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI4_0@toc@ha
+; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI4_0@toc@l
+; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
@@ -190,12 +190,12 @@ define <8 x i16> @load_swap20(ptr %vp1, ptr %vp2){
 define <8 x i16> @load_swap21(ptr %vp1, ptr %vp2){
 ; CHECK-P8-LABEL: load_swap21:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
+; CHECK-P8-NEXT:    addis r3, r2, .LCPI5_0@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI5_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x vs1, 0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxswapd v3, vs1
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
@@ -230,12 +230,12 @@ define <8 x i16> @load_swap21(ptr %vp1, ptr %vp2){
 define <16 x i8> @load_swap30(ptr %vp1, ptr %vp2){
 ; CHECK-P8-LABEL: load_swap30:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI6_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x vs1, 0, r4
+; CHECK-P8-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
+; CHECK-P8-NEXT:    addi r3, r3, .LCPI6_0@toc@l
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxswapd v3, vs1
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
@@ -246,10 +246,10 @@ define <16 x i8> @load_swap30(ptr %vp1, ptr %vp2){
 ;
 ; CHECK-P8-BE-LABEL: load_swap30:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r4, r2, .LCPI6_0@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
-; CHECK-P8-BE-NEXT:    addi r4, r4, .LCPI6_0@toc@l
-; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r4
+; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI6_0@toc@ha
+; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI6_0@toc@l
+; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
@@ -267,12 +267,12 @@ define <16 x i8> @load_swap30(ptr %vp1, ptr %vp2){
 define <16 x i8> @load_swap31(ptr %vp1, ptr %vp2){
 ; CHECK-P8-LABEL: load_swap31:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
+; CHECK-P8-NEXT:    addis r3, r2, .LCPI7_0@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI7_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x vs1, 0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxswapd v3, vs1
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
@@ -332,12 +332,12 @@ define <2 x double> @load_swap40(ptr %vp1, ptr %vp2) {
 define <4 x float> @load_swap50(ptr %vp1, ptr %vp2) {
 ; CHECK-P8-LABEL: load_swap50:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r4, r2, .LCPI9_0@toc@ha
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
-; CHECK-P8-NEXT:    addi r4, r4, .LCPI9_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x vs1, 0, r4
+; CHECK-P8-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
+; CHECK-P8-NEXT:    addi r3, r3, .LCPI9_0@toc@l
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxswapd v3, vs1
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;
@@ -348,10 +348,10 @@ define <4 x float> @load_swap50(ptr %vp1, ptr %vp2) {
 ;
 ; CHECK-P8-BE-LABEL: load_swap50:
 ; CHECK-P8-BE:       # %bb.0:
-; CHECK-P8-BE-NEXT:    addis r4, r2, .LCPI9_0@toc@ha
 ; CHECK-P8-BE-NEXT:    lxvw4x v2, 0, r3
-; CHECK-P8-BE-NEXT:    addi r4, r4, .LCPI9_0@toc@l
-; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r4
+; CHECK-P8-BE-NEXT:    addis r3, r2, .LCPI9_0@toc@ha
+; CHECK-P8-BE-NEXT:    addi r3, r3, .LCPI9_0@toc@l
+; CHECK-P8-BE-NEXT:    lxvw4x v3, 0, r3
 ; CHECK-P8-BE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-BE-NEXT:    blr
 ;
@@ -372,12 +372,12 @@ define <4 x float> @load_swap50(ptr %vp1, ptr %vp2) {
 define <4 x float> @load_swap51(ptr %vp1, ptr %vp2) {
 ; CHECK-P8-LABEL: load_swap51:
 ; CHECK-P8:       # %bb.0:
-; CHECK-P8-NEXT:    addis r3, r2, .LCPI10_0@toc@ha
 ; CHECK-P8-NEXT:    lxvd2x vs0, 0, r4
+; CHECK-P8-NEXT:    addis r3, r2, .LCPI10_0@toc@ha
 ; CHECK-P8-NEXT:    addi r3, r3, .LCPI10_0@toc@l
-; CHECK-P8-NEXT:    lxvd2x vs1, 0, r3
 ; CHECK-P8-NEXT:    xxswapd v2, vs0
-; CHECK-P8-NEXT:    xxswapd v3, vs1
+; CHECK-P8-NEXT:    lxvd2x vs0, 0, r3
+; CHECK-P8-NEXT:    xxswapd v3, vs0
 ; CHECK-P8-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-P8-NEXT:    blr
 ;

diff --git a/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll b/llvm/test/CodeGen/PowerPC/memCmpUsedInZeroEqualityComparison.ll
@@ -40,10 +40,10 @@ define signext i32 @zeroEqualityTest01(ptr %x, ptr %y) {
 ; CHECK-NEXT:    cmpld 5, 6
 ; CHECK-NEXT:    bne 0, .LBB1_2
 ; CHECK-NEXT:  # %bb.1: # %loadbb1
-; CHECK-NEXT:    ld 3, 8(3)
+; CHECK-NEXT:    ld 5, 8(3)
 ; CHECK-NEXT:    ld 4, 8(4)
-; CHECK-NEXT:    cmpld 3, 4
 ; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    cmpld 5, 4
 ; CHECK-NEXT:    beqlr 0
 ; CHECK-NEXT:  .LBB1_2: # %res_block
 ; CHECK-NEXT:    li 3, 1
@@ -68,10 +68,10 @@ define signext i32 @zeroEqualityTest03(ptr %x, ptr %y) {
 ; CHECK-NEXT:    cmplw 5, 6
 ; CHECK-NEXT:    bne 0, .LBB2_3
 ; CHECK-NEXT:  # %bb.2: # %loadbb2
-; CHECK-NEXT:    lbz 3, 6(3)
+; CHECK-NEXT:    lbz 5, 6(3)
 ; CHECK-NEXT:    lbz 4, 6(4)
-; CHECK-NEXT:    cmplw 3, 4
 ; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    cmplw 5, 4
 ; CHECK-NEXT:    beqlr 0
 ; CHECK-NEXT:  .LBB2_3: # %res_block
 ; CHECK-NEXT:    li 3, 1
@@ -121,18 +121,18 @@ define signext i32 @equalityFoldTwoConstants() {
 define signext i32 @equalityFoldOneConstant(ptr %X) {
 ; CHECK-LABEL: equalityFoldOneConstant:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    ld 4, 0(3)
 ; CHECK-NEXT:    li 5, 1
+; CHECK-NEXT:    ld 4, 0(3)
 ; CHECK-NEXT:    rldic 5, 5, 32, 31
 ; CHECK-NEXT:    cmpld 4, 5
 ; CHECK-NEXT:    bne 0, .LBB6_2
 ; CHECK-NEXT:  # %bb.1: # %loadbb1
-; CHECK-NEXT:    lis 4, -32768
-; CHECK-NEXT:    ld 3, 8(3)
-; CHECK-NEXT:    ori 4, 4, 1
-; CHECK-NEXT:    rldic 4, 4, 1, 30
-; CHECK-NEXT:    cmpld 3, 4
+; CHECK-NEXT:    lis 5, -32768
+; CHECK-NEXT:    ld 4, 8(3)
 ; CHECK-NEXT:    li 3, 0
+; CHECK-NEXT:    ori 5, 5, 1
+; CHECK-NEXT:    rldic 5, 5, 1, 30
+; CHECK-NEXT:    cmpld 4, 5
 ; CHECK-NEXT:    beq 0, .LBB6_3
 ; CHECK-NEXT:  .LBB6_2: # %res_block
 ; CHECK-NEXT:    li 3, 1

diff --git a/llvm/test/CodeGen/PowerPC/memcmp.ll b/llvm/test/CodeGen/PowerPC/memcmp.ll
@@ -10,9 +10,9 @@ define signext i32 @memcmp8(ptr nocapture readonly %buffer1, ptr nocapture reado
 ; CHECK-NEXT:    subfe 5, 4, 4
 ; CHECK-NEXT:    subc 4, 3, 4
 ; CHECK-NEXT:    subfe 3, 3, 3
-; CHECK-NEXT:    neg 4, 5
+; CHECK-NEXT:    neg 5, 5
 ; CHECK-NEXT:    neg 3, 3
-; CHECK-NEXT:    sub 3, 4, 3
+; CHECK-NEXT:    sub 3, 5, 3
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
   %call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 8)
@@ -26,9 +26,9 @@ define signext i32 @memcmp4(ptr nocapture readonly %buffer1, ptr nocapture reado
 ; CHECK-NEXT:    lwbrx 4, 0, 4
 ; CHECK-NEXT:    sub 5, 4, 3
 ; CHECK-NEXT:    sub 3, 3, 4
-; CHECK-NEXT:    rldicl 4, 5, 1, 63
+; CHECK-NEXT:    rldicl 5, 5, 1, 63
 ; CHECK-NEXT:    rldicl 3, 3, 1, 63
-; CHECK-NEXT:    sub 3, 4, 3
+; CHECK-NEXT:    sub 3, 5, 3
 ; CHECK-NEXT:    extsw 3, 3
 ; CHECK-NEXT:    blr
   %call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 4)

diff --git a/llvm/test/CodeGen/PowerPC/memset-tail.ll b/llvm/test/CodeGen/PowerPC/memset-tail.ll
@@ -852,10 +852,10 @@ entry:
 define dso_local void @memset2TailV1B2(ptr nocapture noundef writeonly %p) local_unnamed_addr {
 ; P8-BE-LABEL: memset2TailV1B2:
 ; P8-BE:       # %bb.0: # %entry
-; P8-BE-NEXT:    ld 4, L..C7(2) # %const.0
-; P8-BE-NEXT:    lxvw4x 0, 0, 4
 ; P8-BE-NEXT:    li 4, -23131
 ; P8-BE-NEXT:    sth 4, 16(3)
+; P8-BE-NEXT:    ld 4, L..C7(2) # %const.0
+; P8-BE-NEXT:    lxvw4x 0, 0, 4
 ; P8-BE-NEXT:    stxvw4x 0, 0, 3
 ; P8-BE-NEXT:    blr
 ;
@@ -877,11 +877,11 @@ define dso_local void @memset2TailV1B2(ptr nocapture noundef writeonly %p) local
 ;
 ; P8-LE-LABEL: memset2TailV1B2:
 ; P8-LE:       # %bb.0: # %entry
+; P8-LE-NEXT:    li 4, -23131
+; P8-LE-NEXT:    sth 4, 16(3)
 ; P8-LE-NEXT:    addis 4, 2, .LCPI16_0@toc@ha
 ; P8-LE-NEXT:    addi 4, 4, .LCPI16_0@toc@l
 ; P8-LE-NEXT:    lxvd2x 0, 0, 4
-; P8-LE-NEXT:    li 4, -23131
-; P8-LE-NEXT:    sth 4, 16(3)
 ; P8-LE-NEXT:    stxvd2x 0, 0, 3
 ; P8-LE-NEXT:    blr
 ;
@@ -908,10 +908,10 @@ entry:
 define dso_local void @memset2TailV1B1(ptr nocapture noundef writeonly %p) local_unnamed_addr {
 ; P8-BE-LABEL: memset2TailV1B1:
 ; P8-BE:       # %bb.0: # %entry
-; P8-BE-NEXT:    ld 4, L..C8(2) # %const.0
-; P8-BE-NEXT:    lxvw4x 0, 0, 4
 ; P8-BE-NEXT:    li 4, -91
 ; P8-BE-NEXT:    stb 4, 16(3)
+; P8-BE-NEXT:    ld 4, L..C8(2) # %const.0
+; P8-BE-NEXT:    lxvw4x 0, 0, 4
 ; P8-BE-NEXT:    stxvw4x 0, 0, 3
 ; P8-BE-NEXT:    blr
 ;
@@ -933,11 +933,11 @@ define dso_local void @memset2TailV1B1(ptr nocapture noundef writeonly %p) local
 ;
 ; P8-LE-LABEL: memset2TailV1B1:
 ; P8-LE:       # %bb.0: # %entry
+; P8-LE-NEXT:    li 4, -91
+; P8-LE-NEXT:    stb 4, 16(3)
 ; P8-LE-NEXT:    addis 4, 2, .LCPI17_0@toc@ha
 ; P8-LE-NEXT:    addi 4, 4, .LCPI17_0@toc@l
 ; P8-LE-NEXT:    lxvd2x 0, 0, 4
-; P8-LE-NEXT:    li 4, -91
-; P8-LE-NEXT:    stb 4, 16(3)
 ; P8-LE-NEXT:    stxvd2x 0, 0, 3
 ; P8-LE-NEXT:    blr
 ;
@@ -1082,10 +1082,10 @@ entry:
 define dso_local void @memsetTailV0B9(ptr nocapture noundef writeonly %p) local_unnamed_addr {
 ; P8-BE-LABEL: memsetTailV0B9:
 ; P8-BE:       # %bb.0: # %entry
+; P8-BE-NEXT:    li 4, 15
+; P8-BE-NEXT:    stb 4, 8(3)
 ; P8-BE-NEXT:    lis 4, 3855
-; P8-BE-NEXT:    li 5, 15
 ; P8-BE-NEXT:    ori 4, 4, 3855
-; P8-BE-NEXT:    stb 5, 8(3)
 ; P8-BE-NEXT:    rldimi 4, 4, 32, 0
 ; P8-BE-NEXT:    std 4, 0(3)
 ; P8-BE-NEXT:    blr
@@ -1111,10 +1111,10 @@ define dso_local void @memsetTailV0B9(ptr nocapture noundef writeonly %p) local_
 ;
 ; P8-LE-LABEL: memsetTailV0B9:
 ; P8-LE:       # %bb.0: # %entry
+; P8-LE-NEXT:    li 4, 15
+; P8-LE-NEXT:    stb 4, 8(3)
 ; P8-LE-NEXT:    lis 4, 3855
-; P8-LE-NEXT:    li 5, 15
 ; P8-LE-NEXT:    ori 4, 4, 3855
-; P8-LE-NEXT:    stb 5, 8(3)
 ; P8-LE-NEXT:    rldimi 4, 4, 32, 0
 ; P8-LE-NEXT:    std 4, 0(3)
 ; P8-LE-NEXT:    blr
@@ -1247,10 +1247,10 @@ entry:
 define dso_local void @memsetTailV0B5(ptr nocapture noundef writeonly %p) local_unnamed_addr {
 ; P8-BE-LABEL: memsetTailV0B5:
 ; P8-BE:       # %bb.0: # %entry
+; P8-BE-NEXT:    li 4, 15
+; P8-BE-NEXT:    stb 4, 4(3)
 ; P8-BE-NEXT:    lis 4, 3855
-; P8-BE-NEXT:    li 5, 15
 ; P8-BE-NEXT:    ori 4, 4, 3855
-; P8-BE-NEXT:    stb 5, 4(3)
 ; P8-BE-NEXT:    stw 4, 0(3)
 ; P8-BE-NEXT:    blr
 ;
@@ -1273,10 +1273,10 @@ define dso_local void @memsetTailV0B5(ptr nocapture noundef writeonly %p) local_
 ;
 ; P8-LE-LABEL: memsetTailV0B5:
 ; P8-LE:       # %bb.0: # %entry
+; P8-LE-NEXT:    li 4, 15
+; P8-LE-NEXT:    stb 4, 4(3)
 ; P8-LE-NEXT:    lis 4, 3855
-; P8-LE-NEXT:    li 5, 15
 ; P8-LE-NEXT:    ori 4, 4, 3855
-; P8-LE-NEXT:    stb 5, 4(3)
 ; P8-LE-NEXT:    stw 4, 0(3)
 ; P8-LE-NEXT:    blr
 ;

diff --git a/llvm/test/CodeGen/PowerPC/mergeable-string-pool-large.ll b/llvm/test/CodeGen/PowerPC/mergeable-string-pool-large.ll
diff --git a/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll b/llvm/test/CodeGen/PowerPC/mergeable-string-pool.ll
diff --git a/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll b/llvm/test/CodeGen/PowerPC/mma-acc-memops.ll
@@ -67,23 +67,23 @@ define dso_local void @testLdSt(i64 %SrcIdx, i64 %DstIdx) {
 ; LE-PWR8-LABEL: testLdSt:
 ; LE-PWR8:       # %bb.0: # %entry
 ; LE-PWR8-NEXT:    addis r3, r2, f@toc@ha
-; LE-PWR8-NEXT:    li r4, 96
-; LE-PWR8-NEXT:    li r5, 112
+; LE-PWR8-NEXT:    li r4, 64
 ; LE-PWR8-NEXT:    addi r3, r3, f@toc@l
 ; LE-PWR8-NEXT:    lxvd2x vs0, r3, r4
-; LE-PWR8-NEXT:    li r4, 64
-; LE-PWR8-NEXT:    lxvd2x vs1, r3, r5
-; LE-PWR8-NEXT:    li r5, 80
+; LE-PWR8-NEXT:    li r4, 80
+; LE-PWR8-NEXT:    lxvd2x vs1, r3, r4
+; LE-PWR8-NEXT:    li r4, 96
 ; LE-PWR8-NEXT:    lxvd2x vs2, r3, r4
-; LE-PWR8-NEXT:    lxvd2x vs3, r3, r5
+; LE-PWR8-NEXT:    li r4, 112
+; LE-PWR8-NEXT:    lxvd2x vs3, r3, r4
 ; LE-PWR8-NEXT:    li r4, 176
-; LE-PWR8-NEXT:    li r5, 160
-; LE-PWR8-NEXT:    stxvd2x vs1, r3, r4
-; LE-PWR8-NEXT:    li r4, 144
-; LE-PWR8-NEXT:    stxvd2x vs0, r3, r5
-; LE-PWR8-NEXT:    li r5, 128
 ; LE-PWR8-NEXT:    stxvd2x vs3, r3, r4
-; LE-PWR8-NEXT:    stxvd2x vs2, r3, r5
+; LE-PWR8-NEXT:    li r4, 160
+; LE-PWR8-NEXT:    stxvd2x vs2, r3, r4
+; LE-PWR8-NEXT:    li r4, 144
+; LE-PWR8-NEXT:    stxvd2x vs1, r3, r4
+; LE-PWR8-NEXT:    li r4, 128
+; LE-PWR8-NEXT:    stxvd2x vs0, r3, r4
 ; LE-PWR8-NEXT:    blr
 ;
 ; BE-PWR9-LABEL: testLdSt:
@@ -103,23 +103,23 @@ define dso_local void @testLdSt(i64 %SrcIdx, i64 %DstIdx) {
 ; BE-PWR8-LABEL: testLdSt:
 ; BE-PWR8:       # %bb.0: # %entry
 ; BE-PWR8-NEXT:    addis r3, r2, f@toc@ha
-; BE-PWR8-NEXT:    li r4, 96
-; BE-PWR8-NEXT:    li r5, 112
+; BE-PWR8-NEXT:    li r4, 64
 ; BE-PWR8-NEXT:    addi r3, r3, f@toc@l
 ; BE-PWR8-NEXT:    lxvd2x vs0, r3, r4
-; BE-PWR8-NEXT:    li r4, 64
-; BE-PWR8-NEXT:    lxvd2x vs1, r3, r5
-; BE-PWR8-NEXT:    li r5, 80
+; BE-PWR8-NEXT:    li r4, 80
+; BE-PWR8-NEXT:    lxvd2x vs1, r3, r4
+; BE-PWR8-NEXT:    li r4, 96
 ; BE-PWR8-NEXT:    lxvd2x vs2, r3, r4
-; BE-PWR8-NEXT:    lxvd2x vs3, r3, r5
+; BE-PWR8-NEXT:    li r4, 112
+; BE-PWR8-NEXT:    lxvd2x vs3, r3, r4
 ; BE-PWR8-NEXT:    li r4, 176
-; BE-PWR8-NEXT:    li r5, 160
-; BE-PWR8-NEXT:    stxvd2x vs1, r3, r4
-; BE-PWR8-NEXT:    li r4, 144
-; BE-PWR8-NEXT:    stxvd2x vs0, r3, r5
-; BE-PWR8-NEXT:    li r5, 128
 ; BE-PWR8-NEXT:    stxvd2x vs3, r3, r4
-; BE-PWR8-NEXT:    stxvd2x vs2, r3, r5
+; BE-PWR8-NEXT:    li r4, 160
+; BE-PWR8-NEXT:    stxvd2x vs2, r3, r4
+; BE-PWR8-NEXT:    li r4, 144
+; BE-PWR8-NEXT:    stxvd2x vs1, r3, r4
+; BE-PWR8-NEXT:    li r4, 128
+; BE-PWR8-NEXT:    stxvd2x vs0, r3, r4
 ; BE-PWR8-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds <512 x i1>, ptr @f, i64 1
@@ -187,21 +187,21 @@ define dso_local void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
 ; LE-PWR8:       # %bb.0: # %entry
 ; LE-PWR8-NEXT:    addis r5, r2, f@toc@ha
 ; LE-PWR8-NEXT:    sldi r3, r3, 6
-; LE-PWR8-NEXT:    li r6, 48
-; LE-PWR8-NEXT:    li r8, 16
-; LE-PWR8-NEXT:    li r9, 32
+; LE-PWR8-NEXT:    li r7, 16
+; LE-PWR8-NEXT:    li r8, 32
+; LE-PWR8-NEXT:    li r9, 48
 ; LE-PWR8-NEXT:    addi r5, r5, f@toc@l
-; LE-PWR8-NEXT:    add r7, r5, r3
-; LE-PWR8-NEXT:    lxvd2x vs0, r5, r3
+; LE-PWR8-NEXT:    add r6, r5, r3
+; LE-PWR8-NEXT:    lxvd2x vs3, r5, r3
 ; LE-PWR8-NEXT:    sldi r3, r4, 6
-; LE-PWR8-NEXT:    lxvd2x vs1, r7, r6
-; LE-PWR8-NEXT:    lxvd2x vs2, r7, r8
-; LE-PWR8-NEXT:    add r4, r5, r3
-; LE-PWR8-NEXT:    lxvd2x vs3, r7, r9
-; LE-PWR8-NEXT:    stxvd2x vs0, r5, r3
-; LE-PWR8-NEXT:    stxvd2x vs1, r4, r6
-; LE-PWR8-NEXT:    stxvd2x vs3, r4, r9
-; LE-PWR8-NEXT:    stxvd2x vs2, r4, r8
+; LE-PWR8-NEXT:    lxvd2x vs0, r6, r7
+; LE-PWR8-NEXT:    lxvd2x vs1, r6, r8
+; LE-PWR8-NEXT:    lxvd2x vs2, r6, r9
+; LE-PWR8-NEXT:    stxvd2x vs3, r5, r3
+; LE-PWR8-NEXT:    add r3, r5, r3
+; LE-PWR8-NEXT:    stxvd2x vs2, r3, r9
+; LE-PWR8-NEXT:    stxvd2x vs1, r3, r8
+; LE-PWR8-NEXT:    stxvd2x vs0, r3, r7
 ; LE-PWR8-NEXT:    blr
 ;
 ; BE-PWR9-LABEL: testXLdSt:
@@ -226,21 +226,21 @@ define dso_local void @testXLdSt(i64 %SrcIdx, i64 %DstIdx) {
 ; BE-PWR8:       # %bb.0: # %entry
 ; BE-PWR8-NEXT:    addis r5, r2, f@toc@ha
 ; BE-PWR8-NEXT:    sldi r3, r3, 6
-; BE-PWR8-NEXT:    li r6, 32
-; BE-PWR8-NEXT:    li r7, 48
-; BE-PWR8-NEXT:    li r9, 16
+; BE-PWR8-NEXT:    li r7, 32
+; BE-PWR8-NEXT:    li r8, 48
+; BE-PWR8-NEXT:    sldi r4, r4, 6
 ; BE-PWR8-NEXT:    addi r5, r5, f@toc@l
-; BE-PWR8-NEXT:    add r8, r5, r3
-; BE-PWR8-NEXT:    lxvd2x vs2, r5, r3
-; BE-PWR8-NEXT:    sldi r3, r4, 6
-; BE-PWR8-NEXT:    lxvd2x vs0, r8, r6
-; BE-PWR8-NEXT:    lxvd2x vs1, r8, r7
-; BE-PWR8-NEXT:    add r4, r5, r3
-; BE-PWR8-NEXT:    lxvd2x vs3, r8, r9
-; BE-PWR8-NEXT:    stxvd2x vs2, r5, r3
-; BE-PWR8-NEXT:    stxvd2x vs1, r4, r7
-; BE-PWR8-NEXT:    stxvd2x vs0, r4, r6
-; BE-PWR8-NEXT:    stxvd2x vs3, r4, r9
+; BE-PWR8-NEXT:    add r6, r5, r3
+; BE-PWR8-NEXT:    lxvd2x vs0, r5, r3
+; BE-PWR8-NEXT:    li r3, 16
+; BE-PWR8-NEXT:    lxvd2x vs1, r6, r3
+; BE-PWR8-NEXT:    lxvd2x vs2, r6, r7
+; BE-PWR8-NEXT:    lxvd2x vs3, r6, r8
+; BE-PWR8-NEXT:    add r6, r5, r4
+; BE-PWR8-NEXT:    stxvd2x vs0, r5, r4
+; BE-PWR8-NEXT:    stxvd2x vs3, r6, r8
+; BE-PWR8-NEXT:    stxvd2x vs2, r6, r7
+; BE-PWR8-NEXT:    stxvd2x vs1, r6, r3
 ; BE-PWR8-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds <512 x i1>, ptr @f, i64 %SrcIdx
@@ -302,23 +302,23 @@ define dso_local void @testUnalignedLdSt() {
 ; LE-PWR8-LABEL: testUnalignedLdSt:
 ; LE-PWR8:       # %bb.0: # %entry
 ; LE-PWR8-NEXT:    addis r3, r2, f@toc@ha
-; LE-PWR8-NEXT:    li r4, 43
-; LE-PWR8-NEXT:    li r5, 59
+; LE-PWR8-NEXT:    li r4, 11
 ; LE-PWR8-NEXT:    addi r3, r3, f@toc@l
 ; LE-PWR8-NEXT:    lxvd2x vs0, r3, r4
-; LE-PWR8-NEXT:    li r4, 11
-; LE-PWR8-NEXT:    lxvd2x vs1, r3, r5
-; LE-PWR8-NEXT:    li r5, 27
+; LE-PWR8-NEXT:    li r4, 27
+; LE-PWR8-NEXT:    lxvd2x vs1, r3, r4
+; LE-PWR8-NEXT:    li r4, 43
 ; LE-PWR8-NEXT:    lxvd2x vs2, r3, r4
-; LE-PWR8-NEXT:    lxvd2x vs3, r3, r5
+; LE-PWR8-NEXT:    li r4, 59
+; LE-PWR8-NEXT:    lxvd2x vs3, r3, r4
 ; LE-PWR8-NEXT:    li r4, 67
-; LE-PWR8-NEXT:    li r5, 51
-; LE-PWR8-NEXT:    stxvd2x vs1, r3, r4
-; LE-PWR8-NEXT:    li r4, 35
-; LE-PWR8-NEXT:    stxvd2x vs0, r3, r5
-; LE-PWR8-NEXT:    li r5, 19
 ; LE-PWR8-NEXT:    stxvd2x vs3, r3, r4
-; LE-PWR8-NEXT:    stxvd2x vs2, r3, r5
+; LE-PWR8-NEXT:    li r4, 51
+; LE-PWR8-NEXT:    stxvd2x vs2, r3, r4
+; LE-PWR8-NEXT:    li r4, 35
+; LE-PWR8-NEXT:    stxvd2x vs1, r3, r4
+; LE-PWR8-NEXT:    li r4, 19
+; LE-PWR8-NEXT:    stxvd2x vs0, r3, r4
 ; LE-PWR8-NEXT:    blr
 ;
 ; BE-PWR9-LABEL: testUnalignedLdSt:
@@ -346,23 +346,23 @@ define dso_local void @testUnalignedLdSt() {
 ; BE-PWR8-LABEL: testUnalignedLdSt:
 ; BE-PWR8:       # %bb.0: # %entry
 ; BE-PWR8-NEXT:    addis r3, r2, f@toc@ha
-; BE-PWR8-NEXT:    li r4, 43
-; BE-PWR8-NEXT:    li r5, 59
+; BE-PWR8-NEXT:    li r4, 11
 ; BE-PWR8-NEXT:    addi r3, r3, f@toc@l
 ; BE-PWR8-NEXT:    lxvd2x vs0, r3, r4
-; BE-PWR8-NEXT:    li r4, 11
-; BE-PWR8-NEXT:    lxvd2x vs1, r3, r5
-; BE-PWR8-NEXT:    li r5, 27
+; BE-PWR8-NEXT:    li r4, 27
+; BE-PWR8-NEXT:    lxvd2x vs1, r3, r4
+; BE-PWR8-NEXT:    li r4, 43
 ; BE-PWR8-NEXT:    lxvd2x vs2, r3, r4
-; BE-PWR8-NEXT:    lxvd2x vs3, r3, r5
+; BE-PWR8-NEXT:    li r4, 59
+; BE-PWR8-NEXT:    lxvd2x vs3, r3, r4
 ; BE-PWR8-NEXT:    li r4, 67
-; BE-PWR8-NEXT:    li r5, 51
-; BE-PWR8-NEXT:    stxvd2x vs1, r3, r4
-; BE-PWR8-NEXT:    li r4, 35
-; BE-PWR8-NEXT:    stxvd2x vs0, r3, r5
-; BE-PWR8-NEXT:    li r5, 19
 ; BE-PWR8-NEXT:    stxvd2x vs3, r3, r4
-; BE-PWR8-NEXT:    stxvd2x vs2, r3, r5
+; BE-PWR8-NEXT:    li r4, 51
+; BE-PWR8-NEXT:    stxvd2x vs2, r3, r4
+; BE-PWR8-NEXT:    li r4, 35
+; BE-PWR8-NEXT:    stxvd2x vs1, r3, r4
+; BE-PWR8-NEXT:    li r4, 19
+; BE-PWR8-NEXT:    stxvd2x vs0, r3, r4
 ; BE-PWR8-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, ptr @f, i64 11
@@ -405,14 +405,14 @@ define dso_local void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) {
 ; LE-PWR8:       # %bb.0: # %entry
 ; LE-PWR8-NEXT:    addis r3, r2, g@toc@ha
 ; LE-PWR8-NEXT:    li r4, 32
-; LE-PWR8-NEXT:    li r5, 48
 ; LE-PWR8-NEXT:    addi r3, r3, g@toc@l
 ; LE-PWR8-NEXT:    lxvd2x vs0, r3, r4
-; LE-PWR8-NEXT:    lxvd2x vs1, r3, r5
+; LE-PWR8-NEXT:    li r4, 48
+; LE-PWR8-NEXT:    lxvd2x vs1, r3, r4
 ; LE-PWR8-NEXT:    li r4, 80
-; LE-PWR8-NEXT:    li r5, 64
 ; LE-PWR8-NEXT:    stxvd2x vs1, r3, r4
-; LE-PWR8-NEXT:    stxvd2x vs0, r3, r5
+; LE-PWR8-NEXT:    li r4, 64
+; LE-PWR8-NEXT:    stxvd2x vs0, r3, r4
 ; LE-PWR8-NEXT:    blr
 ;
 ; BE-PWR9-LABEL: testLdStPair:
@@ -429,14 +429,14 @@ define dso_local void @testLdStPair(i64 %SrcIdx, i64 %DstIdx) {
 ; BE-PWR8:       # %bb.0: # %entry
 ; BE-PWR8-NEXT:    addis r3, r2, g@toc@ha
 ; BE-PWR8-NEXT:    li r4, 32
-; BE-PWR8-NEXT:    li r5, 48
 ; BE-PWR8-NEXT:    addi r3, r3, g@toc@l
 ; BE-PWR8-NEXT:    lxvd2x vs0, r3, r4
-; BE-PWR8-NEXT:    lxvd2x vs1, r3, r5
+; BE-PWR8-NEXT:    li r4, 48
+; BE-PWR8-NEXT:    lxvd2x vs1, r3, r4
 ; BE-PWR8-NEXT:    li r4, 80
-; BE-PWR8-NEXT:    li r5, 64
 ; BE-PWR8-NEXT:    stxvd2x vs1, r3, r4
-; BE-PWR8-NEXT:    stxvd2x vs0, r3, r5
+; BE-PWR8-NEXT:    li r4, 64
+; BE-PWR8-NEXT:    stxvd2x vs0, r3, r4
 ; BE-PWR8-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds <256 x i1>, ptr @g, i64 1
@@ -521,15 +521,15 @@ define dso_local void @testXLdStPair(i64 %SrcIdx, i64 %DstIdx) {
 ; BE-PWR8:       # %bb.0: # %entry
 ; BE-PWR8-NEXT:    addis r5, r2, g@toc@ha
 ; BE-PWR8-NEXT:    sldi r3, r3, 5
-; BE-PWR8-NEXT:    li r7, 16
+; BE-PWR8-NEXT:    sldi r4, r4, 5
 ; BE-PWR8-NEXT:    addi r5, r5, g@toc@l
 ; BE-PWR8-NEXT:    add r6, r5, r3
 ; BE-PWR8-NEXT:    lxvd2x vs0, r5, r3
-; BE-PWR8-NEXT:    sldi r3, r4, 5
-; BE-PWR8-NEXT:    lxvd2x vs1, r6, r7
-; BE-PWR8-NEXT:    add r4, r5, r3
-; BE-PWR8-NEXT:    stxvd2x vs0, r5, r3
-; BE-PWR8-NEXT:    stxvd2x vs1, r4, r7
+; BE-PWR8-NEXT:    li r3, 16
+; BE-PWR8-NEXT:    lxvd2x vs1, r6, r3
+; BE-PWR8-NEXT:    add r6, r5, r4
+; BE-PWR8-NEXT:    stxvd2x vs0, r5, r4
+; BE-PWR8-NEXT:    stxvd2x vs1, r6, r3
 ; BE-PWR8-NEXT:    blr
 entry:
   %arrayidx = getelementptr inbounds <256 x i1>, ptr @g, i64 %SrcIdx
@@ -576,14 +576,14 @@ define dso_local void @testUnalignedLdStPair() {
 ; LE-PWR8:       # %bb.0: # %entry
 ; LE-PWR8-NEXT:    addis r3, r2, g@toc@ha
 ; LE-PWR8-NEXT:    li r4, 11
-; LE-PWR8-NEXT:    li r5, 27
 ; LE-PWR8-NEXT:    addi r3, r3, g@toc@l
 ; LE-PWR8-NEXT:    lxvd2x vs0, r3, r4
-; LE-PWR8-NEXT:    lxvd2x vs1, r3, r5
+; LE-PWR8-NEXT:    li r4, 27
+; LE-PWR8-NEXT:    lxvd2x vs1, r3, r4
 ; LE-PWR8-NEXT:    li r4, 35
-; LE-PWR8-NEXT:    li r5, 19
 ; LE-PWR8-NEXT:    stxvd2x vs1, r3, r4
-; LE-PWR8-NEXT:    stxvd2x vs0, r3, r5
+; LE-PWR8-NEXT:    li r4, 19
+; LE-PWR8-NEXT:    stxvd2x vs0, r3, r4
 ; LE-PWR8-NEXT:    blr
 ;
 ; BE-PWR9-LABEL: testUnalignedLdStPair:
@@ -604,14 +604,14 @@ define dso_local void @testUnalignedLdStPair() {
 ; BE-PWR8:       # %bb.0: # %entry
 ; BE-PWR8-NEXT:    addis r3, r2, g@toc@ha
 ; BE-PWR8-NEXT:    li r4, 11
-; BE-PWR8-NEXT:    li r5, 27
 ; BE-PWR8-NEXT:    addi r3, r3, g@toc@l
 ; BE-PWR8-NEXT:    lxvd2x vs0, r3, r4
-; BE-PWR8-NEXT:    lxvd2x vs1, r3, r5
+; BE-PWR8-NEXT:    li r4, 27
+; BE-PWR8-NEXT:    lxvd2x vs1, r3, r4
 ; BE-PWR8-NEXT:    li r4, 35
-; BE-PWR8-NEXT:    li r5, 19
 ; BE-PWR8-NEXT:    stxvd2x vs1, r3, r4
-; BE-PWR8-NEXT:    stxvd2x vs0, r3, r5
+; BE-PWR8-NEXT:    li r4, 19
+; BE-PWR8-NEXT:    stxvd2x vs0, r3, r4
 ; BE-PWR8-NEXT:    blr
 entry:
   %add.ptr = getelementptr inbounds i8, ptr @g, i64 11

diff --git a/llvm/test/CodeGen/PowerPC/mulld.ll b/llvm/test/CodeGen/PowerPC/mulld.ll
@@ -20,7 +20,7 @@ define void @bn_mul_comba8(ptr nocapture %r, ptr nocapture readonly %a, ptr noca
 ; CHECK-ITIN:    mulhdu
 ; CHECK-ITIN-NEXT:    mulld
 ; CHECK-ITIN-NEXT:    mulhdu
-; CHECK-ITIN-NEXT:    mulld
+; CHECK-ITIN:    mulld
 ; CHECK-ITIN-NEXT:    mulhdu
 
   %1 = load i64, ptr %a, align 8

diff --git a/llvm/test/CodeGen/PowerPC/no-ctr-loop-if-exit-in-nested-loop.ll b/llvm/test/CodeGen/PowerPC/no-ctr-loop-if-exit-in-nested-loop.ll
@@ -4,46 +4,45 @@
 define signext i32 @test(ptr noalias %PtrA, ptr noalias %PtrB, i32 signext %LenA, i32 signext %LenB) #0 {
 ; CHECK-LABEL: test:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    li 6, 0
-; CHECK-NEXT:    addi 7, 3, 4
+; CHECK-NEXT:    addi 6, 3, 4
 ; CHECK-NEXT:    addi 4, 4, -4
 ; CHECK-NEXT:    li 8, 0
+; CHECK-NEXT:    li 7, 0
 ; CHECK-NEXT:  .LBB0_1: # %block3
 ; CHECK-NEXT:    # =>This Loop Header: Depth=1
 ; CHECK-NEXT:    # Child Loop BB0_2 Depth 2
-; CHECK-NEXT:    mr 9, 6
-; CHECK-NEXT:    addi 6, 6, 1
-; CHECK-NEXT:    extsw 8, 8
-; CHECK-NEXT:    cmpw 6, 5
-; CHECK-NEXT:    extsw 9, 9
-; CHECK-NEXT:    crnot 20, 0
-; CHECK-NEXT:    sldi 10, 8, 2
-; CHECK-NEXT:    sldi 9, 9, 2
+; CHECK-NEXT:    extsw 9, 8
 ; CHECK-NEXT:    addi 8, 8, 1
+; CHECK-NEXT:    extsw 7, 7
+; CHECK-NEXT:    cmpw 8, 5
+; CHECK-NEXT:    sldi 10, 7, 2
+; CHECK-NEXT:    sldi 9, 9, 2
+; CHECK-NEXT:    addi 7, 7, 1
 ; CHECK-NEXT:    add 10, 4, 10
+; CHECK-NEXT:    crnot 20, 0
 ; CHECK-NEXT:    bc 12, 20, .LBB0_5
 ; CHECK-NEXT:    .p2align 5
 ; CHECK-NEXT:  .LBB0_2: # %if.end
 ; CHECK-NEXT:    # Parent Loop BB0_1 Depth=1
 ; CHECK-NEXT:    # => This Inner Loop Header: Depth=2
-; CHECK-NEXT:    lwz 11, 4(10)
-; CHECK-NEXT:    cmplwi 11, 0
+; CHECK-NEXT:    lwz 12, 4(10)
 ; CHECK-NEXT:    addi 11, 10, 4
+; CHECK-NEXT:    cmplwi 12, 0
 ; CHECK-NEXT:    beq 0, .LBB0_4
 ; CHECK-NEXT:  # %bb.3: # %if.then4
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lwzx 12, 7, 9
-; CHECK-NEXT:    addi 8, 8, 1
+; CHECK-NEXT:    lwzx 12, 6, 9
+; CHECK-NEXT:    addi 7, 7, 1
 ; CHECK-NEXT:    stw 12, 8(10)
 ; CHECK-NEXT:    mr 10, 11
 ; CHECK-NEXT:    bc 4, 20, .LBB0_2
 ; CHECK-NEXT:    b .LBB0_5
 ; CHECK-NEXT:    .p2align 4
 ; CHECK-NEXT:  .LBB0_4: # %if.end9
 ; CHECK-NEXT:    #
-; CHECK-NEXT:    lwzx 10, 7, 9
+; CHECK-NEXT:    lwzx 10, 6, 9
 ; CHECK-NEXT:    addi 10, 10, 1
-; CHECK-NEXT:    stwx 10, 7, 9
+; CHECK-NEXT:    stwx 10, 6, 9
 ; CHECK-NEXT:    b .LBB0_1
 ; CHECK-NEXT:  .LBB0_5: # %if.then
 ; CHECK-NEXT:    lwax 3, 9, 3

diff --git a/llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll b/llvm/test/CodeGen/PowerPC/non-debug-mi-search-frspxsrsp.ll
@@ -18,25 +18,25 @@ define dso_local void @test(ptr nocapture readonly %Fptr, ptr nocapture %Vptr) l
 ; CHECK-NEXT:    vspltisw 2, 1
 ; CHECK-NEXT:  .Ltmp0:
 ; CHECK-NEXT:    .loc 1 2 38 prologue_end # test.c:2:38
-; CHECK-NEXT:    lfs 1, 0(3)
+; CHECK-NEXT:    lfs 0, 0(3)
 ; CHECK-NEXT:    addis 3, 2, .LCPI0_0@toc@ha
 ; CHECK-NEXT:  .Ltmp1:
 ; CHECK-NEXT:    .loc 1 0 38 is_stmt 0 # test.c:0:38
+; CHECK-NEXT:    xvcvsxwdp 1, 34
 ; CHECK-NEXT:    lfd 2, .LCPI0_0@toc@l(3)
-; CHECK-NEXT:    xvcvsxwdp 0, 34
 ; CHECK-NEXT:    .loc 1 2 27 # test.c:2:27
-; CHECK-NEXT:    xssubdp 0, 0, 1
+; CHECK-NEXT:    xssubdp 1, 1, 0
 ; CHECK-NEXT:    .loc 1 2 45 # test.c:2:45
-; CHECK-NEXT:    xsadddp 0, 0, 2
+; CHECK-NEXT:    xsadddp 1, 1, 2
 ; CHECK-NEXT:  .Ltmp2:
 ; CHECK-NEXT:    #DEBUG_VALUE: test:Val <- undef
 ; CHECK-NEXT:    .loc 1 0 45 # test.c:0:45
 ; CHECK-NEXT:    xxlxor 2, 2, 2
 ; CHECK-NEXT:    .loc 1 3 26 is_stmt 1 # test.c:3:26
-; CHECK-NEXT:    xxmrghd 1, 1, 2
-; CHECK-NEXT:    xxmrghd 0, 2, 0
-; CHECK-NEXT:    xvcvdpsp 34, 1
-; CHECK-NEXT:    xvcvdpsp 35, 0
+; CHECK-NEXT:    xxmrghd 0, 0, 2
+; CHECK-NEXT:    xvcvdpsp 34, 0
+; CHECK-NEXT:    xxmrghd 1, 2, 1
+; CHECK-NEXT:    xvcvdpsp 35, 1
 ; CHECK-NEXT:    vmrgew 2, 2, 3
 ; CHECK-NEXT:    .loc 1 3 9 is_stmt 0 # test.c:3:9
 ; CHECK-NEXT:    xxswapd 0, 34

diff --git a/llvm/test/CodeGen/PowerPC/p8-isel-sched.ll b/llvm/test/CodeGen/PowerPC/p8-isel-sched.ll
@@ -30,11 +30,11 @@ entry:
 ; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: [[TRUE]]
-; CHECK-NO-ISEL-NEXT: addi {{[0-9]+}}, {{[0-9]+}}, 0
+; CHECK-NO-ISEL: addi {{[0-9]+}}, {{[0-9]+}}, -2
 ; CHECK: addi
 ; CHECK: isel
 ; CHECK-NO-ISEL: bc 12, 2, [[TRUE:.LBB[0-9]+]]
-; CHECK-NO-ISEL: ori 10, 11, 0
+; CHECK-NO-ISEL: ori 3, 7, 0
 ; CHECK-NO-ISEL-NEXT: b [[SUCCESSOR:.LBB[0-9]+]]
 ; CHECK-NO-ISEL: [[TRUE]]
 ; CHECK: blr

diff --git a/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll b/llvm/test/CodeGen/PowerPC/p8-scalar_vector_conversions.ll
@@ -1112,11 +1112,11 @@ entry:
 define signext i8 @getvelsc(<16 x i8> %vsc, i32 signext %i) {
 ; CHECK-LABEL: getvelsc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    clrldi r4, r5, 32
-; CHECK-NEXT:    li r3, 7
-; CHECK-NEXT:    andi. r5, r4, 8
-; CHECK-NEXT:    andc r3, r3, r4
-; CHECK-NEXT:    lvsl v3, 0, r5
+; CHECK-NEXT:    clrldi r3, r5, 32
+; CHECK-NEXT:    andi. r4, r3, 8
+; CHECK-NEXT:    lvsl v3, 0, r4
+; CHECK-NEXT:    li r4, 7
+; CHECK-NEXT:    andc r3, r4, r3
 ; CHECK-NEXT:    sldi r3, r3, 3
 ; CHECK-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-NEXT:    mfvsrd r4, v2
@@ -1126,14 +1126,14 @@ define signext i8 @getvelsc(<16 x i8> %vsc, i32 signext %i) {
 ;
 ; CHECK-LE-LABEL: getvelsc:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    li r3, 8
-; CHECK-LE-NEXT:    clrldi r4, r5, 32
-; CHECK-LE-NEXT:    andc r3, r3, r4
-; CHECK-LE-NEXT:    lvsl v3, 0, r3
-; CHECK-LE-NEXT:    li r3, 7
-; CHECK-LE-NEXT:    and r3, r3, r4
-; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    clrldi r3, r5, 32
+; CHECK-LE-NEXT:    li r4, 8
+; CHECK-LE-NEXT:    andc r4, r4, r3
+; CHECK-LE-NEXT:    lvsl v3, 0, r4
+; CHECK-LE-NEXT:    li r4, 7
+; CHECK-LE-NEXT:    and r3, r4, r3
 ; CHECK-LE-NEXT:    sldi r3, r3, 3
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-LE-NEXT:    mfvsrd r4, v2
 ; CHECK-LE-NEXT:    srd r3, r4, r3
 ; CHECK-LE-NEXT:    extsb r3, r3
@@ -1142,10 +1142,10 @@ define signext i8 @getvelsc(<16 x i8> %vsc, i32 signext %i) {
 ; CHECK-AIX-LABEL: getvelsc:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    clrldi 3, 3, 32
+; CHECK-AIX-NEXT:    andi. 4, 3, 8
+; CHECK-AIX-NEXT:    lvsl 3, 0, 4
 ; CHECK-AIX-NEXT:    li 4, 7
-; CHECK-AIX-NEXT:    andi. 5, 3, 8
 ; CHECK-AIX-NEXT:    andc 3, 4, 3
-; CHECK-AIX-NEXT:    lvsl 3, 0, 5
 ; CHECK-AIX-NEXT:    sldi 3, 3, 3
 ; CHECK-AIX-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-AIX-NEXT:    mfvsrd 4, 34
@@ -1163,11 +1163,11 @@ entry:
 define zeroext i8 @getveluc(<16 x i8> %vuc, i32 signext %i) {
 ; CHECK-LABEL: getveluc:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    clrldi r4, r5, 32
-; CHECK-NEXT:    li r3, 7
-; CHECK-NEXT:    andi. r5, r4, 8
-; CHECK-NEXT:    andc r3, r3, r4
-; CHECK-NEXT:    lvsl v3, 0, r5
+; CHECK-NEXT:    clrldi r3, r5, 32
+; CHECK-NEXT:    andi. r4, r3, 8
+; CHECK-NEXT:    lvsl v3, 0, r4
+; CHECK-NEXT:    li r4, 7
+; CHECK-NEXT:    andc r3, r4, r3
 ; CHECK-NEXT:    sldi r3, r3, 3
 ; CHECK-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-NEXT:    mfvsrd r4, v2
@@ -1177,14 +1177,14 @@ define zeroext i8 @getveluc(<16 x i8> %vuc, i32 signext %i) {
 ;
 ; CHECK-LE-LABEL: getveluc:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    li r3, 8
-; CHECK-LE-NEXT:    clrldi r4, r5, 32
-; CHECK-LE-NEXT:    andc r3, r3, r4
-; CHECK-LE-NEXT:    lvsl v3, 0, r3
-; CHECK-LE-NEXT:    li r3, 7
-; CHECK-LE-NEXT:    and r3, r3, r4
-; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    clrldi r3, r5, 32
+; CHECK-LE-NEXT:    li r4, 8
+; CHECK-LE-NEXT:    andc r4, r4, r3
+; CHECK-LE-NEXT:    lvsl v3, 0, r4
+; CHECK-LE-NEXT:    li r4, 7
+; CHECK-LE-NEXT:    and r3, r4, r3
 ; CHECK-LE-NEXT:    sldi r3, r3, 3
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-LE-NEXT:    mfvsrd r4, v2
 ; CHECK-LE-NEXT:    srd r3, r4, r3
 ; CHECK-LE-NEXT:    clrldi r3, r3, 56
@@ -1193,10 +1193,10 @@ define zeroext i8 @getveluc(<16 x i8> %vuc, i32 signext %i) {
 ; CHECK-AIX-LABEL: getveluc:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    clrldi 3, 3, 32
+; CHECK-AIX-NEXT:    andi. 4, 3, 8
+; CHECK-AIX-NEXT:    lvsl 3, 0, 4
 ; CHECK-AIX-NEXT:    li 4, 7
-; CHECK-AIX-NEXT:    andi. 5, 3, 8
 ; CHECK-AIX-NEXT:    andc 3, 4, 3
-; CHECK-AIX-NEXT:    lvsl 3, 0, 5
 ; CHECK-AIX-NEXT:    sldi 3, 3, 3
 ; CHECK-AIX-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-AIX-NEXT:    mfvsrd 4, 34
@@ -1678,13 +1678,13 @@ entry:
 define signext i16 @getvelss(<8 x i16> %vss, i32 signext %i) {
 ; CHECK-LABEL: getvelss:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    clrldi r4, r5, 32
-; CHECK-NEXT:    li r3, 3
-; CHECK-NEXT:    andi. r5, r4, 4
-; CHECK-NEXT:    andc r3, r3, r4
-; CHECK-NEXT:    sldi r5, r5, 1
+; CHECK-NEXT:    clrldi r3, r5, 32
+; CHECK-NEXT:    andi. r4, r3, 4
+; CHECK-NEXT:    sldi r4, r4, 1
+; CHECK-NEXT:    lvsl v3, 0, r4
+; CHECK-NEXT:    li r4, 3
+; CHECK-NEXT:    andc r3, r4, r3
 ; CHECK-NEXT:    sldi r3, r3, 4
-; CHECK-NEXT:    lvsl v3, 0, r5
 ; CHECK-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-NEXT:    mfvsrd r4, v2
 ; CHECK-NEXT:    srd r3, r4, r3
@@ -1693,15 +1693,15 @@ define signext i16 @getvelss(<8 x i16> %vss, i32 signext %i) {
 ;
 ; CHECK-LE-LABEL: getvelss:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    li r3, 4
-; CHECK-LE-NEXT:    clrldi r4, r5, 32
-; CHECK-LE-NEXT:    andc r3, r3, r4
-; CHECK-LE-NEXT:    sldi r3, r3, 1
-; CHECK-LE-NEXT:    lvsl v3, 0, r3
-; CHECK-LE-NEXT:    li r3, 3
-; CHECK-LE-NEXT:    and r3, r3, r4
-; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    clrldi r3, r5, 32
+; CHECK-LE-NEXT:    li r4, 4
+; CHECK-LE-NEXT:    andc r4, r4, r3
+; CHECK-LE-NEXT:    sldi r4, r4, 1
+; CHECK-LE-NEXT:    lvsl v3, 0, r4
+; CHECK-LE-NEXT:    li r4, 3
+; CHECK-LE-NEXT:    and r3, r4, r3
 ; CHECK-LE-NEXT:    sldi r3, r3, 4
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-LE-NEXT:    mfvsrd r4, v2
 ; CHECK-LE-NEXT:    srd r3, r4, r3
 ; CHECK-LE-NEXT:    extsh r3, r3
@@ -1710,12 +1710,12 @@ define signext i16 @getvelss(<8 x i16> %vss, i32 signext %i) {
 ; CHECK-AIX-LABEL: getvelss:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    clrldi 3, 3, 32
+; CHECK-AIX-NEXT:    andi. 4, 3, 4
+; CHECK-AIX-NEXT:    sldi 4, 4, 1
+; CHECK-AIX-NEXT:    lvsl 3, 0, 4
 ; CHECK-AIX-NEXT:    li 4, 3
-; CHECK-AIX-NEXT:    andi. 5, 3, 4
 ; CHECK-AIX-NEXT:    andc 3, 4, 3
-; CHECK-AIX-NEXT:    sldi 5, 5, 1
 ; CHECK-AIX-NEXT:    sldi 3, 3, 4
-; CHECK-AIX-NEXT:    lvsl 3, 0, 5
 ; CHECK-AIX-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-AIX-NEXT:    mfvsrd 4, 34
 ; CHECK-AIX-NEXT:    srd 3, 4, 3
@@ -1732,13 +1732,13 @@ entry:
 define zeroext i16 @getvelus(<8 x i16> %vus, i32 signext %i) {
 ; CHECK-LABEL: getvelus:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    clrldi r4, r5, 32
-; CHECK-NEXT:    li r3, 3
-; CHECK-NEXT:    andi. r5, r4, 4
-; CHECK-NEXT:    andc r3, r3, r4
-; CHECK-NEXT:    sldi r5, r5, 1
+; CHECK-NEXT:    clrldi r3, r5, 32
+; CHECK-NEXT:    andi. r4, r3, 4
+; CHECK-NEXT:    sldi r4, r4, 1
+; CHECK-NEXT:    lvsl v3, 0, r4
+; CHECK-NEXT:    li r4, 3
+; CHECK-NEXT:    andc r3, r4, r3
 ; CHECK-NEXT:    sldi r3, r3, 4
-; CHECK-NEXT:    lvsl v3, 0, r5
 ; CHECK-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-NEXT:    mfvsrd r4, v2
 ; CHECK-NEXT:    srd r3, r4, r3
@@ -1747,15 +1747,15 @@ define zeroext i16 @getvelus(<8 x i16> %vus, i32 signext %i) {
 ;
 ; CHECK-LE-LABEL: getvelus:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    li r3, 4
-; CHECK-LE-NEXT:    clrldi r4, r5, 32
-; CHECK-LE-NEXT:    andc r3, r3, r4
-; CHECK-LE-NEXT:    sldi r3, r3, 1
-; CHECK-LE-NEXT:    lvsl v3, 0, r3
-; CHECK-LE-NEXT:    li r3, 3
-; CHECK-LE-NEXT:    and r3, r3, r4
-; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    clrldi r3, r5, 32
+; CHECK-LE-NEXT:    li r4, 4
+; CHECK-LE-NEXT:    andc r4, r4, r3
+; CHECK-LE-NEXT:    sldi r4, r4, 1
+; CHECK-LE-NEXT:    lvsl v3, 0, r4
+; CHECK-LE-NEXT:    li r4, 3
+; CHECK-LE-NEXT:    and r3, r4, r3
 ; CHECK-LE-NEXT:    sldi r3, r3, 4
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-LE-NEXT:    mfvsrd r4, v2
 ; CHECK-LE-NEXT:    srd r3, r4, r3
 ; CHECK-LE-NEXT:    clrldi r3, r3, 48
@@ -1764,12 +1764,12 @@ define zeroext i16 @getvelus(<8 x i16> %vus, i32 signext %i) {
 ; CHECK-AIX-LABEL: getvelus:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    clrldi 3, 3, 32
+; CHECK-AIX-NEXT:    andi. 4, 3, 4
+; CHECK-AIX-NEXT:    sldi 4, 4, 1
+; CHECK-AIX-NEXT:    lvsl 3, 0, 4
 ; CHECK-AIX-NEXT:    li 4, 3
-; CHECK-AIX-NEXT:    andi. 5, 3, 4
 ; CHECK-AIX-NEXT:    andc 3, 4, 3
-; CHECK-AIX-NEXT:    sldi 5, 5, 1
 ; CHECK-AIX-NEXT:    sldi 3, 3, 4
-; CHECK-AIX-NEXT:    lvsl 3, 0, 5
 ; CHECK-AIX-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-AIX-NEXT:    mfvsrd 4, 34
 ; CHECK-AIX-NEXT:    srd 3, 4, 3
@@ -2000,13 +2000,13 @@ entry:
 define signext i32 @getvelsi(<4 x i32> %vsi, i32 signext %i) {
 ; CHECK-LABEL: getvelsi:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    clrldi r4, r5, 32
-; CHECK-NEXT:    li r3, 1
-; CHECK-NEXT:    andi. r5, r4, 2
-; CHECK-NEXT:    andc r3, r3, r4
-; CHECK-NEXT:    sldi r5, r5, 2
+; CHECK-NEXT:    clrldi r3, r5, 32
+; CHECK-NEXT:    andi. r4, r3, 2
+; CHECK-NEXT:    sldi r4, r4, 2
+; CHECK-NEXT:    lvsl v3, 0, r4
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    andc r3, r4, r3
 ; CHECK-NEXT:    sldi r3, r3, 5
-; CHECK-NEXT:    lvsl v3, 0, r5
 ; CHECK-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-NEXT:    mfvsrd r4, v2
 ; CHECK-NEXT:    srd r3, r4, r3
@@ -2015,15 +2015,15 @@ define signext i32 @getvelsi(<4 x i32> %vsi, i32 signext %i) {
 ;
 ; CHECK-LE-LABEL: getvelsi:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    li r3, 2
-; CHECK-LE-NEXT:    clrldi r4, r5, 32
-; CHECK-LE-NEXT:    andc r3, r3, r4
-; CHECK-LE-NEXT:    sldi r3, r3, 2
-; CHECK-LE-NEXT:    lvsl v3, 0, r3
-; CHECK-LE-NEXT:    li r3, 1
-; CHECK-LE-NEXT:    and r3, r3, r4
-; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    clrldi r3, r5, 32
+; CHECK-LE-NEXT:    li r4, 2
+; CHECK-LE-NEXT:    andc r4, r4, r3
+; CHECK-LE-NEXT:    sldi r4, r4, 2
+; CHECK-LE-NEXT:    lvsl v3, 0, r4
+; CHECK-LE-NEXT:    li r4, 1
+; CHECK-LE-NEXT:    and r3, r4, r3
 ; CHECK-LE-NEXT:    sldi r3, r3, 5
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-LE-NEXT:    mfvsrd r4, v2
 ; CHECK-LE-NEXT:    srd r3, r4, r3
 ; CHECK-LE-NEXT:    extsw r3, r3
@@ -2032,12 +2032,12 @@ define signext i32 @getvelsi(<4 x i32> %vsi, i32 signext %i) {
 ; CHECK-AIX-LABEL: getvelsi:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    clrldi 3, 3, 32
+; CHECK-AIX-NEXT:    andi. 4, 3, 2
+; CHECK-AIX-NEXT:    sldi 4, 4, 2
+; CHECK-AIX-NEXT:    lvsl 3, 0, 4
 ; CHECK-AIX-NEXT:    li 4, 1
-; CHECK-AIX-NEXT:    andi. 5, 3, 2
 ; CHECK-AIX-NEXT:    andc 3, 4, 3
-; CHECK-AIX-NEXT:    sldi 5, 5, 2
 ; CHECK-AIX-NEXT:    sldi 3, 3, 5
-; CHECK-AIX-NEXT:    lvsl 3, 0, 5
 ; CHECK-AIX-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-AIX-NEXT:    mfvsrd 4, 34
 ; CHECK-AIX-NEXT:    srd 3, 4, 3
@@ -2053,13 +2053,13 @@ entry:
 define zeroext i32 @getvelui(<4 x i32> %vui, i32 signext %i) {
 ; CHECK-LABEL: getvelui:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    clrldi r4, r5, 32
-; CHECK-NEXT:    li r3, 1
-; CHECK-NEXT:    andi. r5, r4, 2
-; CHECK-NEXT:    andc r3, r3, r4
-; CHECK-NEXT:    sldi r5, r5, 2
+; CHECK-NEXT:    clrldi r3, r5, 32
+; CHECK-NEXT:    andi. r4, r3, 2
+; CHECK-NEXT:    sldi r4, r4, 2
+; CHECK-NEXT:    lvsl v3, 0, r4
+; CHECK-NEXT:    li r4, 1
+; CHECK-NEXT:    andc r3, r4, r3
 ; CHECK-NEXT:    sldi r3, r3, 5
-; CHECK-NEXT:    lvsl v3, 0, r5
 ; CHECK-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-NEXT:    mfvsrd r4, v2
 ; CHECK-NEXT:    srd r3, r4, r3
@@ -2068,15 +2068,15 @@ define zeroext i32 @getvelui(<4 x i32> %vui, i32 signext %i) {
 ;
 ; CHECK-LE-LABEL: getvelui:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    li r3, 2
-; CHECK-LE-NEXT:    clrldi r4, r5, 32
-; CHECK-LE-NEXT:    andc r3, r3, r4
-; CHECK-LE-NEXT:    sldi r3, r3, 2
-; CHECK-LE-NEXT:    lvsl v3, 0, r3
-; CHECK-LE-NEXT:    li r3, 1
-; CHECK-LE-NEXT:    and r3, r3, r4
-; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
+; CHECK-LE-NEXT:    clrldi r3, r5, 32
+; CHECK-LE-NEXT:    li r4, 2
+; CHECK-LE-NEXT:    andc r4, r4, r3
+; CHECK-LE-NEXT:    sldi r4, r4, 2
+; CHECK-LE-NEXT:    lvsl v3, 0, r4
+; CHECK-LE-NEXT:    li r4, 1
+; CHECK-LE-NEXT:    and r3, r4, r3
 ; CHECK-LE-NEXT:    sldi r3, r3, 5
+; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
 ; CHECK-LE-NEXT:    mfvsrd r4, v2
 ; CHECK-LE-NEXT:    srd r3, r4, r3
 ; CHECK-LE-NEXT:    clrldi r3, r3, 32
@@ -2085,12 +2085,12 @@ define zeroext i32 @getvelui(<4 x i32> %vui, i32 signext %i) {
 ; CHECK-AIX-LABEL: getvelui:
 ; CHECK-AIX:       # %bb.0: # %entry
 ; CHECK-AIX-NEXT:    clrldi 3, 3, 32
+; CHECK-AIX-NEXT:    andi. 4, 3, 2
+; CHECK-AIX-NEXT:    sldi 4, 4, 2
+; CHECK-AIX-NEXT:    lvsl 3, 0, 4
 ; CHECK-AIX-NEXT:    li 4, 1
-; CHECK-AIX-NEXT:    andi. 5, 3, 2
 ; CHECK-AIX-NEXT:    andc 3, 4, 3
-; CHECK-AIX-NEXT:    sldi 5, 5, 2
 ; CHECK-AIX-NEXT:    sldi 3, 3, 5
-; CHECK-AIX-NEXT:    lvsl 3, 0, 5
 ; CHECK-AIX-NEXT:    vperm 2, 2, 2, 3
 ; CHECK-AIX-NEXT:    mfvsrd 4, 34
 ; CHECK-AIX-NEXT:    srd 3, 4, 3
@@ -2214,9 +2214,9 @@ define i64 @getvelsl(<2 x i64> %vsl, i32 signext %i) {
 ;
 ; CHECK-LE-LABEL: getvelsl:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    li r3, 1
-; CHECK-LE-NEXT:    clrldi r4, r5, 32
-; CHECK-LE-NEXT:    andc r3, r3, r4
+; CHECK-LE-NEXT:    clrldi r3, r5, 32
+; CHECK-LE-NEXT:    li r4, 1
+; CHECK-LE-NEXT:    andc r3, r4, r3
 ; CHECK-LE-NEXT:    sldi r3, r3, 3
 ; CHECK-LE-NEXT:    lvsl v3, 0, r3
 ; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
@@ -2252,9 +2252,9 @@ define i64 @getvelul(<2 x i64> %vul, i32 signext %i) {
 ;
 ; CHECK-LE-LABEL: getvelul:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    li r3, 1
-; CHECK-LE-NEXT:    clrldi r4, r5, 32
-; CHECK-LE-NEXT:    andc r3, r3, r4
+; CHECK-LE-NEXT:    clrldi r3, r5, 32
+; CHECK-LE-NEXT:    li r4, 1
+; CHECK-LE-NEXT:    andc r3, r4, r3
 ; CHECK-LE-NEXT:    sldi r3, r3, 3
 ; CHECK-LE-NEXT:    lvsl v3, 0, r3
 ; CHECK-LE-NEXT:    vperm v2, v2, v2, v3
@@ -2472,9 +2472,9 @@ define double @getveld(<2 x double> %vd, i32 signext %i) {
 ;
 ; CHECK-LE-LABEL: getveld:
 ; CHECK-LE:       # %bb.0: # %entry
-; CHECK-LE-NEXT:    li r3, 1
-; CHECK-LE-NEXT:    clrldi r4, r5, 32
-; CHECK-LE-NEXT:    andc r3, r3, r4
+; CHECK-LE-NEXT:    clrldi r3, r5, 32
+; CHECK-LE-NEXT:    li r4, 1
+; CHECK-LE-NEXT:    andc r3, r4, r3
 ; CHECK-LE-NEXT:    sldi r3, r3, 3
 ; CHECK-LE-NEXT:    lvsl v3, 0, r3
 ; CHECK-LE-NEXT:    vperm v2, v2, v2, v3

diff --git a/llvm/test/CodeGen/PowerPC/peephole-align.ll b/llvm/test/CodeGen/PowerPC/peephole-align.ll
@@ -1,4 +1,4 @@
-; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -O1 -code-model=medium <%s | FileCheck %s
+; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr7 -O1 -code-model=medium <%s | FileCheck %s -check-prefix=P7
 ; RUN: llc -relocation-model=static -verify-machineinstrs -mcpu=pwr8 -O1 -code-model=medium <%s | FileCheck %s
 
 ; Test peephole optimization for medium code model (32-bit TOC offsets)
@@ -208,13 +208,21 @@ entry:
 
 ; CHECK-LABEL: test_d2:
 ; CHECK: addis [[REGSTRUCT:[0-9]+]], 2, d2v@toc@ha
+; CHECK: ld [[REG0_0:[0-9]+]], d2v@toc@l([[REGSTRUCT]])
 ; CHECK: addi [[BASEV:[0-9]+]], [[REGSTRUCT]], d2v@toc@l
-; CHECK-DAG: ld [[REG0_0:[0-9]+]], d2v@toc@l([[REGSTRUCT]])
-; CHECK-DAG: ld [[REG1_0:[0-9]+]], 8([[BASEV]])
 ; CHECK-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1
+; CHECK-DAG: ld [[REG1_0:[0-9]+]], 8([[BASEV]])
 ; CHECK-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2
 ; CHECK-DAG: std [[REG0_1]], d2v@toc@l([[REGSTRUCT]])
 ; CHECK-DAG: std [[REG1_1]], 8([[BASEV]])
+; P7: addis [[REGSTRUCT:[0-9]+]], 2, d2v@toc@ha
+; P7: addi [[BASEV:[0-9]+]], [[REGSTRUCT]], d2v@toc@l
+; P7: ld [[REG0_0:[0-9]+]], d2v@toc@l([[REGSTRUCT]])
+; P7-DAG: addi [[REG0_1:[0-9]+]], [[REG0_0]], 1
+; P7-DAG: ld [[REG1_0:[0-9]+]], 8([[BASEV]])
+; P7-DAG: addi [[REG1_1:[0-9]+]], [[REG1_0]], 2
+; P7-DAG: std [[REG0_1]], d2v@toc@l([[REGSTRUCT]])
+; P7-DAG: std [[REG1_1]], 8([[BASEV]])
 
 define dso_local void @test_d2() nounwind {
 entry: