269 changes: 239 additions & 30 deletions llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv32.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,7 @@ define <vscale x 1 x i16> @intrinsic_vwsub.w_wv_nxv1i16_nxv1i16_nxv1i8(<vscale x
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vwsub.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8(
Expand Down Expand Up @@ -55,8 +54,7 @@ define <vscale x 2 x i16> @intrinsic_vwsub.w_wv_nxv2i16_nxv2i16_nxv2i8(<vscale x
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vwsub.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8(
Expand Down Expand Up @@ -100,8 +98,7 @@ define <vscale x 4 x i16> @intrinsic_vwsub.w_wv_nxv4i16_nxv4i16_nxv4i8(<vscale x
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vwsub.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsub.w.nxv4i16.nxv4i8(
Expand Down Expand Up @@ -145,8 +142,7 @@ define <vscale x 8 x i16> @intrinsic_vwsub.w_wv_nxv8i16_nxv8i16_nxv8i8(<vscale x
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vwsub.wv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: vwsub.wv v8, v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsub.w.nxv8i16.nxv8i8(
Expand Down Expand Up @@ -190,8 +186,7 @@ define <vscale x 16 x i16> @intrinsic_vwsub.w_wv_nxv16i16_nxv16i16_nxv16i8(<vsca
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vwsub.wv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: vwsub.wv v8, v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsub.w.nxv16i16.nxv16i8(
Expand Down Expand Up @@ -235,8 +230,7 @@ define <vscale x 32 x i16> @intrinsic_vwsub.w_wv_nxv32i16_nxv32i16_nxv32i8(<vsca
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vwsub.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: vwsub.wv v8, v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsub.w.nxv32i16.nxv32i8(
Expand Down Expand Up @@ -281,8 +275,7 @@ define <vscale x 1 x i32> @intrinsic_vwsub.w_wv_nxv1i32_nxv1i32_nxv1i16(<vscale
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vwsub.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsub.w.nxv1i32.nxv1i16(
Expand Down Expand Up @@ -326,8 +319,7 @@ define <vscale x 2 x i32> @intrinsic_vwsub.w_wv_nxv2i32_nxv2i32_nxv2i16(<vscale
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vwsub.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsub.w.nxv2i32.nxv2i16(
Expand Down Expand Up @@ -371,8 +363,7 @@ define <vscale x 4 x i32> @intrinsic_vwsub.w_wv_nxv4i32_nxv4i32_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vwsub.wv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: vwsub.wv v8, v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsub.w.nxv4i32.nxv4i16(
Expand Down Expand Up @@ -416,8 +407,7 @@ define <vscale x 8 x i32> @intrinsic_vwsub.w_wv_nxv8i32_nxv8i32_nxv8i16(<vscale
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vwsub.wv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: vwsub.wv v8, v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsub.w.nxv8i32.nxv8i16(
Expand Down Expand Up @@ -461,8 +451,7 @@ define <vscale x 16 x i32> @intrinsic_vwsub.w_wv_nxv16i32_nxv16i32_nxv16i16(<vsc
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vwsub.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: vwsub.wv v8, v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsub.w.nxv16i32.nxv16i16(
Expand Down Expand Up @@ -507,8 +496,7 @@ define <vscale x 1 x i64> @intrinsic_vwsub.w_wv_nxv1i64_nxv1i64_nxv1i32(<vscale
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vwsub.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsub.w.nxv1i64.nxv1i32(
Expand Down Expand Up @@ -552,8 +540,7 @@ define <vscale x 2 x i64> @intrinsic_vwsub.w_wv_nxv2i64_nxv2i64_nxv2i32(<vscale
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vwsub.wv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: vwsub.wv v8, v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsub.w.nxv2i64.nxv2i32(
Expand Down Expand Up @@ -597,8 +584,7 @@ define <vscale x 4 x i64> @intrinsic_vwsub.w_wv_nxv4i64_nxv4i64_nxv4i32(<vscale
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vwsub.wv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: vwsub.wv v8, v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsub.w.nxv4i64.nxv4i32(
Expand Down Expand Up @@ -642,8 +628,7 @@ define <vscale x 8 x i64> @intrinsic_vwsub.w_wv_nxv8i64_nxv8i64_nxv8i32(<vscale
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vwsub.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: vwsub.wv v8, v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsub.w.nxv8i64.nxv8i32(
Expand Down Expand Up @@ -1848,3 +1833,227 @@ entry:

ret <vscale x 8 x i64> %a
}

define <vscale x 1 x i16> @intrinsic_vwsub.w_wv_untie_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vwsub.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8(
<vscale x 1 x i16> %1,
<vscale x 1 x i8> %0,
i32 %2)

ret <vscale x 1 x i16> %a
}

define <vscale x 2 x i16> @intrinsic_vwsub.w_wv_untie_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vwsub.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8(
<vscale x 2 x i16> %1,
<vscale x 2 x i8> %0,
i32 %2)

ret <vscale x 2 x i16> %a
}

define <vscale x 4 x i16> @intrinsic_vwsub.w_wv_untie_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vwsub.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsub.w.nxv4i16.nxv4i8(
<vscale x 4 x i16> %1,
<vscale x 4 x i8> %0,
i32 %2)

ret <vscale x 4 x i16> %a
}

define <vscale x 8 x i16> @intrinsic_vwsub.w_wv_untie_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vwsub.wv v26, v10, v8
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsub.w.nxv8i16.nxv8i8(
<vscale x 8 x i16> %1,
<vscale x 8 x i8> %0,
i32 %2)

ret <vscale x 8 x i16> %a
}

define <vscale x 16 x i16> @intrinsic_vwsub.w_wv_untie_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vwsub.wv v28, v12, v8
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsub.w.nxv16i16.nxv16i8(
<vscale x 16 x i16> %1,
<vscale x 16 x i8> %0,
i32 %2)

ret <vscale x 16 x i16> %a
}

define <vscale x 32 x i16> @intrinsic_vwsub.w_wv_untie_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vwsub.wv v24, v16, v8
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsub.w.nxv32i16.nxv32i8(
<vscale x 32 x i16> %1,
<vscale x 32 x i8> %0,
i32 %2)

ret <vscale x 32 x i16> %a
}

define <vscale x 1 x i32> @intrinsic_vwsub.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vwsub.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsub.w.nxv1i32.nxv1i16(
<vscale x 1 x i32> %1,
<vscale x 1 x i16> %0,
i32 %2)

ret <vscale x 1 x i32> %a
}

define <vscale x 2 x i32> @intrinsic_vwsub.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vwsub.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsub.w.nxv2i32.nxv2i16(
<vscale x 2 x i32> %1,
<vscale x 2 x i16> %0,
i32 %2)

ret <vscale x 2 x i32> %a
}

define <vscale x 4 x i32> @intrinsic_vwsub.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vwsub.wv v26, v10, v8
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsub.w.nxv4i32.nxv4i16(
<vscale x 4 x i32> %1,
<vscale x 4 x i16> %0,
i32 %2)

ret <vscale x 4 x i32> %a
}

define <vscale x 8 x i32> @intrinsic_vwsub.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vwsub.wv v28, v12, v8
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsub.w.nxv8i32.nxv8i16(
<vscale x 8 x i32> %1,
<vscale x 8 x i16> %0,
i32 %2)

ret <vscale x 8 x i32> %a
}

define <vscale x 1 x i64> @intrinsic_vwsub.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vwsub.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsub.w.nxv1i64.nxv1i32(
<vscale x 1 x i64> %1,
<vscale x 1 x i32> %0,
i32 %2)

ret <vscale x 1 x i64> %a
}

define <vscale x 2 x i64> @intrinsic_vwsub.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vwsub.wv v26, v10, v8
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsub.w.nxv2i64.nxv2i32(
<vscale x 2 x i64> %1,
<vscale x 2 x i32> %0,
i32 %2)

ret <vscale x 2 x i64> %a
}

define <vscale x 4 x i64> @intrinsic_vwsub.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vwsub.wv v28, v12, v8
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsub.w.nxv4i64.nxv4i32(
<vscale x 4 x i64> %1,
<vscale x 4 x i32> %0,
i32 %2)

ret <vscale x 4 x i64> %a
}

define <vscale x 8 x i64> @intrinsic_vwsub.w_wv_untie_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vwsub.wv v24, v16, v8
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsub.w.nxv8i64.nxv8i32(
<vscale x 8 x i64> %1,
<vscale x 8 x i32> %0,
i32 %2)

ret <vscale x 8 x i64> %a
}
269 changes: 239 additions & 30 deletions llvm/test/CodeGen/RISCV/rvv/vwsub.w-rv64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,7 @@ define <vscale x 1 x i16> @intrinsic_vwsub.w_wv_nxv1i16_nxv1i16_nxv1i8(<vscale x
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vwsub.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8(
Expand Down Expand Up @@ -55,8 +54,7 @@ define <vscale x 2 x i16> @intrinsic_vwsub.w_wv_nxv2i16_nxv2i16_nxv2i8(<vscale x
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vwsub.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8(
Expand Down Expand Up @@ -100,8 +98,7 @@ define <vscale x 4 x i16> @intrinsic_vwsub.w_wv_nxv4i16_nxv4i16_nxv4i8(<vscale x
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vwsub.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsub.w.nxv4i16.nxv4i8(
Expand Down Expand Up @@ -145,8 +142,7 @@ define <vscale x 8 x i16> @intrinsic_vwsub.w_wv_nxv8i16_nxv8i16_nxv8i8(<vscale x
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vwsub.wv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: vwsub.wv v8, v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsub.w.nxv8i16.nxv8i8(
Expand Down Expand Up @@ -190,8 +186,7 @@ define <vscale x 16 x i16> @intrinsic_vwsub.w_wv_nxv16i16_nxv16i16_nxv16i8(<vsca
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vwsub.wv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: vwsub.wv v8, v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsub.w.nxv16i16.nxv16i8(
Expand Down Expand Up @@ -235,8 +230,7 @@ define <vscale x 32 x i16> @intrinsic_vwsub.w_wv_nxv32i16_nxv32i16_nxv32i8(<vsca
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vwsub.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: vwsub.wv v8, v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsub.w.nxv32i16.nxv32i8(
Expand Down Expand Up @@ -281,8 +275,7 @@ define <vscale x 1 x i32> @intrinsic_vwsub.w_wv_nxv1i32_nxv1i32_nxv1i16(<vscale
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vwsub.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsub.w.nxv1i32.nxv1i16(
Expand Down Expand Up @@ -326,8 +319,7 @@ define <vscale x 2 x i32> @intrinsic_vwsub.w_wv_nxv2i32_nxv2i32_nxv2i16(<vscale
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vwsub.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsub.w.nxv2i32.nxv2i16(
Expand Down Expand Up @@ -371,8 +363,7 @@ define <vscale x 4 x i32> @intrinsic_vwsub.w_wv_nxv4i32_nxv4i32_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vwsub.wv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: vwsub.wv v8, v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsub.w.nxv4i32.nxv4i16(
Expand Down Expand Up @@ -416,8 +407,7 @@ define <vscale x 8 x i32> @intrinsic_vwsub.w_wv_nxv8i32_nxv8i32_nxv8i16(<vscale
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vwsub.wv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: vwsub.wv v8, v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsub.w.nxv8i32.nxv8i16(
Expand Down Expand Up @@ -461,8 +451,7 @@ define <vscale x 16 x i32> @intrinsic_vwsub.w_wv_nxv16i32_nxv16i32_nxv16i16(<vsc
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vwsub.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: vwsub.wv v8, v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsub.w.nxv16i32.nxv16i16(
Expand Down Expand Up @@ -507,8 +496,7 @@ define <vscale x 1 x i64> @intrinsic_vwsub.w_wv_nxv1i64_nxv1i64_nxv1i32(<vscale
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vwsub.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsub.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsub.w.nxv1i64.nxv1i32(
Expand Down Expand Up @@ -552,8 +540,7 @@ define <vscale x 2 x i64> @intrinsic_vwsub.w_wv_nxv2i64_nxv2i64_nxv2i32(<vscale
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vwsub.wv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: vwsub.wv v8, v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsub.w.nxv2i64.nxv2i32(
Expand Down Expand Up @@ -597,8 +584,7 @@ define <vscale x 4 x i64> @intrinsic_vwsub.w_wv_nxv4i64_nxv4i64_nxv4i32(<vscale
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vwsub.wv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: vwsub.wv v8, v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsub.w.nxv4i64.nxv4i32(
Expand Down Expand Up @@ -642,8 +628,7 @@ define <vscale x 8 x i64> @intrinsic_vwsub.w_wv_nxv8i64_nxv8i64_nxv8i32(<vscale
; CHECK-LABEL: intrinsic_vwsub.w_wv_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vwsub.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: vwsub.wv v8, v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsub.w.nxv8i64.nxv8i32(
Expand Down Expand Up @@ -1848,3 +1833,227 @@ entry:

ret <vscale x 8 x i64> %a
}

define <vscale x 1 x i16> @intrinsic_vwsub.w_wv_untie_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vwsub.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsub.w.nxv1i16.nxv1i8(
<vscale x 1 x i16> %1,
<vscale x 1 x i8> %0,
i64 %2)

ret <vscale x 1 x i16> %a
}

define <vscale x 2 x i16> @intrinsic_vwsub.w_wv_untie_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vwsub.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsub.w.nxv2i16.nxv2i8(
<vscale x 2 x i16> %1,
<vscale x 2 x i8> %0,
i64 %2)

ret <vscale x 2 x i16> %a
}

define <vscale x 4 x i16> @intrinsic_vwsub.w_wv_untie_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vwsub.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsub.w.nxv4i16.nxv4i8(
<vscale x 4 x i16> %1,
<vscale x 4 x i8> %0,
i64 %2)

ret <vscale x 4 x i16> %a
}

define <vscale x 8 x i16> @intrinsic_vwsub.w_wv_untie_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vwsub.wv v26, v10, v8
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsub.w.nxv8i16.nxv8i8(
<vscale x 8 x i16> %1,
<vscale x 8 x i8> %0,
i64 %2)

ret <vscale x 8 x i16> %a
}

define <vscale x 16 x i16> @intrinsic_vwsub.w_wv_untie_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vwsub.wv v28, v12, v8
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsub.w.nxv16i16.nxv16i8(
<vscale x 16 x i16> %1,
<vscale x 16 x i8> %0,
i64 %2)

ret <vscale x 16 x i16> %a
}

define <vscale x 32 x i16> @intrinsic_vwsub.w_wv_untie_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vwsub.wv v24, v16, v8
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsub.w.nxv32i16.nxv32i8(
<vscale x 32 x i16> %1,
<vscale x 32 x i8> %0,
i64 %2)

ret <vscale x 32 x i16> %a
}

define <vscale x 1 x i32> @intrinsic_vwsub.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vwsub.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsub.w.nxv1i32.nxv1i16(
<vscale x 1 x i32> %1,
<vscale x 1 x i16> %0,
i64 %2)

ret <vscale x 1 x i32> %a
}

define <vscale x 2 x i32> @intrinsic_vwsub.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vwsub.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsub.w.nxv2i32.nxv2i16(
<vscale x 2 x i32> %1,
<vscale x 2 x i16> %0,
i64 %2)

ret <vscale x 2 x i32> %a
}

define <vscale x 4 x i32> @intrinsic_vwsub.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vwsub.wv v26, v10, v8
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsub.w.nxv4i32.nxv4i16(
<vscale x 4 x i32> %1,
<vscale x 4 x i16> %0,
i64 %2)

ret <vscale x 4 x i32> %a
}

define <vscale x 8 x i32> @intrinsic_vwsub.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vwsub.wv v28, v12, v8
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsub.w.nxv8i32.nxv8i16(
<vscale x 8 x i32> %1,
<vscale x 8 x i16> %0,
i64 %2)

ret <vscale x 8 x i32> %a
}

define <vscale x 1 x i64> @intrinsic_vwsub.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vwsub.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsub.w.nxv1i64.nxv1i32(
<vscale x 1 x i64> %1,
<vscale x 1 x i32> %0,
i64 %2)

ret <vscale x 1 x i64> %a
}

define <vscale x 2 x i64> @intrinsic_vwsub.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vwsub.wv v26, v10, v8
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsub.w.nxv2i64.nxv2i32(
<vscale x 2 x i64> %1,
<vscale x 2 x i32> %0,
i64 %2)

ret <vscale x 2 x i64> %a
}

define <vscale x 4 x i64> @intrinsic_vwsub.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vwsub.wv v28, v12, v8
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsub.w.nxv4i64.nxv4i32(
<vscale x 4 x i64> %1,
<vscale x 4 x i32> %0,
i64 %2)

ret <vscale x 4 x i64> %a
}

define <vscale x 8 x i64> @intrinsic_vwsub.w_wv_untie_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsub.w_wv_untie_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vwsub.wv v24, v16, v8
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsub.w.nxv8i64.nxv8i32(
<vscale x 8 x i64> %1,
<vscale x 8 x i32> %0,
i64 %2)

ret <vscale x 8 x i64> %a
}
269 changes: 239 additions & 30 deletions llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv32.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,7 @@ define <vscale x 1 x i16> @intrinsic_vwsubu.w_wv_nxv1i16_nxv1i16_nxv1i8(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8(
Expand Down Expand Up @@ -55,8 +54,7 @@ define <vscale x 2 x i16> @intrinsic_vwsubu.w_wv_nxv2i16_nxv2i16_nxv2i8(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8(
Expand Down Expand Up @@ -100,8 +98,7 @@ define <vscale x 4 x i16> @intrinsic_vwsubu.w_wv_nxv4i16_nxv4i16_nxv4i8(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.nxv4i16.nxv4i8(
Expand Down Expand Up @@ -145,8 +142,7 @@ define <vscale x 8 x i16> @intrinsic_vwsubu.w_wv_nxv8i16_nxv8i16_nxv8i8(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vwsubu.wv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: vwsubu.wv v8, v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.nxv8i16.nxv8i8(
Expand Down Expand Up @@ -190,8 +186,7 @@ define <vscale x 16 x i16> @intrinsic_vwsubu.w_wv_nxv16i16_nxv16i16_nxv16i8(<vsc
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vwsubu.wv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: vwsubu.wv v8, v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.nxv16i16.nxv16i8(
Expand Down Expand Up @@ -235,8 +230,7 @@ define <vscale x 32 x i16> @intrinsic_vwsubu.w_wv_nxv32i16_nxv32i16_nxv32i8(<vsc
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vwsubu.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: vwsubu.wv v8, v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.nxv32i16.nxv32i8(
Expand Down Expand Up @@ -281,8 +275,7 @@ define <vscale x 1 x i32> @intrinsic_vwsubu.w_wv_nxv1i32_nxv1i32_nxv1i16(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.nxv1i32.nxv1i16(
Expand Down Expand Up @@ -326,8 +319,7 @@ define <vscale x 2 x i32> @intrinsic_vwsubu.w_wv_nxv2i32_nxv2i32_nxv2i16(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.nxv2i32.nxv2i16(
Expand Down Expand Up @@ -371,8 +363,7 @@ define <vscale x 4 x i32> @intrinsic_vwsubu.w_wv_nxv4i32_nxv4i32_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vwsubu.wv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: vwsubu.wv v8, v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.nxv4i32.nxv4i16(
Expand Down Expand Up @@ -416,8 +407,7 @@ define <vscale x 8 x i32> @intrinsic_vwsubu.w_wv_nxv8i32_nxv8i32_nxv8i16(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vwsubu.wv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: vwsubu.wv v8, v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.nxv8i32.nxv8i16(
Expand Down Expand Up @@ -461,8 +451,7 @@ define <vscale x 16 x i32> @intrinsic_vwsubu.w_wv_nxv16i32_nxv16i32_nxv16i16(<vs
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vwsubu.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: vwsubu.wv v8, v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.nxv16i32.nxv16i16(
Expand Down Expand Up @@ -507,8 +496,7 @@ define <vscale x 1 x i64> @intrinsic_vwsubu.w_wv_nxv1i64_nxv1i64_nxv1i32(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.nxv1i64.nxv1i32(
Expand Down Expand Up @@ -552,8 +540,7 @@ define <vscale x 2 x i64> @intrinsic_vwsubu.w_wv_nxv2i64_nxv2i64_nxv2i32(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vwsubu.wv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: vwsubu.wv v8, v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.nxv2i64.nxv2i32(
Expand Down Expand Up @@ -597,8 +584,7 @@ define <vscale x 4 x i64> @intrinsic_vwsubu.w_wv_nxv4i64_nxv4i64_nxv4i32(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vwsubu.wv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: vwsubu.wv v8, v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.nxv4i32(
Expand Down Expand Up @@ -642,8 +628,7 @@ define <vscale x 8 x i64> @intrinsic_vwsubu.w_wv_nxv8i64_nxv8i64_nxv8i32(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vwsubu.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: vwsubu.wv v8, v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.nxv8i64.nxv8i32(
Expand Down Expand Up @@ -1848,3 +1833,227 @@ entry:

ret <vscale x 8 x i64> %a
}

define <vscale x 1 x i16> @intrinsic_vwsubu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8(
<vscale x 1 x i16> %1,
<vscale x 1 x i8> %0,
i32 %2)

ret <vscale x 1 x i16> %a
}

define <vscale x 2 x i16> @intrinsic_vwsubu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8(
<vscale x 2 x i16> %1,
<vscale x 2 x i8> %0,
i32 %2)

ret <vscale x 2 x i16> %a
}

define <vscale x 4 x i16> @intrinsic_vwsubu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.nxv4i16.nxv4i8(
<vscale x 4 x i16> %1,
<vscale x 4 x i8> %0,
i32 %2)

ret <vscale x 4 x i16> %a
}

define <vscale x 8 x i16> @intrinsic_vwsubu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vwsubu.wv v26, v10, v8
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.nxv8i16.nxv8i8(
<vscale x 8 x i16> %1,
<vscale x 8 x i8> %0,
i32 %2)

ret <vscale x 8 x i16> %a
}

define <vscale x 16 x i16> @intrinsic_vwsubu.w_wv_untie_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vwsubu.wv v28, v12, v8
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.nxv16i16.nxv16i8(
<vscale x 16 x i16> %1,
<vscale x 16 x i8> %0,
i32 %2)

ret <vscale x 16 x i16> %a
}

define <vscale x 32 x i16> @intrinsic_vwsubu.w_wv_untie_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vwsubu.wv v24, v16, v8
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.nxv32i16.nxv32i8(
<vscale x 32 x i16> %1,
<vscale x 32 x i8> %0,
i32 %2)

ret <vscale x 32 x i16> %a
}

define <vscale x 1 x i32> @intrinsic_vwsubu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.nxv1i32.nxv1i16(
<vscale x 1 x i32> %1,
<vscale x 1 x i16> %0,
i32 %2)

ret <vscale x 1 x i32> %a
}

define <vscale x 2 x i32> @intrinsic_vwsubu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.nxv2i32.nxv2i16(
<vscale x 2 x i32> %1,
<vscale x 2 x i16> %0,
i32 %2)

ret <vscale x 2 x i32> %a
}

define <vscale x 4 x i32> @intrinsic_vwsubu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vwsubu.wv v26, v10, v8
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.nxv4i32.nxv4i16(
<vscale x 4 x i32> %1,
<vscale x 4 x i16> %0,
i32 %2)

ret <vscale x 4 x i32> %a
}

define <vscale x 8 x i32> @intrinsic_vwsubu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vwsubu.wv v28, v12, v8
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.nxv8i32.nxv8i16(
<vscale x 8 x i32> %1,
<vscale x 8 x i16> %0,
i32 %2)

ret <vscale x 8 x i32> %a
}

define <vscale x 1 x i64> @intrinsic_vwsubu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.nxv1i64.nxv1i32(
<vscale x 1 x i64> %1,
<vscale x 1 x i32> %0,
i32 %2)

ret <vscale x 1 x i64> %a
}

define <vscale x 2 x i64> @intrinsic_vwsubu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vwsubu.wv v26, v10, v8
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.nxv2i64.nxv2i32(
<vscale x 2 x i64> %1,
<vscale x 2 x i32> %0,
i32 %2)

ret <vscale x 2 x i64> %a
}

define <vscale x 4 x i64> @intrinsic_vwsubu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vwsubu.wv v28, v12, v8
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.nxv4i32(
<vscale x 4 x i64> %1,
<vscale x 4 x i32> %0,
i32 %2)

ret <vscale x 4 x i64> %a
}

define <vscale x 8 x i64> @intrinsic_vwsubu.w_wv_untie_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, i32 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vwsubu.wv v24, v16, v8
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.nxv8i64.nxv8i32(
<vscale x 8 x i64> %1,
<vscale x 8 x i32> %0,
i32 %2)

ret <vscale x 8 x i64> %a
}
269 changes: 239 additions & 30 deletions llvm/test/CodeGen/RISCV/rvv/vwsubu.w-rv64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,8 +10,7 @@ define <vscale x 1 x i16> @intrinsic_vwsubu.w_wv_nxv1i16_nxv1i16_nxv1i8(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8(
Expand Down Expand Up @@ -55,8 +54,7 @@ define <vscale x 2 x i16> @intrinsic_vwsubu.w_wv_nxv2i16_nxv2i16_nxv2i8(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8(
Expand Down Expand Up @@ -100,8 +98,7 @@ define <vscale x 4 x i16> @intrinsic_vwsubu.w_wv_nxv4i16_nxv4i16_nxv4i8(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.nxv4i16.nxv4i8(
Expand Down Expand Up @@ -145,8 +142,7 @@ define <vscale x 8 x i16> @intrinsic_vwsubu.w_wv_nxv8i16_nxv8i16_nxv8i8(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vwsubu.wv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: vwsubu.wv v8, v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.nxv8i16.nxv8i8(
Expand Down Expand Up @@ -190,8 +186,7 @@ define <vscale x 16 x i16> @intrinsic_vwsubu.w_wv_nxv16i16_nxv16i16_nxv16i8(<vsc
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vwsubu.wv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: vwsubu.wv v8, v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.nxv16i16.nxv16i8(
Expand Down Expand Up @@ -235,8 +230,7 @@ define <vscale x 32 x i16> @intrinsic_vwsubu.w_wv_nxv32i16_nxv32i16_nxv32i8(<vsc
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vwsubu.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: vwsubu.wv v8, v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.nxv32i16.nxv32i8(
Expand Down Expand Up @@ -281,8 +275,7 @@ define <vscale x 1 x i32> @intrinsic_vwsubu.w_wv_nxv1i32_nxv1i32_nxv1i16(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.nxv1i32.nxv1i16(
Expand Down Expand Up @@ -326,8 +319,7 @@ define <vscale x 2 x i32> @intrinsic_vwsubu.w_wv_nxv2i32_nxv2i32_nxv2i16(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.nxv2i32.nxv2i16(
Expand Down Expand Up @@ -371,8 +363,7 @@ define <vscale x 4 x i32> @intrinsic_vwsubu.w_wv_nxv4i32_nxv4i32_nxv4i16(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vwsubu.wv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: vwsubu.wv v8, v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.nxv4i32.nxv4i16(
Expand Down Expand Up @@ -416,8 +407,7 @@ define <vscale x 8 x i32> @intrinsic_vwsubu.w_wv_nxv8i32_nxv8i32_nxv8i16(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vwsubu.wv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: vwsubu.wv v8, v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.nxv8i32.nxv8i16(
Expand Down Expand Up @@ -461,8 +451,7 @@ define <vscale x 16 x i32> @intrinsic_vwsubu.w_wv_nxv16i32_nxv16i32_nxv16i16(<vs
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv16i32_nxv16i32_nxv16i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vwsubu.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: vwsubu.wv v8, v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i32> @llvm.riscv.vwsubu.w.nxv16i32.nxv16i16(
Expand Down Expand Up @@ -507,8 +496,7 @@ define <vscale x 1 x i64> @intrinsic_vwsubu.w_wv_nxv1i64_nxv1i64_nxv1i32(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v8, v9
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: vwsubu.wv v8, v8, v9
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.nxv1i64.nxv1i32(
Expand Down Expand Up @@ -552,8 +540,7 @@ define <vscale x 2 x i64> @intrinsic_vwsubu.w_wv_nxv2i64_nxv2i64_nxv2i32(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vwsubu.wv v26, v8, v10
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: vwsubu.wv v8, v8, v10
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.nxv2i64.nxv2i32(
Expand Down Expand Up @@ -597,8 +584,7 @@ define <vscale x 4 x i64> @intrinsic_vwsubu.w_wv_nxv4i64_nxv4i64_nxv4i32(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vwsubu.wv v28, v8, v12
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: vwsubu.wv v8, v8, v12
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.nxv4i32(
Expand Down Expand Up @@ -642,8 +628,7 @@ define <vscale x 8 x i64> @intrinsic_vwsubu.w_wv_nxv8i64_nxv8i64_nxv8i32(<vscale
; CHECK-LABEL: intrinsic_vwsubu.w_wv_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vwsubu.wv v24, v8, v16
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: vwsubu.wv v8, v8, v16
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.nxv8i64.nxv8i32(
Expand Down Expand Up @@ -1848,3 +1833,227 @@ entry:

ret <vscale x 8 x i64> %a
}

define <vscale x 1 x i16> @intrinsic_vwsubu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8(<vscale x 1 x i8> %0, <vscale x 1 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i16_nxv1i16_nxv1i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf8,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i16> @llvm.riscv.vwsubu.w.nxv1i16.nxv1i8(
<vscale x 1 x i16> %1,
<vscale x 1 x i8> %0,
i64 %2)

ret <vscale x 1 x i16> %a
}

define <vscale x 2 x i16> @intrinsic_vwsubu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8(<vscale x 2 x i8> %0, <vscale x 2 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i16_nxv2i16_nxv2i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf4,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i16> @llvm.riscv.vwsubu.w.nxv2i16.nxv2i8(
<vscale x 2 x i16> %1,
<vscale x 2 x i8> %0,
i64 %2)

ret <vscale x 2 x i16> %a
}

define <vscale x 4 x i16> @intrinsic_vwsubu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8(<vscale x 4 x i8> %0, <vscale x 4 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i16_nxv4i16_nxv4i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,mf2,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i16> @llvm.riscv.vwsubu.w.nxv4i16.nxv4i8(
<vscale x 4 x i16> %1,
<vscale x 4 x i8> %0,
i64 %2)

ret <vscale x 4 x i16> %a
}

define <vscale x 8 x i16> @intrinsic_vwsubu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8(<vscale x 8 x i8> %0, <vscale x 8 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv8i16_nxv8i16_nxv8i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m1,ta,mu
; CHECK-NEXT: vwsubu.wv v26, v10, v8
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i16> @llvm.riscv.vwsubu.w.nxv8i16.nxv8i8(
<vscale x 8 x i16> %1,
<vscale x 8 x i8> %0,
i64 %2)

ret <vscale x 8 x i16> %a
}

define <vscale x 16 x i16> @intrinsic_vwsubu.w_wv_untie_nxv16i16_nxv16i16_nxv16i8(<vscale x 16 x i8> %0, <vscale x 16 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv16i16_nxv16i16_nxv16i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m2,ta,mu
; CHECK-NEXT: vwsubu.wv v28, v12, v8
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: ret
entry:
%a = call <vscale x 16 x i16> @llvm.riscv.vwsubu.w.nxv16i16.nxv16i8(
<vscale x 16 x i16> %1,
<vscale x 16 x i8> %0,
i64 %2)

ret <vscale x 16 x i16> %a
}

define <vscale x 32 x i16> @intrinsic_vwsubu.w_wv_untie_nxv32i16_nxv32i16_nxv32i8(<vscale x 32 x i8> %0, <vscale x 32 x i16> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv32i16_nxv32i16_nxv32i8:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e8,m4,ta,mu
; CHECK-NEXT: vwsubu.wv v24, v16, v8
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 32 x i16> @llvm.riscv.vwsubu.w.nxv32i16.nxv32i8(
<vscale x 32 x i16> %1,
<vscale x 32 x i8> %0,
i64 %2)

ret <vscale x 32 x i16> %a
}

define <vscale x 1 x i32> @intrinsic_vwsubu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16(<vscale x 1 x i16> %0, <vscale x 1 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i32_nxv1i32_nxv1i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i32> @llvm.riscv.vwsubu.w.nxv1i32.nxv1i16(
<vscale x 1 x i32> %1,
<vscale x 1 x i16> %0,
i64 %2)

ret <vscale x 1 x i32> %a
}

define <vscale x 2 x i32> @intrinsic_vwsubu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16(<vscale x 2 x i16> %0, <vscale x 2 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i32_nxv2i32_nxv2i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i32> @llvm.riscv.vwsubu.w.nxv2i32.nxv2i16(
<vscale x 2 x i32> %1,
<vscale x 2 x i16> %0,
i64 %2)

ret <vscale x 2 x i32> %a
}

define <vscale x 4 x i32> @intrinsic_vwsubu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16(<vscale x 4 x i16> %0, <vscale x 4 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i32_nxv4i32_nxv4i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vwsubu.wv v26, v10, v8
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i32> @llvm.riscv.vwsubu.w.nxv4i32.nxv4i16(
<vscale x 4 x i32> %1,
<vscale x 4 x i16> %0,
i64 %2)

ret <vscale x 4 x i32> %a
}

define <vscale x 8 x i32> @intrinsic_vwsubu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16(<vscale x 8 x i16> %0, <vscale x 8 x i32> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv8i32_nxv8i32_nxv8i16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vwsubu.wv v28, v12, v8
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i32> @llvm.riscv.vwsubu.w.nxv8i32.nxv8i16(
<vscale x 8 x i32> %1,
<vscale x 8 x i16> %0,
i64 %2)

ret <vscale x 8 x i32> %a
}

define <vscale x 1 x i64> @intrinsic_vwsubu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32(<vscale x 1 x i32> %0, <vscale x 1 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv1i64_nxv1i64_nxv1i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vwsubu.wv v25, v9, v8
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
entry:
%a = call <vscale x 1 x i64> @llvm.riscv.vwsubu.w.nxv1i64.nxv1i32(
<vscale x 1 x i64> %1,
<vscale x 1 x i32> %0,
i64 %2)

ret <vscale x 1 x i64> %a
}

define <vscale x 2 x i64> @intrinsic_vwsubu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32(<vscale x 2 x i32> %0, <vscale x 2 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv2i64_nxv2i64_nxv2i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vwsubu.wv v26, v10, v8
; CHECK-NEXT: vmv2r.v v8, v26
; CHECK-NEXT: ret
entry:
%a = call <vscale x 2 x i64> @llvm.riscv.vwsubu.w.nxv2i64.nxv2i32(
<vscale x 2 x i64> %1,
<vscale x 2 x i32> %0,
i64 %2)

ret <vscale x 2 x i64> %a
}

define <vscale x 4 x i64> @intrinsic_vwsubu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32(<vscale x 4 x i32> %0, <vscale x 4 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv4i64_nxv4i64_nxv4i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vwsubu.wv v28, v12, v8
; CHECK-NEXT: vmv4r.v v8, v28
; CHECK-NEXT: ret
entry:
%a = call <vscale x 4 x i64> @llvm.riscv.vwsubu.w.nxv4i64.nxv4i32(
<vscale x 4 x i64> %1,
<vscale x 4 x i32> %0,
i64 %2)

ret <vscale x 4 x i64> %a
}

define <vscale x 8 x i64> @intrinsic_vwsubu.w_wv_untie_nxv8i64_nxv8i64_nxv8i32(<vscale x 8 x i32> %0, <vscale x 8 x i64> %1, i64 %2) nounwind {
; CHECK-LABEL: intrinsic_vwsubu.w_wv_untie_nxv8i64_nxv8i64_nxv8i32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vwsubu.wv v24, v16, v8
; CHECK-NEXT: vmv8r.v v8, v24
; CHECK-NEXT: ret
entry:
%a = call <vscale x 8 x i64> @llvm.riscv.vwsubu.w.nxv8i64.nxv8i32(
<vscale x 8 x i64> %1,
<vscale x 8 x i32> %0,
i64 %2)

ret <vscale x 8 x i64> %a
}