295 changes: 295 additions & 0 deletions llvm/lib/Target/AArch64/SMEInstrFormats.td
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Expand Up @@ -2065,4 +2065,299 @@ multiclass sme2_multi_vec_array_vg4_index_64b<string mnemonic, bits<3> op,
(!cast<Instruction>(NAME) MatrixOp64:$ZAda, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3,
multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexD:$i1), 0>;
}
//===----------------------------------------------------------------------===//
// SME2 multi-vec indexed long long MLA one source 32-bit
class sme2_mla_ll_array_index_32b<string mnemonic, bits<3> op>
: I<(outs MatrixOp32:$ZAda),
(ins MatrixOp32:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm2s4range:$imm2, ZPR8:$Zn, ZPR4b8:$Zm, VectorIndexB:$i),
mnemonic, "\t$ZAda[$Rv, $imm2], $Zn, $Zm$i",
"", []>, Sched<[]> {
bits<4> Zm;
bits<2> Rv;
bits<4> i;
bits<5> Zn;
bits<2> imm2;
let Inst{31-20} = 0b110000010000;
let Inst{19-16} = Zm;
let Inst{15} = i{3};
let Inst{14-13} = Rv;
let Inst{12-10} = i{2-0};
let Inst{9-5} = Zn;
let Inst{4-2} = op;
let Inst{1-0} = imm2;

let Constraints = "$ZAda = $_ZAda";
}

// SME2 multi-vec indexed long long MLA one source 64-bit

class sme2_mla_ll_array_index_64b<string mnemonic, bits<2> op>
: I<(outs MatrixOp64:$ZAda),
(ins MatrixOp64:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm2s4range:$imm2, ZPR16:$Zn, ZPR4b16:$Zm, VectorIndexH:$i),
mnemonic, "\t$ZAda[$Rv, $imm2], $Zn, $Zm$i",
"", []>, Sched<[]> {
bits<4> Zm;
bits<2> Rv;
bits<3> i;
bits<5> Zn;
bits<2> imm2;
let Inst{31-20} = 0b110000011000;
let Inst{19-16} = Zm;
let Inst{15} = i{2};
let Inst{14-13} = Rv;
let Inst{12} = 0b0;
let Inst{11-10} = i{1-0};
let Inst{9-5} = Zn;
let Inst{4-3} = op;
let Inst{2} = 0b0;
let Inst{1-0} = imm2;

let Constraints = "$ZAda = $_ZAda";
}

class sme2_mla_ll_array_vg24_index_32b<bit vg4, bits<3> op,
RegisterOperand vector_ty,
string mnemonic>
: I<(outs MatrixOp32:$ZAda),
(ins MatrixOp32:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm1s4range:$imm,
vector_ty:$Zn, ZPR4b8:$Zm, VectorIndexB:$i),
mnemonic, "\t$ZAda[$Rv, $imm, " # !if(vg4, "vgx4", "vgx2") # "], $Zn, $Zm$i",
"", []>, Sched<[]> {
bits<4> Zm;
bits<2> Rv;
bits<4> i;
bit imm;
let Inst{31-20} = 0b110000010001;
let Inst{19-16} = Zm;
let Inst{15} = vg4;
let Inst{14-13} = Rv;
let Inst{12} = 0b0;
let Inst{11-10} = i{3-2};
let Inst{5-3} = op;
let Inst{2-1} = i{1-0};
let Inst{0} = imm;

let Constraints = "$ZAda = $_ZAda";
}

//SME2 multi-vec indexed long long MLA two sources 32-bit

multiclass sme2_mla_ll_array_vg2_index_32b<string mnemonic, bits<3> op> {
def NAME: sme2_mla_ll_array_vg24_index_32b<0b0, op, ZZ_b_mul_r, mnemonic> {
bits<4> Zn;
let Inst{9-6} = Zn;
}

def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm], $Zn, $Zm$i",
(!cast<Instruction>(NAME) MatrixOp32:$ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm1s4range:$imm, ZZ_b_mul_r:$Zn, ZPR4b8:$Zm, VectorIndexB:$i), 0>;
}

// SME2 multi-vec indexed long long MLA four sources 32-bit

multiclass sme2_mla_ll_array_vg4_index_32b<string mnemonic, bits<3> op> {
def NAME: sme2_mla_ll_array_vg24_index_32b<0b1, op, ZZZZ_b_mul_r, mnemonic> {
bits<3> Zn;
let Inst{9-7} = Zn;
let Inst{6} = 0b0;
}

def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm], $Zn, $Zm$i",
(!cast<Instruction>(NAME) MatrixOp32:$ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm1s4range:$imm, ZZZZ_b_mul_r:$Zn, ZPR4b8:$Zm, VectorIndexB:$i), 0>;
}
class sme2_mla_ll_array_vg24_index_64b<bit vg4, bits<2> op,
RegisterOperand vector_ty,
string mnemonic>
: I<(outs MatrixOp64:$ZAda),
(ins MatrixOp64:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm1s4range:$imm,
vector_ty:$Zn, ZPR4b16:$Zm, VectorIndexH:$i),
mnemonic, "\t$ZAda[$Rv, $imm, " # !if(vg4, "vgx4", "vgx2") # "], $Zn, $Zm$i",
"", []>, Sched<[]> {
bits<4> Zm;
bits<2> Rv;
bits<3> i;
bit imm;
let Inst{31-20} = 0b110000011001;
let Inst{19-16} = Zm;
let Inst{15} = vg4;
let Inst{14-13} = Rv;
let Inst{12-11} = 0b00;
let Inst{10} = i{2};
let Inst{5} = 0b0;
let Inst{4-3} = op;
let Inst{2-1} = i{1-0};
let Inst{0} = imm;

let Constraints = "$ZAda = $_ZAda";
}

// SME2 multi-vec indexed long long MLA two sources 64-bit

multiclass sme2_mla_ll_array_vg2_index_64b<string mnemonic, bits<2> op> {
def NAME: sme2_mla_ll_array_vg24_index_64b<0b0, op, ZZ_h_mul_r, mnemonic>{
bits<4> Zn;
let Inst{9-6} = Zn;
}

def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm], $Zn, $Zm$i",
(!cast<Instruction>(NAME) MatrixOp64:$ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm1s4range:$imm, ZZ_h_mul_r:$Zn, ZPR4b16:$Zm, VectorIndexH:$i), 0>;
}

// SME2 multi-vec indexed long long MLA four sources 64-bit

multiclass sme2_mla_ll_array_vg4_index_64b<string mnemonic, bits<2> op> {
def NAME: sme2_mla_ll_array_vg24_index_64b<0b1, op, ZZZZ_h_mul_r, mnemonic>{
bits<3> Zn;
let Inst{9-7} = Zn;
let Inst{6} = 0b0;
}

def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm], $Zn, $Zm$i",
(!cast<Instruction>(NAME) MatrixOp64:$ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm1s4range:$imm, ZZZZ_h_mul_r:$Zn, ZPR4b16:$Zm, VectorIndexH:$i), 0>;
}


//SME2 multiple and single vector long long FMA one source

class sme2_mla_ll_array_single<string mnemonic, bits<4> op,
MatrixOperand matrix_ty, ZPRRegOp vector_ty,
ZPRRegOp zpr_ty>
: I<(outs matrix_ty:$ZAda),
(ins matrix_ty:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm2s4range:$imm,
vector_ty:$Zn, zpr_ty:$Zm),
mnemonic, "\t$ZAda[$Rv, $imm], $Zn, $Zm",
"", []>, Sched<[]> {
bits<4> Zm;
bits<2> Rv;
bits<5> Zn;
bits<2> imm;
let Inst{31-23} = 0b110000010;
let Inst{22} = op{3}; //sz
let Inst{21-20} = 0b10;
let Inst{19-16} = Zm;
let Inst{15} = 0b0;
let Inst{14-13} = Rv;
let Inst{12-10} = 0b001;
let Inst{9-5} = Zn;
let Inst{4-2} = op{2-0};
let Inst{1-0} = imm;

let Constraints = "$ZAda = $_ZAda";
}

class sme2_mla_ll_array_vg24_single<bits<5> op, MatrixOperand matrix_ty,
RegisterOperand vector_ty, ZPRRegOp zpr_ty,
string mnemonic>
: I<(outs matrix_ty:$ZAda),
(ins matrix_ty:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm1s4range:$imm,
vector_ty:$Zn, zpr_ty:$Zm),
mnemonic, "\t$ZAda[$Rv, $imm, " # !if(op{3}, "vgx4", "vgx2") # "], $Zn, $Zm",
"", []>, Sched<[]> {
bits<4> Zm;
bits<2> Rv;
bits<5> Zn;
bit imm;
let Inst{31-23} = 0b110000010;
let Inst{22} = op{4}; //sz
let Inst{21} = 0b1;
let Inst{20} = op{3}; //vg4
let Inst{19-16} = Zm;
let Inst{15} = 0b0;
let Inst{14-13} = Rv;
let Inst{12-10} = 0b000;
let Inst{9-5} = Zn;
let Inst{4-2} = op{2-0};
let Inst{1} = 0b0;
let Inst{0} = imm;

let Constraints = "$ZAda = $_ZAda";
}

//SME2 single-multi long long MLA two and four sources

multiclass sme2_mla_ll_array_vg24_single<string mnemonic, bits<5> op,
MatrixOperand matrix_ty,
RegisterOperand multi_vector_ty,
ZPRRegOp zpr_ty> {
def NAME: sme2_mla_ll_array_vg24_single<op, matrix_ty, multi_vector_ty,
zpr_ty, mnemonic>;

def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm], $Zn, $Zm",
(!cast<Instruction>(NAME) matrix_ty:$ZAd, MatrixIndexGPR32Op8_11:$Rv, uimm1s4range:$imm, multi_vector_ty:$Zn, zpr_ty:$Zm), 0>;
}

// SME2 multiple vectors long long MLA two sources

class sme2_mla_ll_array_vg2_multi<bits<4> op, MatrixOperand matrix_ty,
RegisterOperand vector_ty,string mnemonic>
: I<(outs matrix_ty:$ZAda),
(ins matrix_ty:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm1s4range:$imm,
vector_ty:$Zn, vector_ty:$Zm),
mnemonic, "\t$ZAda[$Rv, $imm, vgx2], $Zn, $Zm",
"", []>, Sched<[]> {
bits<4> Zm;
bits<2> Rv;
bits<4> Zn;
bit imm;
let Inst{31-23} = 0b110000011;
let Inst{22} = op{3}; // sz
let Inst{21} = 0b1;
let Inst{20-17} = Zm;
let Inst{16-15} = 0b00;
let Inst{14-13} = Rv;
let Inst{12-10} = 0b000;
let Inst{9-6} = Zn;
let Inst{5} = 0b0;
let Inst{4-2} = op{2-0};
let Inst{1} = 0b0;
let Inst{0} = imm;

let Constraints = "$ZAda = $_ZAda";
}

multiclass sme2_mla_ll_array_vg2_multi<string mnemonic, bits<4> op,
MatrixOperand matrix_ty,
RegisterOperand vector_ty> {
def NAME : sme2_mla_ll_array_vg2_multi<op, matrix_ty, vector_ty, mnemonic>;

def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm], $Zn, $Zm",
(!cast<Instruction>(NAME) matrix_ty:$ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm1s4range:$imm, vector_ty:$Zn, vector_ty:$Zm), 0>;
}

// SME2 multiple vectors long long MLA four sources

class sme2_mla_ll_array_vg4_multi<bits<4> op,MatrixOperand matrix_ty,
RegisterOperand vector_ty,
string mnemonic>
: I<(outs matrix_ty:$ZAda),
(ins matrix_ty:$_ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm1s4range:$imm,
vector_ty:$Zn, vector_ty:$Zm),
mnemonic, "\t$ZAda[$Rv, $imm, vgx4], $Zn, $Zm",
"", []>, Sched<[]> {
bits<3> Zm;
bits<2> Rv;
bits<3> Zn;
bit imm;
let Inst{31-23} = 0b110000011;
let Inst{22} = op{3}; // sz
let Inst{21} = 0b1;
let Inst{20-18} = Zm;
let Inst{17-15} = 0b010;
let Inst{14-13} = Rv;
let Inst{12-10} = 0b000;
let Inst{9-7} = Zn;
let Inst{6-5} = 0b00;
let Inst{4-2} = op{2-0};
let Inst{1} = 0b0;
let Inst{0} = imm;

let Constraints = "$ZAda = $_ZAda";
}

multiclass sme2_mla_ll_array_vg4_multi<string mnemonic, bits<4> op,
MatrixOperand matrix_ty,
RegisterOperand vector_ty> {
def NAME : sme2_mla_ll_array_vg4_multi<op, matrix_ty, vector_ty, mnemonic>;

def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm], $Zn, $Zm",
(!cast<Instruction>(NAME) matrix_ty:$ZAda, MatrixIndexGPR32Op8_11:$Rv, uimm1s4range:$imm, vector_ty:$Zn, vector_ty:$Zm), 0>;
}
79 changes: 79 additions & 0 deletions llvm/test/MC/AArch64/SME2/smlall-diagnostics.s
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

smlall za.d[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smlall za.d[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

smlall za.d[w11, 6:7, vgx4], {z12.h-z17.h}, z8.h[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: smlall za.d[w11, 6:7, vgx4], {z12.h-z17.h}, z8.h[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

smlall za.s[w10, 4:7], {z8.b-z11.b}, {z21.b-z24.b}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: smlall za.s[w10, 4:7], {z8.b-z11.b}, {z21.b-z24.b}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid indexed-vector register

smlall za.s[w10, 0:3], z19.b, z4.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: smlall za.s[w10, 0:3], z19.b, z4.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

smlall za.d[w10, 4:7], z10.h, z30.h[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: smlall za.d[w10, 4:7], z10.h, z30.h[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select register

smlall za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: smlall za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

smlall za.s[w12, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: smlall za.s[w12, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select offset

smlall za.s[w11, 4:8], {z30.b-z31.b}, z15.b[15]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smlall za.s[w11, 4:8], {z30.b-z31.b}, z15.b[15]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

smlall za.d[w8, 5:8, vgx2], {z22.h-z23.h}, z14.h[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 4 in the range [0, 4] or [0, 12] depending on the instruction, and the second immediate is immf + 3.
// CHECK-NEXT: smlall za.d[w8, 5:8, vgx2], {z22.h-z23.h}, z14.h[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

smlall za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .d
// CHECK-NEXT: smlall za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector lane index

smlall za.s[w8, 0:3], {z0.b-z3.b}, z0.b[16]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
// CHECK-NEXT: smlall za.s[w8, 0:3], {z0.b-z3.b}, z0.b[16]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

smlall za.s[w8, 0:3], {z0.b-z3.b}, z0.b[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
// CHECK-NEXT: smlall za.s[w8, 0:3], {z0.b-z3.b}, z0.b[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
2,045 changes: 2,045 additions & 0 deletions llvm/test/MC/AArch64/SME2/smlall.s
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79 changes: 79 additions & 0 deletions llvm/test/MC/AArch64/SME2/smlsll-diagnostics.s
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

smlsll za.d[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smlsll za.d[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

smlsll za.d[w11, 6:7, vgx4], {z12.h-z17.h}, z8.h[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: smlsll za.d[w11, 6:7, vgx4], {z12.h-z17.h}, z8.h[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

smlsll za.s[w10, 4:7], {z8.b-z11.b}, {z21.b-z24.b}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: smlsll za.s[w10, 4:7], {z8.b-z11.b}, {z21.b-z24.b}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid indexed-vector register

smlsll za.s[w10, 0:3], z19.b, z4.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: smlsll za.s[w10, 0:3], z19.b, z4.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

smlsll za.d[w10, 4:7], z10.h, z30.h[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: smlsll za.d[w10, 4:7], z10.h, z30.h[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select register

smlsll za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: smlsll za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

smlsll za.s[w12, 6:7, vgx4], {z12.b-z15.b}, z8.b[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: smlsll za.s[w12, 6:7, vgx4], {z12.b-z15.b}, z8.b[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select offset

smlsll za.s[w11, 4:8], {z30.b-z31.b}, z15.b[15]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smlsll za.s[w11, 4:8], {z30.b-z31.b}, z15.b[15]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

smlsll za.d[w8, 5:8, vgx2], {z22.h-z23.h}, z14.h[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 4 in the range [0, 4] or [0, 12] depending on the instruction, and the second immediate is immf + 3.
// CHECK-NEXT: smlsll za.d[w8, 5:8, vgx2], {z22.h-z23.h}, z14.h[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

smlsll za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .d
// CHECK-NEXT: smlsll za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector lane index

smlsll za.s[w8, 0:3], {z0.b-z3.b}, z0.b[16]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
// CHECK-NEXT: smlsll za.s[w8, 0:3], {z0.b-z3.b}, z0.b[16]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

smlsll za.s[w8, 0:3], {z0.b-z3.b}, z0.b[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
// CHECK-NEXT: smlsll za.s[w8, 0:3], {z0.b-z3.b}, z0.b[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
2,045 changes: 2,045 additions & 0 deletions llvm/test/MC/AArch64/SME2/smlsll.s
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2 changes: 1 addition & 1 deletion llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i64 2>&1 < %s | FileCheck %s
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list
Expand Down
74 changes: 74 additions & 0 deletions llvm/test/MC/AArch64/SME2/sumlall-diagnostics.s
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Original file line number Diff line number Diff line change
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// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

sumlall za.s[w11, 4:7, vgx2], {z12.h-z14.h}, z8.h[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sumlall za.s[w11, 4:7, vgx2], {z12.h-z14.h}, z8.h[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

sumlall za.s[w11, 4:7, vgx4], {z12.h-z17.h}, z8.h[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: sumlall za.s[w11, 4:7, vgx4], {z12.h-z17.h}, z8.h[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid indexed-vector register

sumlall za.s[w10, 0:3], z19.b, z4.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: sumlall za.s[w10, 0:3], z19.b, z4.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

sumlall za.s[w10, 4:7], z10.b, z30.b[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: sumlall za.s[w10, 4:7], z10.b, z30.b[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select register

sumlall za.s[w7, 6:7, vgx2], {z12.b-z13.b}, z8.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: sumlall za.s[w7, 6:7, vgx2], {z12.b-z13.b}, z8.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

sumlall za.s[w12, 6:7, vgx2], {z12.b-z13.b}, z8.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: sumlall za.s[w12, 6:7, vgx2], {z12.b-z13.b}, z8.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select offset

sumlall za.s[w11, 4:8], {z30.b-z31.b}, z15.b[15]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sumlall za.s[w11, 4:8], {z30.b-z31.b}, z15.b[15]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

sumlall za.s[w8, 5:8, vgx2], {z22.b-z23.b}, z14.b[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 4 in the range [0, 4] or [0, 12] depending on the instruction, and the second immediate is immf + 3.
// CHECK-NEXT: sumlall za.s[w8, 5:8, vgx2], {z22.b-z23.b}, z14.b[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

sumlall za.h[w8, 6:7, vgx2], {z12.b-z13.b}, z8.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
// CHECK-NEXT: sumlall za.h[w8, 6:7, vgx2], {z12.b-z13.b}, z8.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector lane index

sumlall za.s[w8, 0:3], {z0.b-z1.b}, z0.b[16]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
// CHECK-NEXT: sumlall za.s[w8, 0:3], {z0.b-z1.b}, z0.b[16]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

sumlall za.s[w8, 0:3], {z0.b-z1.b}, z0.b[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
// CHECK-NEXT: sumlall za.s[w8, 0:3], {z0.b-z1.b}, z0.b[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1,029 changes: 1,029 additions & 0 deletions llvm/test/MC/AArch64/SME2/sumlall.s
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74 changes: 74 additions & 0 deletions llvm/test/MC/AArch64/SME2/umlall-diagnostics.s
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Original file line number Diff line number Diff line change
@@ -0,0 +1,74 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

umlall za.d[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umlall za.d[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

umlall za.d[w11, 6:7, vgx4], {z12.h-z17.h}, z8.h[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: umlall za.d[w11, 6:7, vgx4], {z12.h-z17.h}, z8.h[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

umlall za.s[w10, 4:7], {z8.b-z11.b}, {z21.b-z24.b}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: umlall za.s[w10, 4:7], {z8.b-z11.b}, {z21.b-z24.b}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid indexed-vector register

umlall za.s[w10, 0:3], z19.b, z4.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: umlall za.s[w10, 0:3], z19.b, z4.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

umlall za.d[w10, 4:7], z10.h, z30.h[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: umlall za.d[w10, 4:7], z10.h, z30.h[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select register

umlall za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: umlall za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

umlall za.d[w12, 6:7], z12.h, z16.h[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: umlall za.d[w12, 6:7], z12.h, z16.h[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select offset

umlall za.s[w11, 4:8], {z30.b-z31.b}, z15.b[15]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umlall za.s[w11, 4:8], {z30.b-z31.b}, z15.b[15]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

umlall za.d[w8, 5:8, vgx2], {z22.h-z23.h}, z14.h[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 4 in the range [0, 4] or [0, 12] depending on the instruction, and the second immediate is immf + 3.
// CHECK-NEXT: umlall za.d[w8, 5:8, vgx2], {z22.h-z23.h}, z14.h[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

umlall za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .d
// CHECK-NEXT: umlall za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector lane index

umlall za.s[w8, 0:3], {z0.b-z3.b}, z0.b[16]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
// CHECK-NEXT: umlall za.s[w8, 0:3], {z0.b-z3.b}, z0.b[16]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
2,045 changes: 2,045 additions & 0 deletions llvm/test/MC/AArch64/SME2/umlall.s
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74 changes: 74 additions & 0 deletions llvm/test/MC/AArch64/SME2/umlsll-diagnostics.s
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Original file line number Diff line number Diff line change
@@ -0,0 +1,74 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

umlsll za.d[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umlsll za.d[w11, 6:7, vgx2], {z12.h-z14.h}, z8.h[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

umlsll za.d[w11, 6:7, vgx4], {z12.h-z17.h}, z8.h[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: umlsll za.d[w11, 6:7, vgx4], {z12.h-z17.h}, z8.h[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

umlsll za.s[w10, 4:7], {z8.b-z11.b}, {z21.b-z24.b}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: umlsll za.s[w10, 4:7], {z8.b-z11.b}, {z21.b-z24.b}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid indexed-vector register

umlsll za.s[w10, 0:3], z19.b, z4.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: umlsll za.s[w10, 0:3], z19.b, z4.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

umlsll za.d[w10, 4:7], z10.h, z30.h[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: umlsll za.d[w10, 4:7], z10.h, z30.h[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select register

umlsll za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: umlsll za.s[w7, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

umlsll za.d[w12, 6:7, vgx2], {z12.h-z13.h}, z2.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: umlsll za.d[w12, 6:7, vgx2], {z12.h-z13.h}, z2.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select offset

umlsll za.s[w11, 4:8], {z30.b-z31.b}, z15.b[15]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umlsll za.s[w11, 4:8], {z30.b-z31.b}, z15.b[15]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

umlsll za.d[w8, 5:8, vgx2], {z22.h-z23.h}, z14.h[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 4 in the range [0, 4] or [0, 12] depending on the instruction, and the second immediate is immf + 3.
// CHECK-NEXT: umlsll za.d[w8, 5:8, vgx2], {z22.h-z23.h}, z14.h[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

umlsll za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .d
// CHECK-NEXT: umlsll za.h[w8, 6:7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector lane index

umlsll za.s[w8, 0:3], {z0.b-z3.b}, z0.b[16]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
// CHECK-NEXT: umlsll za.s[w8, 0:3], {z0.b-z3.b}, z0.b[16]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
2,045 changes: 2,045 additions & 0 deletions llvm/test/MC/AArch64/SME2/umlsll.s
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84 changes: 84 additions & 0 deletions llvm/test/MC/AArch64/SME2/usmlall-diagnostics.s
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Original file line number Diff line number Diff line change
@@ -0,0 +1,84 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

usmlall za.s[w11, 4:7, vgx2], {z12.h-z14.h}, z8.h[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: usmlall za.s[w11, 4:7, vgx2], {z12.h-z14.h}, z8.h[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

usmlall za.s[w11, 4:7, vgx4], {z12.h-z17.h}, z8.h[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: usmlall za.s[w11, 4:7, vgx4], {z12.h-z17.h}, z8.h[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

usmlall za.s[w10, 4:7], {z8.b-z11.b}, {z21.b-z24.b}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: usmlall za.s[w10, 4:7], {z8.b-z11.b}, {z21.b-z24.b}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

usmlall za.s[w10, 4:7], {z8.b-z9.b}, {z21.b-z22.b}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: usmlall za.s[w10, 4:7], {z8.b-z9.b}, {z21.b-z22.b}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid indexed-vector register

usmlall za.s[w10, 0:3], z19.b, z4.s[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: usmlall za.s[w10, 0:3], z19.b, z4.s[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

usmlall za.s[w10, 4:7], z10.b, z30.b[1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
// CHECK-NEXT: usmlall za.s[w10, 4:7], z10.b, z30.b[1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select register

usmlall za.s[w7, 6:7, vgx2], {z12.b-z13.b}, {z8.b-z9.b}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: usmlall za.s[w7, 6:7, vgx2], {z12.b-z13.b}, {z8.b-z9.b}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

usmlall za.s[w12, 6:7, vgx2], {z12.b-z13.b}, {z8.b-z9.b}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: usmlall za.s[w12, 6:7, vgx2], {z12.b-z13.b}, {z8.b-z9.b}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select offset

usmlall za.s[w11, 4:8], {z30.b-z31.b}, z15.b[15]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: usmlall za.s[w11, 4:8], {z30.b-z31.b}, z15.b[15]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

usmlall za.s[w8, 5:8, vgx2], {z22.b-z23.b}, z14.b[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 4 in the range [0, 4] or [0, 12] depending on the instruction, and the second immediate is immf + 3.
// CHECK-NEXT: usmlall za.s[w8, 5:8, vgx2], {z22.b-z23.b}, z14.b[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

usmlall za.h[w8, 6:7, vgx2], {z12.b-z13.b}, {z8.b-z9.b}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
// CHECK-NEXT: usmlall za.h[w8, 6:7, vgx2], {z12.b-z13.b}, {z8.b-z9.b}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector lane index

usmlall za.s[w8, 0:3], {z0.b-z1.b}, z0.b[16]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
// CHECK-NEXT: usmlall za.s[w8, 0:3], {z0.b-z1.b}, z0.b[16]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

usmlall za.s[w8, 0:3], {z0.b-z1.b}, z0.b[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 15].
// CHECK-NEXT: usmlall za.s[w8, 0:3], {z0.b-z1.b}, z0.b[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1,029 changes: 1,029 additions & 0 deletions llvm/test/MC/AArch64/SME2/usmlall.s
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