69 changes: 27 additions & 42 deletions llvm/test/CodeGen/ARM/fast-isel-ldr-str-thumb-neg-index.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@

define i32 @t1(i32* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t1:
; THUMB: t1
%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -1
%0 = load i32, i32* %add.ptr, align 4
; THUMB: ldr r{{[0-9]}}, [r0, #-4]
Expand All @@ -11,7 +11,7 @@ entry:

define i32 @t2(i32* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t2:
; THUMB: t2
%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -63
%0 = load i32, i32* %add.ptr, align 4
; THUMB: ldr r{{[0-9]}}, [r0, #-252]
Expand All @@ -20,7 +20,7 @@ entry:

define i32 @t3(i32* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t3:
; THUMB: t3
%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -64
%0 = load i32, i32* %add.ptr, align 4
; THUMB: ldr r{{[0-9]}}, [r0]
Expand All @@ -29,7 +29,7 @@ entry:

define zeroext i16 @t4(i16* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t4:
; THUMB: t4
%add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -1
%0 = load i16, i16* %add.ptr, align 2
; THUMB: ldrh r{{[0-9]}}, [r0, #-2]
Expand All @@ -38,7 +38,7 @@ entry:

define zeroext i16 @t5(i16* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t5:
; THUMB: t5
%add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -127
%0 = load i16, i16* %add.ptr, align 2
; THUMB: ldrh r{{[0-9]}}, [r0, #-254]
Expand All @@ -47,7 +47,7 @@ entry:

define zeroext i16 @t6(i16* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t6:
; THUMB: t6
%add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -128
%0 = load i16, i16* %add.ptr, align 2
; THUMB: ldrh r{{[0-9]}}, [r0]
Expand All @@ -56,7 +56,7 @@ entry:

define zeroext i8 @t7(i8* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t7:
; THUMB: t7
%add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -1
%0 = load i8, i8* %add.ptr, align 1
; THUMB: ldrb r{{[0-9]}}, [r0, #-1]
Expand All @@ -65,7 +65,7 @@ entry:

define zeroext i8 @t8(i8* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t8:
; THUMB: t8
%add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -255
%0 = load i8, i8* %add.ptr, align 1
; THUMB: ldrb r{{[0-9]}}, [r0, #-255]
Expand All @@ -74,7 +74,7 @@ entry:

define zeroext i8 @t9(i8* nocapture %ptr) nounwind readonly {
entry:
; THUMB-LABEL: t9:
; THUMB: t9
%add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -256
%0 = load i8, i8* %add.ptr, align 1
; THUMB: ldrb r{{[0-9]}}, [r0]
Expand All @@ -83,96 +83,81 @@ entry:

define void @t10(i32* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t10:
; THUMB: t10
%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -1
store i32 0, i32* %add.ptr, align 4
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: str r{{[0-9]}}, {{\[}}[[REG]], #-4]
; THUMB: str r{{[0-9]}}, [r0, #-4]
ret void
}

define void @t11(i32* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t11:
; THUMB: t11
%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -63
store i32 0, i32* %add.ptr, align 4
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: str r{{[0-9]}}, {{\[}}[[REG]], #-252]
; THUMB: str r{{[0-9]}}, [r0, #-252]
ret void
}

define void @t12(i32* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t12:
; THUMB: t12
%add.ptr = getelementptr inbounds i32, i32* %ptr, i32 -64
store i32 0, i32* %add.ptr, align 4
; THUMB: movw [[REG:r[0-9]+]], #65280
; THUMB: movt [[REG]], #65535
; THUMB: add [[REG]], r0
; THUMB: str r{{[0-9]}}, {{\[}}[[REG]]]
; THUMB: str r{{[0-9]}}, [r0]
ret void
}

define void @t13(i16* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t13:
; THUMB: t13
%add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -1
store i16 0, i16* %add.ptr, align 2
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: strh r{{[0-9]}}, {{\[}}[[REG]], #-2]
; THUMB: strh r{{[0-9]}}, [r0, #-2]
ret void
}

define void @t14(i16* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t14:
; THUMB: t14
%add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -127
store i16 0, i16* %add.ptr, align 2
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: strh r{{[0-9]}}, {{\[}}[[REG]], #-254]
; THUMB: strh r{{[0-9]}}, [r0, #-254]
ret void
}

define void @t15(i16* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t15:
; THUMB: t15
%add.ptr = getelementptr inbounds i16, i16* %ptr, i32 -128
store i16 0, i16* %add.ptr, align 2
; THUMB: movw [[REG:r[0-9]+]], #65280
; THUMB: movt [[REG]], #65535
; THUMB: add [[REG]], r0
; THUMB: strh r{{[0-9]}}, {{\[}}[[REG]]]
; THUMB: strh r{{[0-9]}}, [r0]
ret void
}

define void @t16(i8* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t16:
; THUMB: t16
%add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -1
store i8 0, i8* %add.ptr, align 1
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: strb r{{[0-9]}}, {{\[}}[[REG]], #-1]
; THUMB: strb r{{[0-9]}}, [r0, #-1]
ret void
}

define void @t17(i8* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t17:
; THUMB: t17
%add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -255
store i8 0, i8* %add.ptr, align 1
; THUMB: mov [[REG:r[0-9]+]], r0
; THUMB: strb r{{[0-9]}}, {{\[}}[[REG]], #-255]
; THUMB: strb r{{[0-9]}}, [r0, #-255]
ret void
}

define void @t18(i8* nocapture %ptr) nounwind {
entry:
; THUMB-LABEL: t18:
; THUMB: t18
%add.ptr = getelementptr inbounds i8, i8* %ptr, i32 -256
store i8 0, i8* %add.ptr, align 1
; THUMB: movw [[REG:r[0-9]+]], #65280
; THUMB: movt [[REG]], #65535
; THUMB: add [[REG]], r0
; THUMB: strb r{{[0-9]}}, {{\[}}[[REG]]]
; THUMB: strb r{{[0-9]}}, [r0]
ret void
}
32 changes: 19 additions & 13 deletions llvm/test/CodeGen/ARM/fast-isel-select.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,12 +21,14 @@ entry:
define i32 @t2(i1 %c, i32 %a) nounwind readnone {
entry:
; ARM: t2
; ARM: tst {{r[0-9]+}}, #1
; ARM: moveq {{r[0-9]+}}, #20
; ARM: tst r0, #1
; ARM: moveq r{{[1-9]}}, #20
; ARM: mov r0, r{{[1-9]}}
; THUMB-LABEL: t2
; THUMB: tst.w {{r[0-9]+}}, #1
; THUMB: tst.w r0, #1
; THUMB: it eq
; THUMB: moveq {{r[0-9]+}}, #20
; THUMB: moveq r{{[1-9]}}, #20
; THUMB: mov r0, r{{[1-9]}}
%0 = select i1 %c, i32 %a, i32 20
ret i32 %0
}
Expand All @@ -41,7 +43,7 @@ entry:
; THUMB: tst.w r0, #1
; THUMB: it ne
; THUMB: movne r2, r1
; THUMB: adds r0, r2, r1
; THUMB: add.w r0, r2, r1
%0 = select i1 %c, i32 %a, i32 %b
%1 = add i32 %0, %a
ret i32 %1
Expand All @@ -65,12 +67,14 @@ entry:
define i32 @t5(i1 %c, i32 %a) nounwind readnone {
entry:
; ARM: t5
; ARM: tst {{r[0-9]+}}, #1
; ARM: mvneq {{r[0-9]+}}, #1
; ARM: tst r0, #1
; ARM: mvneq r{{[1-9]}}, #1
; ARM: mov r0, r{{[1-9]}}
; THUMB: t5
; THUMB: tst.w {{r[0-9]+}}, #1
; THUMB: tst.w r0, #1
; THUMB: it eq
; THUMB: mvneq {{r[0-9]+}}, #1
; THUMB: mvneq r{{[1-9]}}, #1
; THUMB: mov r0, r{{[1-9]}}
%0 = select i1 %c, i32 %a, i32 -2
ret i32 %0
}
Expand All @@ -79,12 +83,14 @@ entry:
define i32 @t6(i1 %c, i32 %a) nounwind readnone {
entry:
; ARM: t6
; ARM: tst {{r[0-9]+}}, #1
; ARM: mvneq {{r[0-9]+}}, #978944
; ARM: tst r0, #1
; ARM: mvneq r{{[1-9]}}, #978944
; ARM: mov r0, r{{[1-9]}}
; THUMB: t6
; THUMB: tst.w {{r[0-9]+}}, #1
; THUMB: tst.w r0, #1
; THUMB: it eq
; THUMB: mvneq {{r[0-9]+}}, #978944
; THUMB: mvneq r{{[1-9]}}, #978944
; THUMB: mov r0, r{{[1-9]}}
%0 = select i1 %c, i32 %a, i32 -978945
ret i32 %0
}
28 changes: 15 additions & 13 deletions llvm/test/CodeGen/ARM/fast-isel-vararg.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,24 +17,26 @@ entry:
%4 = load i32, i32* %n, align 4
; ARM: VarArg
; ARM: mov [[FP:r[0-9]+]], sp
; ARM: sub sp, sp, #32
; ARM: sub sp, sp, #{{(36|40)}}
; ARM: ldr r1, {{\[}}[[FP]], #-4]
; ARM: ldr r2, {{\[}}[[FP]], #-8]
; ARM: ldr r3, {{\[}}[[FP]], #-12]
; ARM: ldr [[Ra:r[0-9]+|lr]], [sp, #16]
; ARM: ldr [[Rb:[lr]+[0-9]*]], [sp, #12]
; ARM: movw r0, #5
; ARM: str [[Ra]], [sp]
; ARM: ldr [[Ra:r[0-9]+]], {{\[}}[[FP]], #-16]
; ARM: ldr [[Rb:[lr]+[0-9]*]], [sp, #{{(16|20)}}]
; ARM: movw [[Rc:[lr]+[0-9]*]], #5
; Ra got spilled
; ARM: mov r0, [[Rc]]
; ARM: str {{.*}}, [sp]
; ARM: str [[Rb]], [sp, #4]
; ARM: bl {{_?CallVariadic}}
; THUMB: sub sp, #32
; THUMB: ldr r1, [sp, #28]
; THUMB: ldr r2, [sp, #24]
; THUMB: ldr r3, [sp, #20]
; THUMB: ldr.w [[Ra:r[0-9]+]], [sp, #16]
; THUMB: ldr.w [[Rb:r[0-9]+]], [sp, #12]
; THUMB: str.w [[Ra]], [sp]
; THUMB: str.w [[Rb]], [sp, #4]
; THUMB: sub sp, #{{36}}
; THUMB: ldr r1, [sp, #32]
; THUMB: ldr r2, [sp, #28]
; THUMB: ldr r3, [sp, #24]
; THUMB: ldr {{[a-z0-9]+}}, [sp, #20]
; THUMB: ldr.w {{[a-z0-9]+}}, [sp, #16]
; THUMB: str.w {{[a-z0-9]+}}, [sp]
; THUMB: str.w {{[a-z0-9]+}}, [sp, #4]
; THUMB: bl {{_?}}CallVariadic
%call = call i32 (i32, ...) @CallVariadic(i32 5, i32 %0, i32 %1, i32 %2, i32 %3, i32 %4)
store i32 %call, i32* %tmp, align 4
Expand Down
9 changes: 4 additions & 5 deletions llvm/test/CodeGen/ARM/ldrd.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -81,12 +81,11 @@ return: ; preds = %bb, %entry
; CHECK-LABEL: Func1:
define void @Func1() nounwind ssp "frame-pointer"="all" {
entry:
; A8: movw [[BASER:r[0-9]+]], :lower16:{{.*}}TestVar{{.*}}
; A8: movt [[BASER]], :upper16:{{.*}}TestVar{{.*}}
; A8: ldr [[BASE:r[0-9]+]], {{\[}}[[BASER]]]
; A8: movw [[BASE:r[0-9]+]], :lower16:{{.*}}TestVar{{.*}}
; A8: movt [[BASE]], :upper16:{{.*}}TestVar{{.*}}
; A8: ldrd [[FIELD1:r[0-9]+]], [[FIELD2:r[0-9]+]], {{\[}}[[BASE]], #4]
; A8-NEXT: add [[FIELD2]], [[FIELD1]]
; A8-NEXT: str [[FIELD2]], {{\[}}[[BASE]]{{\]}}
; A8-NEXT: add [[FIELD1]], [[FIELD2]]
; A8-NEXT: str [[FIELD1]], {{\[}}[[BASE]]{{\]}}
; CONSERVATIVE-NOT: ldrd
%orig_blocks = alloca [256 x i16], align 2
%0 = bitcast [256 x i16]* %orig_blocks to i8*call void @llvm.lifetime.start.p0i8(i64 512, i8* %0) nounwind
Expand Down
28 changes: 14 additions & 14 deletions llvm/test/CodeGen/ARM/legalize-bitcast.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,17 +14,17 @@ define i32 @vec_to_int() {
; CHECK-NEXT: ldr r0, [r0]
; CHECK-NEXT: @ implicit-def: $d17
; CHECK-NEXT: vmov.32 d17[0], r0
; CHECK-NEXT: vrev32.16 d18, d17
; CHECK-NEXT: vrev32.16 d17, d17
; CHECK-NEXT: vrev16.8 d16, d16
; CHECK-NEXT: @ kill: def $d16 killed $d16 def $q8
; CHECK-NEXT: vmov.f64 d17, d18
; CHECK-NEXT: vstmia sp, {d16, d17} @ 16-byte Spill
; CHECK-NEXT: vmov.f64 d18, d16
; CHECK-NEXT: vmov.f64 d19, d17
; CHECK-NEXT: vstmia sp, {d18, d19} @ 16-byte Spill
; CHECK-NEXT: b .LBB0_1
; CHECK-NEXT: .LBB0_1: @ %bb.1
; CHECK-NEXT: vldmia sp, {d16, d17} @ 16-byte Reload
; CHECK-NEXT: vrev32.16 q8, q8
; CHECK-NEXT: vmov.f64 d16, d17
; CHECK-NEXT: vmov.32 r0, d16[0]
; CHECK-NEXT: vrev32.16 q9, q8
; CHECK-NEXT: @ kill: def $d19 killed $d19 killed $q9
; CHECK-NEXT: vmov.32 r0, d19[0]
; CHECK-NEXT: add sp, sp, #28
; CHECK-NEXT: pop {r4}
; CHECK-NEXT: bx lr
Expand All @@ -41,15 +41,15 @@ bb.1:
define i16 @int_to_vec(i80 %in) {
; CHECK-LABEL: int_to_vec:
; CHECK: @ %bb.0:
; CHECK-NEXT: @ kill: def $r2 killed $r1
; CHECK-NEXT: @ kill: def $r2 killed $r0
; CHECK-NEXT: mov r3, r1
; CHECK-NEXT: mov r12, r0
; CHECK-NEXT: lsl r0, r0, #16
; CHECK-NEXT: orr r0, r0, r1, lsr #16
; CHECK-NEXT: @ implicit-def: $d18
; CHECK-NEXT: vmov.32 d18[0], r0
; CHECK-NEXT: @ implicit-def: $q8
; CHECK-NEXT: vmov.f64 d16, d18
; CHECK-NEXT: vrev32.16 q8, q8
; CHECK-NEXT: @ implicit-def: $d16
; CHECK-NEXT: vmov.32 d16[0], r0
; CHECK-NEXT: @ implicit-def: $q9
; CHECK-NEXT: vmov.f64 d18, d16
; CHECK-NEXT: vrev32.16 q8, q9
; CHECK-NEXT: @ kill: def $d16 killed $d16 killed $q8
; CHECK-NEXT: vmov.u16 r0, d16[0]
; CHECK-NEXT: bx lr
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/ARM/pr47454.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,23 +16,23 @@ define internal fastcc void @main() {
; CHECK-NEXT: ldrh r0, [r11, #-2]
; CHECK-NEXT: bl __gnu_h2f_ieee
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vstr s0, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: vstr s0, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: bl getConstant
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl __gnu_h2f_ieee
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: bl __gnu_f2h_ieee
; CHECK-NEXT: vldr s0, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: str r0, [sp, #8] @ 4-byte Spill
; CHECK-NEXT: vmov r0, s0
; CHECK-NEXT: vldr s0, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: vmov r1, s0
; CHECK-NEXT: str r0, [sp, #4] @ 4-byte Spill
; CHECK-NEXT: mov r0, r1
; CHECK-NEXT: bl __gnu_f2h_ieee
; CHECK-NEXT: mov r1, r0
; CHECK-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; CHECK-NEXT: uxth r1, r1
; CHECK-NEXT: vmov s0, r1
; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: vmov s1, r0
; CHECK-NEXT: vmov s0, r0
; CHECK-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; CHECK-NEXT: uxth r1, r0
; CHECK-NEXT: vmov s1, r1
; CHECK-NEXT: bl isEqual
; CHECK-NEXT: mov sp, r11
; CHECK-NEXT: pop {r11, pc}
Expand Down
7 changes: 3 additions & 4 deletions llvm/test/CodeGen/ARM/stack-guard-reassign.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,12 +3,11 @@
; Verify that the offset assigned to the stack protector is at the top of the
; frame, covering the locals.
; CHECK-LABEL: fn:
; CHECK: sub sp, sp, #24
; CHECK: sub sp, sp, #32
; CHECK-NEXT: sub sp, sp, #65536
; CHECK-NEXT: ldr r1, .LCPI0_0
; CHECK-NEXT: str r1, [sp, #8]
; CHECK-NEXT: ldr r1, [r1]
; CHECK-NEXT: ldr r2, [r1]
; CHECK-NEXT: add lr, sp, #65536
; CHECK-NEXT: str r1, [lr, #20]
; CHECK-NEXT: str r2, [lr, #28]
; CHECK: .LCPI0_0:
; CHECK-NEXT: .long __stack_chk_guard
38 changes: 20 additions & 18 deletions llvm/test/CodeGen/ARM/swifterror.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,9 +21,9 @@ define float @foo(%swift_error** swifterror %error_ptr_ref) {
; CHECK-O0: mov r{{.*}}, #16
; CHECK-O0: malloc
; CHECK-O0: mov [[ID2:r[0-9]+]], r0
; CHECK-O0: mov r8, [[ID2]]
; CHECK-O0: mov [[ID:r[0-9]+]], #1
; CHECK-O0: strb [[ID]], {{\[}}[[ID2]], #8]
; CHECK-O0: strb [[ID]], [r0, #8]
; CHECK-O0: mov r8, [[ID2]]
entry:
%call = call i8* @malloc(i64 16)
%call.0 = bitcast i8* %call to %swift_error*
Expand All @@ -49,16 +49,16 @@ define float @caller(i8* %error_ref) {
; CHECK-O0-LABEL: caller:
; spill r0
; CHECK-O0-DAG: mov r8, #0
; CHECK-O0-DAG: str r0, [sp[[SLOT:(, #[0-9]+)?]]]
; CHECK-O0-DAG: str r0, [sp, [[SLOT:#[0-9]+]]
; CHECK-O0: bl {{.*}}foo
; CHECK-O0: mov [[TMP:r[0-9]+]], r8
; CHECK-O0: str [[TMP]], [sp[[SLOT2:(, #[0-9]+)?]]]
; CHECK-O0: str [[TMP]], [sp]
; CHECK-O0: bne
; CHECK-O0: ldr [[ID:r[0-9]+]], [sp[[SLOT]]]
; CHECK-O0: ldrb [[CODE:r[0-9]+]], [r0, #8]
; CHECK-O0: ldr [[ID:r[0-9]+]], [sp, [[SLOT]]]
; CHECK-O0: strb [[CODE]], [{{.*}}[[ID]]]
; reload r0
; CHECK-O0: ldr r0, [sp[[SLOT2]]]
; CHECK-O0: ldr r0, [sp]
; CHECK-O0: free
entry:
%error_ptr_ref = alloca swifterror %swift_error*
Expand Down Expand Up @@ -98,14 +98,14 @@ define float @caller2(i8* %error_ref) {
; CHECK-O0-DAG: mov r8, #0
; CHECK-O0: bl {{.*}}foo
; CHECK-O0: mov r{{.*}}, r8
; CHECK-O0: str r0, [sp{{(, #[0-9]+)?}}]
; CHECK-O0: str r0, [sp]
; CHECK-O0: bne
; CHECK-O0: ble
; CHECK-O0: ldrb [[CODE:r[0-9]+]], [r0, #8]
; reload r0
; CHECK-O0: ldr [[ID:r[0-9]+]],
; CHECK-O0: ldrb [[CODE:r[0-9]+]], [r0, #8]
; CHECK-O0: strb [[CODE]], [{{.*}}[[ID]]]
; CHECK-O0: ldr r0, [sp{{(, #[0-9]+)?}}]
; CHECK-O0: ldr r0, [sp]
; CHECK-O0: free
entry:
%error_ptr_ref = alloca swifterror %swift_error*
Expand Down Expand Up @@ -143,15 +143,16 @@ define float @foo_if(%swift_error** swifterror %error_ptr_ref, i32 %cc) {
; CHECK-APPLE-DAG: strb [[ID]], [r{{.*}}, #8]

; CHECK-O0-LABEL: foo_if:
; CHECK-O0: cmp r0, #0
; spill to stack
; CHECK-O0: str r8
; CHECK-O0: cmp r0, #0
; CHECK-O0: beq
; CHECK-O0: mov r0, #16
; CHECK-O0: malloc
; CHECK-O0: mov [[ID:r[0-9]+]], r0
; CHECK-O0: mov [[ID2:[a-z0-9]+]], #1
; CHECK-O0: strb [[ID2]], {{\[}}[[ID]], #8]
; CHECK-O0: strb [[ID2]], [r0, #8]
; CHECK-O0: mov r8, [[ID]]
; reload from stack
; CHECK-O0: ldr r8
entry:
Expand Down Expand Up @@ -232,18 +233,18 @@ define void @foo_sret(%struct.S* sret %agg.result, i32 %val1, %swift_error** swi
; CHECK-APPLE-DAG: str r{{.*}}, [{{.*}}[[SRET]], #4]

; CHECK-O0-LABEL: foo_sret:
; CHECK-O0-DAG: mov r{{.*}}, #16
; CHECK-O0: mov r{{.*}}, #16
; spill to stack: sret and val1
; CHECK-O0-DAG: str r0
; CHECK-O0-DAG: str r1
; CHECK-O0: malloc
; CHECK-O0: mov [[ID:r[0-9]+]], #1
; CHECK-O0: strb [[ID]], [r0, #8]
; reload from stack: sret and val1
; CHECK-O0: ldr
; CHECK-O0: ldr
; CHECK-O0-DAG: mov r8
; CHECK-O0-DAG: mov [[ID:r[0-9]+]], #1
; CHECK-O0-DAG: strb [[ID]], [{{r[0-9]+}}, #8]
; CHECK-O0-DAG: str r{{.*}}, [{{.*}}, #4]
; CHECK-O0: str r{{.*}}, [{{.*}}, #4]
; CHECK-O0: mov r8
entry:
%call = call i8* @malloc(i64 16)
%call.0 = bitcast i8* %call to %swift_error*
Expand All @@ -270,15 +271,16 @@ define float @caller3(i8* %error_ref) {

; CHECK-O0-LABEL: caller3:
; CHECK-O0-DAG: mov r8, #0
; CHECK-O0-DAG: mov r0
; CHECK-O0-DAG: mov r1
; CHECK-O0: bl {{.*}}foo_sret
; CHECK-O0: mov [[ID2:r[0-9]+]], r8
; CHECK-O0: str [[ID2]], [sp[[SLOT:.*]]]
; CHECK-O0: cmp r8
; CHECK-O0: str [[ID2]], [sp[[SLOT:.*]]]
; CHECK-O0: bne
; Access part of the error object and save it to error_ref
; CHECK-O0: ldr [[ID:r[0-9]+]]
; CHECK-O0: ldrb [[CODE:r[0-9]+]]
; CHECK-O0: ldr [[ID:r[0-9]+]]
; CHECK-O0: strb [[CODE]], [{{.*}}[[ID]]]
; CHECK-O0: ldr r0, [sp[[SLOT]]
; CHECK-O0: bl {{.*}}free
Expand Down
2,070 changes: 1,035 additions & 1,035 deletions llvm/test/CodeGen/ARM/thumb-big-stack.ll
View file

Large diffs are not rendered by default.

18 changes: 9 additions & 9 deletions llvm/test/CodeGen/Hexagon/vect/vect-load-v4i16.ll
View file
Original file line number Diff line number Diff line change
@@ -1,22 +1,22 @@
; RUN: llc -march=hexagon -O0 -hexagon-align-loads=0 < %s | FileCheck %s

; CHECK-LABEL: danny:
; CHECK: r1 = r0
; CHECK-DAG: [[T0:r[0-9]+]] = memuh(r1+#0)
; CHECK-DAG: [[T1:r[0-9]+]] = memuh(r1+#2)
; CHECK: r2 |= asl([[T1]],#16)
; CHECK-DAG: [[T2:r[0-9]+]] = memuh(r1+#4)
; CHECK-DAG: [[T3:r[0-9]+]] = memuh(r1+#6)
; CHECK: r1 |= asl([[T3]],#16)
; CHECK-DAG: [[T0:r[0-9]+]] = memuh(r0+#0)
; CHECK-DAG: [[T1:r[0-9]+]] = memuh(r0+#2)
; CHECK: [[T0]] |= asl([[T1]],#16)
; CHECK-DAG: [[T2:r[0-9]+]] = memuh(r0+#4)
; CHECK-DAG: [[T3:r[0-9]+]] = memuh(r0+#6)
; CHECK: [[T2]] |= asl([[T3]],#16)
; CHECK: combine([[T2]],[[T0]])
define <4 x i16> @danny(<4 x i16>* %p) {
%t0 = load <4 x i16>, <4 x i16>* %p, align 2
ret <4 x i16> %t0
}

; CHECK-LABEL: sammy:
; CHECK-DAG: [[T0:r[0-9]+]] = memw(r0+#0)
; CHECK-DAG: r1 = memw(r0+#4)
; CHECK: r0 = [[T0]]
; CHECK-DAG: [[T1:r[0-9]+]] = memw(r0+#4)
; CHECK: combine([[T1]],[[T0]])
define <4 x i16> @sammy(<4 x i16>* %p) {
%t0 = load <4 x i16>, <4 x i16>* %p, align 4
ret <4 x i16> %t0
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Mips/Fast-ISel/callabi.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -244,12 +244,12 @@ define void @cxiiiiconv() {
; ALL-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]])
; ALL-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]])
; 32R1-DAG: sll $[[REG_C1_1:[0-9]+]], $[[REG_C1]], 24
; 32R1-DAG: sra $4, $[[REG_C1_1]], 24
; 32R2-DAG: seb $4, $[[REG_C1]]
; 32R1-DAG: sra $5, $[[REG_C1_1]], 24
; 32R2-DAG: seb $5, $[[REG_C1]]
; FIXME: andi is superfulous
; ALL-DAG: lw $[[REG_UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
; ALL-DAG: lbu $[[REG_UC1:[0-9]+]], 0($[[REG_UC1_ADDR]])
; ALL-DAG: andi $5, $[[REG_UC1]], 255
; ALL-DAG: andi $4, $[[REG_UC1]], 255
; ALL-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
; ALL-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])
; 32R1-DAG: sll $[[REG_S1_1:[0-9]+]], $[[REG_S1]], 16
Expand Down
33 changes: 26 additions & 7 deletions llvm/test/CodeGen/Mips/Fast-ISel/memtest1.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,9 +17,15 @@ declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1)
define void @cpy(i8* %src, i32 %i) {
; ALL-LABEL: cpy:

; ALL: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
; ALL: lw $[[T2:[0-9]+]], %got(memcpy)(${{[0-9]+}})
; ALL: jalr $[[T2]]
; ALL-DAG: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
; ALL-DAG: sw $4, 24($sp)
; ALL-DAG: move $4, $[[T0]]
; ALL-DAG: sw $5, 20($sp)
; ALL-DAG: lw $[[T1:[0-9]+]], 24($sp)
; ALL-DAG: move $5, $[[T1]]
; ALL-DAG: lw $6, 20($sp)
; ALL-DAG: lw $[[T2:[0-9]+]], %got(memcpy)(${{[0-9]+}})
; ALL: jalr $[[T2]]
; ALL-NEXT: nop
; ALL-NOT: {{.*}}$2{{.*}}
call void @llvm.memcpy.p0i8.p0i8.i32(i8* getelementptr inbounds ([50 x i8], [50 x i8]* @dest, i32 0, i32 0), i8* %src, i32 %i, i1 false)
Expand All @@ -30,8 +36,14 @@ define void @mov(i8* %src, i32 %i) {
; ALL-LABEL: mov:


; ALL: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
; ALL: lw $[[T2:[0-9]+]], %got(memmove)(${{[0-9]+}})
; ALL-DAG: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
; ALL-DAG: sw $4, 24($sp)
; ALL-DAG: move $4, $[[T0]]
; ALL-DAG: sw $5, 20($sp)
; ALL-DAG: lw $[[T1:[0-9]+]], 24($sp)
; ALL-DAG: move $5, $[[T1]]
; ALL-DAG: lw $6, 20($sp)
; ALL-DAG: lw $[[T2:[0-9]+]], %got(memmove)(${{[0-9]+}})
; ALL: jalr $[[T2]]
; ALL-NEXT: nop
; ALL-NOT: {{.*}}$2{{.*}}
Expand All @@ -42,8 +54,15 @@ define void @mov(i8* %src, i32 %i) {
define void @clear(i32 %i) {
; ALL-LABEL: clear:

; ALL: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
; ALL: lw $[[T2:[0-9]+]], %got(memset)(${{[0-9]+}})
; ALL-DAG: lw $[[T0:[0-9]+]], %got(dest)(${{[0-9]+}})
; ALL-DAG: sw $4, 16($sp)
; ALL-DAG: move $4, $[[T0]]
; ALL-DAG: addiu $[[T1:[0-9]+]], $zero, 42
; 32R1-DAG: sll $[[T2:[0-9]+]], $[[T1]], 24
; 32R1-DAG: sra $5, $[[T2]], 24
; 32R2-DAG: seb $5, $[[T1]]
; ALL-DAG: lw $6, 16($sp)
; ALL-DAG: lw $[[T2:[0-9]+]], %got(memset)(${{[0-9]+}})
; ALL: jalr $[[T2]]
; ALL-NEXT: nop
; ALL-NOT: {{.*}}$2{{.*}}
Expand Down
5 changes: 2 additions & 3 deletions llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,10 +5,9 @@ define void @test(i32 %x, i1* %p) nounwind {
; CHECK-LABEL: test:
; CHECK: # %bb.0:
; CHECK-NEXT: move $1, $4
; CHECK-NEXT: move $4, $1
; CHECK-NEXT: andi $2, $4, 1
; CHECK-NEXT: sb $2, 0($5)
; CHECK-NEXT: andi $1, $1, 1
; CHECK-NEXT: sb $1, 0($5)
; CHECK-NEXT: andi $1, $4, 1
; CHECK-NEXT: bgtz $1, $BB0_1
; CHECK-NEXT: nop
; CHECK-NEXT: # %bb.1: # %foo
Expand Down
57 changes: 31 additions & 26 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -86,11 +86,12 @@ entry:
define i64 @add_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: add_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addu $2, $6, $4
; MIPS32-NEXT: sltu $3, $2, $4
; MIPS32-NEXT: addu $1, $7, $5
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: addu $3, $1, $3
; MIPS32-NEXT: addu $1, $6, $4
; MIPS32-NEXT: sltu $2, $1, $4
; MIPS32-NEXT: addu $3, $7, $5
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: addu $3, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -101,30 +102,34 @@ entry:
define i128 @add_i128(i128 %a, i128 %b) {
; MIPS32-LABEL: add_i128:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $8, $4
; MIPS32-NEXT: move $3, $5
; MIPS32-NEXT: move $4, $6
; MIPS32-NEXT: addiu $1, $sp, 16
; MIPS32-NEXT: lw $2, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 20
; MIPS32-NEXT: lw $6, 0($1)
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
; MIPS32-NEXT: addiu $1, $sp, 24
; MIPS32-NEXT: lw $5, 0($1)
; MIPS32-NEXT: addiu $1, $sp, 28
; MIPS32-NEXT: lw $1, 0($1)
; MIPS32-NEXT: addu $2, $2, $8
; MIPS32-NEXT: sltu $8, $2, $8
; MIPS32-NEXT: addu $3, $6, $3
; MIPS32-NEXT: andi $8, $8, 1
; MIPS32-NEXT: addu $3, $3, $8
; MIPS32-NEXT: sltu $6, $3, $6
; MIPS32-NEXT: addiu $2, $sp, 28
; MIPS32-NEXT: lw $2, 0($2)
; MIPS32-NEXT: addiu $3, $sp, 32
; MIPS32-NEXT: lw $3, 0($3)
; MIPS32-NEXT: addiu $8, $sp, 36
; MIPS32-NEXT: lw $8, 0($8)
; MIPS32-NEXT: addu $1, $1, $4
; MIPS32-NEXT: sltu $4, $1, $4
; MIPS32-NEXT: addu $5, $2, $5
; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: addu $4, $5, $4
; MIPS32-NEXT: andi $6, $6, 1
; MIPS32-NEXT: addu $4, $4, $6
; MIPS32-NEXT: sltu $5, $4, $5
; MIPS32-NEXT: addu $1, $1, $7
; MIPS32-NEXT: andi $5, $5, 1
; MIPS32-NEXT: addu $5, $1, $5
; MIPS32-NEXT: sltu $2, $4, $2
; MIPS32-NEXT: addu $5, $3, $6
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: addu $2, $5, $2
; MIPS32-NEXT: sltu $3, $2, $3
; MIPS32-NEXT: addu $5, $8, $7
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: addu $5, $5, $3
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: move $3, $4
; MIPS32-NEXT: lw $4, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/add_vec.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,9 @@
define void @add_v16i8(<16 x i8>* %a, <16 x i8>* %b, <16 x i8>* %c) {
; P5600-LABEL: add_v16i8:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.b $w1, 0($4)
; P5600-NEXT: ld.b $w0, 0($5)
; P5600-NEXT: addv.b $w0, $w0, $w1
; P5600-NEXT: ld.b $w0, 0($4)
; P5600-NEXT: ld.b $w1, 0($5)
; P5600-NEXT: addv.b $w0, $w1, $w0
; P5600-NEXT: st.b $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
Expand All @@ -21,9 +21,9 @@ entry:
define void @add_v8i16(<8 x i16>* %a, <8 x i16>* %b, <8 x i16>* %c) {
; P5600-LABEL: add_v8i16:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.h $w1, 0($4)
; P5600-NEXT: ld.h $w0, 0($5)
; P5600-NEXT: addv.h $w0, $w0, $w1
; P5600-NEXT: ld.h $w0, 0($4)
; P5600-NEXT: ld.h $w1, 0($5)
; P5600-NEXT: addv.h $w0, $w1, $w0
; P5600-NEXT: st.h $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
Expand All @@ -38,9 +38,9 @@ entry:
define void @add_v4i32(<4 x i32>* %a, <4 x i32>* %b, <4 x i32>* %c) {
; P5600-LABEL: add_v4i32:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.w $w1, 0($4)
; P5600-NEXT: ld.w $w0, 0($5)
; P5600-NEXT: addv.w $w0, $w0, $w1
; P5600-NEXT: ld.w $w0, 0($4)
; P5600-NEXT: ld.w $w1, 0($5)
; P5600-NEXT: addv.w $w0, $w1, $w0
; P5600-NEXT: st.w $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
Expand All @@ -55,9 +55,9 @@ entry:
define void @add_v2i64(<2 x i64>* %a, <2 x i64>* %b, <2 x i64>* %c) {
; P5600-LABEL: add_v2i64:
; P5600: # %bb.0: # %entry
; P5600-NEXT: ld.d $w1, 0($4)
; P5600-NEXT: ld.d $w0, 0($5)
; P5600-NEXT: addv.d $w0, $w0, $w1
; P5600-NEXT: ld.d $w0, 0($4)
; P5600-NEXT: ld.d $w1, 0($5)
; P5600-NEXT: addv.d $w0, $w1, $w0
; P5600-NEXT: st.d $w0, 0($6)
; P5600-NEXT: jr $ra
; P5600-NEXT: nop
Expand Down
28 changes: 14 additions & 14 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/aggregate_struct_return.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,10 +6,10 @@ define { float, float } @add_complex_float({ float, float }* %a, { float, float
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lwc1 $f0, 0($4)
; MIPS32-NEXT: lwc1 $f1, 4($4)
; MIPS32-NEXT: lwc1 $f3, 0($5)
; MIPS32-NEXT: lwc1 $f2, 4($5)
; MIPS32-NEXT: add.s $f0, $f0, $f3
; MIPS32-NEXT: add.s $f2, $f1, $f2
; MIPS32-NEXT: lwc1 $f2, 0($5)
; MIPS32-NEXT: lwc1 $f3, 4($5)
; MIPS32-NEXT: add.s $f0, $f0, $f2
; MIPS32-NEXT: add.s $f2, $f1, $f3
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -33,10 +33,10 @@ define { double, double } @add_complex_double({ double, double }* %a, { double,
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ldc1 $f0, 0($4)
; MIPS32-NEXT: ldc1 $f2, 8($4)
; MIPS32-NEXT: ldc1 $f6, 0($5)
; MIPS32-NEXT: ldc1 $f4, 8($5)
; MIPS32-NEXT: add.d $f0, $f0, $f6
; MIPS32-NEXT: add.d $f2, $f2, $f4
; MIPS32-NEXT: ldc1 $f4, 0($5)
; MIPS32-NEXT: ldc1 $f6, 8($5)
; MIPS32-NEXT: add.d $f0, $f0, $f4
; MIPS32-NEXT: add.d $f2, $f2, $f6
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand Down Expand Up @@ -66,9 +66,9 @@ define void @call_ret_complex_float({ float, float }* %z) {
; MIPS32-NEXT: sw $4, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: jal ret_complex_float
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $4, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: swc1 $f0, 0($4)
; MIPS32-NEXT: swc1 $f2, 4($4)
; MIPS32-NEXT: lw $1, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: swc1 $f0, 0($1)
; MIPS32-NEXT: swc1 $f2, 4($1)
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
Expand All @@ -95,9 +95,9 @@ define void @call_ret_complex_double({ double, double }* %z) {
; MIPS32-NEXT: sw $4, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: jal ret_complex_double
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $4, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($4)
; MIPS32-NEXT: sdc1 $f2, 8($4)
; MIPS32-NEXT: lw $1, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sdc1 $f0, 0($1)
; MIPS32-NEXT: sdc1 $f2, 8($1)
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
Expand Down
270 changes: 135 additions & 135 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitreverse.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,64 +6,64 @@ declare i32 @llvm.bitreverse.i32(i32)
define i32 @bitreverse_i32(i32 signext %a) {
; MIPS32-LABEL: bitreverse_i32:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sll $2, $4, 24
; MIPS32-NEXT: srl $1, $4, 24
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: sll $1, $4, 24
; MIPS32-NEXT: srl $2, $4, 24
; MIPS32-NEXT: or $1, $2, $1
; MIPS32-NEXT: andi $2, $4, 65280
; MIPS32-NEXT: sll $2, $2, 8
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: srl $2, $4, 8
; MIPS32-NEXT: andi $2, $2, 65280
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: lui $1, 61680
; MIPS32-NEXT: ori $3, $1, 61680
; MIPS32-NEXT: and $1, $2, $3
; MIPS32-NEXT: srl $1, $1, 4
; MIPS32-NEXT: sll $2, $2, 4
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: lui $1, 52428
; MIPS32-NEXT: ori $3, $1, 52428
; MIPS32-NEXT: and $1, $2, $3
; MIPS32-NEXT: srl $1, $1, 2
; MIPS32-NEXT: sll $2, $2, 2
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: lui $1, 43690
; MIPS32-NEXT: ori $3, $1, 43690
; MIPS32-NEXT: and $1, $2, $3
; MIPS32-NEXT: srl $1, $1, 1
; MIPS32-NEXT: sll $2, $2, 1
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: lui $2, 61680
; MIPS32-NEXT: ori $2, $2, 61680
; MIPS32-NEXT: and $3, $1, $2
; MIPS32-NEXT: srl $3, $3, 4
; MIPS32-NEXT: sll $1, $1, 4
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: or $1, $3, $1
; MIPS32-NEXT: lui $2, 52428
; MIPS32-NEXT: ori $2, $2, 52428
; MIPS32-NEXT: and $3, $1, $2
; MIPS32-NEXT: srl $3, $3, 2
; MIPS32-NEXT: sll $1, $1, 2
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: or $1, $3, $1
; MIPS32-NEXT: lui $2, 43690
; MIPS32-NEXT: ori $2, $2, 43690
; MIPS32-NEXT: and $3, $1, $2
; MIPS32-NEXT: srl $3, $3, 1
; MIPS32-NEXT: sll $1, $1, 1
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: or $2, $3, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R2-LABEL: bitreverse_i32:
; MIPS32R2: # %bb.0: # %entry
; MIPS32R2-NEXT: wsbh $1, $4
; MIPS32R2-NEXT: rotr $2, $1, 16
; MIPS32R2-NEXT: lui $1, 61680
; MIPS32R2-NEXT: ori $3, $1, 61680
; MIPS32R2-NEXT: and $1, $2, $3
; MIPS32R2-NEXT: srl $1, $1, 4
; MIPS32R2-NEXT: sll $2, $2, 4
; MIPS32R2-NEXT: and $2, $2, $3
; MIPS32R2-NEXT: or $2, $1, $2
; MIPS32R2-NEXT: lui $1, 52428
; MIPS32R2-NEXT: ori $3, $1, 52428
; MIPS32R2-NEXT: and $1, $2, $3
; MIPS32R2-NEXT: srl $1, $1, 2
; MIPS32R2-NEXT: sll $2, $2, 2
; MIPS32R2-NEXT: and $2, $2, $3
; MIPS32R2-NEXT: or $2, $1, $2
; MIPS32R2-NEXT: lui $1, 43690
; MIPS32R2-NEXT: ori $3, $1, 43690
; MIPS32R2-NEXT: and $1, $2, $3
; MIPS32R2-NEXT: srl $1, $1, 1
; MIPS32R2-NEXT: sll $2, $2, 1
; MIPS32R2-NEXT: and $2, $2, $3
; MIPS32R2-NEXT: or $2, $1, $2
; MIPS32R2-NEXT: rotr $1, $1, 16
; MIPS32R2-NEXT: lui $2, 61680
; MIPS32R2-NEXT: ori $2, $2, 61680
; MIPS32R2-NEXT: and $3, $1, $2
; MIPS32R2-NEXT: srl $3, $3, 4
; MIPS32R2-NEXT: sll $1, $1, 4
; MIPS32R2-NEXT: and $1, $1, $2
; MIPS32R2-NEXT: or $1, $3, $1
; MIPS32R2-NEXT: lui $2, 52428
; MIPS32R2-NEXT: ori $2, $2, 52428
; MIPS32R2-NEXT: and $3, $1, $2
; MIPS32R2-NEXT: srl $3, $3, 2
; MIPS32R2-NEXT: sll $1, $1, 2
; MIPS32R2-NEXT: and $1, $1, $2
; MIPS32R2-NEXT: or $1, $3, $1
; MIPS32R2-NEXT: lui $2, 43690
; MIPS32R2-NEXT: ori $2, $2, 43690
; MIPS32R2-NEXT: and $3, $1, $2
; MIPS32R2-NEXT: srl $3, $3, 1
; MIPS32R2-NEXT: sll $1, $1, 1
; MIPS32R2-NEXT: and $1, $1, $2
; MIPS32R2-NEXT: or $2, $3, $1
; MIPS32R2-NEXT: jr $ra
; MIPS32R2-NEXT: nop
entry:
Expand All @@ -75,107 +75,107 @@ declare i64 @llvm.bitreverse.i64(i64)
define i64 @bitreverse_i64(i64 signext %a) {
; MIPS32-LABEL: bitreverse_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $3, $4
; MIPS32-NEXT: sll $2, $5, 24
; MIPS32-NEXT: srl $1, $5, 24
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: sll $1, $5, 24
; MIPS32-NEXT: srl $2, $5, 24
; MIPS32-NEXT: or $1, $2, $1
; MIPS32-NEXT: andi $2, $5, 65280
; MIPS32-NEXT: sll $2, $2, 8
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: srl $2, $5, 8
; MIPS32-NEXT: andi $2, $2, 65280
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: lui $1, 61680
; MIPS32-NEXT: ori $6, $1, 61680
; MIPS32-NEXT: and $1, $2, $6
; MIPS32-NEXT: srl $1, $1, 4
; MIPS32-NEXT: sll $2, $2, 4
; MIPS32-NEXT: and $2, $2, $6
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: lui $1, 52428
; MIPS32-NEXT: ori $5, $1, 52428
; MIPS32-NEXT: and $1, $2, $5
; MIPS32-NEXT: srl $1, $1, 2
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: lui $2, 61680
; MIPS32-NEXT: ori $2, $2, 61680
; MIPS32-NEXT: and $3, $1, $2
; MIPS32-NEXT: srl $3, $3, 4
; MIPS32-NEXT: sll $1, $1, 4
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: or $1, $3, $1
; MIPS32-NEXT: lui $3, 52428
; MIPS32-NEXT: ori $3, $3, 52428
; MIPS32-NEXT: and $5, $1, $3
; MIPS32-NEXT: srl $5, $5, 2
; MIPS32-NEXT: sll $1, $1, 2
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: or $1, $5, $1
; MIPS32-NEXT: lui $5, 43690
; MIPS32-NEXT: ori $5, $5, 43690
; MIPS32-NEXT: and $6, $1, $5
; MIPS32-NEXT: srl $6, $6, 1
; MIPS32-NEXT: sll $1, $1, 1
; MIPS32-NEXT: and $1, $1, $5
; MIPS32-NEXT: or $1, $6, $1
; MIPS32-NEXT: sll $6, $4, 24
; MIPS32-NEXT: srl $7, $4, 24
; MIPS32-NEXT: or $6, $7, $6
; MIPS32-NEXT: andi $7, $4, 65280
; MIPS32-NEXT: sll $7, $7, 8
; MIPS32-NEXT: or $6, $6, $7
; MIPS32-NEXT: srl $4, $4, 8
; MIPS32-NEXT: andi $4, $4, 65280
; MIPS32-NEXT: or $4, $6, $4
; MIPS32-NEXT: and $6, $4, $2
; MIPS32-NEXT: srl $6, $6, 4
; MIPS32-NEXT: sll $4, $4, 4
; MIPS32-NEXT: and $2, $4, $2
; MIPS32-NEXT: or $2, $6, $2
; MIPS32-NEXT: and $4, $2, $3
; MIPS32-NEXT: srl $4, $4, 2
; MIPS32-NEXT: sll $2, $2, 2
; MIPS32-NEXT: and $2, $2, $5
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: lui $1, 43690
; MIPS32-NEXT: ori $4, $1, 43690
; MIPS32-NEXT: and $1, $2, $4
; MIPS32-NEXT: srl $1, $1, 1
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: or $2, $4, $2
; MIPS32-NEXT: and $3, $2, $5
; MIPS32-NEXT: srl $3, $3, 1
; MIPS32-NEXT: sll $2, $2, 1
; MIPS32-NEXT: and $2, $2, $4
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: sll $7, $3, 24
; MIPS32-NEXT: srl $1, $3, 24
; MIPS32-NEXT: or $1, $1, $7
; MIPS32-NEXT: andi $7, $3, 65280
; MIPS32-NEXT: sll $7, $7, 8
; MIPS32-NEXT: or $1, $1, $7
; MIPS32-NEXT: srl $3, $3, 8
; MIPS32-NEXT: andi $3, $3, 65280
; MIPS32-NEXT: or $3, $1, $3
; MIPS32-NEXT: and $1, $3, $6
; MIPS32-NEXT: srl $1, $1, 4
; MIPS32-NEXT: sll $3, $3, 4
; MIPS32-NEXT: and $3, $3, $6
; MIPS32-NEXT: or $3, $1, $3
; MIPS32-NEXT: and $1, $3, $5
; MIPS32-NEXT: srl $1, $1, 2
; MIPS32-NEXT: sll $3, $3, 2
; MIPS32-NEXT: and $3, $3, $5
; MIPS32-NEXT: or $3, $1, $3
; MIPS32-NEXT: and $1, $3, $4
; MIPS32-NEXT: srl $1, $1, 1
; MIPS32-NEXT: sll $3, $3, 1
; MIPS32-NEXT: and $3, $3, $4
; MIPS32-NEXT: or $3, $1, $3
; MIPS32-NEXT: and $2, $2, $5
; MIPS32-NEXT: or $3, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
; MIPS32R2-LABEL: bitreverse_i64:
; MIPS32R2: # %bb.0: # %entry
; MIPS32R2-NEXT: move $1, $4
; MIPS32R2-NEXT: wsbh $2, $5
; MIPS32R2-NEXT: rotr $3, $2, 16
; MIPS32R2-NEXT: wsbh $1, $5
; MIPS32R2-NEXT: rotr $1, $1, 16
; MIPS32R2-NEXT: lui $2, 61680
; MIPS32R2-NEXT: ori $6, $2, 61680
; MIPS32R2-NEXT: and $2, $3, $6
; MIPS32R2-NEXT: srl $2, $2, 4
; MIPS32R2-NEXT: sll $3, $3, 4
; MIPS32R2-NEXT: and $3, $3, $6
; MIPS32R2-NEXT: or $3, $2, $3
; MIPS32R2-NEXT: lui $2, 52428
; MIPS32R2-NEXT: ori $5, $2, 52428
; MIPS32R2-NEXT: and $2, $3, $5
; MIPS32R2-NEXT: srl $2, $2, 2
; MIPS32R2-NEXT: sll $3, $3, 2
; MIPS32R2-NEXT: and $3, $3, $5
; MIPS32R2-NEXT: or $3, $2, $3
; MIPS32R2-NEXT: lui $2, 43690
; MIPS32R2-NEXT: ori $4, $2, 43690
; MIPS32R2-NEXT: and $2, $3, $4
; MIPS32R2-NEXT: srl $2, $2, 1
; MIPS32R2-NEXT: sll $3, $3, 1
; MIPS32R2-NEXT: and $3, $3, $4
; MIPS32R2-NEXT: or $2, $2, $3
; MIPS32R2-NEXT: wsbh $1, $1
; MIPS32R2-NEXT: rotr $3, $1, 16
; MIPS32R2-NEXT: and $1, $3, $6
; MIPS32R2-NEXT: srl $1, $1, 4
; MIPS32R2-NEXT: sll $3, $3, 4
; MIPS32R2-NEXT: and $3, $3, $6
; MIPS32R2-NEXT: or $3, $1, $3
; MIPS32R2-NEXT: and $1, $3, $5
; MIPS32R2-NEXT: srl $1, $1, 2
; MIPS32R2-NEXT: sll $3, $3, 2
; MIPS32R2-NEXT: and $3, $3, $5
; MIPS32R2-NEXT: or $3, $1, $3
; MIPS32R2-NEXT: and $1, $3, $4
; MIPS32R2-NEXT: srl $1, $1, 1
; MIPS32R2-NEXT: sll $3, $3, 1
; MIPS32R2-NEXT: and $3, $3, $4
; MIPS32R2-NEXT: or $3, $1, $3
; MIPS32R2-NEXT: ori $2, $2, 61680
; MIPS32R2-NEXT: and $3, $1, $2
; MIPS32R2-NEXT: srl $3, $3, 4
; MIPS32R2-NEXT: sll $1, $1, 4
; MIPS32R2-NEXT: and $1, $1, $2
; MIPS32R2-NEXT: or $1, $3, $1
; MIPS32R2-NEXT: lui $3, 52428
; MIPS32R2-NEXT: ori $3, $3, 52428
; MIPS32R2-NEXT: and $5, $1, $3
; MIPS32R2-NEXT: srl $5, $5, 2
; MIPS32R2-NEXT: sll $1, $1, 2
; MIPS32R2-NEXT: and $1, $1, $3
; MIPS32R2-NEXT: or $1, $5, $1
; MIPS32R2-NEXT: lui $5, 43690
; MIPS32R2-NEXT: ori $5, $5, 43690
; MIPS32R2-NEXT: and $6, $1, $5
; MIPS32R2-NEXT: srl $6, $6, 1
; MIPS32R2-NEXT: sll $1, $1, 1
; MIPS32R2-NEXT: and $1, $1, $5
; MIPS32R2-NEXT: or $1, $6, $1
; MIPS32R2-NEXT: wsbh $4, $4
; MIPS32R2-NEXT: rotr $4, $4, 16
; MIPS32R2-NEXT: and $6, $4, $2
; MIPS32R2-NEXT: srl $6, $6, 4
; MIPS32R2-NEXT: sll $4, $4, 4
; MIPS32R2-NEXT: and $2, $4, $2
; MIPS32R2-NEXT: or $2, $6, $2
; MIPS32R2-NEXT: and $4, $2, $3
; MIPS32R2-NEXT: srl $4, $4, 2
; MIPS32R2-NEXT: sll $2, $2, 2
; MIPS32R2-NEXT: and $2, $2, $3
; MIPS32R2-NEXT: or $2, $4, $2
; MIPS32R2-NEXT: and $3, $2, $5
; MIPS32R2-NEXT: srl $3, $3, 1
; MIPS32R2-NEXT: sll $2, $2, 1
; MIPS32R2-NEXT: and $2, $2, $5
; MIPS32R2-NEXT: or $3, $3, $2
; MIPS32R2-NEXT: move $2, $1
; MIPS32R2-NEXT: jr $ra
; MIPS32R2-NEXT: nop
entry:
Expand Down
132 changes: 62 additions & 70 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bitwise.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -320,10 +320,10 @@ define i8 @ashr_i8(i8 %a) {
; MIPS32-LABEL: ashr_i8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 2
; MIPS32-NEXT: andi $2, $1, 255
; MIPS32-NEXT: sll $1, $4, 24
; MIPS32-NEXT: sra $1, $1, 24
; MIPS32-NEXT: srav $2, $1, $2
; MIPS32-NEXT: andi $1, $1, 255
; MIPS32-NEXT: sll $2, $4, 24
; MIPS32-NEXT: sra $2, $2, 24
; MIPS32-NEXT: srav $2, $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -335,9 +335,9 @@ define i16 @lshr_i16(i16 %a) {
; MIPS32-LABEL: lshr_i16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $1, $zero, 2
; MIPS32-NEXT: andi $2, $1, 65535
; MIPS32-NEXT: andi $1, $4, 65535
; MIPS32-NEXT: srlv $2, $1, $2
; MIPS32-NEXT: andi $1, $1, 65535
; MIPS32-NEXT: andi $2, $4, 65535
; MIPS32-NEXT: srlv $2, $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -348,25 +348,29 @@ entry:
define i64 @shl_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: shl_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $3, $4
; MIPS32-NEXT: move $9, $6
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
; MIPS32-NEXT: ori $1, $zero, 32
; MIPS32-NEXT: subu $8, $9, $1
; MIPS32-NEXT: subu $4, $1, $9
; MIPS32-NEXT: ori $2, $zero, 0
; MIPS32-NEXT: sltu $6, $9, $1
; MIPS32-NEXT: sltiu $1, $9, 1
; MIPS32-NEXT: sllv $7, $3, $9
; MIPS32-NEXT: srlv $4, $3, $4
; MIPS32-NEXT: sllv $9, $5, $9
; MIPS32-NEXT: or $4, $4, $9
; MIPS32-NEXT: sllv $3, $3, $8
; MIPS32-NEXT: andi $8, $6, 1
; MIPS32-NEXT: movn $2, $7, $8
; MIPS32-NEXT: andi $6, $6, 1
; MIPS32-NEXT: movn $3, $4, $6
; MIPS32-NEXT: subu $2, $6, $1
; MIPS32-NEXT: subu $3, $1, $6
; MIPS32-NEXT: ori $8, $zero, 0
; MIPS32-NEXT: sltu $1, $6, $1
; MIPS32-NEXT: sltiu $9, $6, 1
; MIPS32-NEXT: sllv $10, $4, $6
; MIPS32-NEXT: srlv $3, $4, $3
; MIPS32-NEXT: sllv $6, $5, $6
; MIPS32-NEXT: or $3, $3, $6
; MIPS32-NEXT: sllv $2, $4, $2
; MIPS32-NEXT: andi $4, $1, 1
; MIPS32-NEXT: movn $8, $10, $4
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: movn $3, $5, $1
; MIPS32-NEXT: movn $2, $3, $1
; MIPS32-NEXT: andi $1, $9, 1
; MIPS32-NEXT: movn $2, $5, $1
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $2, $8
; MIPS32-NEXT: lw $3, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -377,30 +381,24 @@ entry:
define i64 @ashl_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: ashl_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
; MIPS32-NEXT: sw $4, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $2, $5
; MIPS32-NEXT: lw $5, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: move $3, $6
; MIPS32-NEXT: ori $1, $zero, 32
; MIPS32-NEXT: subu $8, $3, $1
; MIPS32-NEXT: subu $7, $1, $3
; MIPS32-NEXT: sltu $4, $3, $1
; MIPS32-NEXT: sltiu $6, $3, 1
; MIPS32-NEXT: srav $1, $2, $3
; MIPS32-NEXT: srlv $3, $5, $3
; MIPS32-NEXT: sllv $7, $2, $7
; MIPS32-NEXT: or $7, $3, $7
; MIPS32-NEXT: sra $3, $2, 31
; MIPS32-NEXT: srav $2, $2, $8
; MIPS32-NEXT: andi $8, $4, 1
; MIPS32-NEXT: movn $2, $7, $8
; MIPS32-NEXT: andi $6, $6, 1
; MIPS32-NEXT: movn $2, $5, $6
; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: movn $3, $1, $4
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: subu $2, $6, $1
; MIPS32-NEXT: subu $3, $1, $6
; MIPS32-NEXT: sltu $1, $6, $1
; MIPS32-NEXT: sltiu $8, $6, 1
; MIPS32-NEXT: srav $9, $5, $6
; MIPS32-NEXT: srlv $6, $4, $6
; MIPS32-NEXT: sllv $3, $5, $3
; MIPS32-NEXT: or $3, $6, $3
; MIPS32-NEXT: sra $6, $5, 31
; MIPS32-NEXT: srav $2, $5, $2
; MIPS32-NEXT: andi $5, $1, 1
; MIPS32-NEXT: movn $2, $3, $5
; MIPS32-NEXT: andi $3, $8, 1
; MIPS32-NEXT: movn $2, $4, $3
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: movn $6, $9, $1
; MIPS32-NEXT: move $3, $6
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -411,30 +409,24 @@ entry:
define i64 @lshr_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: lshr_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
; MIPS32-NEXT: sw $4, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $2, $5
; MIPS32-NEXT: lw $5, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: move $7, $6
; MIPS32-NEXT: ori $1, $zero, 32
; MIPS32-NEXT: subu $8, $7, $1
; MIPS32-NEXT: subu $9, $1, $7
; MIPS32-NEXT: ori $3, $zero, 0
; MIPS32-NEXT: sltu $4, $7, $1
; MIPS32-NEXT: sltiu $6, $7, 1
; MIPS32-NEXT: srlv $1, $2, $7
; MIPS32-NEXT: srlv $7, $5, $7
; MIPS32-NEXT: sllv $9, $2, $9
; MIPS32-NEXT: or $7, $7, $9
; MIPS32-NEXT: srlv $2, $2, $8
; MIPS32-NEXT: andi $8, $4, 1
; MIPS32-NEXT: movn $2, $7, $8
; MIPS32-NEXT: andi $6, $6, 1
; MIPS32-NEXT: movn $2, $5, $6
; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: movn $3, $1, $4
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: subu $2, $6, $1
; MIPS32-NEXT: subu $3, $1, $6
; MIPS32-NEXT: ori $8, $zero, 0
; MIPS32-NEXT: sltu $1, $6, $1
; MIPS32-NEXT: sltiu $9, $6, 1
; MIPS32-NEXT: srlv $10, $5, $6
; MIPS32-NEXT: srlv $6, $4, $6
; MIPS32-NEXT: sllv $3, $5, $3
; MIPS32-NEXT: or $3, $6, $3
; MIPS32-NEXT: srlv $2, $5, $2
; MIPS32-NEXT: andi $5, $1, 1
; MIPS32-NEXT: movn $2, $3, $5
; MIPS32-NEXT: andi $3, $9, 1
; MIPS32-NEXT: movn $2, $4, $3
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: movn $8, $10, $1
; MIPS32-NEXT: move $3, $8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/branch.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -30,21 +30,21 @@ define i32 @Conditional_branch(i1 %cond, i32 %a, i32 %b) {
; MIPS32: # %bb.0:
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
; MIPS32-NEXT: sw $5, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: andi $1, $4, 1
; MIPS32-NEXT: sw $5, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB1_2
; MIPS32-NEXT: nop
; MIPS32-NEXT: # %bb.1:
; MIPS32-NEXT: j $BB1_3
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_2: # %if.then
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB1_3: # %if.else
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/brindirect.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,19 +6,19 @@ define i32 @indirectbr(i8 *%addr) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $2, $zero, 1
; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: jr $4
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_1: # %L1
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_2: # %L2
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 8
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/bswap.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,9 +6,9 @@ declare i32 @llvm.bswap.i32(i32)
define i32 @bswap_i32(i32 %x) {
; MIPS32-LABEL: bswap_i32:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sll $2, $4, 24
; MIPS32-NEXT: srl $1, $4, 24
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: sll $1, $4, 24
; MIPS32-NEXT: srl $2, $4, 24
; MIPS32-NEXT: or $1, $2, $1
; MIPS32-NEXT: andi $2, $4, 65280
; MIPS32-NEXT: sll $2, $2, 8
; MIPS32-NEXT: or $1, $1, $2
Expand All @@ -33,18 +33,18 @@ declare i64 @llvm.bswap.i64(i64)
define i64 @bswap_i64(i64 %x) {
; MIPS32-LABEL: bswap_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sll $2, $5, 24
; MIPS32-NEXT: srl $1, $5, 24
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: sll $1, $5, 24
; MIPS32-NEXT: srl $2, $5, 24
; MIPS32-NEXT: or $1, $2, $1
; MIPS32-NEXT: andi $2, $5, 65280
; MIPS32-NEXT: sll $2, $2, 8
; MIPS32-NEXT: or $1, $1, $2
; MIPS32-NEXT: srl $2, $5, 8
; MIPS32-NEXT: andi $2, $2, 65280
; MIPS32-NEXT: or $2, $1, $2
; MIPS32-NEXT: sll $3, $4, 24
; MIPS32-NEXT: srl $1, $4, 24
; MIPS32-NEXT: or $1, $1, $3
; MIPS32-NEXT: sll $1, $4, 24
; MIPS32-NEXT: srl $3, $4, 24
; MIPS32-NEXT: or $1, $3, $1
; MIPS32-NEXT: andi $3, $4, 65280
; MIPS32-NEXT: sll $3, $3, 8
; MIPS32-NEXT: or $1, $1, $3
Expand Down
18 changes: 11 additions & 7 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/call.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -29,10 +29,11 @@ define i32 @call_global(i32 %a0, i32 %a1, i32 %x, i32 %y) {
; MIPS32_PIC-NEXT: .cfi_def_cfa_offset 24
; MIPS32_PIC-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: .cfi_offset 31, -4
; MIPS32_PIC-NEXT: addu $gp, $2, $25
; MIPS32_PIC-NEXT: addu $1, $2, $25
; MIPS32_PIC-NEXT: lw $25, %call16(f)($1)
; MIPS32_PIC-NEXT: move $4, $6
; MIPS32_PIC-NEXT: move $5, $7
; MIPS32_PIC-NEXT: lw $25, %call16(f)($gp)
; MIPS32_PIC-NEXT: move $gp, $1
; MIPS32_PIC-NEXT: jalr $25
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: addu $2, $2, $2
Expand Down Expand Up @@ -88,11 +89,12 @@ define i32 @call_global_with_local_linkage(i32 %a0, i32 %a1, i32 %x, i32 %y) {
; MIPS32_PIC-NEXT: .cfi_def_cfa_offset 24
; MIPS32_PIC-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: .cfi_offset 31, -4
; MIPS32_PIC-NEXT: addu $gp, $2, $25
; MIPS32_PIC-NEXT: addu $1, $2, $25
; MIPS32_PIC-NEXT: lw $2, %got(f_with_local_linkage)($1)
; MIPS32_PIC-NEXT: addiu $25, $2, %lo(f_with_local_linkage)
; MIPS32_PIC-NEXT: move $4, $6
; MIPS32_PIC-NEXT: move $5, $7
; MIPS32_PIC-NEXT: lw $1, %got(f_with_local_linkage)($gp)
; MIPS32_PIC-NEXT: addiu $25, $1, %lo(f_with_local_linkage)
; MIPS32_PIC-NEXT: move $gp, $1
; MIPS32_PIC-NEXT: jalr $25
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: addu $2, $2, $2
Expand All @@ -113,9 +115,10 @@ define i32 @call_reg(i32 (i32, i32)* %f_ptr, i32 %x, i32 %y) {
; MIPS32-NEXT: .cfi_def_cfa_offset 24
; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: .cfi_offset 31, -4
; MIPS32-NEXT: move $25, $4
; MIPS32-NEXT: sw $4, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: move $4, $5
; MIPS32-NEXT: move $5, $6
; MIPS32-NEXT: lw $25, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: jalr $25
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
Expand All @@ -129,9 +132,10 @@ define i32 @call_reg(i32 (i32, i32)* %f_ptr, i32 %x, i32 %y) {
; MIPS32_PIC-NEXT: .cfi_def_cfa_offset 24
; MIPS32_PIC-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: .cfi_offset 31, -4
; MIPS32_PIC-NEXT: move $25, $4
; MIPS32_PIC-NEXT: sw $4, 16($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: move $4, $5
; MIPS32_PIC-NEXT: move $5, $6
; MIPS32_PIC-NEXT: lw $25, 16($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: jalr $25
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctlz.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,14 +17,14 @@ declare i32 @llvm.ctlz.i32(i32, i1 immarg)
define i64 @ctlz_i64(i64 %a) {
; MIPS32-LABEL: ctlz_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $1, $4
; MIPS32-NEXT: ori $3, $zero, 0
; MIPS32-NEXT: sltiu $4, $5, 1
; MIPS32-NEXT: clz $1, $1
; MIPS32-NEXT: addiu $1, $1, 32
; MIPS32-NEXT: clz $2, $5
; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: movn $2, $1, $4
; MIPS32-NEXT: sltiu $1, $5, 1
; MIPS32-NEXT: clz $2, $4
; MIPS32-NEXT: addiu $2, $2, 32
; MIPS32-NEXT: clz $4, $5
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: movn $4, $2, $1
; MIPS32-NEXT: move $2, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand Down
70 changes: 35 additions & 35 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/ctpop.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,15 +8,15 @@ define i32 @ctpop_i32(i32 %a) {
; MIPS32-NEXT: lui $2, 21845
; MIPS32-NEXT: ori $2, $2, 21845
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: subu $2, $4, $1
; MIPS32-NEXT: srl $1, $2, 2
; MIPS32-NEXT: subu $1, $4, $1
; MIPS32-NEXT: srl $2, $1, 2
; MIPS32-NEXT: lui $3, 13107
; MIPS32-NEXT: ori $3, $3, 13107
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: addu $2, $1, $2
; MIPS32-NEXT: srl $1, $2, 4
; MIPS32-NEXT: addu $1, $1, $2
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: addu $1, $2, $1
; MIPS32-NEXT: srl $2, $1, 4
; MIPS32-NEXT: addu $1, $2, $1
; MIPS32-NEXT: lui $2, 3855
; MIPS32-NEXT: ori $2, $2, 3855
; MIPS32-NEXT: and $1, $1, $2
Expand All @@ -38,37 +38,37 @@ define i64 @ctpop_i64(i64 %a) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: srl $1, $4, 1
; MIPS32-NEXT: lui $2, 21845
; MIPS32-NEXT: ori $7, $2, 21845
; MIPS32-NEXT: and $1, $1, $7
; MIPS32-NEXT: subu $2, $4, $1
; MIPS32-NEXT: srl $1, $2, 2
; MIPS32-NEXT: lui $3, 13107
; MIPS32-NEXT: ori $6, $3, 13107
; MIPS32-NEXT: and $1, $1, $6
; MIPS32-NEXT: and $2, $2, $6
; MIPS32-NEXT: addu $2, $1, $2
; MIPS32-NEXT: srl $1, $2, 4
; MIPS32-NEXT: addu $1, $1, $2
; MIPS32-NEXT: lui $2, 3855
; MIPS32-NEXT: ori $4, $2, 3855
; MIPS32-NEXT: and $1, $1, $4
; MIPS32-NEXT: lui $2, 257
; MIPS32-NEXT: ori $3, $2, 257
; MIPS32-NEXT: mul $1, $1, $3
; MIPS32-NEXT: srl $2, $1, 24
; MIPS32-NEXT: srl $1, $5, 1
; MIPS32-NEXT: and $1, $1, $7
; MIPS32-NEXT: subu $5, $5, $1
; MIPS32-NEXT: srl $1, $5, 2
; MIPS32-NEXT: and $1, $1, $6
; MIPS32-NEXT: and $5, $5, $6
; MIPS32-NEXT: addu $5, $1, $5
; MIPS32-NEXT: srl $1, $5, 4
; MIPS32-NEXT: addu $1, $1, $5
; MIPS32-NEXT: ori $2, $2, 21845
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: subu $1, $4, $1
; MIPS32-NEXT: srl $3, $1, 2
; MIPS32-NEXT: lui $4, 13107
; MIPS32-NEXT: ori $4, $4, 13107
; MIPS32-NEXT: and $3, $3, $4
; MIPS32-NEXT: and $1, $1, $4
; MIPS32-NEXT: mul $1, $1, $3
; MIPS32-NEXT: addu $1, $3, $1
; MIPS32-NEXT: srl $3, $1, 4
; MIPS32-NEXT: addu $1, $3, $1
; MIPS32-NEXT: lui $3, 3855
; MIPS32-NEXT: ori $3, $3, 3855
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: lui $6, 257
; MIPS32-NEXT: ori $6, $6, 257
; MIPS32-NEXT: mul $1, $1, $6
; MIPS32-NEXT: srl $1, $1, 24
; MIPS32-NEXT: addu $2, $1, $2
; MIPS32-NEXT: srl $7, $5, 1
; MIPS32-NEXT: and $2, $7, $2
; MIPS32-NEXT: subu $2, $5, $2
; MIPS32-NEXT: srl $5, $2, 2
; MIPS32-NEXT: and $5, $5, $4
; MIPS32-NEXT: and $2, $2, $4
; MIPS32-NEXT: addu $2, $5, $2
; MIPS32-NEXT: srl $4, $2, 4
; MIPS32-NEXT: addu $2, $4, $2
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: mul $2, $2, $6
; MIPS32-NEXT: srl $2, $2, 24
; MIPS32-NEXT: addu $2, $2, $1
; MIPS32-NEXT: ori $3, $zero, 0
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
Expand Down
86 changes: 44 additions & 42 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/cttz.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,10 +6,10 @@ define i32 @cttz_i32(i32 %a) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: not $1, $4
; MIPS32-NEXT: addiu $2, $4, -1
; MIPS32-NEXT: and $2, $1, $2
; MIPS32-NEXT: ori $1, $zero, 32
; MIPS32-NEXT: clz $2, $2
; MIPS32-NEXT: subu $2, $1, $2
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: ori $2, $zero, 32
; MIPS32-NEXT: clz $1, $1
; MIPS32-NEXT: subu $2, $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -21,23 +21,23 @@ declare i32 @llvm.cttz.i32(i32, i1 immarg)
define i64 @cttz_i64(i64 %a) {
; MIPS32-LABEL: cttz_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: move $6, $4
; MIPS32-NEXT: ori $3, $zero, 0
; MIPS32-NEXT: sltiu $4, $6, 1
; MIPS32-NEXT: not $1, $5
; MIPS32-NEXT: addiu $2, $5, -1
; MIPS32-NEXT: and $1, $1, $2
; MIPS32-NEXT: ori $2, $zero, 32
; MIPS32-NEXT: clz $1, $1
; MIPS32-NEXT: subu $1, $2, $1
; MIPS32-NEXT: addiu $1, $1, 32
; MIPS32-NEXT: not $5, $6
; MIPS32-NEXT: addiu $6, $6, -1
; MIPS32-NEXT: and $5, $5, $6
; MIPS32-NEXT: clz $5, $5
; MIPS32-NEXT: subu $2, $2, $5
; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: movn $2, $1, $4
; MIPS32-NEXT: sltiu $1, $4, 1
; MIPS32-NEXT: not $2, $5
; MIPS32-NEXT: addiu $5, $5, -1
; MIPS32-NEXT: and $2, $2, $5
; MIPS32-NEXT: ori $5, $zero, 32
; MIPS32-NEXT: clz $2, $2
; MIPS32-NEXT: subu $2, $5, $2
; MIPS32-NEXT: addiu $2, $2, 32
; MIPS32-NEXT: not $6, $4
; MIPS32-NEXT: addiu $4, $4, -1
; MIPS32-NEXT: and $4, $6, $4
; MIPS32-NEXT: clz $4, $4
; MIPS32-NEXT: subu $4, $5, $4
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: movn $4, $2, $1
; MIPS32-NEXT: move $2, $4
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -53,10 +53,10 @@ define i32 @ffs_i32_expansion(i32 %a) {
; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: not $2, $4
; MIPS32-NEXT: addiu $3, $4, -1
; MIPS32-NEXT: and $3, $2, $3
; MIPS32-NEXT: ori $2, $zero, 32
; MIPS32-NEXT: clz $3, $3
; MIPS32-NEXT: subu $2, $2, $3
; MIPS32-NEXT: and $2, $2, $3
; MIPS32-NEXT: ori $3, $zero, 32
; MIPS32-NEXT: clz $2, $2
; MIPS32-NEXT: subu $2, $3, $2
; MIPS32-NEXT: addiu $2, $2, 1
; MIPS32-NEXT: sltiu $3, $4, 1
; MIPS32-NEXT: andi $3, $3, 1
Expand All @@ -74,35 +74,37 @@ entry:
define i64 @ffs_i64_expansion(i64 %a) {
; MIPS32-LABEL: ffs_i64_expansion:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: ori $3, $zero, 1
; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: sltiu $7, $4, 1
; MIPS32-NEXT: not $2, $5
; MIPS32-NEXT: addiu $6, $5, -1
; MIPS32-NEXT: and $6, $2, $6
; MIPS32-NEXT: ori $2, $zero, 32
; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: ori $2, $zero, 0
; MIPS32-NEXT: sltiu $3, $4, 1
; MIPS32-NEXT: not $6, $5
; MIPS32-NEXT: addiu $7, $5, -1
; MIPS32-NEXT: and $6, $6, $7
; MIPS32-NEXT: ori $7, $zero, 32
; MIPS32-NEXT: clz $6, $6
; MIPS32-NEXT: subu $6, $2, $6
; MIPS32-NEXT: subu $6, $7, $6
; MIPS32-NEXT: addiu $6, $6, 32
; MIPS32-NEXT: not $8, $4
; MIPS32-NEXT: addiu $9, $4, -1
; MIPS32-NEXT: and $8, $8, $9
; MIPS32-NEXT: clz $8, $8
; MIPS32-NEXT: subu $2, $2, $8
; MIPS32-NEXT: andi $7, $7, 1
; MIPS32-NEXT: movn $2, $6, $7
; MIPS32-NEXT: addiu $2, $2, 1
; MIPS32-NEXT: sltu $6, $2, $3
; MIPS32-NEXT: addiu $3, $1, 0
; MIPS32-NEXT: andi $6, $6, 1
; MIPS32-NEXT: addu $3, $3, $6
; MIPS32-NEXT: subu $7, $7, $8
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $7, $6, $3
; MIPS32-NEXT: addiu $3, $7, 1
; MIPS32-NEXT: sltu $1, $3, $1
; MIPS32-NEXT: addiu $6, $2, 0
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: addu $1, $6, $1
; MIPS32-NEXT: xori $4, $4, 0
; MIPS32-NEXT: xori $5, $5, 0
; MIPS32-NEXT: or $4, $4, $5
; MIPS32-NEXT: sltiu $4, $4, 1
; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: movn $2, $1, $4
; MIPS32-NEXT: movn $3, $1, $4
; MIPS32-NEXT: movn $3, $2, $4
; MIPS32-NEXT: movn $1, $2, $4
; MIPS32-NEXT: move $2, $3
; MIPS32-NEXT: move $3, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand Down
43 changes: 23 additions & 20 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/dyn_stackalloc.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,32 +15,35 @@ define void @Print_c_N_times(i8 %c, i32 %N) {
; MIPS32-NEXT: .cfi_offset 30, -8
; MIPS32-NEXT: move $fp, $sp
; MIPS32-NEXT: .cfi_def_cfa_register 30
; MIPS32-NEXT: sw $4, 8($fp) # 4-byte Folded Spill
; MIPS32-NEXT: move $6, $5
; MIPS32-NEXT: lw $5, 8($fp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $6, 12($fp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $2, $zero, 1
; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: sw $1, 16($fp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $1, $6, 1
; MIPS32-NEXT: mul $1, $1, $2
; MIPS32-NEXT: ori $1, $zero, 1
; MIPS32-NEXT: ori $2, $zero, 0
; MIPS32-NEXT: addiu $3, $5, 1
; MIPS32-NEXT: mul $1, $3, $1
; MIPS32-NEXT: addiu $1, $1, 7
; MIPS32-NEXT: addiu $2, $zero, 65528
; MIPS32-NEXT: and $2, $1, $2
; MIPS32-NEXT: move $1, $sp
; MIPS32-NEXT: subu $4, $1, $2
; MIPS32-NEXT: sw $4, 20($fp) # 4-byte Folded Spill
; MIPS32-NEXT: move $sp, $4
; MIPS32-NEXT: addiu $3, $zero, 65528
; MIPS32-NEXT: and $1, $1, $3
; MIPS32-NEXT: move $3, $sp
; MIPS32-NEXT: subu $1, $3, $1
; MIPS32-NEXT: move $sp, $1
; MIPS32-NEXT: addiu $sp, $sp, -16
; MIPS32-NEXT: sw $4, 20($fp) # 4-byte Folded Spill
; MIPS32-NEXT: move $4, $1
; MIPS32-NEXT: lw $3, 20($fp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $5, 16($fp) # 4-byte Folded Spill
; MIPS32-NEXT: move $5, $3
; MIPS32-NEXT: lw $6, 16($fp) # 4-byte Folded Reload
; MIPS32-NEXT: sw $2, 12($fp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $1, 8($fp) # 4-byte Folded Spill
; MIPS32-NEXT: jal memset
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $5, 12($fp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 16($fp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $4, 20($fp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 16
; MIPS32-NEXT: addu $2, $4, $5
; MIPS32-NEXT: sb $1, 0($2)
; MIPS32-NEXT: lw $1, 8($fp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 16($fp) # 4-byte Folded Reload
; MIPS32-NEXT: addu $3, $1, $2
; MIPS32-NEXT: lw $4, 12($fp) # 4-byte Folded Reload
; MIPS32-NEXT: sb $4, 0($3)
; MIPS32-NEXT: addiu $sp, $sp, -16
; MIPS32-NEXT: move $4, $1
; MIPS32-NEXT: jal puts
; MIPS32-NEXT: nop
; MIPS32-NEXT: addiu $sp, $sp, 16
Expand Down
140 changes: 84 additions & 56 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fcmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,9 +27,10 @@ entry:
define i1 @uno_s(float %x, float %y) {
; MIPS32-LABEL: uno_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.un.s $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -39,9 +40,10 @@ entry:
define i1 @ord_s(float %x, float %y) {
; MIPS32-LABEL: ord_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.un.s $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -53,9 +55,10 @@ entry:
define i1 @oeq_s(float %x, float %y) {
; MIPS32-LABEL: oeq_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.eq.s $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -65,9 +68,10 @@ entry:
define i1 @une_s(float %x, float %y) {
; MIPS32-LABEL: une_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.eq.s $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -79,9 +83,10 @@ entry:
define i1 @ueq_s(float %x, float %y) {
; MIPS32-LABEL: ueq_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ueq.s $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -91,9 +96,10 @@ entry:
define i1 @one_s(float %x, float %y) {
; MIPS32-LABEL: one_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ueq.s $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -105,9 +111,10 @@ entry:
define i1 @olt_s(float %x, float %y) {
; MIPS32-LABEL: olt_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.olt.s $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -117,9 +124,10 @@ entry:
define i1 @uge_s(float %x, float %y) {
; MIPS32-LABEL: uge_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.olt.s $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -131,9 +139,10 @@ entry:
define i1 @ult_s(float %x, float %y) {
; MIPS32-LABEL: ult_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -143,9 +152,10 @@ entry:
define i1 @oge_s(float %x, float %y) {
; MIPS32-LABEL: oge_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -157,9 +167,10 @@ entry:
define i1 @ole_s(float %x, float %y) {
; MIPS32-LABEL: ole_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ole.s $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -169,9 +180,10 @@ entry:
define i1 @ugt_s(float %x, float %y) {
; MIPS32-LABEL: ugt_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ole.s $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -183,9 +195,10 @@ entry:
define i1 @ule_s(float %x, float %y) {
; MIPS32-LABEL: ule_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ule.s $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -195,9 +208,10 @@ entry:
define i1 @ogt_s(float %x, float %y) {
; MIPS32-LABEL: ogt_s:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ule.s $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand Down Expand Up @@ -231,9 +245,10 @@ entry:
define i1 @uno_d(double %x, double %y) {
; MIPS32-LABEL: uno_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.un.d $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -243,9 +258,10 @@ entry:
define i1 @ord_d(double %x, double %y) {
; MIPS32-LABEL: ord_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.un.d $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -257,9 +273,10 @@ entry:
define i1 @oeq_d(double %x, double %y) {
; MIPS32-LABEL: oeq_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.eq.d $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -269,9 +286,10 @@ entry:
define i1 @une_d(double %x, double %y) {
; MIPS32-LABEL: une_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.eq.d $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -283,9 +301,10 @@ entry:
define i1 @ueq_d(double %x, double %y) {
; MIPS32-LABEL: ueq_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ueq.d $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -295,9 +314,10 @@ entry:
define i1 @one_d(double %x, double %y) {
; MIPS32-LABEL: one_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ueq.d $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -309,9 +329,10 @@ entry:
define i1 @olt_d(double %x, double %y) {
; MIPS32-LABEL: olt_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.olt.d $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -321,9 +342,10 @@ entry:
define i1 @uge_d(double %x, double %y) {
; MIPS32-LABEL: uge_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.olt.d $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -335,9 +357,10 @@ entry:
define i1 @ult_d(double %x, double %y) {
; MIPS32-LABEL: ult_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ult.d $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -347,9 +370,10 @@ entry:
define i1 @oge_d(double %x, double %y) {
; MIPS32-LABEL: oge_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ult.d $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -361,9 +385,10 @@ entry:
define i1 @ole_d(double %x, double %y) {
; MIPS32-LABEL: ole_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ole.d $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -373,9 +398,10 @@ entry:
define i1 @ugt_d(double %x, double %y) {
; MIPS32-LABEL: ugt_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ole.d $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -387,9 +413,10 @@ entry:
define i1 @ule_d(double %x, double %y) {
; MIPS32-LABEL: ule_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ule.d $f12, $f14
; MIPS32-NEXT: movf $2, $zero, $fcc0
; MIPS32-NEXT: movf $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -399,9 +426,10 @@ entry:
define i1 @ogt_d(double %x, double %y) {
; MIPS32-LABEL: ogt_d:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $2, $zero, 1
; MIPS32-NEXT: addiu $1, $zero, 1
; MIPS32-NEXT: c.ule.d $f12, $f14
; MIPS32-NEXT: movt $2, $zero, $fcc0
; MIPS32-NEXT: movt $1, $zero, $fcc0
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/float_constants.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,22 +18,22 @@ define double @e_double_precision() {
; FP32-LABEL: e_double_precision:
; FP32: # %bb.0: # %entry
; FP32-NEXT: lui $1, 16389
; FP32-NEXT: ori $2, $1, 48906
; FP32-NEXT: lui $1, 35604
; FP32-NEXT: ori $1, $1, 22377
; FP32-NEXT: mtc1 $1, $f0
; FP32-NEXT: mtc1 $2, $f1
; FP32-NEXT: ori $1, $1, 48906
; FP32-NEXT: lui $2, 35604
; FP32-NEXT: ori $2, $2, 22377
; FP32-NEXT: mtc1 $2, $f0
; FP32-NEXT: mtc1 $1, $f1
; FP32-NEXT: jr $ra
; FP32-NEXT: nop
;
; FP64-LABEL: e_double_precision:
; FP64: # %bb.0: # %entry
; FP64-NEXT: lui $1, 16389
; FP64-NEXT: ori $2, $1, 48906
; FP64-NEXT: lui $1, 35604
; FP64-NEXT: ori $1, $1, 22377
; FP64-NEXT: mtc1 $1, $f0
; FP64-NEXT: mthc1 $2, $f0
; FP64-NEXT: ori $1, $1, 48906
; FP64-NEXT: lui $2, 35604
; FP64-NEXT: ori $2, $2, 22377
; FP64-NEXT: mtc1 $2, $f0
; FP64-NEXT: mthc1 $1, $f0
; FP64-NEXT: jr $ra
; FP64-NEXT: nop
entry:
Expand Down
116 changes: 58 additions & 58 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/fptosi_and_fptoui.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -164,20 +164,20 @@ define zeroext i16 @f32tou16(float %a) {
; MIPS32-LABEL: f32tou16:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: trunc.w.s $f0, $f12
; MIPS32-NEXT: mfc1 $2, $f0
; MIPS32-NEXT: lui $1, 20224
; MIPS32-NEXT: mtc1 $1, $f0
; MIPS32-NEXT: mfc1 $1, $f0
; MIPS32-NEXT: lui $2, 20224
; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: sub.s $f1, $f12, $f0
; MIPS32-NEXT: trunc.w.s $f1, $f1
; MIPS32-NEXT: mfc1 $1, $f1
; MIPS32-NEXT: mfc1 $2, $f1
; MIPS32-NEXT: lui $3, 32768
; MIPS32-NEXT: xor $1, $1, $3
; MIPS32-NEXT: xor $2, $2, $3
; MIPS32-NEXT: addiu $3, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f0
; MIPS32-NEXT: movf $3, $zero, $fcc0
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $1, $2, $3
; MIPS32-NEXT: andi $2, $1, 65535
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: andi $2, $2, 65535
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -189,20 +189,20 @@ define zeroext i8 @f32tou8(float %a) {
; MIPS32-LABEL: f32tou8:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: trunc.w.s $f0, $f12
; MIPS32-NEXT: mfc1 $2, $f0
; MIPS32-NEXT: lui $1, 20224
; MIPS32-NEXT: mtc1 $1, $f0
; MIPS32-NEXT: mfc1 $1, $f0
; MIPS32-NEXT: lui $2, 20224
; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: sub.s $f1, $f12, $f0
; MIPS32-NEXT: trunc.w.s $f1, $f1
; MIPS32-NEXT: mfc1 $1, $f1
; MIPS32-NEXT: mfc1 $2, $f1
; MIPS32-NEXT: lui $3, 32768
; MIPS32-NEXT: xor $1, $1, $3
; MIPS32-NEXT: xor $2, $2, $3
; MIPS32-NEXT: addiu $3, $zero, 1
; MIPS32-NEXT: c.ult.s $f12, $f0
; MIPS32-NEXT: movf $3, $zero, $fcc0
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $1, $2, $3
; MIPS32-NEXT: andi $2, $1, 255
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: andi $2, $2, 255
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand Down Expand Up @@ -233,10 +233,10 @@ define i32 @f64tou32(double %a) {
; FP32: # %bb.0: # %entry
; FP32-NEXT: trunc.w.d $f0, $f12
; FP32-NEXT: mfc1 $1, $f0
; FP32-NEXT: lui $3, 16864
; FP32-NEXT: ori $2, $zero, 0
; FP32-NEXT: mtc1 $2, $f0
; FP32-NEXT: mtc1 $3, $f1
; FP32-NEXT: lui $2, 16864
; FP32-NEXT: ori $3, $zero, 0
; FP32-NEXT: mtc1 $3, $f0
; FP32-NEXT: mtc1 $2, $f1
; FP32-NEXT: sub.d $f2, $f12, $f0
; FP32-NEXT: trunc.w.d $f2, $f2
; FP32-NEXT: mfc1 $2, $f2
Expand All @@ -254,10 +254,10 @@ define i32 @f64tou32(double %a) {
; FP64: # %bb.0: # %entry
; FP64-NEXT: trunc.w.d $f0, $f12
; FP64-NEXT: mfc1 $1, $f0
; FP64-NEXT: lui $3, 16864
; FP64-NEXT: ori $2, $zero, 0
; FP64-NEXT: mtc1 $2, $f0
; FP64-NEXT: mthc1 $3, $f0
; FP64-NEXT: lui $2, 16864
; FP64-NEXT: ori $3, $zero, 0
; FP64-NEXT: mtc1 $3, $f0
; FP64-NEXT: mthc1 $2, $f0
; FP64-NEXT: sub.d $f1, $f12, $f0
; FP64-NEXT: trunc.w.d $f1, $f1
; FP64-NEXT: mfc1 $2, $f1
Expand All @@ -279,44 +279,44 @@ define zeroext i16 @f64tou16(double %a) {
; FP32-LABEL: f64tou16:
; FP32: # %bb.0: # %entry
; FP32-NEXT: trunc.w.d $f0, $f12
; FP32-NEXT: mfc1 $2, $f0
; FP32-NEXT: lui $3, 16864
; FP32-NEXT: ori $1, $zero, 0
; FP32-NEXT: mtc1 $1, $f0
; FP32-NEXT: mtc1 $3, $f1
; FP32-NEXT: mfc1 $1, $f0
; FP32-NEXT: lui $2, 16864
; FP32-NEXT: ori $3, $zero, 0
; FP32-NEXT: mtc1 $3, $f0
; FP32-NEXT: mtc1 $2, $f1
; FP32-NEXT: sub.d $f2, $f12, $f0
; FP32-NEXT: trunc.w.d $f2, $f2
; FP32-NEXT: mfc1 $1, $f2
; FP32-NEXT: mfc1 $2, $f2
; FP32-NEXT: lui $3, 32768
; FP32-NEXT: xor $1, $1, $3
; FP32-NEXT: xor $2, $2, $3
; FP32-NEXT: addiu $3, $zero, 1
; FP32-NEXT: c.ult.d $f12, $f0
; FP32-NEXT: movf $3, $zero, $fcc0
; FP32-NEXT: andi $3, $3, 1
; FP32-NEXT: movn $1, $2, $3
; FP32-NEXT: andi $2, $1, 65535
; FP32-NEXT: movn $2, $1, $3
; FP32-NEXT: andi $2, $2, 65535
; FP32-NEXT: jr $ra
; FP32-NEXT: nop
;
; FP64-LABEL: f64tou16:
; FP64: # %bb.0: # %entry
; FP64-NEXT: trunc.w.d $f0, $f12
; FP64-NEXT: mfc1 $2, $f0
; FP64-NEXT: lui $3, 16864
; FP64-NEXT: ori $1, $zero, 0
; FP64-NEXT: mtc1 $1, $f0
; FP64-NEXT: mthc1 $3, $f0
; FP64-NEXT: mfc1 $1, $f0
; FP64-NEXT: lui $2, 16864
; FP64-NEXT: ori $3, $zero, 0
; FP64-NEXT: mtc1 $3, $f0
; FP64-NEXT: mthc1 $2, $f0
; FP64-NEXT: sub.d $f1, $f12, $f0
; FP64-NEXT: trunc.w.d $f1, $f1
; FP64-NEXT: mfc1 $1, $f1
; FP64-NEXT: mfc1 $2, $f1
; FP64-NEXT: lui $3, 32768
; FP64-NEXT: xor $1, $1, $3
; FP64-NEXT: xor $2, $2, $3
; FP64-NEXT: addiu $3, $zero, 1
; FP64-NEXT: c.ult.d $f12, $f0
; FP64-NEXT: movf $3, $zero, $fcc0
; FP64-NEXT: andi $3, $3, 1
; FP64-NEXT: movn $1, $2, $3
; FP64-NEXT: andi $2, $1, 65535
; FP64-NEXT: movn $2, $1, $3
; FP64-NEXT: andi $2, $2, 65535
; FP64-NEXT: jr $ra
; FP64-NEXT: nop
entry:
Expand All @@ -328,44 +328,44 @@ define zeroext i8 @f64tou8(double %a) {
; FP32-LABEL: f64tou8:
; FP32: # %bb.0: # %entry
; FP32-NEXT: trunc.w.d $f0, $f12
; FP32-NEXT: mfc1 $2, $f0
; FP32-NEXT: lui $3, 16864
; FP32-NEXT: ori $1, $zero, 0
; FP32-NEXT: mtc1 $1, $f0
; FP32-NEXT: mtc1 $3, $f1
; FP32-NEXT: mfc1 $1, $f0
; FP32-NEXT: lui $2, 16864
; FP32-NEXT: ori $3, $zero, 0
; FP32-NEXT: mtc1 $3, $f0
; FP32-NEXT: mtc1 $2, $f1
; FP32-NEXT: sub.d $f2, $f12, $f0
; FP32-NEXT: trunc.w.d $f2, $f2
; FP32-NEXT: mfc1 $1, $f2
; FP32-NEXT: mfc1 $2, $f2
; FP32-NEXT: lui $3, 32768
; FP32-NEXT: xor $1, $1, $3
; FP32-NEXT: xor $2, $2, $3
; FP32-NEXT: addiu $3, $zero, 1
; FP32-NEXT: c.ult.d $f12, $f0
; FP32-NEXT: movf $3, $zero, $fcc0
; FP32-NEXT: andi $3, $3, 1
; FP32-NEXT: movn $1, $2, $3
; FP32-NEXT: andi $2, $1, 255
; FP32-NEXT: movn $2, $1, $3
; FP32-NEXT: andi $2, $2, 255
; FP32-NEXT: jr $ra
; FP32-NEXT: nop
;
; FP64-LABEL: f64tou8:
; FP64: # %bb.0: # %entry
; FP64-NEXT: trunc.w.d $f0, $f12
; FP64-NEXT: mfc1 $2, $f0
; FP64-NEXT: lui $3, 16864
; FP64-NEXT: ori $1, $zero, 0
; FP64-NEXT: mtc1 $1, $f0
; FP64-NEXT: mthc1 $3, $f0
; FP64-NEXT: mfc1 $1, $f0
; FP64-NEXT: lui $2, 16864
; FP64-NEXT: ori $3, $zero, 0
; FP64-NEXT: mtc1 $3, $f0
; FP64-NEXT: mthc1 $2, $f0
; FP64-NEXT: sub.d $f1, $f12, $f0
; FP64-NEXT: trunc.w.d $f1, $f1
; FP64-NEXT: mfc1 $1, $f1
; FP64-NEXT: mfc1 $2, $f1
; FP64-NEXT: lui $3, 32768
; FP64-NEXT: xor $1, $1, $3
; FP64-NEXT: xor $2, $2, $3
; FP64-NEXT: addiu $3, $zero, 1
; FP64-NEXT: c.ult.d $f12, $f0
; FP64-NEXT: movf $3, $zero, $fcc0
; FP64-NEXT: andi $3, $3, 1
; FP64-NEXT: movn $1, $2, $3
; FP64-NEXT: andi $2, $1, 255
; FP64-NEXT: movn $2, $1, $3
; FP64-NEXT: andi $2, $2, 255
; FP64-NEXT: jr $ra
; FP64-NEXT: nop
entry:
Expand Down
7 changes: 4 additions & 3 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,11 +14,12 @@ define i32 @main() {
; MIPS32-NEXT: addiu $4, $1, %lo($.str)
; MIPS32-NEXT: lui $1, 18838
; MIPS32-NEXT: ori $5, $1, 722
; MIPS32-NEXT: ori $1, $zero, 0
; MIPS32-NEXT: sw $1, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $2, $zero, 0
; MIPS32-NEXT: sw $2, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: jal printf
; MIPS32-NEXT: nop
; MIPS32-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $1, 16($sp) # 4-byte Folded Reload
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 24
; MIPS32-NEXT: jr $ra
Expand Down
12 changes: 7 additions & 5 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/global_address_pic.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,8 +23,9 @@ define i32 @call_global(i32 %a, i32 %b) {
; MIPS32_PIC-NEXT: .cfi_def_cfa_offset 24
; MIPS32_PIC-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: .cfi_offset 31, -4
; MIPS32_PIC-NEXT: addu $gp, $2, $25
; MIPS32_PIC-NEXT: lw $25, %call16(f)($gp)
; MIPS32_PIC-NEXT: addu $1, $2, $25
; MIPS32_PIC-NEXT: lw $25, %call16(f)($1)
; MIPS32_PIC-NEXT: move $gp, $1
; MIPS32_PIC-NEXT: jalr $25
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
Expand All @@ -45,9 +46,10 @@ define i32 @call_global_with_local_linkage(i32 %a, i32 %b) {
; MIPS32_PIC-NEXT: .cfi_def_cfa_offset 24
; MIPS32_PIC-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: .cfi_offset 31, -4
; MIPS32_PIC-NEXT: addu $gp, $2, $25
; MIPS32_PIC-NEXT: lw $1, %got(f_with_local_linkage)($gp)
; MIPS32_PIC-NEXT: addiu $25, $1, %lo(f_with_local_linkage)
; MIPS32_PIC-NEXT: addu $1, $2, $25
; MIPS32_PIC-NEXT: lw $2, %got(f_with_local_linkage)($1)
; MIPS32_PIC-NEXT: addiu $25, $2, %lo(f_with_local_linkage)
; MIPS32_PIC-NEXT: move $gp, $1
; MIPS32_PIC-NEXT: jalr $25
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
Expand Down
104 changes: 56 additions & 48 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/icmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -188,12 +188,13 @@ entry:
define i1 @sgt_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: sgt_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $2, $7, $5
; MIPS32-NEXT: xor $1, $5, $7
; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $6, $4
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: slt $1, $7, $5
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: sltiu $2, $2, 1
; MIPS32-NEXT: sltu $3, $6, $4
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: movn $1, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -205,13 +206,14 @@ define i1 @sge_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: sge_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $1, $5, $7
; MIPS32-NEXT: xori $2, $1, 1
; MIPS32-NEXT: xor $1, $5, $7
; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $4, $6
; MIPS32-NEXT: xori $1, $1, 1
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: sltiu $2, $2, 1
; MIPS32-NEXT: sltu $3, $4, $6
; MIPS32-NEXT: xori $3, $3, 1
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: movn $1, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -222,12 +224,13 @@ entry:
define i1 @slt_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: slt_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $2, $5, $7
; MIPS32-NEXT: xor $1, $5, $7
; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $4, $6
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: slt $1, $5, $7
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: sltiu $2, $2, 1
; MIPS32-NEXT: sltu $3, $4, $6
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: movn $1, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -239,13 +242,14 @@ define i1 @sle_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: sle_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: slt $1, $7, $5
; MIPS32-NEXT: xori $2, $1, 1
; MIPS32-NEXT: xor $1, $5, $7
; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $6, $4
; MIPS32-NEXT: xori $1, $1, 1
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: sltiu $2, $2, 1
; MIPS32-NEXT: sltu $3, $6, $4
; MIPS32-NEXT: xori $3, $3, 1
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: movn $1, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -256,12 +260,13 @@ entry:
define i1 @ugt_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: ugt_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sltu $2, $7, $5
; MIPS32-NEXT: xor $1, $5, $7
; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $6, $4
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: sltu $1, $7, $5
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: sltiu $2, $2, 1
; MIPS32-NEXT: sltu $3, $6, $4
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: movn $1, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -273,13 +278,14 @@ define i1 @uge_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: uge_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sltu $1, $5, $7
; MIPS32-NEXT: xori $2, $1, 1
; MIPS32-NEXT: xor $1, $5, $7
; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $4, $6
; MIPS32-NEXT: xori $1, $1, 1
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: sltiu $2, $2, 1
; MIPS32-NEXT: sltu $3, $4, $6
; MIPS32-NEXT: xori $3, $3, 1
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: movn $1, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -290,12 +296,13 @@ entry:
define i1 @ult_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: ult_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sltu $2, $5, $7
; MIPS32-NEXT: xor $1, $5, $7
; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $4, $6
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: sltu $1, $5, $7
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: sltiu $2, $2, 1
; MIPS32-NEXT: sltu $3, $4, $6
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: movn $1, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand All @@ -307,13 +314,14 @@ define i1 @ule_i64(i64 %a, i64 %b) {
; MIPS32-LABEL: ule_i64:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: sltu $1, $7, $5
; MIPS32-NEXT: xori $2, $1, 1
; MIPS32-NEXT: xor $1, $5, $7
; MIPS32-NEXT: sltiu $3, $1, 1
; MIPS32-NEXT: sltu $1, $6, $4
; MIPS32-NEXT: xori $1, $1, 1
; MIPS32-NEXT: andi $3, $3, 1
; MIPS32-NEXT: movn $2, $1, $3
; MIPS32-NEXT: xor $2, $5, $7
; MIPS32-NEXT: sltiu $2, $2, 1
; MIPS32-NEXT: sltu $3, $6, $4
; MIPS32-NEXT: xori $3, $3, 1
; MIPS32-NEXT: andi $2, $2, 1
; MIPS32-NEXT: movn $1, $3, $2
; MIPS32-NEXT: move $2, $1
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
entry:
Expand Down
202 changes: 115 additions & 87 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,35 +7,35 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: addiu $sp, $sp, -32
; MIPS32-NEXT: .cfi_def_cfa_offset 32
; MIPS32-NEXT: sw $4, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $1, $zero, 7
; MIPS32-NEXT: ori $2, $zero, 3
; MIPS32-NEXT: sw $2, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $2, $zero, 2
; MIPS32-NEXT: sw $2, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $2, $zero, 1
; MIPS32-NEXT: sw $2, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $2, $zero, 0
; MIPS32-NEXT: sw $2, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: addiu $2, $zero, 65535
; MIPS32-NEXT: sw $2, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: ori $2, $zero, 0
; MIPS32-NEXT: subu $2, $4, $2
; MIPS32-NEXT: sw $2, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sltu $1, $1, $2
; MIPS32-NEXT: ori $3, $zero, 2
; MIPS32-NEXT: ori $5, $zero, 1
; MIPS32-NEXT: ori $6, $zero, 0
; MIPS32-NEXT: addiu $7, $zero, 65535
; MIPS32-NEXT: ori $8, $zero, 0
; MIPS32-NEXT: subu $8, $4, $8
; MIPS32-NEXT: sltu $1, $1, $8
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: sw $4, 28($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $2, 24($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $3, 20($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $5, 16($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $6, 12($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $7, 8($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sw $8, 4($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $1, $BB0_6
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_1: # %entry
; MIPS32-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lui $1, %hi($JTI0_0)
; MIPS32-NEXT: sll $2, $2, 2
; MIPS32-NEXT: addu $1, $1, $2
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sll $3, $2, 2
; MIPS32-NEXT: addu $1, $1, $3
; MIPS32-NEXT: lw $1, %lo($JTI0_0)($1)
; MIPS32-NEXT: jr $1
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_2: # %sw.bb
; MIPS32-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
Expand All @@ -45,37 +45,37 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_4: # %sw.bb2
; MIPS32-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_5: # %sw.bb3
; MIPS32-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_6: # %sw.default
; MIPS32-NEXT: .insn
; MIPS32-NEXT: # %bb.7: # %sw.epilog
; MIPS32-NEXT: lw $1, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 4($sp) # 4-byte Folded Reload
; MIPS32-NEXT: ori $3, $zero, 8
; MIPS32-NEXT: subu $2, $2, $3
; MIPS32-NEXT: sw $2, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: sltu $1, $1, $2
; MIPS32-NEXT: andi $1, $1, 1
; MIPS32-NEXT: bnez $1, $BB0_13
; MIPS32-NEXT: ori $1, $zero, 8
; MIPS32-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MIPS32-NEXT: subu $1, $2, $1
; MIPS32-NEXT: lw $3, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sltu $4, $3, $1
; MIPS32-NEXT: andi $4, $4, 1
; MIPS32-NEXT: sw $1, 0($sp) # 4-byte Folded Spill
; MIPS32-NEXT: bnez $4, $BB0_13
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_8: # %sw.epilog
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lui $1, %hi($JTI0_1)
; MIPS32-NEXT: sll $2, $2, 2
; MIPS32-NEXT: addu $1, $1, $2
; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload
; MIPS32-NEXT: sll $3, $2, 2
; MIPS32-NEXT: addu $1, $1, $3
; MIPS32-NEXT: lw $1, %lo($JTI0_1)($1)
; MIPS32-NEXT: jr $1
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_9: # %sw.bb4
; MIPS32-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
Expand All @@ -85,20 +85,35 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_11: # %sw.bb6
; MIPS32-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_12: # %sw.bb7
; MIPS32-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32-NEXT: $BB0_13: # %sw.default8
; MIPS32-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
; MIPS32-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32-NEXT: addiu $sp, $sp, 32
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
; MIPS32: $JTI0_0:
; MIPS32-NEXT: .4byte ($BB0_2)
; MIPS32-NEXT: .4byte ($BB0_3)
; MIPS32-NEXT: .4byte ($BB0_4)
; MIPS32-NEXT: .4byte ($BB0_5)
; MIPS32-NEXT: .4byte ($BB0_2)
; MIPS32-NEXT: .4byte ($BB0_3)
; MIPS32-NEXT: .4byte ($BB0_4)
; MIPS32-NEXT: .4byte ($BB0_5)
; MIPS32-NEXT: $JTI0_1:
; MIPS32-NEXT: .4byte ($BB0_9)
; MIPS32-NEXT: .4byte ($BB0_10)
; MIPS32-NEXT: .4byte ($BB0_11)
; MIPS32-NEXT: .4byte ($BB0_12)

;
; MIPS32_PIC-LABEL: mod4_0_to_11:
; MIPS32_PIC: # %bb.0: # %entry
Expand All @@ -107,104 +122,117 @@ define i32 @mod4_0_to_11(i32 %a) {
; MIPS32_PIC-NEXT: addiu $sp, $sp, -40
; MIPS32_PIC-NEXT: .cfi_def_cfa_offset 40
; MIPS32_PIC-NEXT: addu $1, $2, $25
; MIPS32_PIC-NEXT: sw $1, 8($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sw $4, 12($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: ori $1, $zero, 7
; MIPS32_PIC-NEXT: ori $2, $zero, 3
; MIPS32_PIC-NEXT: sw $2, 16($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: ori $2, $zero, 2
; MIPS32_PIC-NEXT: sw $2, 20($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: ori $2, $zero, 1
; MIPS32_PIC-NEXT: sw $2, 24($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: ori $2, $zero, 0
; MIPS32_PIC-NEXT: sw $2, 28($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: addiu $2, $zero, 65535
; MIPS32_PIC-NEXT: sw $2, 32($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: ori $2, $zero, 0
; MIPS32_PIC-NEXT: subu $2, $4, $2
; MIPS32_PIC-NEXT: sw $2, 36($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sltu $1, $1, $2
; MIPS32_PIC-NEXT: andi $1, $1, 1
; MIPS32_PIC-NEXT: bnez $1, $BB0_6
; MIPS32_PIC-NEXT: ori $2, $zero, 7
; MIPS32_PIC-NEXT: ori $3, $zero, 3
; MIPS32_PIC-NEXT: ori $5, $zero, 2
; MIPS32_PIC-NEXT: ori $6, $zero, 1
; MIPS32_PIC-NEXT: ori $7, $zero, 0
; MIPS32_PIC-NEXT: addiu $8, $zero, 65535
; MIPS32_PIC-NEXT: ori $9, $zero, 0
; MIPS32_PIC-NEXT: subu $9, $4, $9
; MIPS32_PIC-NEXT: sltu $2, $2, $9
; MIPS32_PIC-NEXT: andi $2, $2, 1
; MIPS32_PIC-NEXT: sw $1, 36($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sw $4, 32($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sw $3, 28($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sw $5, 24($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sw $6, 20($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sw $7, 16($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sw $8, 12($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sw $9, 8($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: bnez $2, $BB0_6
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_1: # %entry
; MIPS32_PIC-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $3, 36($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $1, %got($JTI0_0)($2)
; MIPS32_PIC-NEXT: sll $3, $3, 2
; MIPS32_PIC-NEXT: addu $1, $1, $3
; MIPS32_PIC-NEXT: lw $1, %lo($JTI0_0)($1)
; MIPS32_PIC-NEXT: addu $1, $1, $2
; MIPS32_PIC-NEXT: jr $1
; MIPS32_PIC-NEXT: lw $1, 36($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, %got($JTI0_0)($1)
; MIPS32_PIC-NEXT: lw $3, 8($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: sll $4, $3, 2
; MIPS32_PIC-NEXT: addu $2, $2, $4
; MIPS32_PIC-NEXT: lw $2, %lo($JTI0_0)($2)
; MIPS32_PIC-NEXT: addu $2, $2, $1
; MIPS32_PIC-NEXT: jr $2
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_2: # %sw.bb
; MIPS32_PIC-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_3: # %sw.bb1
; MIPS32_PIC-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_4: # %sw.bb2
; MIPS32_PIC-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_5: # %sw.bb3
; MIPS32_PIC-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_6: # %sw.default
; MIPS32_PIC-NEXT: .insn
; MIPS32_PIC-NEXT: # %bb.7: # %sw.epilog
; MIPS32_PIC-NEXT: lw $1, 16($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: ori $3, $zero, 8
; MIPS32_PIC-NEXT: subu $2, $2, $3
; MIPS32_PIC-NEXT: sw $2, 4($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: sltu $1, $1, $2
; MIPS32_PIC-NEXT: andi $1, $1, 1
; MIPS32_PIC-NEXT: bnez $1, $BB0_13
; MIPS32_PIC-NEXT: ori $1, $zero, 8
; MIPS32_PIC-NEXT: lw $2, 32($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: subu $1, $2, $1
; MIPS32_PIC-NEXT: lw $3, 28($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: sltu $4, $3, $1
; MIPS32_PIC-NEXT: andi $4, $4, 1
; MIPS32_PIC-NEXT: sw $1, 4($sp) # 4-byte Folded Spill
; MIPS32_PIC-NEXT: bnez $4, $BB0_13
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_8: # %sw.epilog
; MIPS32_PIC-NEXT: lw $2, 8($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $1, 36($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, %got($JTI0_1)($1)
; MIPS32_PIC-NEXT: lw $3, 4($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $1, %got($JTI0_1)($2)
; MIPS32_PIC-NEXT: sll $3, $3, 2
; MIPS32_PIC-NEXT: addu $1, $1, $3
; MIPS32_PIC-NEXT: lw $1, %lo($JTI0_1)($1)
; MIPS32_PIC-NEXT: addu $1, $1, $2
; MIPS32_PIC-NEXT: jr $1
; MIPS32_PIC-NEXT: sll $4, $3, 2
; MIPS32_PIC-NEXT: addu $2, $2, $4
; MIPS32_PIC-NEXT: lw $2, %lo($JTI0_1)($2)
; MIPS32_PIC-NEXT: addu $2, $2, $1
; MIPS32_PIC-NEXT: jr $2
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_9: # %sw.bb4
; MIPS32_PIC-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_10: # %sw.bb5
; MIPS32_PIC-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_11: # %sw.bb6
; MIPS32_PIC-NEXT: lw $2, 20($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, 24($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_12: # %sw.bb7
; MIPS32_PIC-NEXT: lw $2, 16($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, 28($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop
; MIPS32_PIC-NEXT: $BB0_13: # %sw.default8
; MIPS32_PIC-NEXT: lw $2, 32($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: lw $2, 12($sp) # 4-byte Folded Reload
; MIPS32_PIC-NEXT: addiu $sp, $sp, 40
; MIPS32_PIC-NEXT: jr $ra
; MIPS32_PIC-NEXT: nop

; MIPS32_PIC: $JTI0_0:
; MIPS32_PIC-NEXT: .gpword ($BB0_2)
; MIPS32_PIC-NEXT: .gpword ($BB0_3)
; MIPS32_PIC-NEXT: .gpword ($BB0_4)
; MIPS32_PIC-NEXT: .gpword ($BB0_5)
; MIPS32_PIC-NEXT: .gpword ($BB0_2)
; MIPS32_PIC-NEXT: .gpword ($BB0_3)
; MIPS32_PIC-NEXT: .gpword ($BB0_4)
; MIPS32_PIC-NEXT: .gpword ($BB0_5)
; MIPS32_PIC-NEXT: $JTI0_1:
; MIPS32_PIC-NEXT: .gpword ($BB0_9)
; MIPS32_PIC-NEXT: .gpword ($BB0_10)
; MIPS32_PIC-NEXT: .gpword ($BB0_11)
; MIPS32_PIC-NEXT: .gpword ($BB0_12)

entry:
switch i32 %a, label %sw.default [
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/load_4_unaligned.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,11 +15,11 @@ define float @load_float_align1() {
; MIPS32-LABEL: load_float_align1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(float_align1)
; MIPS32-NEXT: addiu $2, $1, %lo(float_align1)
; MIPS32-NEXT: # implicit-def: $at
; MIPS32-NEXT: lwl $1, 3($2)
; MIPS32-NEXT: lwr $1, 0($2)
; MIPS32-NEXT: mtc1 $1, $f0
; MIPS32-NEXT: addiu $1, $1, %lo(float_align1)
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 3($1)
; MIPS32-NEXT: lwr $2, 0($1)
; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
Expand All @@ -38,11 +38,11 @@ define float @load_float_align2() {
; MIPS32-LABEL: load_float_align2:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(float_align2)
; MIPS32-NEXT: addiu $2, $1, %lo(float_align2)
; MIPS32-NEXT: # implicit-def: $at
; MIPS32-NEXT: lwl $1, 3($2)
; MIPS32-NEXT: lwr $1, 0($2)
; MIPS32-NEXT: mtc1 $1, $f0
; MIPS32-NEXT: addiu $1, $1, %lo(float_align2)
; MIPS32-NEXT: # implicit-def: $v0
; MIPS32-NEXT: lwl $2, 3($1)
; MIPS32-NEXT: lwr $2, 0($1)
; MIPS32-NEXT: mtc1 $2, $f0
; MIPS32-NEXT: jr $ra
; MIPS32-NEXT: nop
;
Expand Down
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