4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/fastcc-int.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -45,8 +45,8 @@ define i32 @caller(<16 x i32> %A) nounwind {
; RV32-NEXT: sw t1, 0(sp)
; RV32-NEXT: mv a0, t0
; RV32-NEXT: call callee@plt
; RV32-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 32
; RV32-NEXT: ret
;
Expand Down Expand Up @@ -76,8 +76,8 @@ define i32 @caller(<16 x i32> %A) nounwind {
; RV64-NEXT: sd t1, 0(sp)
; RV64-NEXT: mv a0, t0
; RV64-NEXT: call callee@plt
; RV64-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 48
; RV64-NEXT: ret
%C = call fastcc i32 @callee(<16 x i32> %A)
Expand Down
96 changes: 48 additions & 48 deletions llvm/test/CodeGen/RISCV/float-arith.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -329,8 +329,8 @@ define float @fsgnjn_s(float %a, float %b) nounwind {
; RV32I-NEXT: and a2, s0, a2
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: or a0, a2, a0
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -347,8 +347,8 @@ define float @fsgnjn_s(float %a, float %b) nounwind {
; RV64I-NEXT: and a2, s0, a2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = fadd float %a, %b
Expand Down Expand Up @@ -693,9 +693,9 @@ define float @fmsub_s(float %a, float %b, float %c) nounwind {
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -715,9 +715,9 @@ define float @fmsub_s(float %a, float %b, float %c) nounwind {
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%c_ = fadd float 0.0, %c ; avoid negation using xor
Expand Down Expand Up @@ -772,10 +772,10 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind {
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -800,10 +800,10 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind {
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%a_ = fadd float 0.0, %a
Expand Down Expand Up @@ -860,10 +860,10 @@ define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {
; RV32I-NEXT: xor a2, a0, a2
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -888,10 +888,10 @@ define float @fnmadd_s_2(float %a, float %b, float %c) nounwind {
; RV64I-NEXT: xor a2, a0, a2
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%b_ = fadd float 0.0, %b
Expand Down Expand Up @@ -940,9 +940,9 @@ define float @fnmsub_s(float %a, float %b, float %c) nounwind {
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -961,9 +961,9 @@ define float @fnmsub_s(float %a, float %b, float %c) nounwind {
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%a_ = fadd float 0.0, %a
Expand Down Expand Up @@ -1011,9 +1011,9 @@ define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -1033,9 +1033,9 @@ define float @fnmsub_s_2(float %a, float %b, float %c) nounwind {
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a2, s0
; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%b_ = fadd float 0.0, %b
Expand Down Expand Up @@ -1072,8 +1072,8 @@ define float @fmadd_s_contract(float %a, float %b, float %c) nounwind {
; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -1086,8 +1086,8 @@ define float @fmadd_s_contract(float %a, float %b, float %c) nounwind {
; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = fmul contract float %a, %b
Expand Down Expand Up @@ -1136,10 +1136,10 @@ define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {
; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __subsf3@plt
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -1161,10 +1161,10 @@ define float @fmsub_s_contract(float %a, float %b, float %c) nounwind {
; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __subsf3@plt
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%c_ = fadd float 0.0, %c ; avoid negation using xor
Expand Down Expand Up @@ -1228,11 +1228,11 @@ define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __subsf3@plt
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -1264,11 +1264,11 @@ define float @fnmadd_s_contract(float %a, float %b, float %c) nounwind {
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __subsf3@plt
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
%a_ = fadd float 0.0, %a ; avoid negation using xor
Expand Down Expand Up @@ -1326,10 +1326,10 @@ define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: call __subsf3@plt
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -1354,10 +1354,10 @@ define float @fnmsub_s_contract(float %a, float %b, float %c) nounwind {
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: call __subsf3@plt
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%a_ = fadd float 0.0, %a ; avoid negation using xor
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/RISCV/float-bit-preserving-dagcombines.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -79,9 +79,9 @@ define double @bitcast_double_and(double %a1, double %a2) nounwind {
; RV32F-NEXT: mv a0, s1
; RV32F-NEXT: mv a1, s0
; RV32F-NEXT: call __adddf3@plt
; RV32F-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret
;
Expand Down Expand Up @@ -115,8 +115,8 @@ define double @bitcast_double_and(double %a1, double %a2) nounwind {
; RV64F-NEXT: and a1, a0, a1
; RV64F-NEXT: mv a0, s0
; RV64F-NEXT: call __adddf3@plt
; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64F-NEXT: addi sp, sp, 16
; RV64F-NEXT: ret
;
Expand Down Expand Up @@ -202,9 +202,9 @@ define double @bitcast_double_xor(double %a1, double %a2) nounwind {
; RV32F-NEXT: mv a0, s1
; RV32F-NEXT: mv a1, s0
; RV32F-NEXT: call __muldf3@plt
; RV32F-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret
;
Expand Down Expand Up @@ -238,8 +238,8 @@ define double @bitcast_double_xor(double %a1, double %a2) nounwind {
; RV64F-NEXT: xor a1, a0, a1
; RV64F-NEXT: mv a0, s0
; RV64F-NEXT: call __muldf3@plt
; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64F-NEXT: addi sp, sp, 16
; RV64F-NEXT: ret
;
Expand Down Expand Up @@ -328,9 +328,9 @@ define double @bitcast_double_or(double %a1, double %a2) nounwind {
; RV32F-NEXT: mv a0, s1
; RV32F-NEXT: mv a1, s0
; RV32F-NEXT: call __muldf3@plt
; RV32F-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32F-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32F-NEXT: addi sp, sp, 16
; RV32F-NEXT: ret
;
Expand Down Expand Up @@ -365,8 +365,8 @@ define double @bitcast_double_or(double %a1, double %a2) nounwind {
; RV64F-NEXT: or a1, a0, a1
; RV64F-NEXT: mv a0, s0
; RV64F-NEXT: call __muldf3@plt
; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64F-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64F-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64F-NEXT: addi sp, sp, 16
; RV64F-NEXT: ret
;
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/float-br-fcmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -668,8 +668,8 @@ define i32 @br_fcmp_store_load_stack_slot(float %a, float %b) nounwind {
; RV64IF-NEXT: beqz a0, .LBB17_3
; RV64IF-NEXT: # %bb.2: # %if.end4
; RV64IF-NEXT: li a0, 0
; RV64IF-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 32
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB17_3: # %if.then
Expand Down
94 changes: 47 additions & 47 deletions llvm/test/CodeGen/RISCV/float-convert.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -107,12 +107,12 @@ define i32 @fcvt_w_s_sat(float %a) nounwind {
; RV32I-NEXT: mv s1, s3
; RV32I-NEXT: .LBB1_6: # %start
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -154,12 +154,12 @@ define i32 @fcvt_w_s_sat(float %a) nounwind {
; RV64I-NEXT: mv s1, s3
; RV64I-NEXT: .LBB1_6: # %start
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
start:
Expand Down Expand Up @@ -319,10 +319,10 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind {
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: .LBB4_4: # %start
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -354,10 +354,10 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind {
; RV64I-NEXT: srli s1, a0, 32
; RV64I-NEXT: .LBB4_4: # %start
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
start:
Expand Down Expand Up @@ -669,8 +669,8 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV32IF-NEXT: .LBB12_7: # %start
; RV32IF-NEXT: li a1, 0
; RV32IF-NEXT: .LBB12_8: # %start
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB12_9: # %start
Expand Down Expand Up @@ -768,14 +768,14 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV32I-NEXT: .LBB12_12: # %start
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -819,12 +819,12 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV64I-NEXT: mv s1, s2
; RV64I-NEXT: .LBB12_7: # %start
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
start:
Expand Down Expand Up @@ -901,8 +901,8 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV32IF-NEXT: mv a2, a1
; RV32IF-NEXT: .LBB14_6: # %start
; RV32IF-NEXT: mv a1, a2
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB14_7: # %start
Expand Down Expand Up @@ -975,13 +975,13 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV32I-NEXT: .LBB14_8: # %start
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -1013,10 +1013,10 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: .LBB14_4: # %start
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
start:
Expand Down Expand Up @@ -1267,9 +1267,9 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) {
; RV32I-NEXT: call __floatsisf@plt
; RV32I-NEXT: sw a0, 0(s0)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -1289,9 +1289,9 @@ define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) {
; RV64I-NEXT: call __floatsisf@plt
; RV64I-NEXT: sw a0, 0(s0)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%3 = add i32 %0, 1
Expand Down Expand Up @@ -1332,9 +1332,9 @@ define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, float* %1) {
; RV32I-NEXT: call __floatunsisf@plt
; RV32I-NEXT: sw a0, 0(s0)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -1354,9 +1354,9 @@ define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, float* %1) {
; RV64I-NEXT: call __floatunsisf@plt
; RV64I-NEXT: sw a0, 0(s0)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%3 = add i32 %0, 1
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/float-fcmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -265,10 +265,10 @@ define i32 @fcmp_one(float %a, float %b) nounwind {
; RV32I-NEXT: call __unordsf2@plt
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: and a0, a0, s2
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -288,10 +288,10 @@ define i32 @fcmp_one(float %a, float %b) nounwind {
; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%1 = fcmp one float %a, %b
Expand Down Expand Up @@ -379,10 +379,10 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind {
; RV32I-NEXT: call __unordsf2@plt
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: or a0, a0, s2
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -402,10 +402,10 @@ define i32 @fcmp_ueq(float %a, float %b) nounwind {
; RV64I-NEXT: call __unordsf2@plt
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: or a0, a0, s2
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%1 = fcmp ueq float %a, %b
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/float-intrinsics.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -195,8 +195,8 @@ define float @sincos_f32(float %a) nounwind {
; RV32IF-NEXT: flw ft1, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
;
Expand All @@ -215,8 +215,8 @@ define float @sincos_f32(float %a) nounwind {
; RV64IF-NEXT: flw ft1, 12(sp) # 4-byte Folded Reload
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 32
; RV64IF-NEXT: ret
;
Expand All @@ -234,9 +234,9 @@ define float @sincos_f32(float %a) nounwind {
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -254,9 +254,9 @@ define float @sincos_f32(float %a) nounwind {
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%1 = call float @llvm.sin.f32(float %a)
Expand Down Expand Up @@ -589,8 +589,8 @@ define float @fmuladd_f32(float %a, float %b, float %c) nounwind {
; RV32I-NEXT: call __mulsf3@plt
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -603,8 +603,8 @@ define float @fmuladd_f32(float %a, float %b, float %c) nounwind {
; RV64I-NEXT: call __mulsf3@plt
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/fp16-promote.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -52,8 +52,8 @@ define void @test_fptrunc_float(float %f, half* %p) nounwind {
; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: call __gnu_f2h_ieee@plt
; CHECK-NEXT: sh a0, 0(s0)
; CHECK-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%a = fptrunc float %f to half
Expand All @@ -70,8 +70,8 @@ define void @test_fptrunc_double(double %d, half* %p) nounwind {
; CHECK-NEXT: mv s0, a0
; CHECK-NEXT: call __truncdfhf2@plt
; CHECK-NEXT: sh a0, 0(s0)
; CHECK-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
%a = fptrunc double %d to half
Expand All @@ -97,10 +97,10 @@ define void @test_fadd(half* %p, half* %q) nounwind {
; CHECK-NEXT: fadd.s fa0, fa0, fs0
; CHECK-NEXT: call __gnu_f2h_ieee@plt
; CHECK-NEXT: sh a0, 0(s0)
; CHECK-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; CHECK-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
%a = load half, half* %p
Expand Down Expand Up @@ -128,10 +128,10 @@ define void @test_fmul(half* %p, half* %q) nounwind {
; CHECK-NEXT: fmul.s fa0, fa0, fs0
; CHECK-NEXT: call __gnu_f2h_ieee@plt
; CHECK-NEXT: sh a0, 0(s0)
; CHECK-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; CHECK-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; CHECK-NEXT: fld fs0, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
%a = load half, half* %p
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/frame-info.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -27,8 +27,8 @@ define void @trivial() {
; RV32-WITHFP-NEXT: .cfi_offset s0, -8
; RV32-WITHFP-NEXT: addi s0, sp, 16
; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: addi sp, sp, 16
; RV32-WITHFP-NEXT: ret
;
Expand All @@ -42,8 +42,8 @@ define void @trivial() {
; RV64-WITHFP-NEXT: .cfi_offset s0, -16
; RV64-WITHFP-NEXT: addi s0, sp, 16
; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: addi sp, sp, 16
; RV64-WITHFP-NEXT: ret
ret void
Expand All @@ -66,8 +66,8 @@ define void @stack_alloc(i32 signext %size) {
; RV32-NEXT: mv sp, a0
; RV32-NEXT: call callee_with_args@plt
; RV32-NEXT: addi sp, s0, -16
; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
;
Expand All @@ -89,8 +89,8 @@ define void @stack_alloc(i32 signext %size) {
; RV64-NEXT: mv sp, a0
; RV64-NEXT: call callee_with_args@plt
; RV64-NEXT: addi sp, s0, -16
; RV64-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret
;
Expand All @@ -110,8 +110,8 @@ define void @stack_alloc(i32 signext %size) {
; RV32-WITHFP-NEXT: mv sp, a0
; RV32-WITHFP-NEXT: call callee_with_args@plt
; RV32-WITHFP-NEXT: addi sp, s0, -16
; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: addi sp, sp, 16
; RV32-WITHFP-NEXT: ret
;
Expand All @@ -133,8 +133,8 @@ define void @stack_alloc(i32 signext %size) {
; RV64-WITHFP-NEXT: mv sp, a0
; RV64-WITHFP-NEXT: call callee_with_args@plt
; RV64-WITHFP-NEXT: addi sp, s0, -16
; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: addi sp, sp, 16
; RV64-WITHFP-NEXT: ret
entry:
Expand Down Expand Up @@ -192,8 +192,8 @@ define void @branch_and_tail_call(i1 %a) {
; RV32-WITHFP-NEXT: addi s0, sp, 16
; RV32-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV32-WITHFP-NEXT: call callee2@plt
; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-WITHFP-NEXT: addi sp, sp, 16
; RV32-WITHFP-NEXT: ret
;
Expand All @@ -213,8 +213,8 @@ define void @branch_and_tail_call(i1 %a) {
; RV64-WITHFP-NEXT: addi s0, sp, 16
; RV64-WITHFP-NEXT: .cfi_def_cfa s0, 0
; RV64-WITHFP-NEXT: call callee2@plt
; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64-WITHFP-NEXT: addi sp, sp, 16
; RV64-WITHFP-NEXT: ret
br i1 %a, label %blue_pill, label %red_pill
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/frame.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,8 +37,8 @@ define i32 @test() nounwind {
; RV32I-WITHFP-NEXT: addi a0, s0, -28
; RV32I-WITHFP-NEXT: call test1@plt
; RV32I-WITHFP-NEXT: li a0, 0
; RV32I-WITHFP-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 32
; RV32I-WITHFP-NEXT: ret
%key = alloca %struct.key_t, align 4
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/frameaddr-returnaddr.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,8 +16,8 @@ define i8* @test_frameaddress_0() nounwind {
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -28,8 +28,8 @@ define i8* @test_frameaddress_0() nounwind {
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi s0, sp, 16
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call i8* @llvm.frameaddress(i32 0)
Expand All @@ -45,8 +45,8 @@ define i8* @test_frameaddress_2() nounwind {
; RV32I-NEXT: addi s0, sp, 16
; RV32I-NEXT: lw a0, -8(s0)
; RV32I-NEXT: lw a0, -8(a0)
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -58,8 +58,8 @@ define i8* @test_frameaddress_2() nounwind {
; RV64I-NEXT: addi s0, sp, 16
; RV64I-NEXT: ld a0, -16(s0)
; RV64I-NEXT: ld a0, -16(a0)
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call i8* @llvm.frameaddress(i32 2)
Expand All @@ -78,8 +78,8 @@ define i8* @test_frameaddress_3_alloca() nounwind {
; RV32I-NEXT: lw a0, -8(s0)
; RV32I-NEXT: lw a0, -8(a0)
; RV32I-NEXT: lw a0, -8(a0)
; RV32I-NEXT: lw s0, 104(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 108(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 104(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 112
; RV32I-NEXT: ret
;
Expand All @@ -94,8 +94,8 @@ define i8* @test_frameaddress_3_alloca() nounwind {
; RV64I-NEXT: ld a0, -16(s0)
; RV64I-NEXT: ld a0, -16(a0)
; RV64I-NEXT: ld a0, -16(a0)
; RV64I-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 128
; RV64I-NEXT: ret
%1 = alloca [100 x i8]
Expand Down Expand Up @@ -129,8 +129,8 @@ define i8* @test_returnaddress_2() nounwind {
; RV32I-NEXT: lw a0, -8(s0)
; RV32I-NEXT: lw a0, -8(a0)
; RV32I-NEXT: lw a0, -4(a0)
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -143,8 +143,8 @@ define i8* @test_returnaddress_2() nounwind {
; RV64I-NEXT: ld a0, -16(s0)
; RV64I-NEXT: ld a0, -16(a0)
; RV64I-NEXT: ld a0, -8(a0)
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
%1 = call i8* @llvm.returnaddress(i32 2)
Expand Down
328 changes: 164 additions & 164 deletions llvm/test/CodeGen/RISCV/half-arith.ll
View file

Large diffs are not rendered by default.

138 changes: 69 additions & 69 deletions llvm/test/CodeGen/RISCV/half-convert.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -176,11 +176,11 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV32I-NEXT: mv s1, s3
; RV32I-NEXT: .LBB1_6: # %start
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -225,11 +225,11 @@ define i16 @fcvt_si_h_sat(half %a) nounwind {
; RV64I-NEXT: mv s1, s3
; RV64I-NEXT: .LBB1_6: # %start
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
start:
Expand Down Expand Up @@ -457,11 +457,11 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV32I-NEXT: mv s2, s3
; RV32I-NEXT: .LBB4_4: # %start
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -497,11 +497,11 @@ define i16 @fcvt_ui_h_sat(half %a) nounwind {
; RV64I-NEXT: mv s2, s3
; RV64I-NEXT: .LBB4_4: # %start
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
start:
Expand Down Expand Up @@ -647,12 +647,12 @@ define i32 @fcvt_w_h_sat(half %a) nounwind {
; RV32I-NEXT: mv s1, s3
; RV32I-NEXT: .LBB6_6: # %start
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -698,12 +698,12 @@ define i32 @fcvt_w_h_sat(half %a) nounwind {
; RV64I-NEXT: mv s1, s3
; RV64I-NEXT: .LBB6_6: # %start
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
start:
Expand Down Expand Up @@ -839,10 +839,10 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: .LBB8_4: # %start
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -878,10 +878,10 @@ define i32 @fcvt_wu_h_sat(half %a) nounwind {
; RV64I-NEXT: srli s1, a0, 32
; RV64I-NEXT: .LBB8_4: # %start
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
start:
Expand Down Expand Up @@ -984,9 +984,9 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV32IZFH-NEXT: .LBB10_7: # %start
; RV32IZFH-NEXT: li a1, 0
; RV32IZFH-NEXT: .LBB10_8: # %start
; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB10_9: # %start
Expand Down Expand Up @@ -1051,9 +1051,9 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV32IDZFH-NEXT: .LBB10_7: # %start
; RV32IDZFH-NEXT: li a1, 0
; RV32IDZFH-NEXT: .LBB10_8: # %start
; RV32IDZFH-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IDZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
; RV32IDZFH-NEXT: .LBB10_9: # %start
Expand Down Expand Up @@ -1154,14 +1154,14 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV32I-NEXT: .LBB10_12: # %start
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -1209,12 +1209,12 @@ define i64 @fcvt_l_h_sat(half %a) nounwind {
; RV64I-NEXT: mv s1, s2
; RV64I-NEXT: .LBB10_7: # %start
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s4, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
start:
Expand Down Expand Up @@ -1312,9 +1312,9 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; RV32IZFH-NEXT: mv a2, a1
; RV32IZFH-NEXT: .LBB12_6: # %start
; RV32IZFH-NEXT: mv a1, a2
; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB12_7: # %start
Expand Down Expand Up @@ -1366,9 +1366,9 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; RV32IDZFH-NEXT: mv a2, a1
; RV32IDZFH-NEXT: .LBB12_6: # %start
; RV32IDZFH-NEXT: mv a1, a2
; RV32IDZFH-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IDZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IDZFH-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
; RV32IDZFH-NEXT: addi sp, sp, 16
; RV32IDZFH-NEXT: ret
; RV32IDZFH-NEXT: .LBB12_7: # %start
Expand Down Expand Up @@ -1444,13 +1444,13 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; RV32I-NEXT: .LBB12_8: # %start
; RV32I-NEXT: mv a0, s4
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -1486,10 +1486,10 @@ define i64 @fcvt_lu_h_sat(half %a) nounwind {
; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: mv a0, s2
; RV64I-NEXT: .LBB12_4: # %start
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
start:
Expand Down Expand Up @@ -2313,9 +2313,9 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) {
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: sh a0, 0(s0)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -2336,9 +2336,9 @@ define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) {
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: sh a0, 0(s0)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%3 = add i32 %0, 1
Expand Down Expand Up @@ -2394,9 +2394,9 @@ define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, half* %1) {
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: sh a0, 0(s0)
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -2417,9 +2417,9 @@ define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, half* %1) {
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: sh a0, 0(s0)
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%3 = add i32 %0, 1
Expand Down
56 changes: 28 additions & 28 deletions llvm/test/CodeGen/RISCV/half-intrinsics.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -120,11 +120,11 @@ define half @fma_f16(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call fmaf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -153,11 +153,11 @@ define half @fma_f16(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: mv a1, s1
; RV64I-NEXT: call fmaf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
%1 = call half @llvm.fma.f16(half %a, half %b, half %c)
Expand Down Expand Up @@ -217,11 +217,11 @@ define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -255,11 +255,11 @@ define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: mv a1, s2
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s3, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
%1 = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
Expand Down Expand Up @@ -348,10 +348,10 @@ define half @minnum_f16(half %a, half %b) nounwind {
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call fminf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -374,10 +374,10 @@ define half @minnum_f16(half %a, half %b) nounwind {
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call fminf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%1 = call half @llvm.minnum.f16(half %a, half %b)
Expand Down Expand Up @@ -426,10 +426,10 @@ define half @maxnum_f16(half %a, half %b) nounwind {
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call fmaxf@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -452,10 +452,10 @@ define half @maxnum_f16(half %a, half %b) nounwind {
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call fmaxf@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%1 = call half @llvm.maxnum.f16(half %a, half %b)
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/half-mem.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -124,8 +124,8 @@ define half @flh_stack(half %a) nounwind {
; RV32IZFH-NEXT: call notdead@plt
; RV32IZFH-NEXT: flh ft0, 4(sp)
; RV32IZFH-NEXT: fadd.h fa0, ft0, fs0
; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret
;
Expand All @@ -139,8 +139,8 @@ define half @flh_stack(half %a) nounwind {
; RV64IZFH-NEXT: call notdead@plt
; RV64IZFH-NEXT: flh ft0, 0(sp)
; RV64IZFH-NEXT: fadd.h fa0, ft0, fs0
; RV64IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret
%1 = alloca half, align 4
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/interrupt-attr-callee.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,8 +22,8 @@ define dso_local void @handler() nounwind {
; CHECK-RV32-NEXT: mv s0, a0
; CHECK-RV32-NEXT: call callee@plt
; CHECK-RV32-NEXT: mv a0, s0
; CHECK-RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-NEXT: addi sp, sp, 16
; CHECK-RV32-NEXT: tail write@plt
;
Expand All @@ -38,8 +38,8 @@ define dso_local void @handler() nounwind {
; CHECK-RV32-F-NEXT: mv s0, a0
; CHECK-RV32-F-NEXT: call callee@plt
; CHECK-RV32-F-NEXT: mv a0, s0
; CHECK-RV32-F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-F-NEXT: addi sp, sp, 16
; CHECK-RV32-F-NEXT: tail write@plt
;
Expand All @@ -54,8 +54,8 @@ define dso_local void @handler() nounwind {
; CHECK-RV32-FD-NEXT: mv s0, a0
; CHECK-RV32-FD-NEXT: call callee@plt
; CHECK-RV32-FD-NEXT: mv a0, s0
; CHECK-RV32-FD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK-RV32-FD-NEXT: addi sp, sp, 16
; CHECK-RV32-FD-NEXT: tail write@plt
entry:
Expand Down
374 changes: 187 additions & 187 deletions llvm/test/CodeGen/RISCV/interrupt-attr-nocall.ll
View file

Large diffs are not rendered by default.

884 changes: 442 additions & 442 deletions llvm/test/CodeGen/RISCV/interrupt-attr.ll
View file

Large diffs are not rendered by default.

10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/large-stack.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -34,8 +34,8 @@ define void @test() {
; RV32I-WITHFP-NEXT: lui a0, 74565
; RV32I-WITHFP-NEXT: addi a0, a0, -352
; RV32I-WITHFP-NEXT: add sp, sp, a0
; RV32I-WITHFP-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 2032
; RV32I-WITHFP-NEXT: ret
%tmp = alloca [ 305419896 x i8 ] , align 4
Expand Down Expand Up @@ -74,8 +74,8 @@ define void @test_emergency_spill_slot(i32 %a) {
; RV32I-FPELIM-NEXT: lui a0, 97
; RV32I-FPELIM-NEXT: addi a0, a0, 672
; RV32I-FPELIM-NEXT: add sp, sp, a0
; RV32I-FPELIM-NEXT: lw s1, 2024(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: lw s0, 2028(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: lw s1, 2024(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 2032
; RV32I-FPELIM-NEXT: ret
;
Expand Down Expand Up @@ -114,10 +114,10 @@ define void @test_emergency_spill_slot(i32 %a) {
; RV32I-WITHFP-NEXT: lui a0, 97
; RV32I-WITHFP-NEXT: addi a0, a0, 688
; RV32I-WITHFP-NEXT: add sp, sp, a0
; RV32I-WITHFP-NEXT: lw s2, 2016(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 2028(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 2024(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s1, 2020(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s2, 2016(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 2032
; RV32I-WITHFP-NEXT: ret
%data = alloca [ 100000 x i32 ] , align 4
Expand Down
26 changes: 13 additions & 13 deletions llvm/test/CodeGen/RISCV/mul.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1239,9 +1239,9 @@ define i128 @muli128_m3840(i128 %a) nounwind {
; RV32IM-NEXT: sw t0, 4(a0)
; RV32IM-NEXT: sw t6, 8(a0)
; RV32IM-NEXT: sw a1, 12(a0)
; RV32IM-NEXT: lw s2, 4(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s2, 4(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: ret
;
Expand Down Expand Up @@ -1370,8 +1370,8 @@ define i128 @muli128_m63(i128 %a) nounwind {
; RV32IM-NEXT: sw t0, 4(a0)
; RV32IM-NEXT: sw t6, 8(a0)
; RV32IM-NEXT: sw a1, 12(a0)
; RV32IM-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 16
; RV32IM-NEXT: ret
;
Expand Down Expand Up @@ -1476,17 +1476,17 @@ define i64 @mulhsu_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: add a0, a5, a0
; RV32I-NEXT: add a1, a0, a4
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 48
; RV32I-NEXT: ret
;
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/out-of-reach-emergency-slot.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,8 +41,8 @@
; CHECK-NEXT: lui a0, 2
; CHECK-NEXT: addiw a0, a0, -2032
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 2032
; CHECK-NEXT: ret
entry:
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/remat.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -113,19 +113,19 @@ define i32 @test() nounwind {
; RV32I-NEXT: j .LBB0_2
; RV32I-NEXT: .LBB0_11: # %for.end
; RV32I-NEXT: li a0, 1
; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s10, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 48(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 48(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 44(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 40(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 36(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 32(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s7, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s8, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s10, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 64
; RV32I-NEXT: ret
entry:
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/rv32i-rv64i-float-double.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,8 +21,8 @@ define float @float_test(float %a, float %b) nounwind {
; RV32IF-NEXT: call __addsf3@plt
; RV32IF-NEXT: mv a1, s0
; RV32IF-NEXT: call __divsf3@plt
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
;
Expand All @@ -35,8 +35,8 @@ define float @float_test(float %a, float %b) nounwind {
; RV64IF-NEXT: call __addsf3@plt
; RV64IF-NEXT: mv a1, s0
; RV64IF-NEXT: call __divsf3@plt
; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
%1 = fadd float %a, %b
Expand All @@ -57,9 +57,9 @@ define double @double_test(double %a, double %b) nounwind {
; RV32IF-NEXT: mv a2, s1
; RV32IF-NEXT: mv a3, s0
; RV32IF-NEXT: call __divdf3@plt
; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
;
Expand All @@ -72,8 +72,8 @@ define double @double_test(double %a, double %b) nounwind {
; RV64IF-NEXT: call __adddf3@plt
; RV64IF-NEXT: mv a1, s0
; RV64IF-NEXT: call __divdf3@plt
; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
%1 = fadd double %a, %b
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/rv32i-rv64i-half.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -35,10 +35,10 @@ define half @half_test(half %a, half %b) nounwind {
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: call __divsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -67,10 +67,10 @@ define half @half_test(half %a, half %b) nounwind {
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __divsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
%1 = fadd half %a, %b
Expand Down
40 changes: 20 additions & 20 deletions llvm/test/CodeGen/RISCV/rv32zbb.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -139,14 +139,14 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV32I-NEXT: srli a0, s2, 24
; RV32I-NEXT: .LBB1_3:
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -277,14 +277,14 @@ define i64 @cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: srli a0, s2, 24
; RV32I-NEXT: .LBB3_3:
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -393,13 +393,13 @@ define i64 @ctpop_i64(i64 %a) nounwind {
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: add a0, a0, s5
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 32
; RV32I-NEXT: ret
;
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/rv64i-complex-float.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,10 +24,10 @@ define i64 @complex_float_add(i64 %a.coerce, i64 %b.coerce) nounwind {
; CHECK-NEXT: slli a1, s0, 32
; CHECK-NEXT: srli a1, a1, 32
; CHECK-NEXT: or a0, a0, a1
; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s2, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
entry:
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rv64zbb.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -162,8 +162,8 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srliw a1, a0, 24
; RV64I-NEXT: .LBB2_2: # %cond.end
; RV64I-NEXT: sub a0, s0, a1
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
Expand Down Expand Up @@ -224,8 +224,8 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srliw a0, a1, 24
; RV64I-NEXT: xori a0, a0, 31
; RV64I-NEXT: .LBB3_2:
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
Expand Down Expand Up @@ -507,8 +507,8 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: srliw a0, a1, 24
; RV64I-NEXT: .LBB8_2:
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
Expand Down Expand Up @@ -563,8 +563,8 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind {
; RV64I-NEXT: srliw a0, a1, 24
; RV64I-NEXT: addi a0, a0, 1
; RV64I-NEXT: .LBB9_2:
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rvv/addi-scalable-offset.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -50,8 +50,8 @@ body: |
; CHECK-NEXT: $x10 = frame-destroy PseudoReadVLENB
; CHECK-NEXT: $x2 = frame-destroy ADD $x2, killed $x10
; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 240
; CHECK-NEXT: $x8 = LD $x2, 2016 :: (load (s64) from %stack.4)
; CHECK-NEXT: $x1 = LD $x2, 2024 :: (load (s64) from %stack.3)
; CHECK-NEXT: $x8 = LD $x2, 2016 :: (load (s64) from %stack.4)
; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 2032
; CHECK-NEXT: PseudoRET
%1:gprnox0 = COPY $x11
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/rvv/allocate-lmul-2-4-8.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -40,8 +40,8 @@ define void @lmul4() nounwind {
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -32
; CHECK-NEXT: addi sp, s0, -32
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
%v = alloca <vscale x 4 x i64>
Expand All @@ -60,8 +60,8 @@ define void @lmul8() nounwind {
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: addi sp, s0, -64
; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret
%v = alloca <vscale x 8 x i64>
Expand Down Expand Up @@ -98,8 +98,8 @@ define void @lmul2_and_4() nounwind {
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -32
; CHECK-NEXT: addi sp, s0, -32
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
%v1 = alloca <vscale x 2 x i64>
Expand All @@ -120,8 +120,8 @@ define void @lmul1_and_4() nounwind {
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -32
; CHECK-NEXT: addi sp, s0, -32
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
%v1 = alloca <vscale x 1 x i64>
Expand Down Expand Up @@ -159,8 +159,8 @@ define void @lmul4_and_1() nounwind {
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -32
; CHECK-NEXT: addi sp, s0, -32
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
%v1 = alloca <vscale x 4 x i64>
Expand All @@ -181,8 +181,8 @@ define void @lmul4_and_2() nounwind {
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -32
; CHECK-NEXT: addi sp, s0, -32
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
%v1 = alloca <vscale x 4 x i64>
Expand All @@ -203,8 +203,8 @@ define void @lmul4_and_2_x2_0() nounwind {
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -32
; CHECK-NEXT: addi sp, s0, -32
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
%v1 = alloca <vscale x 4 x i64>
Expand All @@ -227,8 +227,8 @@ define void @lmul4_and_2_x2_1() nounwind {
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -32
; CHECK-NEXT: addi sp, s0, -32
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
%v1 = alloca <vscale x 4 x i64>
Expand Down Expand Up @@ -277,8 +277,8 @@ define void @gpr_and_lmul1_and_4() nounwind {
; CHECK-NEXT: li a0, 3
; CHECK-NEXT: sd a0, 8(sp)
; CHECK-NEXT: addi sp, s0, -32
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
%x1 = alloca i64
Expand All @@ -301,8 +301,8 @@ define void @lmul_1_2_4_8() nounwind {
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: addi sp, s0, -64
; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret
%v1 = alloca <vscale x 1 x i64>
Expand All @@ -325,8 +325,8 @@ define void @lmul_1_2_4_8_x2_0() nounwind {
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: addi sp, s0, -64
; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret
%v1 = alloca <vscale x 1 x i64>
Expand All @@ -353,8 +353,8 @@ define void @lmul_1_2_4_8_x2_1() nounwind {
; CHECK-NEXT: sub sp, sp, a0
; CHECK-NEXT: andi sp, sp, -64
; CHECK-NEXT: addi sp, s0, -64
; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 64
; CHECK-NEXT: ret
%v8 = alloca <vscale x 8 x i64>
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/rvv/emergency-slot.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -163,19 +163,19 @@ body: |
; CHECK-NEXT: $x10 = frame-destroy ADDIW killed $x10, -1792
; CHECK-NEXT: $x2 = frame-destroy SUB $x8, killed $x10
; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 272
; CHECK-NEXT: $x27 = LD $x2, 1928 :: (load (s64) from %stack.15)
; CHECK-NEXT: $x26 = LD $x2, 1936 :: (load (s64) from %stack.14)
; CHECK-NEXT: $x25 = LD $x2, 1944 :: (load (s64) from %stack.13)
; CHECK-NEXT: $x24 = LD $x2, 1952 :: (load (s64) from %stack.12)
; CHECK-NEXT: $x23 = LD $x2, 1960 :: (load (s64) from %stack.11)
; CHECK-NEXT: $x22 = LD $x2, 1968 :: (load (s64) from %stack.10)
; CHECK-NEXT: $x21 = LD $x2, 1976 :: (load (s64) from %stack.9)
; CHECK-NEXT: $x20 = LD $x2, 1984 :: (load (s64) from %stack.8)
; CHECK-NEXT: $x19 = LD $x2, 1992 :: (load (s64) from %stack.7)
; CHECK-NEXT: $x18 = LD $x2, 2000 :: (load (s64) from %stack.6)
; CHECK-NEXT: $x9 = LD $x2, 2008 :: (load (s64) from %stack.5)
; CHECK-NEXT: $x8 = LD $x2, 2016 :: (load (s64) from %stack.4)
; CHECK-NEXT: $x1 = LD $x2, 2024 :: (load (s64) from %stack.3)
; CHECK-NEXT: $x8 = LD $x2, 2016 :: (load (s64) from %stack.4)
; CHECK-NEXT: $x9 = LD $x2, 2008 :: (load (s64) from %stack.5)
; CHECK-NEXT: $x18 = LD $x2, 2000 :: (load (s64) from %stack.6)
; CHECK-NEXT: $x19 = LD $x2, 1992 :: (load (s64) from %stack.7)
; CHECK-NEXT: $x20 = LD $x2, 1984 :: (load (s64) from %stack.8)
; CHECK-NEXT: $x21 = LD $x2, 1976 :: (load (s64) from %stack.9)
; CHECK-NEXT: $x22 = LD $x2, 1968 :: (load (s64) from %stack.10)
; CHECK-NEXT: $x23 = LD $x2, 1960 :: (load (s64) from %stack.11)
; CHECK-NEXT: $x24 = LD $x2, 1952 :: (load (s64) from %stack.12)
; CHECK-NEXT: $x25 = LD $x2, 1944 :: (load (s64) from %stack.13)
; CHECK-NEXT: $x26 = LD $x2, 1936 :: (load (s64) from %stack.14)
; CHECK-NEXT: $x27 = LD $x2, 1928 :: (load (s64) from %stack.15)
; CHECK-NEXT: $x2 = frame-destroy ADDI $x2, 2032
; CHECK-NEXT: PseudoRET
bb.0:
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv-fastcc.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -302,8 +302,8 @@ define fastcc <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x
; LMULMAX8-NEXT: vmv.v.v v8, v24
; LMULMAX8-NEXT: call ext3@plt
; LMULMAX8-NEXT: addi sp, s0, -384
; LMULMAX8-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: addi sp, sp, 384
; LMULMAX8-NEXT: ret
;
Expand Down Expand Up @@ -332,8 +332,8 @@ define fastcc <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x
; LMULMAX4-NEXT: vmv.v.v v12, v28
; LMULMAX4-NEXT: call ext3@plt
; LMULMAX4-NEXT: addi sp, s0, -384
; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: addi sp, sp, 384
; LMULMAX4-NEXT: ret
%t = call fastcc <32 x i32> @ext3(<32 x i32> %z, <32 x i32> %y, <32 x i32> %x, i32 %w, i32 42)
Expand Down Expand Up @@ -396,8 +396,8 @@ define fastcc <32 x i32> @pass_vector_arg_indirect_stack(<32 x i32> %x, <32 x i3
; LMULMAX8-NEXT: vmv.v.i v16, 0
; LMULMAX8-NEXT: call vector_arg_indirect_stack@plt
; LMULMAX8-NEXT: addi sp, s0, -384
; LMULMAX8-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: addi sp, sp, 384
; LMULMAX8-NEXT: ret
;
Expand Down Expand Up @@ -433,8 +433,8 @@ define fastcc <32 x i32> @pass_vector_arg_indirect_stack(<32 x i32> %x, <32 x i3
; LMULMAX4-NEXT: vmv.v.i v20, 0
; LMULMAX4-NEXT: call vector_arg_indirect_stack@plt
; LMULMAX4-NEXT: addi sp, s0, -384
; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: addi sp, sp, 384
; LMULMAX4-NEXT: ret
%s = call fastcc <32 x i32> @vector_arg_indirect_stack(i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer, <32 x i32> zeroinitializer, i32 8)
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-calling-conv.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -801,8 +801,8 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x
; LMULMAX8-NEXT: vmv.v.v v8, v24
; LMULMAX8-NEXT: call ext3@plt
; LMULMAX8-NEXT: addi sp, s0, -384
; LMULMAX8-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: addi sp, sp, 384
; LMULMAX8-NEXT: ret
;
Expand Down Expand Up @@ -831,8 +831,8 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x
; LMULMAX4-NEXT: vmv.v.v v12, v28
; LMULMAX4-NEXT: call ext3@plt
; LMULMAX4-NEXT: addi sp, s0, -384
; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: addi sp, sp, 384
; LMULMAX4-NEXT: ret
;
Expand Down Expand Up @@ -871,8 +871,8 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x
; LMULMAX2-NEXT: vmv.v.v v14, v30
; LMULMAX2-NEXT: call ext3@plt
; LMULMAX2-NEXT: addi sp, s0, -384
; LMULMAX2-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX2-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; LMULMAX2-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX2-NEXT: addi sp, sp, 384
; LMULMAX2-NEXT: ret
;
Expand Down Expand Up @@ -934,8 +934,8 @@ define <32 x i32> @ret_v32i32_call_v32i32_v32i32_v32i32_i32(<32 x i32> %x, <32 x
; LMULMAX1-NEXT: vmv.v.v v15, v31
; LMULMAX1-NEXT: call ext3@plt
; LMULMAX1-NEXT: addi sp, s0, -384
; LMULMAX1-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX1-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; LMULMAX1-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX1-NEXT: addi sp, sp, 384
; LMULMAX1-NEXT: ret
%t = call <32 x i32> @ext3(<32 x i32> %z, <32 x i32> %y, <32 x i32> %x, i32 %w, i32 42)
Expand Down Expand Up @@ -1039,8 +1039,8 @@ define <32 x i32> @call_split_vector_args(<2 x i32>* %pa, <32 x i32>* %pb) {
; LMULMAX8-NEXT: vmv1r.v v12, v8
; LMULMAX8-NEXT: call split_vector_args@plt
; LMULMAX8-NEXT: addi sp, s0, -384
; LMULMAX8-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX8-NEXT: addi sp, sp, 384
; LMULMAX8-NEXT: ret
;
Expand Down Expand Up @@ -1072,8 +1072,8 @@ define <32 x i32> @call_split_vector_args(<2 x i32>* %pa, <32 x i32>* %pb) {
; LMULMAX4-NEXT: vmv1r.v v12, v8
; LMULMAX4-NEXT: call split_vector_args@plt
; LMULMAX4-NEXT: addi sp, s0, -384
; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: ld ra, 376(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: ld s0, 368(sp) # 8-byte Folded Reload
; LMULMAX4-NEXT: addi sp, sp, 384
; LMULMAX4-NEXT: ret
;
Expand Down Expand Up @@ -1112,8 +1112,8 @@ define <32 x i32> @call_split_vector_args(<2 x i32>* %pa, <32 x i32>* %pb) {
; LMULMAX2-NEXT: vmv.v.v v22, v14
; LMULMAX2-NEXT: call split_vector_args@plt
; LMULMAX2-NEXT: addi sp, s0, -256
; LMULMAX2-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; LMULMAX2-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; LMULMAX2-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; LMULMAX2-NEXT: addi sp, sp, 256
; LMULMAX2-NEXT: ret
;
Expand Down Expand Up @@ -1166,8 +1166,8 @@ define <32 x i32> @call_split_vector_args(<2 x i32>* %pa, <32 x i32>* %pb) {
; LMULMAX1-NEXT: vmv.v.v v23, v15
; LMULMAX1-NEXT: call split_vector_args@plt
; LMULMAX1-NEXT: addi sp, s0, -256
; LMULMAX1-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; LMULMAX1-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; LMULMAX1-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; LMULMAX1-NEXT: addi sp, sp, 256
; LMULMAX1-NEXT: ret
%a = load <2 x i32>, <2 x i32>* %pa
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-extract-i1.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -176,8 +176,8 @@ define i1 @extractelt_v256i1(<256 x i8>* %x, i64 %idx) nounwind {
; RV32-NEXT: vse8.v v8, (a1)
; RV32-NEXT: lb a0, 0(a0)
; RV32-NEXT: addi sp, s0, -512
; RV32-NEXT: lw s0, 504(sp) # 4-byte Folded Reload
; RV32-NEXT: lw ra, 508(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 504(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 512
; RV32-NEXT: ret
;
Expand Down Expand Up @@ -208,8 +208,8 @@ define i1 @extractelt_v256i1(<256 x i8>* %x, i64 %idx) nounwind {
; RV64-NEXT: vse8.v v8, (a1)
; RV64-NEXT: lb a0, 0(a0)
; RV64-NEXT: addi sp, s0, -512
; RV64-NEXT: ld s0, 496(sp) # 8-byte Folded Reload
; RV64-NEXT: ld ra, 504(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 496(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 512
; RV64-NEXT: ret
%a = load <256 x i8>, <256 x i8>* %x
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rvv/large-rvv-stack-size.mir
View file
Original file line number Diff line number Diff line change
Expand Up @@ -36,8 +36,8 @@
; CHECK-NEXT: addiw a0, a0, -1792
; CHECK-NEXT: sub sp, s0, a0
; CHECK-NEXT: addi sp, sp, 272
; CHECK-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 2024(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 2016(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 2032
; CHECK-NEXT: ret
ret void
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/rvv/localvar.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -105,8 +105,8 @@ define void @local_var_m4() {
; RV64IV-NEXT: addi a0, sp, 16
; RV64IV-NEXT: vl4r.v v8, (a0)
; RV64IV-NEXT: addi sp, s0, -32
; RV64IV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IV-NEXT: addi sp, sp, 32
; RV64IV-NEXT: ret
%local0 = alloca <vscale x 32 x i8>
Expand Down Expand Up @@ -139,8 +139,8 @@ define void @local_var_m8() {
; RV64IV-NEXT: addi a0, sp, 48
; RV64IV-NEXT: vl8r.v v8, (a0)
; RV64IV-NEXT: addi sp, s0, -64
; RV64IV-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; RV64IV-NEXT: addi sp, sp, 64
; RV64IV-NEXT: ret
%local0 = alloca <vscale x 64 x i8>
Expand Down Expand Up @@ -217,8 +217,8 @@ define void @local_var_m2_with_varsize_object(i64 %n) {
; RV64IV-NEXT: addi a0, a0, -32
; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: addi sp, s0, -32
; RV64IV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64IV-NEXT: addi sp, sp, 32
; RV64IV-NEXT: ret
%1 = alloca i8, i64 %n
Expand Down Expand Up @@ -268,9 +268,9 @@ define void @local_var_m2_with_bp(i64 %n) {
; RV64IV-NEXT: vl2r.v v8, (a0)
; RV64IV-NEXT: lw a0, 120(s1)
; RV64IV-NEXT: addi sp, s0, -256
; RV64IV-NEXT: ld s1, 232(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld ra, 248(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld s0, 240(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld s1, 232(sp) # 8-byte Folded Reload
; RV64IV-NEXT: addi sp, sp, 256
; RV64IV-NEXT: ret
%1 = alloca i8, i64 %n
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rvv/memory-args.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -59,8 +59,8 @@ define <vscale x 64 x i8> @caller() {
; RV64IV-NEXT: vs8r.v v24, (a1)
; RV64IV-NEXT: call callee@plt
; RV64IV-NEXT: addi sp, s0, -64
; RV64IV-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64IV-NEXT: ld s0, 48(sp) # 8-byte Folded Reload
; RV64IV-NEXT: addi sp, sp, 64
; RV64IV-NEXT: ret
%local0 = alloca <vscale x 64 x i8>
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rvv/rv32-spill-vector-csr.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -74,8 +74,8 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
; SPILL-O2-NEXT: csrr a0, vlenb
; SPILL-O2-NEXT: slli a0, a0, 1
; SPILL-O2-NEXT: add sp, sp, a0
; SPILL-O2-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; SPILL-O2-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; SPILL-O2-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; SPILL-O2-NEXT: addi sp, sp, 16
; SPILL-O2-NEXT: ret
{
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/rvv/rv64-spill-vector-csr.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -74,8 +74,8 @@ define <vscale x 1 x double> @foo(<vscale x 1 x double> %a, <vscale x 1 x double
; SPILL-O2-NEXT: csrr a0, vlenb
; SPILL-O2-NEXT: slli a0, a0, 1
; SPILL-O2-NEXT: add sp, sp, a0
; SPILL-O2-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; SPILL-O2-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; SPILL-O2-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; SPILL-O2-NEXT: addi sp, sp, 32
; SPILL-O2-NEXT: ret
{
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rvv/rvv-framelayout.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,8 +31,8 @@ define void @rvv_vla(i64 %n, i64 %i) nounwind {
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: lw a0, 0(a0)
; CHECK-NEXT: addi sp, s0, -32
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
%vla.addr = alloca i32, i64 %n
Expand Down Expand Up @@ -69,8 +69,8 @@ define void @rvv_overaligned() nounwind {
; CHECK-NEXT: vl2re64.v v8, (a0)
; CHECK-NEXT: lw a0, 64(sp)
; CHECK-NEXT: addi sp, s0, -128
; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 128
; CHECK-NEXT: ret
%overaligned = alloca i32, align 64
Expand Down Expand Up @@ -116,9 +116,9 @@ define void @rvv_vla_and_overaligned(i64 %n, i64 %i) nounwind {
; CHECK-NEXT: add a0, a0, a1
; CHECK-NEXT: lw a0, 0(a0)
; CHECK-NEXT: addi sp, s0, -128
; CHECK-NEXT: ld s1, 104(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 120(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 112(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s1, 104(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 128
; CHECK-NEXT: ret
%overaligned = alloca i32, align 64
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rvv/rvv-out-arguments.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,8 @@ define dso_local void @lots_args(i32 signext %x0, i32 signext %x1, <vscale x 16
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 3
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 64(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 80
; CHECK-NEXT: ret
entry:
Expand Down Expand Up @@ -141,8 +141,8 @@ define dso_local signext i32 @main() #0 {
; CHECK-NEXT: csrr a1, vlenb
; CHECK-NEXT: slli a1, a1, 3
; CHECK-NEXT: add sp, sp, a1
; CHECK-NEXT: ld s0, 96(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 104(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 96(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 112
; CHECK-NEXT: ret
entry:
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -358,8 +358,8 @@ define <vscale x 1 x double> @test8(i64 %avl, i8 zeroext %cond, <vscale x 1 x do
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
entry:
Expand Down Expand Up @@ -418,8 +418,8 @@ define <vscale x 1 x double> @test9(i64 %avl, i8 zeroext %cond, <vscale x 1 x do
; CHECK-NEXT: csrr a0, vlenb
; CHECK-NEXT: slli a0, a0, 1
; CHECK-NEXT: add sp, sp, a0
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 32
; CHECK-NEXT: ret
entry:
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/select-cc.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -179,8 +179,8 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
; RV32I-NEXT: call bar@plt
; RV32I-NEXT: .LBB1_4:
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand All @@ -196,8 +196,8 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
; RV32IBT-NEXT: call bar@plt
; RV32IBT-NEXT: .LBB1_2:
; RV32IBT-NEXT: mv a0, s0
; RV32IBT-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IBT-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IBT-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IBT-NEXT: addi sp, sp, 16
; RV32IBT-NEXT: ret
%5 = icmp eq i16 %0, 0
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/shadowcallstack.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -91,10 +91,10 @@ define i32 @f4() shadowcallstack {
; RV32-NEXT: add a1, s3, s1
; RV32-NEXT: add a0, s0, a0
; RV32-NEXT: add a0, a1, a0
; RV32-NEXT: lw s3, 0(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32-NEXT: lw s3, 0(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: lw ra, -4(s2)
; RV32-NEXT: addi s2, s2, -4
Expand Down Expand Up @@ -124,10 +124,10 @@ define i32 @f4() shadowcallstack {
; RV64-NEXT: addw a1, s3, s1
; RV64-NEXT: addw a0, s0, a0
; RV64-NEXT: addw a0, a1, a0
; RV64-NEXT: ld s3, 0(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: ld s3, 0(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 32
; RV64-NEXT: ld ra, -8(s2)
; RV64-NEXT: addi s2, s2, -8
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/shifts.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -402,8 +402,8 @@ define i128 @ashr128(i128 %a, i128 %b) nounwind {
; RV32I-NEXT: sw a4, 8(a0)
; RV32I-NEXT: sw s1, 0(a0)
; RV32I-NEXT: sw t0, 4(a0)
; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/shrinkwrap.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -86,8 +86,8 @@ define void @conditional_alloca(i32 %n) nounwind {
; RV32I-SW-NO-NEXT: call notdead@plt
; RV32I-SW-NO-NEXT: .LBB1_2: # %if.end
; RV32I-SW-NO-NEXT: addi sp, s0, -16
; RV32I-SW-NO-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-SW-NO-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-SW-NO-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-SW-NO-NEXT: addi sp, sp, 16
; RV32I-SW-NO-NEXT: ret
;
Expand All @@ -106,8 +106,8 @@ define void @conditional_alloca(i32 %n) nounwind {
; RV32I-SW-NEXT: mv sp, a0
; RV32I-SW-NEXT: call notdead@plt
; RV32I-SW-NEXT: addi sp, s0, -16
; RV32I-SW-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-SW-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-SW-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-SW-NEXT: addi sp, sp, 16
; RV32I-SW-NEXT: .LBB1_2: # %if.end
; RV32I-SW-NEXT: ret
Expand Down Expand Up @@ -147,8 +147,8 @@ define void @conditional_alloca(i32 %n) nounwind {
; RV64I-SW-NEXT: mv sp, a0
; RV64I-SW-NEXT: call notdead@plt
; RV64I-SW-NEXT: addi sp, s0, -16
; RV64I-SW-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-SW-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-SW-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-SW-NEXT: addi sp, sp, 16
; RV64I-SW-NEXT: .LBB1_2: # %if.end
; RV64I-SW-NEXT: ret
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/srem-lkk.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -243,9 +243,9 @@ define i32 @combine_srem_sdiv(i32 %x) nounwind {
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __divsi3@plt
; RV32I-NEXT: add a0, s1, a0
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -279,9 +279,9 @@ define i32 @combine_srem_sdiv(i32 %x) nounwind {
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __divdi3@plt
; RV64I-NEXT: addw a0, s1, a0
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
;
Expand Down
Loading