36 changes: 18 additions & 18 deletions llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memcpy-inline.ll
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Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=aarch64-unknown-unknown -global-isel -global-isel-abort=1 -verify-machineinstrs -stop-after=irtranslator %s -o - | FileCheck %s

define void @copy(i8* %dst, i8* %src) {
define void @copy(ptr %dst, ptr %src) {
; CHECK-LABEL: name: copy
; CHECK: bb.1.entry:
; CHECK: liveins: $x0, $x1
Expand All @@ -12,11 +12,11 @@ define void @copy(i8* %dst, i8* %src) {
; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 0 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
; CHECK: RET_ReallyLR
entry:
call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src, i32 4, i1 false)
call void @llvm.memcpy.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 false)
ret void
}

define void @inline_copy(i8* %dst, i8* %src) {
define void @inline_copy(ptr %dst, ptr %src) {
; CHECK-LABEL: name: inline_copy
; CHECK: bb.1.entry:
; CHECK: liveins: $x0, $x1
Expand All @@ -27,11 +27,11 @@ define void @inline_copy(i8* %dst, i8* %src) {
; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
; CHECK: RET_ReallyLR
entry:
call void @llvm.memcpy.inline.p0i8.p0i8.i32(i8* %dst, i8* %src, i32 4, i1 false)
call void @llvm.memcpy.inline.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 false)
ret void
}

define void @copy_volatile(i8* %dst, i8* %src) {
define void @copy_volatile(ptr %dst, ptr %src) {
; CHECK-LABEL: name: copy_volatile
; CHECK: bb.1.entry:
; CHECK: liveins: $x0, $x1
Expand All @@ -42,11 +42,11 @@ define void @copy_volatile(i8* %dst, i8* %src) {
; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 0 :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
; CHECK: RET_ReallyLR
entry:
call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src, i32 4, i1 true)
call void @llvm.memcpy.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 true)
ret void
}

define void @inline_copy_volatile(i8* %dst, i8* %src) {
define void @inline_copy_volatile(ptr %dst, ptr %src) {
; CHECK-LABEL: name: inline_copy_volatile
; CHECK: bb.1.entry:
; CHECK: liveins: $x0, $x1
Expand All @@ -57,11 +57,11 @@ define void @inline_copy_volatile(i8* %dst, i8* %src) {
; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
; CHECK: RET_ReallyLR
entry:
call void @llvm.memcpy.inline.p0i8.p0i8.i32(i8* %dst, i8* %src, i32 4, i1 true)
call void @llvm.memcpy.inline.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 true)
ret void
}

define void @tail_copy(i8* %dst, i8* %src) {
define void @tail_copy(ptr %dst, ptr %src) {
; CHECK-LABEL: name: tail_copy
; CHECK: bb.1.entry:
; CHECK: liveins: $x0, $x1
Expand All @@ -72,11 +72,11 @@ define void @tail_copy(i8* %dst, i8* %src) {
; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 1 :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
; CHECK: RET_ReallyLR
entry:
tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src, i32 4, i1 false)
tail call void @llvm.memcpy.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 false)
ret void
}

define void @tail_inline_copy(i8* %dst, i8* %src) {
define void @tail_inline_copy(ptr %dst, ptr %src) {
; CHECK-LABEL: name: tail_inline_copy
; CHECK: bb.1.entry:
; CHECK: liveins: $x0, $x1
Expand All @@ -87,11 +87,11 @@ define void @tail_inline_copy(i8* %dst, i8* %src) {
; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (store (s8) into %ir.dst), (load (s8) from %ir.src)
; CHECK: RET_ReallyLR
entry:
tail call void @llvm.memcpy.inline.p0i8.p0i8.i32(i8* %dst, i8* %src, i32 4, i1 false)
tail call void @llvm.memcpy.inline.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 false)
ret void
}

define void @tail_copy_volatile(i8* %dst, i8* %src) {
define void @tail_copy_volatile(ptr %dst, ptr %src) {
; CHECK-LABEL: name: tail_copy_volatile
; CHECK: bb.1.entry:
; CHECK: liveins: $x0, $x1
Expand All @@ -102,11 +102,11 @@ define void @tail_copy_volatile(i8* %dst, i8* %src) {
; CHECK: G_MEMCPY [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64), 1 :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
; CHECK: RET_ReallyLR
entry:
tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %dst, i8* %src, i32 4, i1 true)
tail call void @llvm.memcpy.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 true)
ret void
}

define void @tail_inline_copy_volatile(i8* %dst, i8* %src) {
define void @tail_inline_copy_volatile(ptr %dst, ptr %src) {
; CHECK-LABEL: name: tail_inline_copy_volatile
; CHECK: bb.1.entry:
; CHECK: liveins: $x0, $x1
Expand All @@ -117,9 +117,9 @@ define void @tail_inline_copy_volatile(i8* %dst, i8* %src) {
; CHECK: G_MEMCPY_INLINE [[COPY]](p0), [[COPY1]](p0), [[ZEXT]](s64) :: (volatile store (s8) into %ir.dst), (volatile load (s8) from %ir.src)
; CHECK: RET_ReallyLR
entry:
tail call void @llvm.memcpy.inline.p0i8.p0i8.i32(i8* %dst, i8* %src, i32 4, i1 true)
tail call void @llvm.memcpy.inline.p0.p0.i32(ptr %dst, ptr %src, i32 4, i1 true)
ret void
}

declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1) nounwind
declare void @llvm.memcpy.inline.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1) nounwind
declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture readonly, i32, i1) nounwind
declare void @llvm.memcpy.inline.p0.p0.i32(ptr nocapture writeonly, ptr nocapture readonly, i32, i1) nounwind
15 changes: 6 additions & 9 deletions llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-memfunc-undef.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -7,8 +7,7 @@ define void @memset() {
; CHECK-NEXT: RET_ReallyLR
entry:
%buf = alloca [512 x i8], align 1
%ptr = getelementptr inbounds [512 x i8], [512 x i8]* %buf, i32 0, i32 0
call void @llvm.memset.p0i8.i32(i8* %ptr, i8 undef, i32 512, i1 false)
call void @llvm.memset.p0.i32(ptr %buf, i8 undef, i32 512, i1 false)
ret void
}

Expand All @@ -19,8 +18,7 @@ define void @memcpy() {
; CHECK-NEXT: RET_ReallyLR
entry:
%buf = alloca [512 x i8], align 1
%ptr = getelementptr inbounds [512 x i8], [512 x i8]* %buf, i32 0, i32 0
call void @llvm.memcpy.p0i8.p0i8.i32(i8* %ptr, i8* undef, i32 512, i1 false)
call void @llvm.memcpy.p0.p0.i32(ptr %buf, ptr undef, i32 512, i1 false)
ret void
}

Expand All @@ -31,11 +29,10 @@ define void @memmove() {
; CHECK-NEXT: RET_ReallyLR
entry:
%buf = alloca [512 x i8], align 1
%ptr = getelementptr inbounds [512 x i8], [512 x i8]* %buf, i32 0, i32 0
call void @llvm.memmove.p0i8.p0i8.i32(i8* %ptr, i8* undef, i32 512, i1 false)
call void @llvm.memmove.p0.p0.i32(ptr %buf, ptr undef, i32 512, i1 false)
ret void
}

declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) nounwind
declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture writeonly, i8* nocapture readonly, i32, i1) nounwind
declare void @llvm.memmove.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i1) nounwind
declare void @llvm.memset.p0.i32(ptr nocapture, i8, i32, i1) nounwind
declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture readonly, i32, i1) nounwind
declare void @llvm.memmove.p0.p0.i32(ptr nocapture, ptr nocapture, i32, i1) nounwind
28 changes: 14 additions & 14 deletions llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-op-intrinsics.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ define i64 @expect_i64(i64 %arg0) {
ret i64 %expval
}

define i8* @ptr_annotate(i8* %arg0, i8* %arg1, i8* %arg2, i32 %arg3) {
define ptr @ptr_annotate(ptr %arg0, ptr %arg1, ptr %arg2, i32 %arg3) {
; CHECK-LABEL: name: ptr_annotate
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $w3, $x0, $x1, $x2
Expand All @@ -24,8 +24,8 @@ define i8* @ptr_annotate(i8* %arg0, i8* %arg1, i8* %arg2, i32 %arg3) {
; CHECK: [[COPY4:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK: $x0 = COPY [[COPY4]](p0)
; CHECK: RET_ReallyLR implicit $x0
%call = call i8* @llvm.ptr.annotation.p0i8(i8* %arg0, i8* %arg1, i8* %arg2, i32 %arg3, i8* null)
ret i8* %call
%call = call ptr @llvm.ptr.annotation.p0(ptr %arg0, ptr %arg1, ptr %arg2, i32 %arg3, ptr null)
ret ptr %call
}

@.str = private unnamed_addr constant [4 x i8] c"sth\00", section "llvm.metadata"
Expand All @@ -39,39 +39,39 @@ define i32 @annotation(i32 %a) {
; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY [[COPY]](s32)
; CHECK: $w0 = COPY [[COPY1]](s32)
; CHECK: RET_ReallyLR implicit $w0
%call = call i32 @llvm.annotation.i32(i32 %a, i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0), i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str1, i32 0, i32 0), i32 2)
%call = call i32 @llvm.annotation.i32(i32 %a, ptr @.str, ptr @.str1, i32 2)
ret i32 %call
}

define i8* @launder_invariant_group(i8* %p) {
define ptr @launder_invariant_group(ptr %p) {
; CHECK-LABEL: name: launder_invariant_group
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK: $x0 = COPY [[COPY1]](p0)
; CHECK: RET_ReallyLR implicit $x0
%q = call i8* @llvm.launder.invariant.group.p0i8(i8* %p)
ret i8* %q
%q = call ptr @llvm.launder.invariant.group.p0(ptr %p)
ret ptr %q
}

define i8* @strip_invariant_group(i8* %p) {
define ptr @strip_invariant_group(ptr %p) {
; CHECK-LABEL: name: strip_invariant_group
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK: $x0 = COPY [[COPY1]](p0)
; CHECK: RET_ReallyLR implicit $x0
%q = call i8* @llvm.strip.invariant.group.p0i8(i8* %p)
ret i8* %q
%q = call ptr @llvm.strip.invariant.group.p0(ptr %p)
ret ptr %q
}

declare i64 @llvm.expect.i64(i64, i64) #0
declare i8* @llvm.ptr.annotation.p0i8(i8*, i8*, i8*, i32, i8*) #1
declare i32 @llvm.annotation.i32(i32, i8*, i8*, i32) #1
declare i8* @llvm.launder.invariant.group.p0i8(i8*) #2
declare i8* @llvm.strip.invariant.group.p0i8(i8*) #3
declare ptr @llvm.ptr.annotation.p0(ptr, ptr, ptr, i32, ptr) #1
declare i32 @llvm.annotation.i32(i32, ptr, ptr, i32) #1
declare ptr @llvm.launder.invariant.group.p0(ptr) #2
declare ptr @llvm.strip.invariant.group.p0(ptr) #3

attributes #0 = { nounwind readnone willreturn }
attributes #1 = { nounwind willreturn }
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-no-unwind-inline-asm.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ entry:
unreachable
}

define dso_local void @test() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
define dso_local void @test() personality ptr @__gxx_personality_v0 {
entry:

; CHECK-LABEL: name: test
Expand All @@ -30,13 +30,13 @@ lpad:
; CHECK: bb.3.lpad
; CHECK: EH_LABEL

%0 = landingpad { i8*, i32 }
%0 = landingpad { ptr, i32 }
cleanup
call void (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str.2, i64 0, i64 0))
resume { i8*, i32 } %0
call void (ptr, ...) @printf(ptr @.str.2)
resume { ptr, i32 } %0

}

declare dso_local i32 @__gxx_personality_v0(...)

declare dso_local void @printf(i8*, ...)
declare dso_local void @printf(ptr, ...)
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-one-by-n-vector-ptr-add.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@
; We should not create a splat vector for the non-vector index on this
; getelementptr. The entire getelementptr should be translated to a scalar
; G_PTR_ADD.
define <1 x i8*> @one_elt_vector_ptr_add_non_vector_idx(<1 x i8*> %vec) {
define <1 x ptr> @one_elt_vector_ptr_add_non_vector_idx(<1 x ptr> %vec) {
; CHECK-LABEL: name: one_elt_vector_ptr_add_non_vector_idx
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $d0
Expand All @@ -18,14 +18,14 @@ define <1 x i8*> @one_elt_vector_ptr_add_non_vector_idx(<1 x i8*> %vec) {
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK: $d0 = COPY [[COPY2]](p0)
; CHECK: RET_ReallyLR implicit $d0
%ptr_add = getelementptr i8, <1 x i8*> %vec, <1 x i32> <i32 1>
ret <1 x i8*> %ptr_add
%ptr_add = getelementptr i8, <1 x ptr> %vec, <1 x i32> <i32 1>
ret <1 x ptr> %ptr_add
}

; We should not create a splat vector for the non-vector pointer on this
; getelementptr. The entire getelementptr should be translated to a scalar
; G_PTR_ADD.
define <1 x i8*> @one_elt_vector_ptr_add_non_vector_ptr(i8* %vec) {
define <1 x ptr> @one_elt_vector_ptr_add_non_vector_ptr(ptr %vec) {
; CHECK-LABEL: name: one_elt_vector_ptr_add_non_vector_ptr
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0
Expand All @@ -37,6 +37,6 @@ define <1 x i8*> @one_elt_vector_ptr_add_non_vector_ptr(i8* %vec) {
; CHECK: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK: $d0 = COPY [[COPY2]](p0)
; CHECK: RET_ReallyLR implicit $d0
%ptr_add = getelementptr i8, i8* %vec, <1 x i32> <i32 1>
ret <1 x i8*> %ptr_add
%ptr_add = getelementptr i8, ptr %vec, <1 x i32> <i32 1>
ret <1 x ptr> %ptr_add
}
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-objects.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@
; CHECK: - { id: 1, type: default, offset: 0, size: 8, alignment: 16, stack-id: default,
; CHECK-NEXT: isImmutable: true, isAliased: false,
define void @stack_passed_i64(i64 %arg, i64 %arg1, i64 %arg2, i64 %arg3, i64 %arg4, i64 %arg5, i64 %arg6,
i64 %arg7, i64 %arg8, i64* byval(i64) %arg9) {
i64 %arg7, i64 %arg8, ptr byval(i64) %arg9) {
; CHECK: bb.1 (%ir-block.0):
; CHECK: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.1
; CHECK: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[FRAME_INDEX]](p0) :: (invariant load (s64) from %fixed-stack.1, align 16)
Expand All @@ -21,8 +21,8 @@ define void @stack_passed_i64(i64 %arg, i64 %arg1, i64 %arg2, i64 %arg3, i64 %ar
; CHECK: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[LOAD1]], [[LOAD]]
; CHECK: G_STORE [[ADD]](s64), [[COPY8]](p0) :: (volatile store (s64) into %ir.arg9)
; CHECK: RET_ReallyLR
%load = load i64, i64* %arg9
%load = load i64, ptr %arg9
%add = add i64 %load, %arg8
store volatile i64 %add, i64* %arg9
store volatile i64 %add, ptr %arg9
ret void
}
5 changes: 2 additions & 3 deletions llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-stack-protector-windows.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -30,9 +30,8 @@ define void @caller() sspreq {
; CHECK-NEXT: .seh_endproc
entry:
%x = alloca i32, align 4
%0 = bitcast i32* %x to i8*
call void @callee(i32* nonnull %x)
call void @callee(ptr nonnull %x)
ret void
}

declare void @callee(i32*)
declare void @callee(ptr)
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-store-metadata.ll
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Original file line number Diff line number Diff line change
@@ -1,51 +1,51 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=aarch64-- -mcpu=falkor -O0 -aarch64-enable-atomic-cfg-tidy=0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - | FileCheck %s

define void @store_nontemporal(i32* dereferenceable(4) %ptr) {
define void @store_nontemporal(ptr dereferenceable(4) %ptr) {
; CHECK-LABEL: name: store_nontemporal
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: G_STORE [[C]](s32), [[COPY]](p0) :: (non-temporal store (s32) into %ir.ptr)
; CHECK: RET_ReallyLR
store i32 0, i32* %ptr, align 4, !nontemporal !0
store i32 0, ptr %ptr, align 4, !nontemporal !0
ret void
}

define void @store_dereferenceable(i32* dereferenceable(4) %ptr) {
define void @store_dereferenceable(ptr dereferenceable(4) %ptr) {
; CHECK-LABEL: name: store_dereferenceable
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: G_STORE [[C]](s32), [[COPY]](p0) :: (store (s32) into %ir.ptr)
; CHECK: RET_ReallyLR
store i32 0, i32* %ptr, align 4
store i32 0, ptr %ptr, align 4
ret void
}

define void @store_volatile_dereferenceable(i32* dereferenceable(4) %ptr) {
define void @store_volatile_dereferenceable(ptr dereferenceable(4) %ptr) {
; CHECK-LABEL: name: store_volatile_dereferenceable
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: G_STORE [[C]](s32), [[COPY]](p0) :: (volatile store (s32) into %ir.ptr)
; CHECK: RET_ReallyLR
store volatile i32 0, i32* %ptr, align 4
store volatile i32 0, ptr %ptr, align 4
ret void
}

define void @store_falkor_strided_access(i32* %ptr) {
define void @store_falkor_strided_access(ptr %ptr) {
; CHECK-LABEL: name: store_falkor_strided_access
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
; CHECK: G_STORE [[C]](s32), [[COPY]](p0) :: ("aarch64-strided-access" store (s32) into %ir.ptr)
; CHECK: RET_ReallyLR
store i32 0, i32* %ptr, align 4, !falkor.strided.access !0
store i32 0, ptr %ptr, align 4, !falkor.strided.access !0
ret void
}

Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-switch-bittest.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -229,7 +229,7 @@ define void @bit_test_block_incomplete_phi() {
; CHECK: bb.3.if.end:
; CHECK-NEXT: successors: %bb.4(0x80000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[DEF1]](p0) :: (load (p0) from `i8** undef`)
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(p0) = G_LOAD [[DEF1]](p0) :: (load (p0) from `ptr undef`)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.4.return:
; CHECK-NEXT: [[PHI:%[0-9]+]]:_(s1) = G_PHI [[C]](s1), %bb.3, [[C1]](s1), %bb.5
Expand All @@ -253,7 +253,7 @@ sw.epilog.i: ; preds = %entry
unreachable

if.end: ; preds = %entry, %entry, %entry, %entry, %entry, %entry, %entry
%0 = load i8*, i8** undef, align 8
%0 = load ptr, ptr undef, align 8
br label %return

return: ; preds = %if.end, %entry, %entry, %entry, %entry
Expand Down
9 changes: 4 additions & 5 deletions llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-tbaa.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,11 +4,10 @@ target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16

define void @snork() {
bb:
%tmp1 = getelementptr i16, i16* null, i64 0
%tmp5 = getelementptr i16, i16* null, i64 2
%tmp6 = load i16, i16* %tmp1, align 2, !tbaa !0
store i16 %tmp6, i16* %tmp5, align 2, !tbaa !0
; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD %{{[0-9]+}}(p0) :: (load (s16) from %ir.tmp1, !tbaa !0)
%tmp5 = getelementptr i16, ptr null, i64 2
%tmp6 = load i16, ptr null, align 2, !tbaa !0
store i16 %tmp6, ptr %tmp5, align 2, !tbaa !0
; CHECK: [[LOAD:%[0-9]+]]:_(s16) = G_LOAD %{{[0-9]+}}(p0) :: (load (s16) from `ptr null`, !tbaa !0)
; CHECK: G_STORE [[LOAD]](s16), %{{[0-9]+}}(p0) :: (store (s16) into %ir.tmp5, !tbaa !0)
ret void
}
Expand Down
29 changes: 14 additions & 15 deletions llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-unwind-inline-asm.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,13 +13,12 @@ entry:
unreachable
}

define dso_local void @test() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
define dso_local void @test() personality ptr @__gxx_personality_v0 {
; CHECK-LABEL: name: test
; CHECK: bb.1.entry:
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[GV:%[0-9]+]]:_(p0) = G_GLOBAL_VALUE @.str.2
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY [[GV]](p0)
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: INLINEASM &"bl trap", 1 /* sideeffect attdialect */
; CHECK-NEXT: EH_LABEL <mcsymbol >
Expand All @@ -33,15 +32,15 @@ define dso_local void @test() personality i8* bitcast (i32 (...)* @__gxx_persona
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: EH_LABEL <mcsymbol >
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s128) = G_IMPLICIT_DEF
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY2]](p0)
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[PTRTOINT:%[0-9]+]]:_(s32) = G_PTRTOINT [[COPY1]](p0)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
; CHECK-NEXT: $x0 = COPY [[GV]](p0)
; CHECK-NEXT: BL @printf, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: $x0 = COPY [[COPY1]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY]](p0)
; CHECK-NEXT: BL @_Unwind_Resume, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
entry:
Expand All @@ -55,14 +54,14 @@ invoke.cont:

lpad:

%0 = landingpad { i8*, i32 }
%0 = landingpad { ptr, i32 }
cleanup
call void (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str.2, i64 0, i64 0))
resume { i8*, i32 } %0
call void (ptr, ...) @printf(ptr @.str.2)
resume { ptr, i32 } %0

}

define void @test2() #0 personality i32 (...)* @__gcc_personality_v0 {
define void @test2() #0 personality ptr @__gcc_personality_v0 {
; CHECK-LABEL: name: test2
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)
Expand All @@ -87,15 +86,15 @@ define void @test2() #0 personality i32 (...)* @__gcc_personality_v0 {
; CHECK-NEXT: $x0 = COPY [[COPY1]](p0)
; CHECK-NEXT: BL @_Unwind_Resume, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
invoke void asm sideeffect "", "r"(i64* undef) to label %a unwind label %b
invoke void asm sideeffect "", "r"(ptr undef) to label %a unwind label %b
a:
ret void
b:
%landing_pad = landingpad { i8*, i32 } cleanup
resume { i8*, i32 } %landing_pad
%landing_pad = landingpad { ptr, i32 } cleanup
resume { ptr, i32 } %landing_pad
}

declare i32 @__gcc_personality_v0(...)
declare dso_local i32 @__gxx_personality_v0(...)

declare dso_local void @printf(i8*, ...)
declare dso_local void @printf(ptr, ...)
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-volatile-load-pr36018.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ declare void @bar(i32)
define hidden void @foo() {
; CHECK-NOT: ldrh
; CHECK: ldrsh
%1 = load volatile i16, i16* @g, align 2
%1 = load volatile i16, ptr @g, align 2
%2 = sext i16 %1 to i32
call void @bar(i32 %2)
ret void
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-weird-alloca-size.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,8 +12,8 @@
; CHECK-NEXT: - { id: 0, name: stack_slot, type: default, offset: 0, size: 4, alignment: 4
define void @foo() {
%stack_slot = alloca i19
call void @bar(i19* %stack_slot)
call void @bar(ptr %stack_slot)
ret void
}

declare void @bar(i19* %a)
declare void @bar(ptr %a)
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/AArch64/GlobalISel/legalize-exceptions.ll
View file
Original file line number Diff line number Diff line change
@@ -1,14 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -O0 -mtriple=aarch64-apple-ios -verify-machineinstrs -global-isel -stop-after=legalizer %s -o - | FileCheck %s

@_ZTIi = external global i8*
@_ZTIi = external global ptr

declare i32 @foo(i32)
declare i32 @__gxx_personality_v0(...)
declare i32 @llvm.eh.typeid.for(i8*)
declare void @_Unwind_Resume(i8*)
declare i32 @llvm.eh.typeid.for(ptr)
declare void @_Unwind_Resume(ptr)

define void @bar() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
define void @bar() personality ptr @__gxx_personality_v0 {
; CHECK-LABEL: name: bar
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
Expand Down Expand Up @@ -47,23 +47,23 @@ define void @bar() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to
; CHECK-NEXT: BL @_Unwind_Resume, csr_darwin_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0
; CHECK-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $sp, implicit $sp
; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.trap)
%exn.slot = alloca i8*
%exn.slot = alloca ptr
%ehselector.slot = alloca i32
%1 = invoke i32 @foo(i32 42) to label %continue unwind label %cleanup

cleanup:
%2 = landingpad { i8*, i32 } cleanup
%3 = extractvalue { i8*, i32 } %2, 0
store i8* %3, i8** %exn.slot, align 8
%4 = extractvalue { i8*, i32 } %2, 1
store i32 %4, i32* %ehselector.slot, align 4
%2 = landingpad { ptr, i32 } cleanup
%3 = extractvalue { ptr, i32 } %2, 0
store ptr %3, ptr %exn.slot, align 8
%4 = extractvalue { ptr, i32 } %2, 1
store i32 %4, ptr %ehselector.slot, align 4
br label %eh.resume

continue:
ret void

eh.resume:
%exn = load i8*, i8** %exn.slot, align 8
call void @_Unwind_Resume(i8* %exn)
%exn = load ptr, ptr %exn.slot, align 8
call void @_Unwind_Resume(ptr %exn)
unreachable
}
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/AArch64/GlobalISel/localizer-arm64-tti.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -50,15 +50,15 @@ define i32 @foo() {
; CHECK-NEXT: $w0 = COPY [[C6]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = load i32, i32* @var1, align 4
%0 = load i32, ptr @var1, align 4
%cmp = icmp eq i32 %0, 1
br i1 %cmp, label %if.then, label %if.end

if.then:
store i32 2, i32* @var2, align 4
store i32 3, i32* @var1, align 4
store i32 2, i32* @var3, align 4
store i32 3, i32* @var1, align 4
store i32 2, ptr @var2, align 4
store i32 3, ptr @var1, align 4
store i32 2, ptr @var3, align 4
store i32 3, ptr @var1, align 4
br label %if.end

if.end:
Expand Down Expand Up @@ -101,13 +101,13 @@ define i32 @darwin_tls() {
; CHECK-NEXT: $w0 = COPY [[C2]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = load i32, i32* @var1, align 4
%0 = load i32, ptr @var1, align 4
%cmp = icmp eq i32 %0, 1
br i1 %cmp, label %if.then, label %if.end

if.then:
%tls = load i32, i32* @tls_gv, align 4
store i32 %tls, i32* @var2, align 4
%tls = load i32, ptr @tls_gv, align 4
store i32 %tls, ptr @var2, align 4
br label %if.end

if.end:
Expand Down Expand Up @@ -152,21 +152,21 @@ define i32 @imm_cost_too_large_cost_of_2() {
; CHECK-NEXT: $w0 = COPY [[C3]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $w0
entry:
%0 = load i32, i32* @var1, align 4
%0 = load i32, ptr @var1, align 4
%cst1 = bitcast i32 -2228259 to i32
%cmp = icmp eq i32 %0, 1
br i1 %cmp, label %if.then, label %if.end

if.then:
store i32 %cst1, i32* @var2
store i32 %cst1, ptr @var2
br label %if.then2

if.then2:
store i32 %cst1, i32* @var1
store i32 %cst1, ptr @var1
br label %if.end

if.end:
store i32 %cst1, i32* @var3
store i32 %cst1, ptr @var3
ret i32 0
}

Expand Down Expand Up @@ -209,21 +209,21 @@ define i64 @imm_cost_too_large_cost_of_4() {
; CHECK-NEXT: $x0 = COPY [[C4]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0
entry:
%0 = load i64, i64* @var1_64, align 4
%0 = load i64, ptr @var1_64, align 4
%cst1 = bitcast i64 -2228259 to i64
%cmp = icmp eq i64 %0, 1
br i1 %cmp, label %if.then, label %if.end

if.then:
store i64 %cst1, i64* @var2_64
store i64 %cst1, ptr @var2_64
br label %if.then2

if.then2:
store i64 %cst1, i64* @var1_64
store i64 %cst1, ptr @var1_64
br label %if.end

if.end:
store i64 %cst1, i64* @var3_64
store i64 %cst1, ptr @var3_64
ret i64 0
}

Expand Down
12 changes: 5 additions & 7 deletions llvm/test/CodeGen/AArch64/GlobalISel/memcpy_chk_no_tail.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,20 +9,18 @@ target triple = "arm64-apple-ios13.0.0"
; CHECK-LABEL: @usqrt
; CHECK-NOT: b memcpy
; CHECK: bl _memcpy
define void @usqrt(i32 %x, %struct.int_sqrt* %q) local_unnamed_addr #0 {
define void @usqrt(i32 %x, ptr %q) local_unnamed_addr #0 {
%a = alloca i32, align 4
%bc = bitcast i32* %a to i8*
%bc2 = bitcast %struct.int_sqrt* %q to i8*
%obj = tail call i64 @llvm.objectsize.i64.p0i8(i8* %bc2, i1 false, i1 true, i1 false)
%call = call i8* @__memcpy_chk(i8* %bc2, i8* nonnull %bc, i64 1000, i64 %obj) #4
%obj = tail call i64 @llvm.objectsize.i64.p0(ptr %q, i1 false, i1 true, i1 false)
%call = call ptr @__memcpy_chk(ptr %q, ptr nonnull %a, i64 1000, i64 %obj) #4
ret void
}

; Function Attrs: nofree nounwind optsize
declare i8* @__memcpy_chk(i8*, i8*, i64, i64) local_unnamed_addr #2
declare ptr @__memcpy_chk(ptr, ptr, i64, i64) local_unnamed_addr #2

; Function Attrs: nounwind readnone speculatable willreturn
declare i64 @llvm.objectsize.i64.p0i8(i8*, i1 immarg, i1 immarg, i1 immarg) #3
declare i64 @llvm.objectsize.i64.p0(ptr, i1 immarg, i1 immarg, i1 immarg) #3
attributes #0 = { optsize "disable-tail-calls"="false" "frame-pointer"="all" }
attributes #2 = { nofree nounwind "disable-tail-calls"="false" "frame-pointer"="all" }
attributes #3 = { nounwind readnone speculatable willreturn }
Expand Down
204 changes: 100 additions & 104 deletions llvm/test/CodeGen/AArch64/GlobalISel/merge-stores-truncating.ll
View file

Large diffs are not rendered by default.

4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/no-neon-no-fp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,9 @@ target triple = "aarch64-unknown-unknown"

; We should fall back in the translator if we don't have no-neon/no-fp support.
; CHECK: Instruction selection used fallback path for foo
define void @foo(i128 *%ptr) #0 align 2 {
define void @foo(ptr %ptr) #0 align 2 {
entry:
store i128 0, i128* %ptr, align 16
store i128 0, ptr %ptr, align 16
ret void
}

Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/GlobalISel/ret-1x-vec.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,22 +14,22 @@ define <1 x float> @ret_v1f32(<1 x float> %v) {
ret <1 x float> %v
}

define <1 x i8*> @ret_v1p0(<1 x i8*> %v) {
define <1 x ptr> @ret_v1p0(<1 x ptr> %v) {
; CHECK-LABEL: name: ret_v1p0
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $d0
; CHECK: $d0 = COPY [[COPY]](p0)
; CHECK: RET_ReallyLR implicit $d0
ret <1 x i8*> %v
ret <1 x ptr> %v
}

define <1 x i8 addrspace(1)*> @ret_v1p1(<1 x i8 addrspace(1)*> %v) {
define <1 x ptr addrspace(1)> @ret_v1p1(<1 x ptr addrspace(1)> %v) {
; CHECK-LABEL: name: ret_v1p1
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $d0
; CHECK: [[COPY:%[0-9]+]]:_(p1) = COPY $d0
; CHECK: $d0 = COPY [[COPY]](p1)
; CHECK: RET_ReallyLR implicit $d0
ret <1 x i8 addrspace(1)*> %v
ret <1 x ptr addrspace(1)> %v
}
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/AArch64/GlobalISel/ret-vec-promote.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
; RUN: llc -mtriple=aarch64-linux-gnu -O0 -global-isel -stop-after=irtranslator -o - %s | FileCheck %s

; Tests vectors of i1 types can appropriately extended first before return handles it.
define <4 x i1> @ret_v4i1(<4 x i1> *%v) {
define <4 x i1> @ret_v4i1(ptr %v) {
; CHECK-LABEL: name: ret_v4i1
; CHECK: bb.1 (%ir-block.0):
; CHECK: liveins: $x0
Expand All @@ -11,6 +11,6 @@ define <4 x i1> @ret_v4i1(<4 x i1> *%v) {
; CHECK: [[ANYEXT:%[0-9]+]]:_(<4 x s16>) = G_ANYEXT [[LOAD]](<4 x s1>)
; CHECK: $d0 = COPY [[ANYEXT]](<4 x s16>)
; CHECK: RET_ReallyLR implicit $d0
%v2 = load <4 x i1>, <4 x i1> *%v
%v2 = load <4 x i1>, ptr %v
ret <4 x i1> %v2
}
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/GlobalISel/select-bitfield-insert.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -109,7 +109,7 @@ bb:
ret i64 %out
}

define i64 @extra_use1(i64 %in1, i64 %in2, i64* %p) {
define i64 @extra_use1(i64 %in1, i64 %in2, ptr %p) {
; GISEL-LABEL: extra_use1:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: lsl x8, x0, #1
Expand All @@ -129,11 +129,11 @@ bb:
%tmp3 = shl i64 %in1, 1
%tmp4 = and i64 %in2, 1
%out = or i64 %tmp3, %tmp4
store i64 %tmp3, i64* %p
store i64 %tmp3, ptr %p
ret i64 %out
}

define i64 @extra_use2(i64 %in1, i64 %in2, i64* %p) {
define i64 @extra_use2(i64 %in1, i64 %in2, ptr %p) {
; GISEL-LABEL: extra_use2:
; GISEL: ; %bb.0: ; %bb
; GISEL-NEXT: and x8, x1, #0x1
Expand All @@ -152,6 +152,6 @@ bb:
%tmp3 = shl i64 %in1, 1
%tmp4 = and i64 %in2, 1
%out = or i64 %tmp3, %tmp4
store i64 %tmp4, i64* %p
store i64 %tmp4, ptr %p
ret i64 %out
}
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/AArch64/GlobalISel/select-frameaddr.ll
View file
Original file line number Diff line number Diff line change
@@ -1,20 +1,20 @@
; RUN: llc -mtriple=arm64-apple-ios -global-isel -o - %s | FileCheck %s

define i8* @rt0(i32 %x) nounwind readnone {
define ptr @rt0(i32 %x) nounwind readnone {
entry:
; CHECK-LABEL: rt0:
; CHECK: mov x0, x29
%0 = tail call i8* @llvm.frameaddress(i32 0)
ret i8* %0
%0 = tail call ptr @llvm.frameaddress(i32 0)
ret ptr %0
}

define i8* @rt2() nounwind readnone {
define ptr @rt2() nounwind readnone {
entry:
; CHECK-LABEL: rt2:
; CHECK: ldr x[[reg:[0-9]+]], [x29]
; CHECK: ldr x0, [x[[reg]]]
%0 = tail call i8* @llvm.frameaddress(i32 2)
ret i8* %0
%0 = tail call ptr @llvm.frameaddress(i32 2)
ret ptr %0
}

declare i8* @llvm.frameaddress(i32) nounwind readnone
declare ptr @llvm.frameaddress(i32) nounwind readnone
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/AArch64/GlobalISel/select-returnaddr.ll
View file
Original file line number Diff line number Diff line change
@@ -1,15 +1,15 @@
; RUN: llc -mtriple=arm64-apple-ios -global-isel -o - %s | FileCheck %s

define i8* @rt0(i32 %x) nounwind readnone {
define ptr @rt0(i32 %x) nounwind readnone {
entry:
; CHECK-LABEL: rt0:
; CHECK: hint #7
; CHECK-NEXT: mov x0, x30
%0 = tail call i8* @llvm.returnaddress(i32 0)
ret i8* %0
%0 = tail call ptr @llvm.returnaddress(i32 0)
ret ptr %0
}

define i8* @rt0_call_clobber(i32 %x) nounwind readnone {
define ptr @rt0_call_clobber(i32 %x) nounwind readnone {
entry:
; CHECK-LABEL: rt0_call_clobber:
; CHECK: stp x20, x19, [sp, #-32]!
Expand All @@ -22,11 +22,11 @@ entry:
; CHECK-NOT: x0
; CHECK: ret
%ret = call i32 @foo()
%0 = tail call i8* @llvm.returnaddress(i32 0)
ret i8* %0
%0 = tail call ptr @llvm.returnaddress(i32 0)
ret ptr %0
}

define i8* @rt2() nounwind readnone {
define ptr @rt2() nounwind readnone {
entry:
; CHECK-LABEL: rt2:
; CHECK: ldr x[[reg:[0-9]+]], [x29]
Expand All @@ -36,10 +36,10 @@ entry:
; CHECK: mov x0, x30
; CHECK-NOT: x0
; CHECK: ret
%0 = tail call i8* @llvm.returnaddress(i32 2)
ret i8* %0
%0 = tail call ptr @llvm.returnaddress(i32 2)
ret ptr %0
}


declare i32 @foo()
declare i8* @llvm.returnaddress(i32) nounwind readnone
declare ptr @llvm.returnaddress(i32) nounwind readnone
212 changes: 97 additions & 115 deletions llvm/test/CodeGen/AArch64/GlobalISel/store-merging.ll
View file
Original file line number Diff line number Diff line change
@@ -1,36 +1,34 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-apple-ios -global-isel -global-isel-abort=1 - < %s | FileCheck %s

define void @test_simple_2xs8(i8 *%ptr) {
define void @test_simple_2xs8(ptr %ptr) {
; CHECK-LABEL: test_simple_2xs8:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov w8, #4
; CHECK-NEXT: mov w9, #5
; CHECK-NEXT: strb w8, [x0]
; CHECK-NEXT: strb w9, [x0, #1]
; CHECK-NEXT: ret
%addr1 = getelementptr i8, i8 *%ptr, i64 0
store i8 4, i8 *%addr1
%addr2 = getelementptr i8, i8 *%ptr, i64 1
store i8 5, i8 *%addr2
store i8 4, ptr %ptr
%addr2 = getelementptr i8, ptr %ptr, i64 1
store i8 5, ptr %addr2
ret void
}

define void @test_simple_2xs16(i16 *%ptr) {
define void @test_simple_2xs16(ptr %ptr) {
; CHECK-LABEL: test_simple_2xs16:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov w8, #4
; CHECK-NEXT: movk w8, #5, lsl #16
; CHECK-NEXT: str w8, [x0]
; CHECK-NEXT: ret
%addr1 = getelementptr i16, i16 *%ptr, i64 0
store i16 4, i16 *%addr1
%addr2 = getelementptr i16, i16 *%ptr, i64 1
store i16 5, i16 *%addr2
store i16 4, ptr %ptr
%addr2 = getelementptr i16, ptr %ptr, i64 1
store i16 5, ptr %addr2
ret void
}

define void @test_simple_4xs16(i16 *%ptr) {
define void @test_simple_4xs16(ptr %ptr) {
; CHECK-LABEL: test_simple_4xs16:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov x8, #4
Expand All @@ -39,47 +37,44 @@ define void @test_simple_4xs16(i16 *%ptr) {
; CHECK-NEXT: movk x8, #14, lsl #48
; CHECK-NEXT: str x8, [x0]
; CHECK-NEXT: ret
%addr1 = getelementptr i16, i16 *%ptr, i64 0
store i16 4, i16 *%addr1
%addr2 = getelementptr i16, i16 *%ptr, i64 1
store i16 5, i16 *%addr2
%addr3 = getelementptr i16, i16 *%ptr, i64 2
store i16 9, i16 *%addr3
%addr4 = getelementptr i16, i16 *%ptr, i64 3
store i16 14, i16 *%addr4
store i16 4, ptr %ptr
%addr2 = getelementptr i16, ptr %ptr, i64 1
store i16 5, ptr %addr2
%addr3 = getelementptr i16, ptr %ptr, i64 2
store i16 9, ptr %addr3
%addr4 = getelementptr i16, ptr %ptr, i64 3
store i16 14, ptr %addr4
ret void
}

define void @test_simple_2xs32(i32 *%ptr) {
define void @test_simple_2xs32(ptr %ptr) {
; CHECK-LABEL: test_simple_2xs32:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov x8, #4
; CHECK-NEXT: movk x8, #5, lsl #32
; CHECK-NEXT: str x8, [x0]
; CHECK-NEXT: ret
%addr1 = getelementptr i32, i32 *%ptr, i64 0
store i32 4, i32 *%addr1
%addr2 = getelementptr i32, i32 *%ptr, i64 1
store i32 5, i32 *%addr2
store i32 4, ptr %ptr
%addr2 = getelementptr i32, ptr %ptr, i64 1
store i32 5, ptr %addr2
ret void
}

define void @test_simple_2xs64_illegal(i64 *%ptr) {
define void @test_simple_2xs64_illegal(ptr %ptr) {
; CHECK-LABEL: test_simple_2xs64_illegal:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov w8, #4
; CHECK-NEXT: mov w9, #5
; CHECK-NEXT: stp x8, x9, [x0]
; CHECK-NEXT: ret
%addr1 = getelementptr i64, i64 *%ptr, i64 0
store i64 4, i64 *%addr1
%addr2 = getelementptr i64, i64 *%ptr, i64 1
store i64 5, i64 *%addr2
store i64 4, ptr %ptr
%addr2 = getelementptr i64, ptr %ptr, i64 1
store i64 5, ptr %addr2
ret void
}

; Don't merge vectors...yet.
define void @test_simple_vector(<2 x i16> *%ptr) {
define void @test_simple_vector(ptr %ptr) {
; CHECK-LABEL: test_simple_vector:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov w8, #4
Expand All @@ -91,14 +86,13 @@ define void @test_simple_vector(<2 x i16> *%ptr) {
; CHECK-NEXT: strh w10, [x0, #4]
; CHECK-NEXT: strh w11, [x0, #6]
; CHECK-NEXT: ret
%addr1 = getelementptr <2 x i16>, <2 x i16> *%ptr, i64 0
store <2 x i16> <i16 4, i16 7>, <2 x i16> *%addr1
%addr2 = getelementptr <2 x i16>, <2 x i16> *%ptr, i64 1
store <2 x i16> <i16 5, i16 8>, <2 x i16> *%addr2
store <2 x i16> <i16 4, i16 7>, ptr %ptr
%addr2 = getelementptr <2 x i16>, ptr %ptr, i64 1
store <2 x i16> <i16 5, i16 8>, ptr %addr2
ret void
}

define i32 @test_unknown_alias(i32 *%ptr, i32 *%aliasptr) {
define i32 @test_unknown_alias(ptr %ptr, ptr %aliasptr) {
; CHECK-LABEL: test_unknown_alias:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov w9, #4
Expand All @@ -108,15 +102,14 @@ define i32 @test_unknown_alias(i32 *%ptr, i32 *%aliasptr) {
; CHECK-NEXT: ldr w0, [x1]
; CHECK-NEXT: str w9, [x8, #4]
; CHECK-NEXT: ret
%addr1 = getelementptr i32, i32 *%ptr, i64 0
store i32 4, i32 *%addr1
%ld = load i32, i32 *%aliasptr
%addr2 = getelementptr i32, i32 *%ptr, i64 1
store i32 5, i32 *%addr2
store i32 4, ptr %ptr
%ld = load i32, ptr %aliasptr
%addr2 = getelementptr i32, ptr %ptr, i64 1
store i32 5, ptr %addr2
ret i32 %ld
}

define void @test_2x_2xs32(i32 *%ptr, i32 *%ptr2) {
define void @test_2x_2xs32(ptr %ptr, ptr %ptr2) {
; CHECK-LABEL: test_2x_2xs32:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov x10, #9
Expand All @@ -126,60 +119,55 @@ define void @test_2x_2xs32(i32 *%ptr, i32 *%ptr2) {
; CHECK-NEXT: stp w8, w9, [x0]
; CHECK-NEXT: str x10, [x1]
; CHECK-NEXT: ret
%addr1 = getelementptr i32, i32 *%ptr, i64 0
store i32 4, i32 *%addr1
%addr2 = getelementptr i32, i32 *%ptr, i64 1
store i32 5, i32 *%addr2
store i32 4, ptr %ptr
%addr2 = getelementptr i32, ptr %ptr, i64 1
store i32 5, ptr %addr2

%addr3 = getelementptr i32, i32 *%ptr2, i64 0
store i32 9, i32 *%addr3
%addr4 = getelementptr i32, i32 *%ptr2, i64 1
store i32 17, i32 *%addr4
store i32 9, ptr %ptr2
%addr4 = getelementptr i32, ptr %ptr2, i64 1
store i32 17, ptr %addr4
ret void
}

define void @test_simple_var_2xs8(i8 *%ptr, i8 %v1, i8 %v2) {
define void @test_simple_var_2xs8(ptr %ptr, i8 %v1, i8 %v2) {
; CHECK-LABEL: test_simple_var_2xs8:
; CHECK: ; %bb.0:
; CHECK-NEXT: strb w1, [x0]
; CHECK-NEXT: strb w2, [x0, #1]
; CHECK-NEXT: ret
%addr1 = getelementptr i8, i8 *%ptr, i64 0
store i8 %v1, i8 *%addr1
%addr2 = getelementptr i8, i8 *%ptr, i64 1
store i8 %v2, i8 *%addr2
store i8 %v1, ptr %ptr
%addr2 = getelementptr i8, ptr %ptr, i64 1
store i8 %v2, ptr %addr2
ret void
}

define void @test_simple_var_2xs16(i16 *%ptr, i16 %v1, i16 %v2) {
define void @test_simple_var_2xs16(ptr %ptr, i16 %v1, i16 %v2) {
; CHECK-LABEL: test_simple_var_2xs16:
; CHECK: ; %bb.0:
; CHECK-NEXT: strh w1, [x0]
; CHECK-NEXT: strh w2, [x0, #2]
; CHECK-NEXT: ret
%addr1 = getelementptr i16, i16 *%ptr, i64 0
store i16 %v1, i16 *%addr1
%addr2 = getelementptr i16, i16 *%ptr, i64 1
store i16 %v2, i16 *%addr2
store i16 %v1, ptr %ptr
%addr2 = getelementptr i16, ptr %ptr, i64 1
store i16 %v2, ptr %addr2
ret void
}

define void @test_simple_var_2xs32(i32 *%ptr, i32 %v1, i32 %v2) {
define void @test_simple_var_2xs32(ptr %ptr, i32 %v1, i32 %v2) {
; CHECK-LABEL: test_simple_var_2xs32:
; CHECK: ; %bb.0:
; CHECK-NEXT: stp w1, w2, [x0]
; CHECK-NEXT: ret
%addr1 = getelementptr i32, i32 *%ptr, i64 0
store i32 %v1, i32 *%addr1
%addr2 = getelementptr i32, i32 *%ptr, i64 1
store i32 %v2, i32 *%addr2
store i32 %v1, ptr %ptr
%addr2 = getelementptr i32, ptr %ptr, i64 1
store i32 %v2, ptr %addr2
ret void
}


; The store to ptr2 prevents merging into a single store.
; We can still merge the stores into addr1 and addr2.
define void @test_alias_4xs16(i16 *%ptr, i16 *%ptr2) {
define void @test_alias_4xs16(ptr %ptr, ptr %ptr2) {
; CHECK-LABEL: test_alias_4xs16:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov w8, #4
Expand All @@ -191,20 +179,19 @@ define void @test_alias_4xs16(i16 *%ptr, i16 *%ptr2) {
; CHECK-NEXT: strh wzr, [x1]
; CHECK-NEXT: strh w10, [x0, #6]
; CHECK-NEXT: ret
%addr1 = getelementptr i16, i16 *%ptr, i64 0
store i16 4, i16 *%addr1
%addr2 = getelementptr i16, i16 *%ptr, i64 1
store i16 5, i16 *%addr2
%addr3 = getelementptr i16, i16 *%ptr, i64 2
store i16 9, i16 *%addr3
store i16 0, i16 *%ptr2
%addr4 = getelementptr i16, i16 *%ptr, i64 3
store i16 14, i16 *%addr4
store i16 4, ptr %ptr
%addr2 = getelementptr i16, ptr %ptr, i64 1
store i16 5, ptr %addr2
%addr3 = getelementptr i16, ptr %ptr, i64 2
store i16 9, ptr %addr3
store i16 0, ptr %ptr2
%addr4 = getelementptr i16, ptr %ptr, i64 3
store i16 14, ptr %addr4
ret void
}

; Here store of 5 and 9 can be merged, others have aliasing barriers.
define void @test_alias2_4xs16(i16 *%ptr, i16 *%ptr2, i16* %ptr3) {
define void @test_alias2_4xs16(ptr %ptr, ptr %ptr2, ptr %ptr3) {
; CHECK-LABEL: test_alias2_4xs16:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov w8, #4
Expand All @@ -217,21 +204,20 @@ define void @test_alias2_4xs16(i16 *%ptr, i16 *%ptr2, i16* %ptr3) {
; CHECK-NEXT: strh wzr, [x1]
; CHECK-NEXT: strh w8, [x0, #6]
; CHECK-NEXT: ret
%addr1 = getelementptr i16, i16 *%ptr, i64 0
store i16 4, i16 *%addr1
%addr2 = getelementptr i16, i16 *%ptr, i64 1
store i16 0, i16 *%ptr3
store i16 5, i16 *%addr2
%addr3 = getelementptr i16, i16 *%ptr, i64 2
store i16 9, i16 *%addr3
store i16 0, i16 *%ptr2
%addr4 = getelementptr i16, i16 *%ptr, i64 3
store i16 14, i16 *%addr4
store i16 4, ptr %ptr
%addr2 = getelementptr i16, ptr %ptr, i64 1
store i16 0, ptr %ptr3
store i16 5, ptr %addr2
%addr3 = getelementptr i16, ptr %ptr, i64 2
store i16 9, ptr %addr3
store i16 0, ptr %ptr2
%addr4 = getelementptr i16, ptr %ptr, i64 3
store i16 14, ptr %addr4
ret void
}

; No merging can be done here.
define void @test_alias3_4xs16(i16 *%ptr, i16 *%ptr2, i16 *%ptr3, i16 *%ptr4) {
define void @test_alias3_4xs16(ptr %ptr, ptr %ptr2, ptr %ptr3, ptr %ptr4) {
; CHECK-LABEL: test_alias3_4xs16:
; CHECK: ; %bb.0:
; CHECK-NEXT: mov w8, #4
Expand All @@ -246,22 +232,21 @@ define void @test_alias3_4xs16(i16 *%ptr, i16 *%ptr2, i16 *%ptr3, i16 *%ptr4) {
; CHECK-NEXT: strh wzr, [x1]
; CHECK-NEXT: strh w9, [x0, #6]
; CHECK-NEXT: ret
%addr1 = getelementptr i16, i16 *%ptr, i64 0
store i16 4, i16 *%addr1
%addr2 = getelementptr i16, i16 *%ptr, i64 1
store i16 0, i16 *%ptr3
store i16 5, i16 *%addr2
store i16 0, i16 *%ptr4
%addr3 = getelementptr i16, i16 *%ptr, i64 2
store i16 9, i16 *%addr3
store i16 0, i16 *%ptr2
%addr4 = getelementptr i16, i16 *%ptr, i64 3
store i16 14, i16 *%addr4
store i16 4, ptr %ptr
%addr2 = getelementptr i16, ptr %ptr, i64 1
store i16 0, ptr %ptr3
store i16 5, ptr %addr2
store i16 0, ptr %ptr4
%addr3 = getelementptr i16, ptr %ptr, i64 2
store i16 9, ptr %addr3
store i16 0, ptr %ptr2
%addr4 = getelementptr i16, ptr %ptr, i64 3
store i16 14, ptr %addr4
ret void
}

; Can merge because the load is from a different alloca and can't alias.
define i32 @test_alias_allocas_2xs32(i32 *%ptr) {
define i32 @test_alias_allocas_2xs32(ptr %ptr) {
; CHECK-LABEL: test_alias_allocas_2xs32:
; CHECK: ; %bb.0:
; CHECK-NEXT: sub sp, sp, #32
Expand All @@ -274,31 +259,29 @@ define i32 @test_alias_allocas_2xs32(i32 *%ptr) {
; CHECK-NEXT: ret
%a1 = alloca [6 x i32]
%a2 = alloca i32, align 4
%addr1 = getelementptr [6 x i32], [6 x i32] *%a1, i64 0, i32 0
store i32 4, i32 *%addr1
%ld = load i32, i32 *%a2
%addr2 = getelementptr [6 x i32], [6 x i32] *%a1, i64 0, i32 1
store i32 5, i32 *%addr2
store i32 4, ptr %a1
%ld = load i32, ptr %a2
%addr2 = getelementptr [6 x i32], ptr %a1, i64 0, i32 1
store i32 5, ptr %addr2
ret i32 %ld
}

define void @test_volatile(i32 **%ptr) {
define void @test_volatile(ptr %ptr) {
; CHECK-LABEL: test_volatile:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: ldr x8, [x0]
; CHECK-NEXT: str wzr, [x8]
; CHECK-NEXT: str wzr, [x8, #4]
; CHECK-NEXT: ret
entry:
%0 = load i32*, i32** %ptr, align 8
store volatile i32 0, i32* %0, align 4;
%1 = bitcast i32** %ptr to i8**
%add.ptr.i.i38 = getelementptr inbounds i32, i32* %0, i64 1
store volatile i32 0, i32* %add.ptr.i.i38, align 4
%0 = load ptr, ptr %ptr, align 8
store volatile i32 0, ptr %0, align 4;
%add.ptr.i.i38 = getelementptr inbounds i32, ptr %0, i64 1
store volatile i32 0, ptr %add.ptr.i.i38, align 4
ret void
}

define void @test_atomic(i32 **%ptr) {
define void @test_atomic(ptr %ptr) {
; CHECK-LABEL: test_atomic:
; CHECK: ; %bb.0: ; %entry
; CHECK-NEXT: ldr x8, [x0]
Expand All @@ -307,10 +290,9 @@ define void @test_atomic(i32 **%ptr) {
; CHECK-NEXT: stlr wzr, [x9]
; CHECK-NEXT: ret
entry:
%0 = load i32*, i32** %ptr, align 8
store atomic i32 0, i32* %0 release, align 4;
%1 = bitcast i32** %ptr to i8**
%add.ptr.i.i38 = getelementptr inbounds i32, i32* %0, i64 1
store atomic i32 0, i32* %add.ptr.i.i38 release, align 4
%0 = load ptr, ptr %ptr, align 8
store atomic i32 0, ptr %0 release, align 4;
%add.ptr.i.i38 = getelementptr inbounds i32, ptr %0, i64 1
store atomic i32 0, ptr %add.ptr.i.i38 release, align 4
ret void
}
278 changes: 133 additions & 145 deletions llvm/test/CodeGen/AArch64/GlobalISel/swifterror.ll
View file

Large diffs are not rendered by default.

38 changes: 19 additions & 19 deletions llvm/test/CodeGen/AArch64/GlobalISel/swiftself.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,18 +4,18 @@
; CHECK-LABEL: swiftself_param:
; CHECK: mov x0, x20
; CHECK-NEXT: ret
define i8* @swiftself_param(i8* swiftself %addr0) {
ret i8 *%addr0
define ptr @swiftself_param(ptr swiftself %addr0) {
ret ptr %addr0
}

; Check that x20 is used to pass a swiftself argument.
; CHECK-LABEL: call_swiftself:
; CHECK: mov x20, x0
; CHECK: bl {{_?}}swiftself_param
; CHECK: ret
define i8 *@call_swiftself(i8* %arg) {
%res = call i8 *@swiftself_param(i8* swiftself %arg)
ret i8 *%res
define ptr @call_swiftself(ptr %arg) {
%res = call ptr @swiftself_param(ptr swiftself %arg)
ret ptr %res
}

; Demonstrate that we do not need any movs when calling multiple functions
Expand All @@ -26,9 +26,9 @@ define i8 *@call_swiftself(i8* %arg) {
; CHECK-NOT: mov{{.*}}x20
; CHECK-NEXT: bl {{_?}}swiftself_param
; CHECK: ret
define void @swiftself_passthrough(i8* swiftself %addr0) {
call i8 *@swiftself_param(i8* swiftself %addr0)
call i8 *@swiftself_param(i8* swiftself %addr0)
define void @swiftself_passthrough(ptr swiftself %addr0) {
call ptr @swiftself_param(ptr swiftself %addr0)
call ptr @swiftself_param(ptr swiftself %addr0)
ret void
}

Expand All @@ -38,26 +38,26 @@ define void @swiftself_passthrough(i8* swiftself %addr0) {
; CHECK: mov x20, x0
; CHECK: bl {{_?}}swiftself_param
; CHECK: ret
define i8* @swiftself_notail(i8* swiftself %addr0, i8* %addr1) nounwind {
%res = tail call i8* @swiftself_param(i8* swiftself %addr1)
ret i8* %res
define ptr @swiftself_notail(ptr swiftself %addr0, ptr %addr1) nounwind {
%res = tail call ptr @swiftself_param(ptr swiftself %addr1)
ret ptr %res
}

; We cannot pretend that 'x0' is alive across the thisreturn_attribute call as
; we normally would. We marked the first parameter with swiftself which means it
; will no longer be passed in x0.
declare swiftcc i8* @thisreturn_attribute(i8* returned swiftself)
declare swiftcc ptr @thisreturn_attribute(ptr returned swiftself)
; CHECK-LABEL: swiftself_nothisreturn:
; CHECK-DAG: ldr x20, [x20]
; CHECK-DAG: mov [[CSREG:x[1-9].*]], x8
; CHECK: bl {{_?}}thisreturn_attribute
; CHECK: str x0, [[[CSREG]]
; CHECK: ret
define hidden swiftcc void @swiftself_nothisreturn(i8** noalias nocapture sret(i8*), i8** noalias nocapture readonly swiftself) {
define hidden swiftcc void @swiftself_nothisreturn(ptr noalias nocapture sret(ptr), ptr noalias nocapture readonly swiftself) {
entry:
%2 = load i8*, i8** %1, align 8
%3 = tail call swiftcc i8* @thisreturn_attribute(i8* swiftself %2)
store i8* %3, i8** %0, align 8
%2 = load ptr, ptr %1, align 8
%3 = tail call swiftcc ptr @thisreturn_attribute(ptr swiftself %2)
store ptr %3, ptr %0, align 8
ret void
}

Expand All @@ -67,7 +67,7 @@ entry:
; CHECK: mov x20, x0
; CHECK: bl {{_?}}swiftself_param
; CHECK: ret
define i8 *@swiftself_not_on_call_params(i8* %arg) {
%res = call i8 *@swiftself_param(i8* %arg)
ret i8 *%res
define ptr @swiftself_not_on_call_params(ptr %arg) {
%res = call ptr @swiftself_param(ptr %arg)
ret ptr %res
}
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/GlobalISel/translate-constant-dag.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

%dag = type { { { i8, { i8 } }, { { i8, { i8 } }, { i8 } } }, { { i8, { i8 } }, { i8 } } }

define void @test_const(%dag* %dst) {
define void @test_const(ptr %dst) {
; CHECK-LABEL: name: test_const
; CHECK: bb.1.entry:
; CHECK: liveins: $x0
Expand Down Expand Up @@ -63,7 +63,7 @@ entry:
},
0,
1
store %dag %updated, %dag* %dst
store %dag %updated, ptr %dst
; 10, 20, 10, 20, 50, 10, 20, 20 sequence is expected

store
Expand Down Expand Up @@ -91,7 +91,7 @@ entry:
{ i8 } { i8 20 }
}
},
%dag* %dst
ptr %dst
; 10, 20, 10, 20, 20, 10, 20, 20 sequence is expected
ret void
}
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/AArch64/GlobalISel/translate-gep.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

%type = type [4 x {i8, i32}]

define i8* @translate_element_size1(i64 %arg) {
define ptr @translate_element_size1(i64 %arg) {
; CHECK-LABEL: name: translate_element_size1
; CHECK: bb.1 (%ir-block.0):
; CHECK-NEXT: liveins: $x0
Expand All @@ -14,11 +14,11 @@ define i8* @translate_element_size1(i64 %arg) {
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%tmp = getelementptr i8, i8* null, i64 %arg
ret i8* %tmp
%tmp = getelementptr i8, ptr null, i64 %arg
ret ptr %tmp
}

define %type* @first_offset_const(%type* %addr) {
define ptr @first_offset_const(ptr %addr) {

; CHECK-LABEL: name: first_offset_const
; CHECK: bb.1 (%ir-block.0):
Expand All @@ -29,11 +29,11 @@ define %type* @first_offset_const(%type* %addr) {
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = getelementptr %type, %type* %addr, i32 1
ret %type* %res
%res = getelementptr %type, ptr %addr, i32 1
ret ptr %res
}

define %type* @first_offset_trivial(%type* %addr) {
define ptr @first_offset_trivial(ptr %addr) {

; CHECK-LABEL: name: first_offset_trivial
; CHECK: bb.1 (%ir-block.0):
Expand All @@ -43,11 +43,11 @@ define %type* @first_offset_trivial(%type* %addr) {
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY [[COPY]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = getelementptr %type, %type* %addr, i32 0
ret %type* %res
%res = getelementptr %type, ptr %addr, i32 0
ret ptr %res
}

define %type* @first_offset_variable(%type* %addr, i64 %idx) {
define ptr @first_offset_variable(ptr %addr, i64 %idx) {

; CHECK-LABEL: name: first_offset_variable
; CHECK: bb.1 (%ir-block.0):
Expand All @@ -61,11 +61,11 @@ define %type* @first_offset_variable(%type* %addr, i64 %idx) {
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = getelementptr %type, %type* %addr, i64 %idx
ret %type* %res
%res = getelementptr %type, ptr %addr, i64 %idx
ret ptr %res
}

define %type* @first_offset_ext(%type* %addr, i32 %idx) {
define ptr @first_offset_ext(ptr %addr, i32 %idx) {

; CHECK-LABEL: name: first_offset_ext
; CHECK: bb.1 (%ir-block.0):
Expand All @@ -80,12 +80,12 @@ define %type* @first_offset_ext(%type* %addr, i32 %idx) {
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = getelementptr %type, %type* %addr, i32 %idx
ret %type* %res
%res = getelementptr %type, ptr %addr, i32 %idx
ret ptr %res
}

%type1 = type [4 x [4 x i32]]
define i32* @const_then_var(%type1* %addr, i64 %idx) {
define ptr @const_then_var(ptr %addr, i64 %idx) {

; CHECK-LABEL: name: const_then_var
; CHECK: bb.1 (%ir-block.0):
Expand All @@ -101,11 +101,11 @@ define i32* @const_then_var(%type1* %addr, i64 %idx) {
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(p0) = COPY [[PTR_ADD1]](p0)
; CHECK-NEXT: $x0 = COPY [[COPY2]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = getelementptr %type1, %type1* %addr, i32 4, i32 1, i64 %idx
ret i32* %res
%res = getelementptr %type1, ptr %addr, i32 4, i32 1, i64 %idx
ret ptr %res
}

define i32* @var_then_const(%type1* %addr, i64 %idx) {
define ptr @var_then_const(ptr %addr, i64 %idx) {

; CHECK-LABEL: name: var_then_const
; CHECK: bb.1 (%ir-block.0):
Expand All @@ -120,13 +120,13 @@ define i32* @var_then_const(%type1* %addr, i64 %idx) {
; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:_(p0) = G_PTR_ADD [[PTR_ADD]], [[C1]](s64)
; CHECK-NEXT: $x0 = COPY [[PTR_ADD1]](p0)
; CHECK-NEXT: RET_ReallyLR implicit $x0
%res = getelementptr %type1, %type1* %addr, i64 %idx, i32 2, i32 2
ret i32* %res
%res = getelementptr %type1, ptr %addr, i64 %idx, i32 2, i32 2
ret ptr %res
}

@arr = external global [8 x i32]

define <2 x i32*> @vec_gep_scalar_base(<2 x i64> %offs) {
define <2 x ptr> @vec_gep_scalar_base(<2 x i64> %offs) {
; CHECK-LABEL: name: vec_gep_scalar_base
; CHECK: bb.1.entry:
; CHECK-NEXT: liveins: $q0
Expand All @@ -142,6 +142,6 @@ define <2 x i32*> @vec_gep_scalar_base(<2 x i64> %offs) {
; CHECK-NEXT: $q0 = COPY [[COPY1]](<2 x p0>)
; CHECK-NEXT: RET_ReallyLR implicit $q0
entry:
%0 = getelementptr inbounds [8 x i32], [8 x i32]* @arr, i64 0, <2 x i64> %offs
ret <2 x i32*> %0
%0 = getelementptr inbounds [8 x i32], ptr @arr, i64 0, <2 x i64> %offs
ret <2 x ptr> %0
}
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/AArch64/GlobalISel/translate-ret.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
; RUN: llc -mtriple=arm64-apple-ios %s -o - -global-isel -global-isel-abort=1 -stop-after=irtranslator | FileCheck %s

define i128 @func_i128(i128* %ptr) {
define i128 @func_i128(ptr %ptr) {

; CHECK-LABEL: name: func_i128
; CHECK: bb.1 (%ir-block.0):
Expand All @@ -13,11 +13,11 @@ define i128 @func_i128(i128* %ptr) {
; CHECK-NEXT: $x0 = COPY [[UV]](s64)
; CHECK-NEXT: $x1 = COPY [[UV1]](s64)
; CHECK-NEXT: RET_ReallyLR implicit $x0, implicit $x1
%val = load i128, i128* %ptr
%val = load i128, ptr %ptr
ret i128 %val
}

define <8 x float> @func_v8f32(<8 x float>* %ptr) {
define <8 x float> @func_v8f32(ptr %ptr) {

; CHECK-LABEL: name: func_v8f32
; CHECK: bb.1 (%ir-block.0):
Expand All @@ -29,12 +29,12 @@ define <8 x float> @func_v8f32(<8 x float>* %ptr) {
; CHECK-NEXT: $q0 = COPY [[UV]](<4 x s32>)
; CHECK-NEXT: $q1 = COPY [[UV1]](<4 x s32>)
; CHECK-NEXT: RET_ReallyLR implicit $q0, implicit $q1
%val = load <8 x float>, <8 x float>* %ptr
%val = load <8 x float>, ptr %ptr
ret <8 x float> %val
}

; A bit weird, but s0-s5 is what SDAG does too.
define <6 x float> @func_v6f32(<6 x float>* %ptr) {
define <6 x float> @func_v6f32(ptr %ptr) {

; CHECK-LABEL: name: func_v6f32
; CHECK: bb.1 (%ir-block.0):
Expand All @@ -50,7 +50,7 @@ define <6 x float> @func_v6f32(<6 x float>* %ptr) {
; CHECK-NEXT: $s4 = COPY [[UV4]](s32)
; CHECK-NEXT: $s5 = COPY [[UV5]](s32)
; CHECK-NEXT: RET_ReallyLR implicit $s0, implicit $s1, implicit $s2, implicit $s3, implicit $s4, implicit $s5
%val = load <6 x float>, <6 x float>* %ptr
%val = load <6 x float>, ptr %ptr
ret <6 x float> %val
}

Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/AArch64/GlobalISel/unknown-intrinsic.ll
View file
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
; RUN: llc -O0 -mtriple=arm64 < %s

declare i8* @llvm.launder.invariant.group(i8*)
declare ptr @llvm.launder.invariant.group(ptr)

define i8* @barrier(i8* %p) {
define ptr @barrier(ptr %p) {
; CHECK: bl llvm.launder.invariant.group
%q = call i8* @llvm.launder.invariant.group(i8* %p)
ret i8* %q
%q = call ptr @llvm.launder.invariant.group(ptr %p)
ret ptr %q
}

10 changes: 5 additions & 5 deletions llvm/test/CodeGen/AArch64/GlobalISel/unwind-inline-asm.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ entry:
unreachable
}

define dso_local void @test() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) {
define dso_local void @test() personality ptr @__gxx_personality_v0 {
entry:

; CHECK-LABEL: test:
Expand All @@ -25,17 +25,17 @@ invoke.cont:
ret void

lpad:
%0 = landingpad { i8*, i32 }
%0 = landingpad { ptr, i32 }
cleanup
; CHECK: bl printf
call void (i8*, ...) @printf(i8* getelementptr inbounds ([7 x i8], [7 x i8]* @.str.2, i64 0, i64 0))
resume { i8*, i32 } %0
call void (ptr, ...) @printf(ptr @.str.2)
resume { ptr, i32 } %0

}

declare dso_local i32 @__gxx_personality_v0(...)

declare dso_local void @printf(i8*, ...)
declare dso_local void @printf(ptr, ...)

; Exception table generation around the inline assembly

Expand Down
130 changes: 55 additions & 75 deletions llvm/test/CodeGen/AArch64/GlobalISel/v8.4-atomic-128.ll
View file
Original file line number Diff line number Diff line change
@@ -1,212 +1,192 @@
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+v8.4a %s -o - -global-isel=1 -global-isel-abort=1 | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+lse2 %s -o - -global-isel=1 -global-isel-abort=1 | FileCheck %s

define void @test_atomic_load(i128* %addr) {
define void @test_atomic_load(ptr %addr) {
; CHECK-LABEL: test_atomic_load:

; CHECK: ldp [[LO:x[0-9]+]], [[HI:x[0-9]+]], [x0]
; CHECK: mov v[[Q:[0-9]+]].d[0], [[LO]]
; CHECK: mov v[[Q]].d[1], [[HI]]
; CHECK: str q[[Q]], [x0]
%res.0 = load atomic i128, i128* %addr monotonic, align 16
store i128 %res.0, i128* %addr
%res.0 = load atomic i128, ptr %addr monotonic, align 16
store i128 %res.0, ptr %addr

; CHECK: ldp [[LO:x[0-9]+]], [[HI:x[0-9]+]], [x0]
; CHECK: mov v[[Q:[0-9]+]].d[0], [[LO]]
; CHECK: mov v[[Q]].d[1], [[HI]]
; CHECK: str q[[Q]], [x0]
%res.1 = load atomic i128, i128* %addr unordered, align 16
store i128 %res.1, i128* %addr
%res.1 = load atomic i128, ptr %addr unordered, align 16
store i128 %res.1, ptr %addr

; CHECK: ldp [[LO:x[0-9]+]], [[HI:x[0-9]+]], [x0]
; CHECK: dmb ish
; CHECK: mov v[[Q:[0-9]+]].d[0], [[LO]]
; CHECK: mov v[[Q]].d[1], [[HI]]
; CHECK: str q[[Q]], [x0]
%res.2 = load atomic i128, i128* %addr acquire, align 16
store i128 %res.2, i128* %addr
%res.2 = load atomic i128, ptr %addr acquire, align 16
store i128 %res.2, ptr %addr

; CHECK: ldp [[LO:x[0-9]+]], [[HI:x[0-9]+]], [x0]
; CHECK: dmb ish
; CHECK: mov v[[Q:[0-9]+]].d[0], [[LO]]
; CHECK: mov v[[Q]].d[1], [[HI]]
; CHECK: str q[[Q]], [x0]
%res.3 = load atomic i128, i128* %addr seq_cst, align 16
store i128 %res.3, i128* %addr
%res.3 = load atomic i128, ptr %addr seq_cst, align 16
store i128 %res.3, ptr %addr

%addr8 = bitcast i128* %addr to i8*

; CHECK: ldp [[LO:x[0-9]+]], [[HI:x[0-9]+]], [x0, #8]
; CHECK: mov v[[Q:[0-9]+]].d[0], [[LO]]
; CHECK: mov v[[Q]].d[1], [[HI]]
; CHECK: str q[[Q]], [x0]
%addr8.1 = getelementptr i8, i8* %addr8, i32 8
%addr128.1 = bitcast i8* %addr8.1 to i128*
%res.5 = load atomic i128, i128* %addr128.1 monotonic, align 16
store i128 %res.5, i128* %addr
%addr8.1 = getelementptr i8, ptr %addr, i32 8
%res.5 = load atomic i128, ptr %addr8.1 monotonic, align 16
store i128 %res.5, ptr %addr

; CHECK: ldp [[LO:x[0-9]+]], [[HI:x[0-9]+]], [x0, #504]
; CHECK: mov v[[Q:[0-9]+]].d[0], [[LO]]
; CHECK: mov v[[Q]].d[1], [[HI]]
; CHECK: str q[[Q]], [x0]
%addr8.2 = getelementptr i8, i8* %addr8, i32 504
%addr128.2 = bitcast i8* %addr8.2 to i128*
%res.6 = load atomic i128, i128* %addr128.2 monotonic, align 16
store i128 %res.6, i128* %addr
%addr8.2 = getelementptr i8, ptr %addr, i32 504
%res.6 = load atomic i128, ptr %addr8.2 monotonic, align 16
store i128 %res.6, ptr %addr

; CHECK: ldp [[LO:x[0-9]+]], [[HI:x[0-9]+]], [x0, #-512]
; CHECK: mov v[[Q:[0-9]+]].d[0], [[LO]]
; CHECK: mov v[[Q]].d[1], [[HI]]
; CHECK: str q[[Q]], [x0]
%addr8.3 = getelementptr i8, i8* %addr8, i32 -512
%addr128.3 = bitcast i8* %addr8.3 to i128*
%res.7 = load atomic i128, i128* %addr128.3 monotonic, align 16
store i128 %res.7, i128* %addr
%addr8.3 = getelementptr i8, ptr %addr, i32 -512
%res.7 = load atomic i128, ptr %addr8.3 monotonic, align 16
store i128 %res.7, ptr %addr

ret void
}

define void @test_libcall_load(i128* %addr) {
define void @test_libcall_load(ptr %addr) {
; CHECK-LABEL: test_libcall_load:
; CHECK: bl __atomic_load
%res.8 = load atomic i128, i128* %addr unordered, align 8
store i128 %res.8, i128* %addr
%res.8 = load atomic i128, ptr %addr unordered, align 8
store i128 %res.8, ptr %addr

ret void
}

define void @test_nonfolded_load1(i128* %addr) {
define void @test_nonfolded_load1(ptr %addr) {
; CHECK-LABEL: test_nonfolded_load1:
%addr8 = bitcast i128* %addr to i8*

; CHECK: add x[[ADDR:[0-9]+]], x0, #4
; CHECK: ldp [[LO:x[0-9]+]], [[HI:x[0-9]+]], [x[[ADDR]]]
; CHECK: mov v[[Q:[0-9]+]].d[0], [[LO]]
; CHECK: mov v[[Q]].d[1], [[HI]]
; CHECK: str q[[Q]], [x0]
%addr8.1 = getelementptr i8, i8* %addr8, i32 4
%addr128.1 = bitcast i8* %addr8.1 to i128*
%res.1 = load atomic i128, i128* %addr128.1 monotonic, align 16
store i128 %res.1, i128* %addr
%addr8.1 = getelementptr i8, ptr %addr, i32 4
%res.1 = load atomic i128, ptr %addr8.1 monotonic, align 16
store i128 %res.1, ptr %addr

ret void
}

define void @test_nonfolded_load2(i128* %addr) {
define void @test_nonfolded_load2(ptr %addr) {
; CHECK-LABEL: test_nonfolded_load2:
%addr8 = bitcast i128* %addr to i8*

; CHECK: add x[[ADDR:[0-9]+]], x0, #512
; CHECK: ldp [[LO:x[0-9]+]], [[HI:x[0-9]+]], [x[[ADDR]]]
; CHECK: mov v[[Q:[0-9]+]].d[0], [[LO]]
; CHECK: mov v[[Q]].d[1], [[HI]]
; CHECK: str q[[Q]], [x0]
%addr8.1 = getelementptr i8, i8* %addr8, i32 512
%addr128.1 = bitcast i8* %addr8.1 to i128*
%res.1 = load atomic i128, i128* %addr128.1 monotonic, align 16
store i128 %res.1, i128* %addr
%addr8.1 = getelementptr i8, ptr %addr, i32 512
%res.1 = load atomic i128, ptr %addr8.1 monotonic, align 16
store i128 %res.1, ptr %addr

ret void
}

define void @test_nonfolded_load3(i128* %addr) {
define void @test_nonfolded_load3(ptr %addr) {
; CHECK-LABEL: test_nonfolded_load3:
%addr8 = bitcast i128* %addr to i8*

; CHECK: sub x[[ADDR:[0-9]+]], x0, #520
; CHECK: ldp [[LO:x[0-9]+]], [[HI:x[0-9]+]], [x[[ADDR]]]
; CHECK: mov v[[Q:[0-9]+]].d[0], [[LO]]
; CHECK: mov v[[Q]].d[1], [[HI]]
; CHECK: str q[[Q]], [x0]
%addr8.1 = getelementptr i8, i8* %addr8, i32 -520
%addr128.1 = bitcast i8* %addr8.1 to i128*
%res.1 = load atomic i128, i128* %addr128.1 monotonic, align 16
store i128 %res.1, i128* %addr
%addr8.1 = getelementptr i8, ptr %addr, i32 -520
%res.1 = load atomic i128, ptr %addr8.1 monotonic, align 16
store i128 %res.1, ptr %addr

ret void
}

define void @test_atomic_store(i128* %addr, i128 %val) {
define void @test_atomic_store(ptr %addr, i128 %val) {
; CHECK-LABEL: test_atomic_store:

; CHECK: stp x2, x3, [x0]
store atomic i128 %val, i128* %addr monotonic, align 16
store atomic i128 %val, ptr %addr monotonic, align 16

; CHECK: stp x2, x3, [x0]
store atomic i128 %val, i128* %addr unordered, align 16
store atomic i128 %val, ptr %addr unordered, align 16

; CHECK: dmb ish
; CHECK: stp x2, x3, [x0]
store atomic i128 %val, i128* %addr release, align 16
store atomic i128 %val, ptr %addr release, align 16

; CHECK: dmb ish
; CHECK: stp x2, x3, [x0]
; CHECK: dmb ish
store atomic i128 %val, i128* %addr seq_cst, align 16
store atomic i128 %val, ptr %addr seq_cst, align 16

%addr8 = bitcast i128* %addr to i8*

; CHECK: stp x2, x3, [x0, #8]
%addr8.1 = getelementptr i8, i8* %addr8, i32 8
%addr128.1 = bitcast i8* %addr8.1 to i128*
store atomic i128 %val, i128* %addr128.1 monotonic, align 16
%addr8.1 = getelementptr i8, ptr %addr, i32 8
store atomic i128 %val, ptr %addr8.1 monotonic, align 16

; CHECK: stp x2, x3, [x0, #504]
%addr8.2 = getelementptr i8, i8* %addr8, i32 504
%addr128.2 = bitcast i8* %addr8.2 to i128*
store atomic i128 %val, i128* %addr128.2 monotonic, align 16
%addr8.2 = getelementptr i8, ptr %addr, i32 504
store atomic i128 %val, ptr %addr8.2 monotonic, align 16

; CHECK: stp x2, x3, [x0, #-512]
%addr8.3 = getelementptr i8, i8* %addr8, i32 -512
%addr128.3 = bitcast i8* %addr8.3 to i128*
store atomic i128 %val, i128* %addr128.3 monotonic, align 16
%addr8.3 = getelementptr i8, ptr %addr, i32 -512
store atomic i128 %val, ptr %addr8.3 monotonic, align 16

ret void
}

define void @test_libcall_store(i128* %addr, i128 %val) {
define void @test_libcall_store(ptr %addr, i128 %val) {
; CHECK-LABEL: test_libcall_store:
; CHECK: bl __atomic_store
store atomic i128 %val, i128* %addr unordered, align 8
store atomic i128 %val, ptr %addr unordered, align 8

ret void
}

define void @test_nonfolded_store1(i128* %addr, i128 %val) {
define void @test_nonfolded_store1(ptr %addr, i128 %val) {
; CHECK-LABEL: test_nonfolded_store1:
%addr8 = bitcast i128* %addr to i8*

; CHECK: add x[[ADDR:[0-9]+]], x0, #4
; CHECK: stp x2, x3, [x[[ADDR]]]
%addr8.1 = getelementptr i8, i8* %addr8, i32 4
%addr128.1 = bitcast i8* %addr8.1 to i128*
store atomic i128 %val, i128* %addr128.1 monotonic, align 16
%addr8.1 = getelementptr i8, ptr %addr, i32 4
store atomic i128 %val, ptr %addr8.1 monotonic, align 16

ret void
}

define void @test_nonfolded_store2(i128* %addr, i128 %val) {
define void @test_nonfolded_store2(ptr %addr, i128 %val) {
; CHECK-LABEL: test_nonfolded_store2:
%addr8 = bitcast i128* %addr to i8*

; CHECK: add x[[ADDR:[0-9]+]], x0, #512
; CHECK: stp x2, x3, [x[[ADDR]]]
%addr8.1 = getelementptr i8, i8* %addr8, i32 512
%addr128.1 = bitcast i8* %addr8.1 to i128*
store atomic i128 %val, i128* %addr128.1 monotonic, align 16
%addr8.1 = getelementptr i8, ptr %addr, i32 512
store atomic i128 %val, ptr %addr8.1 monotonic, align 16

ret void
}

define void @test_nonfolded_store3(i128* %addr, i128 %val) {
define void @test_nonfolded_store3(ptr %addr, i128 %val) {
; CHECK-LABEL: test_nonfolded_store3:
%addr8 = bitcast i128* %addr to i8*

; CHECK: sub x[[ADDR:[0-9]+]], x0, #520
; CHECK: stp x2, x3, [x[[ADDR]]]
%addr8.1 = getelementptr i8, i8* %addr8, i32 -520
%addr128.1 = bitcast i8* %addr8.1 to i128*
store atomic i128 %val, i128* %addr128.1 monotonic, align 16
%addr8.1 = getelementptr i8, ptr %addr, i32 -520
store atomic i128 %val, ptr %addr8.1 monotonic, align 16

ret void
}
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/GlobalISel/varargs-ios-translator.ll
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
; RUN: llc -mtriple=aarch64-apple-ios -stop-after=instruction-select -global-isel -verify-machineinstrs %s -o - | FileCheck %s

define void @test_varargs_sentinel(i8* %list, i64, i64, i64, i64, i64, i64, i64,
define void @test_varargs_sentinel(ptr %list, i64, i64, i64, i64, i64, i64, i64,
i32, ...) {
; CHECK-LABEL: name: test_varargs_sentinel
; CHECK: fixedStack:
Expand All @@ -9,8 +9,8 @@ define void @test_varargs_sentinel(i8* %list, i64, i64, i64, i64, i64, i64, i64,
; CHECK: [[LIST:%[0-9]+]]:gpr64sp = COPY $x0
; CHECK: [[VARARGS_AREA:%[0-9]+]]:gpr64common = ADDXri %fixed-stack.[[VARARGS_SLOT]], 0, 0
; CHECK: STRXui [[VARARGS_AREA]], [[LIST]], 0 :: (store (s64) into %ir.list, align 1)
call void @llvm.va_start(i8* %list)
call void @llvm.va_start(ptr %list)
ret void
}

declare void @llvm.va_start(i8*)
declare void @llvm.va_start(ptr)
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/AArch64/GlobalISel/vastart.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,12 +2,12 @@
; RUN: llc -O0 -stop-after=irtranslator -global-isel -verify-machineinstrs %s -o - -mtriple=aarch64-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LINUX %s


declare void @llvm.va_start(i8*)
define void @test_va_start(i8* %list) {
declare void @llvm.va_start(ptr)
define void @test_va_start(ptr %list) {
; CHECK-LABEL: name: test_va_start
; CHECK: [[LIST:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-IOS: G_VASTART [[LIST]](p0) :: (store (s64) into %ir.list, align 1)
; CHECK-LINUX: G_VASTART [[LIST]](p0) :: (store (s256) into %ir.list, align 1)
call void @llvm.va_start(i8* %list)
call void @llvm.va_start(ptr %list)
ret void
}