4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/lsr-sort.ll
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Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s

@X = common global i16 0 ; <i16*> [#uses=1]
@X = common dso_local global i16 0 ; <i16*> [#uses=1]

define i32 @foo(i32 %N) nounwind {
define dso_local i32 @foo(i32 %N) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/mempcpy.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -13,14 +13,14 @@

; Also see mempcpy-32.ll

@G = common global i8* null, align 8
@G = common dso_local global i8* null, align 8

; CHECK-LABEL: RET_MEMPCPY:
; CHECK: movq [[REG:%r[a-z0-9]+]], {{.*}}G
; CHECK: callq {{.*}}memcpy
; CHECK: movq [[REG]], %rax
;
define i8* @RET_MEMPCPY(i8* %DST, i8* %SRC, i64 %N) {
define dso_local i8* @RET_MEMPCPY(i8* %DST, i8* %SRC, i64 %N) {
%add.ptr = getelementptr inbounds i8, i8* %DST, i64 %N
store i8* %add.ptr, i8** @G, align 8
%call = tail call i8* @mempcpy(i8* %DST, i8* %SRC, i64 %N)
Expand Down
74 changes: 37 additions & 37 deletions llvm/test/CodeGen/X86/min-legal-vector-width.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@

; This file primarily contains tests for specific places in X86ISelLowering.cpp that needed be made aware of the legalizer not allowing 512-bit vectors due to prefer-256-bit even though AVX512 is enabled.

define void @add256(<16 x i32>* %a, <16 x i32>* %b, <16 x i32>* %c) "min-legal-vector-width"="256" {
define dso_local void @add256(<16 x i32>* %a, <16 x i32>* %b, <16 x i32>* %c) "min-legal-vector-width"="256" {
; CHECK-LABEL: add256:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rdi), %ymm0
Expand All @@ -30,7 +30,7 @@ define void @add256(<16 x i32>* %a, <16 x i32>* %b, <16 x i32>* %c) "min-legal-v
ret void
}

define void @add512(<16 x i32>* %a, <16 x i32>* %b, <16 x i32>* %c) "min-legal-vector-width"="512" {
define dso_local void @add512(<16 x i32>* %a, <16 x i32>* %b, <16 x i32>* %c) "min-legal-vector-width"="512" {
; CHECK-LABEL: add512:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa64 (%rdi), %zmm0
Expand All @@ -45,7 +45,7 @@ define void @add512(<16 x i32>* %a, <16 x i32>* %b, <16 x i32>* %c) "min-legal-v
ret void
}

define void @avg_v64i8_256(<64 x i8>* %a, <64 x i8>* %b) "min-legal-vector-width"="256" {
define dso_local void @avg_v64i8_256(<64 x i8>* %a, <64 x i8>* %b) "min-legal-vector-width"="256" {
; CHECK-LABEL: avg_v64i8_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rsi), %ymm0
Expand All @@ -69,7 +69,7 @@ define void @avg_v64i8_256(<64 x i8>* %a, <64 x i8>* %b) "min-legal-vector-width
}


define void @avg_v64i8_512(<64 x i8>* %a, <64 x i8>* %b) "min-legal-vector-width"="512" {
define dso_local void @avg_v64i8_512(<64 x i8>* %a, <64 x i8>* %b) "min-legal-vector-width"="512" {
; CHECK-LABEL: avg_v64i8_512:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa64 (%rsi), %zmm0
Expand All @@ -89,7 +89,7 @@ define void @avg_v64i8_512(<64 x i8>* %a, <64 x i8>* %b) "min-legal-vector-width
ret void
}

define void @pmaddwd_32_256(<32 x i16>* %APtr, <32 x i16>* %BPtr, <16 x i32>* %CPtr) "min-legal-vector-width"="256" {
define dso_local void @pmaddwd_32_256(<32 x i16>* %APtr, <32 x i16>* %BPtr, <16 x i32>* %CPtr) "min-legal-vector-width"="256" {
; CHECK-LABEL: pmaddwd_32_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rdi), %ymm0
Expand All @@ -112,7 +112,7 @@ define void @pmaddwd_32_256(<32 x i16>* %APtr, <32 x i16>* %BPtr, <16 x i32>* %C
ret void
}

define void @pmaddwd_32_512(<32 x i16>* %APtr, <32 x i16>* %BPtr, <16 x i32>* %CPtr) "min-legal-vector-width"="512" {
define dso_local void @pmaddwd_32_512(<32 x i16>* %APtr, <32 x i16>* %BPtr, <16 x i32>* %CPtr) "min-legal-vector-width"="512" {
; CHECK-LABEL: pmaddwd_32_512:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa64 (%rdi), %zmm0
Expand All @@ -132,7 +132,7 @@ define void @pmaddwd_32_512(<32 x i16>* %APtr, <32 x i16>* %BPtr, <16 x i32>* %C
ret void
}

define void @psubus_64i8_max_256(<64 x i8>* %xptr, <64 x i8>* %yptr, <64 x i8>* %zptr) "min-legal-vector-width"="256" {
define dso_local void @psubus_64i8_max_256(<64 x i8>* %xptr, <64 x i8>* %yptr, <64 x i8>* %zptr) "min-legal-vector-width"="256" {
; CHECK-LABEL: psubus_64i8_max_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rdi), %ymm0
Expand All @@ -152,7 +152,7 @@ define void @psubus_64i8_max_256(<64 x i8>* %xptr, <64 x i8>* %yptr, <64 x i8>*
ret void
}

define void @psubus_64i8_max_512(<64 x i8>* %xptr, <64 x i8>* %yptr, <64 x i8>* %zptr) "min-legal-vector-width"="512" {
define dso_local void @psubus_64i8_max_512(<64 x i8>* %xptr, <64 x i8>* %yptr, <64 x i8>* %zptr) "min-legal-vector-width"="512" {
; CHECK-LABEL: psubus_64i8_max_512:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa64 (%rdi), %zmm0
Expand All @@ -169,7 +169,7 @@ define void @psubus_64i8_max_512(<64 x i8>* %xptr, <64 x i8>* %yptr, <64 x i8>*
ret void
}

define i32 @_Z9test_charPcS_i_256(i8* nocapture readonly, i8* nocapture readonly, i32) "min-legal-vector-width"="256" {
define dso_local i32 @_Z9test_charPcS_i_256(i8* nocapture readonly, i8* nocapture readonly, i32) "min-legal-vector-width"="256" {
; CHECK-LABEL: _Z9test_charPcS_i_256:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %edx, %eax
Expand Down Expand Up @@ -240,7 +240,7 @@ middle.block:
ret i32 %13
}

define i32 @_Z9test_charPcS_i_512(i8* nocapture readonly, i8* nocapture readonly, i32) "min-legal-vector-width"="512" {
define dso_local i32 @_Z9test_charPcS_i_512(i8* nocapture readonly, i8* nocapture readonly, i32) "min-legal-vector-width"="512" {
; CHECK-LABEL: _Z9test_charPcS_i_512:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl %edx, %eax
Expand Down Expand Up @@ -306,10 +306,10 @@ middle.block:
ret i32 %13
}

@a = global [1024 x i8] zeroinitializer, align 16
@b = global [1024 x i8] zeroinitializer, align 16
@a = dso_local global [1024 x i8] zeroinitializer, align 16
@b = dso_local global [1024 x i8] zeroinitializer, align 16

define i32 @sad_16i8_256() "min-legal-vector-width"="256" {
define dso_local i32 @sad_16i8_256() "min-legal-vector-width"="256" {
; CHECK-LABEL: sad_16i8_256:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
Expand Down Expand Up @@ -370,7 +370,7 @@ middle.block:
ret i32 %12
}

define i32 @sad_16i8_512() "min-legal-vector-width"="512" {
define dso_local i32 @sad_16i8_512() "min-legal-vector-width"="512" {
; CHECK-LABEL: sad_16i8_512:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vpxor %xmm0, %xmm0, %xmm0
Expand Down Expand Up @@ -431,7 +431,7 @@ middle.block:
ret i32 %12
}

define void @sbto16f32_256(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-width"="256" {
define dso_local void @sbto16f32_256(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-width"="256" {
; CHECK-LABEL: sbto16f32_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0
Expand All @@ -450,7 +450,7 @@ define void @sbto16f32_256(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-
ret void
}

define void @sbto16f32_512(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-width"="512" {
define dso_local void @sbto16f32_512(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-width"="512" {
; CHECK-LABEL: sbto16f32_512:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0
Expand All @@ -465,7 +465,7 @@ define void @sbto16f32_512(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-
ret void
}

define void @sbto16f64_256(<16 x i16> %a, <16 x double>* %res) "min-legal-vector-width"="256" {
define dso_local void @sbto16f64_256(<16 x i16> %a, <16 x double>* %res) "min-legal-vector-width"="256" {
; CHECK-LABEL: sbto16f64_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0
Expand All @@ -490,7 +490,7 @@ define void @sbto16f64_256(<16 x i16> %a, <16 x double>* %res) "min-legal-vecto
ret void
}

define void @sbto16f64_512(<16 x i16> %a, <16 x double>* %res) "min-legal-vector-width"="512" {
define dso_local void @sbto16f64_512(<16 x i16> %a, <16 x double>* %res) "min-legal-vector-width"="512" {
; CHECK-LABEL: sbto16f64_512:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0
Expand All @@ -508,7 +508,7 @@ define void @sbto16f64_512(<16 x i16> %a, <16 x double>* %res) "min-legal-vecto
ret void
}

define void @ubto16f32_256(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-width"="256" {
define dso_local void @ubto16f32_256(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-width"="256" {
; CHECK-LABEL: ubto16f32_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0
Expand All @@ -529,7 +529,7 @@ define void @ubto16f32_256(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-
ret void
}

define void @ubto16f32_512(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-width"="512" {
define dso_local void @ubto16f32_512(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-width"="512" {
; CHECK-LABEL: ubto16f32_512:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0
Expand All @@ -545,7 +545,7 @@ define void @ubto16f32_512(<16 x i16> %a, <16 x float>* %res) "min-legal-vector-
ret void
}

define void @ubto16f64_256(<16 x i16> %a, <16 x double>* %res) "min-legal-vector-width"="256" {
define dso_local void @ubto16f64_256(<16 x i16> %a, <16 x double>* %res) "min-legal-vector-width"="256" {
; CHECK-LABEL: ubto16f64_256:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0
Expand All @@ -572,7 +572,7 @@ define void @ubto16f64_256(<16 x i16> %a, <16 x double>* %res) "min-legal-vector
ret void
}

define void @ubto16f64_512(<16 x i16> %a, <16 x double>* %res) "min-legal-vector-width"="512" {
define dso_local void @ubto16f64_512(<16 x i16> %a, <16 x double>* %res) "min-legal-vector-width"="512" {
; CHECK-LABEL: ubto16f64_512:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovw2m %ymm0, %k0
Expand Down Expand Up @@ -652,7 +652,7 @@ define <16 x i16> @test_16f32tosb_512(<16 x float>* %ptr, <16 x i16> %passthru)
ret <16 x i16> %select
}

define void @mul256(<64 x i8>* %a, <64 x i8>* %b, <64 x i8>* %c) "min-legal-vector-width"="256" {
define dso_local void @mul256(<64 x i8>* %a, <64 x i8>* %b, <64 x i8>* %c) "min-legal-vector-width"="256" {
; CHECK-AVX512-LABEL: mul256:
; CHECK-AVX512: # %bb.0:
; CHECK-AVX512-NEXT: vmovdqa (%rdi), %ymm0
Expand Down Expand Up @@ -715,7 +715,7 @@ define void @mul256(<64 x i8>* %a, <64 x i8>* %b, <64 x i8>* %c) "min-legal-vect
ret void
}

define void @mul512(<64 x i8>* %a, <64 x i8>* %b, <64 x i8>* %c) "min-legal-vector-width"="512" {
define dso_local void @mul512(<64 x i8>* %a, <64 x i8>* %b, <64 x i8>* %c) "min-legal-vector-width"="512" {
; CHECK-AVX512-LABEL: mul512:
; CHECK-AVX512: # %bb.0:
; CHECK-AVX512-NEXT: vmovdqa64 (%rdi), %zmm0
Expand Down Expand Up @@ -945,7 +945,7 @@ define <32 x i8> @trunc_v32i16_v32i8_sign(<32 x i16>* %x) nounwind "min-legal-ve
ret <32 x i8> %c
}

define void @zext_v16i8_v16i64(<16 x i8> %x, <16 x i64>* %y) nounwind "min-legal-vector-width"="256" {
define dso_local void @zext_v16i8_v16i64(<16 x i8> %x, <16 x i64>* %y) nounwind "min-legal-vector-width"="256" {
; CHECK-LABEL: zext_v16i8_v16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
Expand All @@ -967,7 +967,7 @@ define void @zext_v16i8_v16i64(<16 x i8> %x, <16 x i64>* %y) nounwind "min-legal
ret void
}

define void @sext_v16i8_v16i64(<16 x i8> %x, <16 x i64>* %y) nounwind "min-legal-vector-width"="256" {
define dso_local void @sext_v16i8_v16i64(<16 x i8> %x, <16 x i64>* %y) nounwind "min-legal-vector-width"="256" {
; CHECK-LABEL: sext_v16i8_v16i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vpmovsxbw %xmm0, %ymm1
Expand All @@ -989,7 +989,7 @@ define void @sext_v16i8_v16i64(<16 x i8> %x, <16 x i64>* %y) nounwind "min-legal
ret void
}

define void @vselect_split_v8i16_setcc(<8 x i16> %s, <8 x i16> %t, <8 x i64>* %p, <8 x i64>* %q, <8 x i64>* %r) "min-legal-vector-width"="256" {
define dso_local void @vselect_split_v8i16_setcc(<8 x i16> %s, <8 x i16> %t, <8 x i64>* %p, <8 x i64>* %q, <8 x i64>* %r) "min-legal-vector-width"="256" {
; CHECK-LABEL: vselect_split_v8i16_setcc:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rsi), %ymm2
Expand All @@ -1010,7 +1010,7 @@ define void @vselect_split_v8i16_setcc(<8 x i16> %s, <8 x i16> %t, <8 x i64>* %p
ret void
}

define void @vselect_split_v8i32_setcc(<8 x i32> %s, <8 x i32> %t, <8 x i64>* %p, <8 x i64>* %q, <8 x i64>* %r) "min-legal-vector-width"="256" {
define dso_local void @vselect_split_v8i32_setcc(<8 x i32> %s, <8 x i32> %t, <8 x i64>* %p, <8 x i64>* %q, <8 x i64>* %r) "min-legal-vector-width"="256" {
; CHECK-LABEL: vselect_split_v8i32_setcc:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rsi), %ymm2
Expand All @@ -1031,7 +1031,7 @@ define void @vselect_split_v8i32_setcc(<8 x i32> %s, <8 x i32> %t, <8 x i64>* %p
ret void
}

define void @vselect_split_v16i8_setcc(<16 x i8> %s, <16 x i8> %t, <16 x i32>* %p, <16 x i32>* %q, <16 x i32>* %r) "min-legal-vector-width"="256" {
define dso_local void @vselect_split_v16i8_setcc(<16 x i8> %s, <16 x i8> %t, <16 x i32>* %p, <16 x i32>* %q, <16 x i32>* %r) "min-legal-vector-width"="256" {
; CHECK-LABEL: vselect_split_v16i8_setcc:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rsi), %ymm2
Expand All @@ -1052,7 +1052,7 @@ define void @vselect_split_v16i8_setcc(<16 x i8> %s, <16 x i8> %t, <16 x i32>* %
ret void
}

define void @vselect_split_v16i16_setcc(<16 x i16> %s, <16 x i16> %t, <16 x i32>* %p, <16 x i32>* %q, <16 x i32>* %r) "min-legal-vector-width"="256" {
define dso_local void @vselect_split_v16i16_setcc(<16 x i16> %s, <16 x i16> %t, <16 x i32>* %p, <16 x i32>* %q, <16 x i32>* %r) "min-legal-vector-width"="256" {
; CHECK-LABEL: vselect_split_v16i16_setcc:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rsi), %ymm2
Expand Down Expand Up @@ -1091,7 +1091,7 @@ define <16 x i8> @trunc_packus_v16i32_v16i8(<16 x i32>* %p) "min-legal-vector-wi
ret <16 x i8> %f
}

define void @trunc_packus_v16i32_v16i8_store(<16 x i32>* %p, <16 x i8>* %q) "min-legal-vector-width"="256" {
define dso_local void @trunc_packus_v16i32_v16i8_store(<16 x i32>* %p, <16 x i8>* %q) "min-legal-vector-width"="256" {
; CHECK-LABEL: trunc_packus_v16i32_v16i8_store:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rdi), %ymm0
Expand All @@ -1117,7 +1117,7 @@ define <64 x i1> @v64i1_argument_return(<64 x i1> %x) "min-legal-vector-width"="
ret <64 x i1> %x
}

define void @v64i1_shuffle(<64 x i8>* %x, <64 x i8>* %y) "min-legal-vector-width"="256" {
define dso_local void @v64i1_shuffle(<64 x i8>* %x, <64 x i8>* %y) "min-legal-vector-width"="256" {
; CHECK-LABEL: v64i1_shuffle:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmovdqa (%rdi), %ymm1
Expand Down Expand Up @@ -1575,9 +1575,9 @@ entry:
}
declare void @llvm.masked.store.v64i8.p0v64i8(<64 x i8>, <64 x i8>*, i32, <64 x i1>)

@mem64_dst = global i64 0, align 8
@mem64_src = global i64 0, align 8
define i32 @v64i1_inline_asm() "min-legal-vector-width"="256" {
@mem64_dst = dso_local global i64 0, align 8
@mem64_src = dso_local global i64 0, align 8
define dso_local i32 @v64i1_inline_asm() "min-legal-vector-width"="256" {
; CHECK-LABEL: v64i1_inline_asm:
; CHECK: # %bb.0:
; CHECK-NEXT: kmovq {{.*}}(%rip), %k0
Expand All @@ -1594,7 +1594,7 @@ define i32 @v64i1_inline_asm() "min-legal-vector-width"="256" {
ret i32 %4
}

define void @cmp_v8i64_sext(<8 x i64>* %xptr, <8 x i64>* %yptr, <8 x i64>* %zptr) "min-legal-vector-width"="256" {
define dso_local void @cmp_v8i64_sext(<8 x i64>* %xptr, <8 x i64>* %yptr, <8 x i64>* %zptr) "min-legal-vector-width"="256" {
; CHECK-LABEL: cmp_v8i64_sext:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rsi), %ymm0
Expand All @@ -1613,7 +1613,7 @@ define void @cmp_v8i64_sext(<8 x i64>* %xptr, <8 x i64>* %yptr, <8 x i64>* %zptr
ret void
}

define void @cmp_v8i64_zext(<8 x i64>* %xptr, <8 x i64>* %yptr, <8 x i64>* %zptr) "min-legal-vector-width"="256" {
define dso_local void @cmp_v8i64_zext(<8 x i64>* %xptr, <8 x i64>* %yptr, <8 x i64>* %zptr) "min-legal-vector-width"="256" {
; CHECK-LABEL: cmp_v8i64_zext:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovdqa (%rsi), %ymm0
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/ms-inline-asm-PR44272.ll
View file
Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
; RUN: llc < %s -mtriple=i686-- | FileCheck %s
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s

define void @func() {
define dso_local void @func() {
entry:
ret void
}

define void @main() {
define dso_local void @main() {
entry:
call void asm sideeffect inteldialect "call ${0:P}", "*m,~{dirflag},~{fpsr},~{flags}"(void ()* @func)
ret void
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/musttail-tailcc.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@

declare dso_local tailcc i32 @tailcallee(i32 %a1, i32 %a2)

define tailcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind {
define dso_local tailcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind {
; X64-LABEL: tailcaller:
; X64: # %bb.0: # %entry
; X64-NEXT: jmp tailcallee # TAILCALL
Expand Down Expand Up @@ -35,7 +35,7 @@ define tailcc noalias i8* @noalias_caller() nounwind {

declare dso_local tailcc noalias i8* @noalias_callee()

define tailcc i8* @alias_caller() nounwind {
define dso_local tailcc i8* @alias_caller() nounwind {
; X64-LABEL: alias_caller:
; X64: # %bb.0:
; X64-NEXT: jmp noalias_callee # TAILCALL
Expand All @@ -47,7 +47,7 @@ define tailcc i8* @alias_caller() nounwind {
ret i8* %p
}

define tailcc void @void_test(i32, i32, i32, i32) {
define dso_local tailcc void @void_test(i32, i32, i32, i32) {
; X64-LABEL: void_test:
; X64: # %bb.0: # %entry
; X64-NEXT: jmp void_test # TAILCALL
Expand All @@ -69,7 +69,7 @@ define tailcc void @void_test(i32, i32, i32, i32) {
ret void
}

define tailcc i1 @i1test(i32, i32, i32, i32) {
define dso_local tailcc i1 @i1test(i32, i32, i32, i32) {
; X64-LABEL: i1test:
; X64: # %bb.0: # %entry
; X64-NEXT: jmp i1test # TAILCALL
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/narrow_op-1.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,9 +2,9 @@
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s

%struct.bf = type { i64, i16, i16, i32 }
@bfi = common global %struct.bf zeroinitializer, align 16
@bfi = common dso_local global %struct.bf zeroinitializer, align 16

define void @t1() nounwind optsize ssp {
define dso_local void @t1() nounwind optsize ssp {
; CHECK-LABEL: t1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: orb $1, bfi+{{.*}}(%rip)
Expand All @@ -17,7 +17,7 @@ entry:

}

define void @t2() nounwind optsize ssp {
define dso_local void @t2() nounwind optsize ssp {
; CHECK-LABEL: t2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: orl $16842752, bfi+{{.*}}(%rip) # imm = 0x1010000
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/peephole-fold-movsd.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,11 +7,11 @@

%struct.S1 = type { double, double }

@g = common global %struct.S1 zeroinitializer, align 8
@g = common dso_local global %struct.S1 zeroinitializer, align 8

declare void @foo3(%struct.S1*)

define void @foo1(double %a.coerce0, double %a.coerce1, double %b.coerce0, double %b.coerce1) nounwind {
define dso_local void @foo1(double %a.coerce0, double %a.coerce1, double %b.coerce0, double %b.coerce1) nounwind {
; CHECK-LABEL: foo1:
; CHECK: # %bb.0:
; CHECK-NEXT: subq $24, %rsp
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/pie.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -10,11 +10,11 @@
; CHECK: call{{l|q}} internal_foo{{$}}
; CHECK: call{{l|q}} ext_baz@PLT

define weak void @weak_foo() {
define weak dso_local void @weak_foo() {
ret void
}

define weak_odr void @weak_odr_foo() {
define weak_odr dso_local void @weak_odr_foo() {
ret void
}

Expand All @@ -24,11 +24,11 @@ define internal void @internal_foo() {

declare i32 @ext_baz()

define void @foo() {
define dso_local void @foo() {
ret void
}

define void @bar() {
define dso_local void @bar() {
entry:
call void @foo()
call void @weak_odr_foo()
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/pr22774.ll
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Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-pc-linux-gnu -mattr=+avx < %s | FileCheck %s

@in = global <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, align 32
@out = global <2 x i64> zeroinitializer, align 16
@in = dso_local global <4 x i64> <i64 -1, i64 -1, i64 -1, i64 -1>, align 32
@out = dso_local global <2 x i64> zeroinitializer, align 16

define i32 @_Z3foov() {
define dso_local i32 @_Z3foov() {
; CHECK-LABEL: _Z3foov:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/pr31956.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,8 @@
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-scei-ps4"

@G1 = common global <2 x float> zeroinitializer, align 8
@G2 = common global <8 x float> zeroinitializer, align 32
@G1 = common dso_local global <2 x float> zeroinitializer, align 8
@G2 = common dso_local global <8 x float> zeroinitializer, align 32

define <4 x float> @foo() {
; CHECK-LABEL: foo:
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/X86/pr32282.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,12 +4,12 @@

; Check for assert in foldMaskAndShiftToScale due to out of range mask scaling.

@b = common global i8 zeroinitializer, align 1
@c = common global i8 zeroinitializer, align 1
@d = common global i64 zeroinitializer, align 8
@e = common global i64 zeroinitializer, align 8
@b = common dso_local global i8 zeroinitializer, align 1
@c = common dso_local global i8 zeroinitializer, align 1
@d = common dso_local global i64 zeroinitializer, align 8
@e = common dso_local global i64 zeroinitializer, align 8

define void @foo(i64 %x) nounwind {
define dso_local void @foo(i64 %x) nounwind {
; X86-LABEL: foo:
; X86: # %bb.0:
; X86-NEXT: pushl %eax
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/pr33290.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,11 +2,11 @@
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64

@a = common global i32 0, align 4
@c = common local_unnamed_addr global i8 0, align 1
@b = common local_unnamed_addr global i32* null, align 8
@a = common dso_local global i32 0, align 4
@c = common dso_local local_unnamed_addr global i8 0, align 1
@b = common dso_local local_unnamed_addr global i32* null, align 8

define void @e() {
define dso_local void @e() {
; X86-LABEL: e:
; X86: # %bb.0: # %entry
; X86-NEXT: movl b, %eax
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/pr34629.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,11 +4,11 @@
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@b = common local_unnamed_addr global i64 0, align 8
@a = common local_unnamed_addr global i8 0, align 1
@b = common dso_local local_unnamed_addr global i64 0, align 8
@a = common dso_local local_unnamed_addr global i8 0, align 1

; Function Attrs: norecurse nounwind uwtable
define void @c() local_unnamed_addr #0 {
define dso_local void @c() local_unnamed_addr #0 {
; CHECK-LABEL: c:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq {{.*}}(%rip), %rax
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/X86/pr34634.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,12 +3,12 @@
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

@a = common local_unnamed_addr global [1 x [10 x i32]] zeroinitializer, align 16
@c = common local_unnamed_addr global i32 0, align 4
@b = common local_unnamed_addr global [1 x [7 x i32]] zeroinitializer, align 16
@a = common dso_local local_unnamed_addr global [1 x [10 x i32]] zeroinitializer, align 16
@c = common dso_local local_unnamed_addr global i32 0, align 4
@b = common dso_local local_unnamed_addr global [1 x [7 x i32]] zeroinitializer, align 16

; Function Attrs: norecurse nounwind uwtable
define void @fn1() local_unnamed_addr #0 {
define dso_local void @fn1() local_unnamed_addr #0 {
; CHECK-LABEL: fn1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movslq {{.*}}(%rip), %rax
Expand All @@ -31,7 +31,7 @@ entry:
}

; Function Attrs: norecurse nounwind uwtable
define i32 @main() local_unnamed_addr #0 {
define dso_local i32 @main() local_unnamed_addr #0 {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movslq {{.*}}(%rip), %rax
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/pr35761.ll
View file
Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-unknown-linux %s -o - | FileCheck %s

@x = global i8 0, align 1
@y = global i32 0, align 4
@z = global i24 0, align 4
@x = dso_local global i8 0, align 1
@y = dso_local global i32 0, align 4
@z = dso_local global i24 0, align 4

define void @PR35761(i32 %call) {
define dso_local void @PR35761(i32 %call) {
; CHECK-LABEL: PR35761:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movzbl {{.*}}(%rip), %eax
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/pr35763.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,11 +3,11 @@

%struct.S = type <{ i16, i24, [5 x i8], i8, i16, [2 x i8] }>

@z = global { i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, [5 x i8] } { i16 -724, i8 94, i8 -18, i8 5, i8 undef, i8 96, i8 104, i8 -24, i8 10, i8 0, [5 x i8] undef }, align 8
@tf_3_var_136 = global i64 0, align 8
@z = dso_local global { i16, i8, i8, i8, i8, i8, i8, i8, i8, i8, [5 x i8] } { i16 -724, i8 94, i8 -18, i8 5, i8 undef, i8 96, i8 104, i8 -24, i8 10, i8 0, [5 x i8] undef }, align 8
@tf_3_var_136 = dso_local global i64 0, align 8
@.str = private unnamed_addr constant [6 x i8] c"%llu\0A\00", align 1

define void @PR35763() {
define dso_local void @PR35763() {
; CHECK-LABEL: PR35763:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl {{.*}}(%rip), %eax
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/X86/pr35765.ll
View file
Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=x86_64-unknown-linux-gnu %s -o - | FileCheck %s

@ll = local_unnamed_addr global i64 0, align 8
@x = local_unnamed_addr global i64 2651237805702985558, align 8
@s1 = local_unnamed_addr global { i8, i8 } { i8 123, i8 5 }, align 2
@s2 = local_unnamed_addr global { i8, i8 } { i8 -122, i8 3 }, align 2
@ll = dso_local local_unnamed_addr global i64 0, align 8
@x = dso_local local_unnamed_addr global i64 2651237805702985558, align 8
@s1 = dso_local local_unnamed_addr global { i8, i8 } { i8 123, i8 5 }, align 2
@s2 = dso_local local_unnamed_addr global { i8, i8 } { i8 -122, i8 3 }, align 2

define void @PR35765() {
define dso_local void @PR35765() {
; CHECK-LABEL: PR35765:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb {{.*}}(%rip), %cl
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/pr36312.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,10 +3,10 @@

%struct.anon = type { i32, i32 }

@c = common global %struct.anon zeroinitializer, align 4
@d = local_unnamed_addr global %struct.anon* @c, align 8
@a = common local_unnamed_addr global i32 0, align 4
@b = common local_unnamed_addr global i32 0, align 4
@c = common dso_local global %struct.anon zeroinitializer, align 4
@d = dso_local local_unnamed_addr global %struct.anon* @c, align 8
@a = common dso_local local_unnamed_addr global i32 0, align 4
@b = common dso_local local_unnamed_addr global i32 0, align 4

; Function Attrs: norecurse nounwind uwtable
define void @g() local_unnamed_addr #0 {
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/X86/pr37826.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,13 +4,13 @@
; When compiled and run this should print zero.


@c = common local_unnamed_addr global i32 0, align 4
@f = common local_unnamed_addr global i32 0, align 4
@e = common local_unnamed_addr global i32 0, align 4
@c = common dso_local local_unnamed_addr global i32 0, align 4
@f = common dso_local local_unnamed_addr global i32 0, align 4
@e = common dso_local local_unnamed_addr global i32 0, align 4
@.str.1 = private unnamed_addr constant [4 x i8] c"%d\0A\00", align 1

; We should only see a single store to f (a bytes store to f+3).
define void @k(i32 %l) {
define dso_local void @k(i32 %l) {
; CHECK-LABEL: k:
; CHECK: # %bb.0:
; CHECK-NEXT: movl {{.*}}(%rip), %eax
Expand Down Expand Up @@ -38,7 +38,7 @@ define void @k(i32 %l) {

declare i32 @printf(i8* nocapture readonly, ...)

define i32 @main() {
define dso_local i32 @main() {
; CHECK-LABEL: main:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/pr38217.ll
View file
Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s

@_ZL11DIGIT_TABLE = constant [201 x i8] c"00010203040506070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899\00", align 16
@_ZL11DIGIT_TABLE = dso_local constant [201 x i8] c"00010203040506070809101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899\00", align 16

define void @_Z12d2s_bufferedmPc(i64, i8* nocapture) {
define dso_local void @_Z12d2s_bufferedmPc(i64, i8* nocapture) {
; CHECK-LABEL: _Z12d2s_bufferedmPc:
; CHECK: # %bb.0:
; CHECK-NEXT: cmpq $10000, %rdi # imm = 0x2710
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/pr38803.ll
View file
Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=skylake-avx512 -mtriple=x86_64-unknown-unknown | FileCheck %s

@b = local_unnamed_addr global i32 0, align 4
@c = local_unnamed_addr global i32 0, align 4
@d = local_unnamed_addr global float 0.000000e+00, align 4
@b = dso_local local_unnamed_addr global i32 0, align 4
@c = dso_local local_unnamed_addr global i32 0, align 4
@d = dso_local local_unnamed_addr global float 0.000000e+00, align 4

define float @_Z3fn2v() {
define dso_local float @_Z3fn2v() {
; CHECK-LABEL: _Z3fn2v:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/pr38865.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,9 +6,9 @@ target triple = "x86_64-unknown-linux-gnux32"

%struct.a = type { [65 x i32] }

@c = global %struct.a zeroinitializer, align 4
@c = dso_local global %struct.a zeroinitializer, align 4

define void @e() nounwind {
define dso_local void @e() nounwind {
; CHECK-LABEL: e:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbx # encoding: [0x53]
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/pr43866.ll
View file
Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s

@v2_0 = global <2 x i32> zeroinitializer, align 8
@v2_0 = dso_local global <2 x i32> zeroinitializer, align 8

define void @test() {
define dso_local void @test() {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rbp
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

%struct.obj = type { i64 }

define void @_Z7releaseP3obj(%struct.obj* nocapture %o) nounwind uwtable ssp {
define dso_local void @_Z7releaseP3obj(%struct.obj* nocapture %o) nounwind uwtable ssp {
; CHECK-LABEL: _Z7releaseP3obj:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: decq (%rdi)
Expand All @@ -29,12 +29,12 @@ return: ; preds = %entry, %if.end
ret void
}

@c = common global i64 0, align 8
@a = common global i32 0, align 4
@c = common dso_local global i64 0, align 8
@a = common dso_local global i32 0, align 4
@.str = private unnamed_addr constant [5 x i8] c"%ld\0A\00", align 1
@b = common global i32 0, align 4
@b = common dso_local global i32 0, align 4

define i32 @test() nounwind uwtable ssp {
define dso_local i32 @test() nounwind uwtable ssp {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
Expand Down Expand Up @@ -63,7 +63,7 @@ store i32 %lor.ext.i, i32* @a, align 4
ret i32 0
}

define i32 @test2() nounwind uwtable ssp {
define dso_local i32 @test2() nounwind uwtable ssp {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
Expand Down Expand Up @@ -100,7 +100,7 @@ declare dso_local void @free(i8* nocapture) nounwind

declare dso_local void @other(%struct.obj2* ) nounwind;

define void @example_dec(%struct.obj2* %o) nounwind uwtable ssp {
define dso_local void @example_dec(%struct.obj2* %o) nounwind uwtable ssp {
; 64 bit dec
; CHECK-LABEL: example_dec:
; CHECK: # %bb.0: # %entry
Expand Down Expand Up @@ -162,7 +162,7 @@ return: ; preds = %if.end4, %if.end, %
ret void
}

define void @example_inc(%struct.obj2* %o) nounwind uwtable ssp {
define dso_local void @example_inc(%struct.obj2* %o) nounwind uwtable ssp {
; 64 bit inc
; CHECK-LABEL: example_inc:
; CHECK: # %bb.0: # %entry
Expand Down Expand Up @@ -228,7 +228,7 @@ return:
; rdar://11236106
@foo = external dso_local global i64*, align 8

define void @test3() nounwind ssp {
define dso_local void @test3() nounwind ssp {
; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movq {{.*}}(%rip), %rax
Expand Down Expand Up @@ -265,7 +265,7 @@ declare dso_local void @baz()
@y = external dso_local global i32, align 4
@z = external dso_local global i32, align 4

define void @test4() nounwind uwtable ssp {
define dso_local void @test4() nounwind uwtable ssp {
; CHECK-LABEL: test4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
Expand Down
28 changes: 14 additions & 14 deletions llvm/test/CodeGen/X86/sad.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,10 +5,10 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,AVX512,AVX512F
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefixes=AVX,AVX512,AVX512BW

@a = global [1024 x i8] zeroinitializer, align 16
@b = global [1024 x i8] zeroinitializer, align 16
@a = dso_local global [1024 x i8] zeroinitializer, align 16
@b = dso_local global [1024 x i8] zeroinitializer, align 16

define i32 @sad_16i8() nounwind {
define dso_local i32 @sad_16i8() nounwind {
; SSE2-LABEL: sad_16i8:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: pxor %xmm0, %xmm0
Expand Down Expand Up @@ -147,7 +147,7 @@ middle.block:
ret i32 %12
}

define i32 @sad_32i8() nounwind {
define dso_local i32 @sad_32i8() nounwind {
; SSE2-LABEL: sad_32i8:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: pxor %xmm0, %xmm0
Expand Down Expand Up @@ -306,7 +306,7 @@ middle.block:
ret i32 %12
}

define i32 @sad_avx64i8() nounwind {
define dso_local i32 @sad_avx64i8() nounwind {
; SSE2-LABEL: sad_avx64i8:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: pxor %xmm4, %xmm4
Expand Down Expand Up @@ -539,7 +539,7 @@ middle.block:
ret i32 %12
}

define i32 @sad_2i8() nounwind {
define dso_local i32 @sad_2i8() nounwind {
; SSE2-LABEL: sad_2i8:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: pxor %xmm0, %xmm0
Expand Down Expand Up @@ -613,7 +613,7 @@ middle.block:
ret i32 %12
}

define i32 @sad_4i8() nounwind {
define dso_local i32 @sad_4i8() nounwind {
; SSE2-LABEL: sad_4i8:
; SSE2: # %bb.0: # %entry
; SSE2-NEXT: pxor %xmm0, %xmm0
Expand Down Expand Up @@ -688,7 +688,7 @@ middle.block:
}


define i32 @sad_nonloop_4i8(<4 x i8>* nocapture readonly %p, i64, <4 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
define dso_local i32 @sad_nonloop_4i8(<4 x i8>* nocapture readonly %p, i64, <4 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
; SSE2-LABEL: sad_nonloop_4i8:
; SSE2: # %bb.0:
; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero
Expand Down Expand Up @@ -720,7 +720,7 @@ define i32 @sad_nonloop_4i8(<4 x i8>* nocapture readonly %p, i64, <4 x i8>* noca
ret i32 %sum
}

define i32 @sad_nonloop_8i8(<8 x i8>* nocapture readonly %p, i64, <8 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
define dso_local i32 @sad_nonloop_8i8(<8 x i8>* nocapture readonly %p, i64, <8 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
; SSE2-LABEL: sad_nonloop_8i8:
; SSE2: # %bb.0:
; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
Expand Down Expand Up @@ -754,7 +754,7 @@ define i32 @sad_nonloop_8i8(<8 x i8>* nocapture readonly %p, i64, <8 x i8>* noca
ret i32 %sum
}

define i32 @sad_nonloop_16i8(<16 x i8>* nocapture readonly %p, i64, <16 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
define dso_local i32 @sad_nonloop_16i8(<16 x i8>* nocapture readonly %p, i64, <16 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
; SSE2-LABEL: sad_nonloop_16i8:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqu (%rdi), %xmm0
Expand Down Expand Up @@ -793,7 +793,7 @@ define i32 @sad_nonloop_16i8(<16 x i8>* nocapture readonly %p, i64, <16 x i8>* n
ret i32 %sum
}

define i32 @sad_nonloop_32i8(<32 x i8>* nocapture readonly %p, i64, <32 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
define dso_local i32 @sad_nonloop_32i8(<32 x i8>* nocapture readonly %p, i64, <32 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
; SSE2-LABEL: sad_nonloop_32i8:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqu (%rdx), %xmm0
Expand Down Expand Up @@ -865,7 +865,7 @@ define i32 @sad_nonloop_32i8(<32 x i8>* nocapture readonly %p, i64, <32 x i8>* n
ret i32 %sum
}

define i32 @sad_nonloop_64i8(<64 x i8>* nocapture readonly %p, i64, <64 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
define dso_local i32 @sad_nonloop_64i8(<64 x i8>* nocapture readonly %p, i64, <64 x i8>* nocapture readonly %q) local_unnamed_addr #0 {
; SSE2-LABEL: sad_nonloop_64i8:
; SSE2: # %bb.0:
; SSE2-NEXT: movdqu (%rdx), %xmm0
Expand Down Expand Up @@ -976,7 +976,7 @@ define i32 @sad_nonloop_64i8(<64 x i8>* nocapture readonly %p, i64, <64 x i8>* n

; This contains an unrolled sad loop with a non-zero initial value.
; DAGCombiner reassociation previously rewrote the adds to move the constant vector further down the tree. This resulted in the vector-reduction flag being lost.
define i32 @sad_unroll_nonzero_initial(<16 x i8>* %arg, <16 x i8>* %arg1, <16 x i8>* %arg2, <16 x i8>* %arg3) {
define dso_local i32 @sad_unroll_nonzero_initial(<16 x i8>* %arg, <16 x i8>* %arg1, <16 x i8>* %arg2, <16 x i8>* %arg3) {
; SSE2-LABEL: sad_unroll_nonzero_initial:
; SSE2: # %bb.0: # %bb
; SSE2-NEXT: movdqu (%rdi), %xmm0
Expand Down Expand Up @@ -1041,7 +1041,7 @@ bb:

; This test contains two absolute difference patterns joined by an add. The result of that add is then reduced to a single element.
; SelectionDAGBuilder should tag the joining add as a vector reduction. We neeed to recognize that both sides can use psadbw.
define i32 @sad_double_reduction(<16 x i8>* %arg, <16 x i8>* %arg1, <16 x i8>* %arg2, <16 x i8>* %arg3) {
define dso_local i32 @sad_double_reduction(<16 x i8>* %arg, <16 x i8>* %arg1, <16 x i8>* %arg2, <16 x i8>* %arg3) {
; SSE2-LABEL: sad_double_reduction:
; SSE2: # %bb.0: # %bb
; SSE2-NEXT: movdqu (%rdi), %xmm0
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/X86/shift-combine.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,9 +2,9 @@
; RUN: llc -mtriple=i686-unknown < %s | FileCheck %s --check-prefix=X32
; RUN: llc -mtriple=x86_64-unknown < %s | FileCheck %s --check-prefix=X64

@array = weak global [4 x i32] zeroinitializer
@array = weak dso_local global [4 x i32] zeroinitializer

define i32 @test_lshr_and(i32 %x) {
define dso_local i32 @test_lshr_and(i32 %x) {
; X32-LABEL: test_lshr_and:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
Expand All @@ -26,7 +26,7 @@ define i32 @test_lshr_and(i32 %x) {
ret i32 %tmp5
}

define i32* @test_exact1(i32 %a, i32 %b, i32* %x) {
define dso_local i32* @test_exact1(i32 %a, i32 %b, i32* %x) {
; X32-LABEL: test_exact1:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
Expand All @@ -48,7 +48,7 @@ define i32* @test_exact1(i32 %a, i32 %b, i32* %x) {
ret i32* %gep
}

define i32* @test_exact2(i32 %a, i32 %b, i32* %x) {
define dso_local i32* @test_exact2(i32 %a, i32 %b, i32* %x) {
; X32-LABEL: test_exact2:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
Expand All @@ -70,7 +70,7 @@ define i32* @test_exact2(i32 %a, i32 %b, i32* %x) {
ret i32* %gep
}

define i32* @test_exact3(i32 %a, i32 %b, i32* %x) {
define dso_local i32* @test_exact3(i32 %a, i32 %b, i32* %x) {
; X32-LABEL: test_exact3:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
Expand All @@ -91,7 +91,7 @@ define i32* @test_exact3(i32 %a, i32 %b, i32* %x) {
ret i32* %gep
}

define i32* @test_exact4(i32 %a, i32 %b, i32* %x) {
define dso_local i32* @test_exact4(i32 %a, i32 %b, i32* %x) {
; X32-LABEL: test_exact4:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
Expand All @@ -113,7 +113,7 @@ define i32* @test_exact4(i32 %a, i32 %b, i32* %x) {
ret i32* %gep
}

define i32* @test_exact5(i32 %a, i32 %b, i32* %x) {
define dso_local i32* @test_exact5(i32 %a, i32 %b, i32* %x) {
; X32-LABEL: test_exact5:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
Expand All @@ -135,7 +135,7 @@ define i32* @test_exact5(i32 %a, i32 %b, i32* %x) {
ret i32* %gep
}

define i32* @test_exact6(i32 %a, i32 %b, i32* %x) {
define dso_local i32* @test_exact6(i32 %a, i32 %b, i32* %x) {
; X32-LABEL: test_exact6:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
Expand Down Expand Up @@ -304,7 +304,7 @@ define i64 @ashr_add_shl_mismatch_shifts2(i64 %r) nounwind {
ret i64 %conv1
}

define i32 @ashr_add_shl_i32_i8_extra_use1(i32 %r, i32* %p) nounwind {
define dso_local i32 @ashr_add_shl_i32_i8_extra_use1(i32 %r, i32* %p) nounwind {
; X32-LABEL: ashr_add_shl_i32_i8_extra_use1:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
Expand All @@ -330,7 +330,7 @@ define i32 @ashr_add_shl_i32_i8_extra_use1(i32 %r, i32* %p) nounwind {
ret i32 %conv1
}

define i32 @ashr_add_shl_i32_i8_extra_use2(i32 %r, i32* %p) nounwind {
define dso_local i32 @ashr_add_shl_i32_i8_extra_use2(i32 %r, i32* %p) nounwind {
; X32-LABEL: ashr_add_shl_i32_i8_extra_use2:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
Expand All @@ -356,7 +356,7 @@ define i32 @ashr_add_shl_i32_i8_extra_use2(i32 %r, i32* %p) nounwind {
ret i32 %conv1
}

define i32 @ashr_add_shl_i32_i8_extra_use3(i32 %r, i32* %p1, i32* %p2) nounwind {
define dso_local i32 @ashr_add_shl_i32_i8_extra_use3(i32 %r, i32* %p1, i32* %p2) nounwind {
; X32-LABEL: ashr_add_shl_i32_i8_extra_use3:
; X32: # %bb.0:
; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
Expand Down Expand Up @@ -388,7 +388,7 @@ define i32 @ashr_add_shl_i32_i8_extra_use3(i32 %r, i32* %p1, i32* %p2) nounwind

%"class.QPainterPath" = type { double, double, i32 }

define void @PR42880(i32 %t0) {
define dso_local void @PR42880(i32 %t0) {
; X32-LABEL: PR42880:
; X32: # %bb.0:
; X32-NEXT: xorl %eax, %eax
Expand Down
28 changes: 14 additions & 14 deletions llvm/test/CodeGen/X86/shrink-compare-pgso.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

declare dso_local void @bar()

define void @test1(i32* nocapture %X) nounwind !prof !14 {
define dso_local void @test1(i32* nocapture %X) nounwind !prof !14 {
; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $47, (%rdi)
Expand All @@ -24,7 +24,7 @@ if.end:
ret void
}

define void @test2(i32 %X) nounwind !prof !14 {
define dso_local void @test2(i32 %X) nounwind !prof !14 {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $47, %dil
Expand All @@ -44,7 +44,7 @@ if.end:
ret void
}

define void @test3(i32 %X) nounwind !prof !14 {
define dso_local void @test3(i32 %X) nounwind !prof !14 {
; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-1, %dil
Expand Down Expand Up @@ -92,10 +92,10 @@ lor.end: ; preds = %lor.rhs, %entry
ret i1 %p
}

@x = global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 1 }, align 4
@x = dso_local global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 1 }, align 4

; PR16551
define void @test5(i32 %X) nounwind !prof !14 {
define dso_local void @test5(i32 %X) nounwind !prof !14 {
; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movzbl x+{{.*}}(%rip), %eax
Expand All @@ -121,7 +121,7 @@ if.end:
ret void
}

define void @test2_1(i32 %X) nounwind !prof !14 {
define dso_local void @test2_1(i32 %X) nounwind !prof !14 {
; CHECK-LABEL: test2_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movzbl %dil, %eax
Expand All @@ -142,7 +142,7 @@ if.end:
ret void
}

define void @test_sext_i8_icmp_1(i8 %x) nounwind !prof !14 {
define dso_local void @test_sext_i8_icmp_1(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $1, %dil
Expand All @@ -162,7 +162,7 @@ if.end:
ret void
}

define void @test_sext_i8_icmp_47(i8 %x) nounwind !prof !14 {
define dso_local void @test_sext_i8_icmp_47(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_47:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $47, %dil
Expand All @@ -182,7 +182,7 @@ if.end:
ret void
}

define void @test_sext_i8_icmp_127(i8 %x) nounwind !prof !14 {
define dso_local void @test_sext_i8_icmp_127(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_127:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $127, %dil
Expand All @@ -202,7 +202,7 @@ if.end:
ret void
}

define void @test_sext_i8_icmp_neg1(i8 %x) nounwind !prof !14 {
define dso_local void @test_sext_i8_icmp_neg1(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_neg1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-1, %dil
Expand All @@ -222,7 +222,7 @@ if.end:
ret void
}

define void @test_sext_i8_icmp_neg2(i8 %x) nounwind !prof !14 {
define dso_local void @test_sext_i8_icmp_neg2(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_neg2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-2, %dil
Expand All @@ -242,7 +242,7 @@ if.end:
ret void
}

define void @test_sext_i8_icmp_neg127(i8 %x) nounwind !prof !14 {
define dso_local void @test_sext_i8_icmp_neg127(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_neg127:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-127, %dil
Expand All @@ -262,7 +262,7 @@ if.end:
ret void
}

define void @test_sext_i8_icmp_neg128(i8 %x) nounwind !prof !14 {
define dso_local void @test_sext_i8_icmp_neg128(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_neg128:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-128, %dil
Expand All @@ -282,7 +282,7 @@ if.end:
ret void
}

define void @test_sext_i8_icmp_255(i8 %x) nounwind !prof !14 {
define dso_local void @test_sext_i8_icmp_255(i8 %x) nounwind !prof !14 {
; CHECK-LABEL: test_sext_i8_icmp_255:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb $1, %al
Expand Down
28 changes: 14 additions & 14 deletions llvm/test/CodeGen/X86/shrink-compare.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@

declare dso_local void @bar()

define void @test1(i32* nocapture %X) nounwind minsize {
define dso_local void @test1(i32* nocapture %X) nounwind minsize {
; CHECK-LABEL: test1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $47, (%rdi)
Expand All @@ -24,7 +24,7 @@ if.end:
ret void
}

define void @test2(i32 %X) nounwind minsize {
define dso_local void @test2(i32 %X) nounwind minsize {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $47, %dil
Expand All @@ -44,7 +44,7 @@ if.end:
ret void
}

define void @test3(i32 %X) nounwind minsize {
define dso_local void @test3(i32 %X) nounwind minsize {
; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-1, %dil
Expand Down Expand Up @@ -92,10 +92,10 @@ lor.end: ; preds = %lor.rhs, %entry
ret i1 %p
}

@x = global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 1 }, align 4
@x = dso_local global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 1 }, align 4

; PR16551
define void @test5(i32 %X) nounwind minsize {
define dso_local void @test5(i32 %X) nounwind minsize {
; CHECK-LABEL: test5:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movzbl x+{{.*}}(%rip), %eax
Expand All @@ -121,7 +121,7 @@ if.end:
ret void
}

define void @test2_1(i32 %X) nounwind minsize {
define dso_local void @test2_1(i32 %X) nounwind minsize {
; CHECK-LABEL: test2_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movzbl %dil, %eax
Expand All @@ -142,7 +142,7 @@ if.end:
ret void
}

define void @test_sext_i8_icmp_1(i8 %x) nounwind minsize {
define dso_local void @test_sext_i8_icmp_1(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $1, %dil
Expand All @@ -162,7 +162,7 @@ if.end:
ret void
}

define void @test_sext_i8_icmp_47(i8 %x) nounwind minsize {
define dso_local void @test_sext_i8_icmp_47(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_47:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $47, %dil
Expand All @@ -182,7 +182,7 @@ if.end:
ret void
}

define void @test_sext_i8_icmp_127(i8 %x) nounwind minsize {
define dso_local void @test_sext_i8_icmp_127(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_127:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $127, %dil
Expand All @@ -202,7 +202,7 @@ if.end:
ret void
}

define void @test_sext_i8_icmp_neg1(i8 %x) nounwind minsize {
define dso_local void @test_sext_i8_icmp_neg1(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_neg1:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-1, %dil
Expand All @@ -222,7 +222,7 @@ if.end:
ret void
}

define void @test_sext_i8_icmp_neg2(i8 %x) nounwind minsize {
define dso_local void @test_sext_i8_icmp_neg2(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_neg2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-2, %dil
Expand All @@ -242,7 +242,7 @@ if.end:
ret void
}

define void @test_sext_i8_icmp_neg127(i8 %x) nounwind minsize {
define dso_local void @test_sext_i8_icmp_neg127(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_neg127:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-127, %dil
Expand All @@ -262,7 +262,7 @@ if.end:
ret void
}

define void @test_sext_i8_icmp_neg128(i8 %x) nounwind minsize {
define dso_local void @test_sext_i8_icmp_neg128(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_neg128:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: cmpb $-128, %dil
Expand All @@ -282,7 +282,7 @@ if.end:
ret void
}

define void @test_sext_i8_icmp_255(i8 %x) nounwind minsize {
define dso_local void @test_sext_i8_icmp_255(i8 %x) nounwind minsize {
; CHECK-LABEL: test_sext_i8_icmp_255:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movb $1, %al
Expand Down
36 changes: 18 additions & 18 deletions llvm/test/CodeGen/X86/sibcall.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=x86_64-linux -mcpu=core2 -mattr=+sse2 | FileCheck %s --check-prefix=X64
; RUN: llc -verify-machineinstrs < %s -mtriple=x86_64-linux-gnux32 -mcpu=core2 -mattr=+sse2 | FileCheck %s --check-prefix=X32

define void @t1(i32 %x) nounwind ssp {
define dso_local void @t1(i32 %x) nounwind ssp {
; X86-LABEL: t1:
; X86: # %bb.0:
; X86-NEXT: jmp foo # TAILCALL
Expand All @@ -21,7 +21,7 @@ define void @t1(i32 %x) nounwind ssp {

declare dso_local void @foo()

define void @t2() nounwind ssp {
define dso_local void @t2() nounwind ssp {
; X86-LABEL: t2:
; X86: # %bb.0:
; X86-NEXT: jmp foo2 # TAILCALL
Expand All @@ -39,7 +39,7 @@ define void @t2() nounwind ssp {

declare dso_local i32 @foo2()

define void @t3() nounwind ssp {
define dso_local void @t3() nounwind ssp {
; X86-LABEL: t3:
; X86: # %bb.0:
; X86-NEXT: jmp foo3 # TAILCALL
Expand All @@ -57,7 +57,7 @@ define void @t3() nounwind ssp {

declare dso_local i32 @foo3()

define void @t4(void (i32)* nocapture %x) nounwind ssp {
define dso_local void @t4(void (i32)* nocapture %x) nounwind ssp {
; X86-LABEL: t4:
; X86: # %bb.0:
; X86-NEXT: subl $12, %esp
Expand All @@ -81,7 +81,7 @@ define void @t4(void (i32)* nocapture %x) nounwind ssp {
ret void
}

define void @t5(void ()* nocapture %x) nounwind ssp {
define dso_local void @t5(void ()* nocapture %x) nounwind ssp {
; X86-LABEL: t5:
; X86: # %bb.0:
; X86-NEXT: jmpl *{{[0-9]+}}(%esp) # TAILCALL
Expand All @@ -100,7 +100,7 @@ define void @t5(void ()* nocapture %x) nounwind ssp {
; Basically the same test as t5, except pass the function pointer on the stack
; for x86_64.

define void @t5_x64(i32, i32, i32, i32, i32, i32, void ()* nocapture %x) nounwind ssp {
define dso_local void @t5_x64(i32, i32, i32, i32, i32, i32, void ()* nocapture %x) nounwind ssp {
; X86-LABEL: t5_x64:
; X86: # %bb.0:
; X86-NEXT: jmpl *{{[0-9]+}}(%esp) # TAILCALL
Expand All @@ -118,7 +118,7 @@ define void @t5_x64(i32, i32, i32, i32, i32, i32, void ()* nocapture %x) nounwin
}


define i32 @t6(i32 %x) nounwind ssp {
define dso_local i32 @t6(i32 %x) nounwind ssp {
; X86-LABEL: t6:
; X86: # %bb.0:
; X86-NEXT: subl $12, %esp
Expand Down Expand Up @@ -169,7 +169,7 @@ bb1:

declare dso_local i32 @bar(i32)

define i32 @t7(i32 %a, i32 %b, i32 %c) nounwind ssp {
define dso_local i32 @t7(i32 %a, i32 %b, i32 %c) nounwind ssp {
; X86-LABEL: t7:
; X86: # %bb.0:
; X86-NEXT: jmp bar2 # TAILCALL
Expand Down Expand Up @@ -232,7 +232,7 @@ entry:
ret i16 %1
}

define void @t10() nounwind ssp {
define dso_local void @t10() nounwind ssp {
; X86-LABEL: t10:
; X86: # %bb.0: # %entry
; X86-NEXT: subl $12, %esp
Expand All @@ -257,7 +257,7 @@ declare dso_local i32 @foo4()
; In 32-bit mode, it's emitting a bunch of dead loads that are not being
; eliminated currently.

define i32 @t11(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind ssp {
define dso_local i32 @t11(i32 %x, i32 %y, i32 %z.0, i32 %z.1, i32 %z.2) nounwind ssp {
; X86-LABEL: t11:
; X86: # %bb.0: # %entry
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
Expand Down Expand Up @@ -303,7 +303,7 @@ declare dso_local i32 @foo5(i32, i32, i32, i32, i32)

%struct.t = type { i32, i32, i32, i32, i32 }

define i32 @t12(i32 %x, i32 %y, %struct.t* byval(%struct.t) align 4 %z) nounwind ssp {
define dso_local i32 @t12(i32 %x, i32 %y, %struct.t* byval(%struct.t) align 4 %z) nounwind ssp {
; X86-LABEL: t12:
; X86: # %bb.0: # %entry
; X86-NEXT: cmpl $0, {{[0-9]+}}(%esp)
Expand Down Expand Up @@ -413,7 +413,7 @@ declare dso_local fastcc %struct.ns* @foo7(%struct.cp* byval(%struct.cp) align 4
%struct.__block_literal_1 = type { i8*, i32, i32, i8*, %struct.__block_descriptor* }
%struct.__block_literal_2 = type { i8*, i32, i32, i8*, %struct.__block_descriptor_withcopydispose*, void ()* }

define void @t14(%struct.__block_literal_2* nocapture %.block_descriptor) nounwind ssp {
define dso_local void @t14(%struct.__block_literal_2* nocapture %.block_descriptor) nounwind ssp {
; X86-LABEL: t14:
; X86: # %bb.0: # %entry
; X86-NEXT: subl $12, %esp
Expand Down Expand Up @@ -449,7 +449,7 @@ entry:
; rdar://7726868
%struct.foo = type { [4 x i32] }

define void @t15(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind {
define dso_local void @t15(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind {
; X86-LABEL: t15:
; X86: # %bb.0:
; X86-NEXT: pushl %esi
Expand Down Expand Up @@ -485,7 +485,7 @@ define void @t15(%struct.foo* noalias sret(%struct.foo) %agg.result) nounwind {

declare dso_local void @f(%struct.foo* noalias sret(%struct.foo)) nounwind

define void @t16() nounwind ssp {
define dso_local void @t16() nounwind ssp {
; X86-LABEL: t16:
; X86: # %bb.0: # %entry
; X86-NEXT: subl $12, %esp
Expand All @@ -509,7 +509,7 @@ entry:
declare dso_local double @bar4()

; rdar://6283267
define void @t17() nounwind ssp {
define dso_local void @t17() nounwind ssp {
; X86-LABEL: t17:
; X86: # %bb.0: # %entry
; X86-NEXT: jmp bar5 # TAILCALL
Expand All @@ -531,7 +531,7 @@ entry:
declare dso_local void @bar5(...)

; rdar://7774847
define void @t18() nounwind ssp {
define dso_local void @t18() nounwind ssp {
; X86-LABEL: t18:
; X86: # %bb.0: # %entry
; X86-NEXT: subl $12, %esp
Expand All @@ -556,7 +556,7 @@ entry:

declare dso_local double @bar6(...)

define void @t19() alignstack(32) nounwind {
define dso_local void @t19() alignstack(32) nounwind {
; X86-LABEL: t19:
; X86: # %bb.0: # %entry
; X86-NEXT: pushl %ebp
Expand Down Expand Up @@ -598,7 +598,7 @@ entry:
; values are returned in the same registers.
; rdar://7874780

define double @t20(double %x) nounwind {
define dso_local double @t20(double %x) nounwind {
; X86-LABEL: t20:
; X86: # %bb.0: # %entry
; X86-NEXT: subl $12, %esp
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/speculative-execution-side-effect-suppression.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -x86-seses-enable-without-lvi-cfi -x86-seses-omit-branch-lfences %s -o - | FileCheck %s --check-prefix=X86-OMIT-BR
; RUN: llc -mtriple=x86_64-unknown-linux-gnu -x86-seses-enable-without-lvi-cfi -x86-seses-only-lfence-non-const %s -o - | FileCheck %s --check-prefix=X86-NON-CONST

define void @_Z4buzzv() {
define dso_local void @_Z4buzzv() {
; CHECK-LABEL: _Z4buzzv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfence
Expand Down Expand Up @@ -34,7 +34,7 @@ entry:
ret void
}

define i32 @_Z3barPi(i32* %p) {
define dso_local i32 @_Z3barPi(i32* %p) {
; CHECK-LABEL: _Z3barPi:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfence
Expand Down Expand Up @@ -173,7 +173,7 @@ return: ; preds = %if.else, %if.then
ret i32 %7
}

define i32 (i32*)* @_Z3bazv() {
define dso_local i32 (i32*)* @_Z3bazv() {
; CHECK-LABEL: _Z3bazv:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lfence
Expand Down Expand Up @@ -223,7 +223,7 @@ entry:
ret i32 (i32*)* %0
}

define void @_Z3fooPi(i32* %p) {
define dso_local void @_Z3fooPi(i32* %p) {
; CHECK-LABEL: _Z3fooPi:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/X86/speculative-load-hardening-indirect.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,14 +13,14 @@

@global_fnptr = external global i32 ()*

@global_blockaddrs = constant [4 x i8*] [
@global_blockaddrs = dso_local constant [4 x i8*] [
i8* blockaddress(@test_indirectbr_global, %bb0),
i8* blockaddress(@test_indirectbr_global, %bb1),
i8* blockaddress(@test_indirectbr_global, %bb2),
i8* blockaddress(@test_indirectbr_global, %bb3)
]

define i32 @test_indirect_call(i32 ()** %ptr) nounwind {
define dso_local i32 @test_indirect_call(i32 ()** %ptr) nounwind {
; X64-LABEL: test_indirect_call:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rbx
Expand Down Expand Up @@ -93,7 +93,7 @@ entry:
ret i32 %v
}

define i32 @test_indirect_tail_call(i32 ()** %ptr) nounwind {
define dso_local i32 @test_indirect_tail_call(i32 ()** %ptr) nounwind {
; X64-LABEL: test_indirect_tail_call:
; X64: # %bb.0: # %entry
; X64-NEXT: movq %rsp, %rax
Expand Down Expand Up @@ -132,7 +132,7 @@ entry:
ret i32 %v
}

define i32 @test_indirect_call_global() nounwind {
define dso_local i32 @test_indirect_call_global() nounwind {
; X64-LABEL: test_indirect_call_global:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rbx
Expand Down Expand Up @@ -208,7 +208,7 @@ entry:
ret i32 %v
}

define i32 @test_indirect_tail_call_global() nounwind {
define dso_local i32 @test_indirect_tail_call_global() nounwind {
; X64-LABEL: test_indirect_tail_call_global:
; X64: # %bb.0: # %entry
; X64-NEXT: movq %rsp, %rax
Expand Down Expand Up @@ -250,7 +250,7 @@ entry:
ret i32 %v
}

define i32 @test_indirectbr(i8** %ptr) nounwind {
define dso_local i32 @test_indirectbr(i8** %ptr) nounwind {
; X64-LABEL: test_indirectbr:
; X64: # %bb.0: # %entry
; X64-NEXT: movq %rsp, %rcx
Expand Down Expand Up @@ -356,7 +356,7 @@ bb3:
ret i32 42
}

define i32 @test_indirectbr_global(i32 %idx) nounwind {
define dso_local i32 @test_indirectbr_global(i32 %idx) nounwind {
; X64-LABEL: test_indirectbr_global:
; X64: # %bb.0: # %entry
; X64-NEXT: movq %rsp, %rcx
Expand Down Expand Up @@ -405,7 +405,7 @@ define i32 @test_indirectbr_global(i32 %idx) nounwind {
; X64-PIC-NEXT: movq $-1, %rax
; X64-PIC-NEXT: sarq $63, %rcx
; X64-PIC-NEXT: movslq %edi, %rdx
; X64-PIC-NEXT: movq global_blockaddrs@{{.*}}(%rip), %rsi
; X64-PIC-NEXT: leaq .Lglobal_blockaddrs$local(%rip), %rsi
; X64-PIC-NEXT: movq (%rsi,%rdx,8), %rdx
; X64-PIC-NEXT: orq %rcx, %rdx
; X64-PIC-NEXT: jmpq *%rdx
Expand Down Expand Up @@ -512,7 +512,7 @@ bb3:

; This function's switch is crafted to trigger jump-table lowering in the x86
; backend so that we can test how the exact jump table lowering behaves.
define i32 @test_switch_jumptable(i32 %idx) nounwind {
define dso_local i32 @test_switch_jumptable(i32 %idx) nounwind {
; X64-LABEL: test_switch_jumptable:
; X64: # %bb.0: # %entry
; X64-NEXT: movq %rsp, %rcx
Expand Down Expand Up @@ -704,7 +704,7 @@ bb5:
; backend so that we can test how the exact jump table lowering behaves, but
; also arranges for fallthroughs from case to case to ensure that this pattern
; too can be handled.
define i32 @test_switch_jumptable_fallthrough(i32 %idx, i32* %a.ptr, i32* %b.ptr, i32* %c.ptr, i32* %d.ptr) nounwind {
define dso_local i32 @test_switch_jumptable_fallthrough(i32 %idx, i32* %a.ptr, i32* %b.ptr, i32* %c.ptr, i32* %d.ptr) nounwind {
; X64-LABEL: test_switch_jumptable_fallthrough:
; X64: # %bb.0: # %entry
; X64-NEXT: movq %rsp, %r9
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/X86/splat-for-size.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -382,7 +382,7 @@ define <32 x i8> @splat_v32i8_pgso(<32 x i8> %x) !prof !14 {
; due to a missing AVX pattern to select a v2i64 X86ISD::BROADCAST of a
; loadi64 with multiple uses.

@A = common global <3 x i64> zeroinitializer, align 32
@A = common dso_local global <3 x i64> zeroinitializer, align 32

define <8 x i64> @pr23259() #1 {
; AVX-LABEL: pr23259:
Expand Down
56 changes: 28 additions & 28 deletions llvm/test/CodeGen/X86/stores-merging.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,14 +3,14 @@

%structTy = type { i8, i32, i32 }

@e = common global %structTy zeroinitializer, align 4
@e = common dso_local global %structTy zeroinitializer, align 4

;; Ensure that MergeConsecutiveStores doesn't incorrectly reorder
;; store operations. The first test stores in increasing address
;; order, the second in decreasing -- but in both cases should have
;; the same result in memory in the end.

define void @redundant_stores_merging() {
define dso_local void @redundant_stores_merging() {
; CHECK-LABEL: redundant_stores_merging:
; CHECK: # %bb.0:
; CHECK-NEXT: movabsq $1958505086977, %rax # imm = 0x1C800000001
Expand All @@ -23,7 +23,7 @@ define void @redundant_stores_merging() {
}

;; This variant tests PR25154.
define void @redundant_stores_merging_reverse() {
define dso_local void @redundant_stores_merging_reverse() {
; CHECK-LABEL: redundant_stores_merging_reverse:
; CHECK: # %bb.0:
; CHECK-NEXT: movabsq $528280977409, %rax # imm = 0x7B00000001
Expand All @@ -36,14 +36,14 @@ define void @redundant_stores_merging_reverse() {
ret void
}

@b = common global [8 x i8] zeroinitializer, align 2
@b = common dso_local global [8 x i8] zeroinitializer, align 2

;; The 2-byte store to offset 3 overlaps the 2-byte store to offset 2;
;; these must not be reordered in MergeConsecutiveStores such that the
;; store to 3 comes first (e.g. by merging the stores to 0 and 2 into
;; a movl, after the store to 3).

define void @overlapping_stores_merging() {
define dso_local void @overlapping_stores_merging() {
; CHECK-LABEL: overlapping_stores_merging:
; CHECK: # %bb.0:
; CHECK-NEXT: movl $1, {{.*}}(%rip)
Expand All @@ -55,7 +55,7 @@ define void @overlapping_stores_merging() {
ret void
}

define void @extract_vector_store_16_consecutive_bytes(<2 x i64> %v, i8* %ptr) #0 {
define dso_local void @extract_vector_store_16_consecutive_bytes(<2 x i64> %v, i8* %ptr) #0 {
; CHECK-LABEL: extract_vector_store_16_consecutive_bytes:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovups %xmm0, (%rdi)
Expand Down Expand Up @@ -114,7 +114,7 @@ define void @extract_vector_store_16_consecutive_bytes(<2 x i64> %v, i8* %ptr) #

; PR34217 - https://bugs.llvm.org/show_bug.cgi?id=34217

define void @extract_vector_store_32_consecutive_bytes(<4 x i64> %v, i8* %ptr) #0 {
define dso_local void @extract_vector_store_32_consecutive_bytes(<4 x i64> %v, i8* %ptr) #0 {
; CHECK-LABEL: extract_vector_store_32_consecutive_bytes:
; CHECK: # %bb.0:
; CHECK-NEXT: vmovups %ymm0, (%rdi)
Expand Down Expand Up @@ -221,7 +221,7 @@ define void @extract_vector_store_32_consecutive_bytes(<4 x i64> %v, i8* %ptr) #
}

; https://bugs.llvm.org/show_bug.cgi?id=43446
define void @pr43446_0(i64 %x) {
define dso_local void @pr43446_0(i64 %x) {
; CHECK-LABEL: pr43446_0:
; CHECK: # %bb.0:
; CHECK-NEXT: movb $1, (%rdi)
Expand All @@ -232,7 +232,7 @@ define void @pr43446_0(i64 %x) {
store i1 true, i1* %b, align 1
ret void
}
define void @pr43446_1(i8* %a) {
define dso_local void @pr43446_1(i8* %a) {
; CHECK-LABEL: pr43446_1:
; CHECK: # %bb.0:
; CHECK-NEXT: movb $1, (%rdi)
Expand All @@ -243,7 +243,7 @@ define void @pr43446_1(i8* %a) {
ret void
}

define void @rotate16_in_place(i8* %p) {
define dso_local void @rotate16_in_place(i8* %p) {
; CHECK-LABEL: rotate16_in_place:
; CHECK: # %bb.0:
; CHECK-NEXT: rolw $8, (%rdi)
Expand All @@ -257,7 +257,7 @@ define void @rotate16_in_place(i8* %p) {
ret void
}

define void @rotate16(i8* %p, i8* %q) {
define dso_local void @rotate16(i8* %p, i8* %q) {
; CHECK-LABEL: rotate16:
; CHECK: # %bb.0:
; CHECK-NEXT: movzwl (%rdi), %eax
Expand All @@ -275,7 +275,7 @@ define void @rotate16(i8* %p, i8* %q) {
ret void
}

define void @rotate32_in_place(i16* %p) {
define dso_local void @rotate32_in_place(i16* %p) {
; CHECK-LABEL: rotate32_in_place:
; CHECK: # %bb.0:
; CHECK-NEXT: roll $16, (%rdi)
Expand All @@ -289,7 +289,7 @@ define void @rotate32_in_place(i16* %p) {
ret void
}

define void @rotate32(i16* %p) {
define dso_local void @rotate32(i16* %p) {
; CHECK-LABEL: rotate32:
; CHECK: # %bb.0:
; CHECK-NEXT: movl (%rdi), %eax
Expand All @@ -307,7 +307,7 @@ define void @rotate32(i16* %p) {
ret void
}

define void @rotate64_in_place(i32* %p) {
define dso_local void @rotate64_in_place(i32* %p) {
; CHECK-LABEL: rotate64_in_place:
; CHECK: # %bb.0:
; CHECK-NEXT: rolq $32, (%rdi)
Expand All @@ -321,7 +321,7 @@ define void @rotate64_in_place(i32* %p) {
ret void
}

define void @rotate64(i32* %p) {
define dso_local void @rotate64(i32* %p) {
; CHECK-LABEL: rotate64:
; CHECK: # %bb.0:
; CHECK-NEXT: movq (%rdi), %rax
Expand All @@ -339,7 +339,7 @@ define void @rotate64(i32* %p) {
ret void
}

define void @rotate64_iterate(i16* %p) {
define dso_local void @rotate64_iterate(i16* %p) {
; CHECK-LABEL: rotate64_iterate:
; CHECK: # %bb.0:
; CHECK-NEXT: movq (%rdi), %rax
Expand Down Expand Up @@ -367,7 +367,7 @@ define void @rotate64_iterate(i16* %p) {

; TODO: recognize this as 2 rotates?

define void @rotate32_consecutive(i16* %p) {
define dso_local void @rotate32_consecutive(i16* %p) {
; CHECK-LABEL: rotate32_consecutive:
; CHECK: # %bb.0:
; CHECK-NEXT: movzwl (%rdi), %eax
Expand Down Expand Up @@ -400,7 +400,7 @@ define void @rotate32_consecutive(i16* %p) {

; Same as above, but now the stores are not all consecutive.

define void @rotate32_twice(i16* %p) {
define dso_local void @rotate32_twice(i16* %p) {
; CHECK-LABEL: rotate32_twice:
; CHECK: # %bb.0:
; CHECK-NEXT: movl (%rdi), %eax
Expand Down Expand Up @@ -429,7 +429,7 @@ define void @rotate32_twice(i16* %p) {
ret void
}

define void @trunc_i16_to_i8(i16 %x, i8* %p) {
define dso_local void @trunc_i16_to_i8(i16 %x, i8* %p) {
; CHECK-LABEL: trunc_i16_to_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: movw %di, (%rsi)
Expand All @@ -443,7 +443,7 @@ define void @trunc_i16_to_i8(i16 %x, i8* %p) {
ret void
}

define void @trunc_i32_to_i8(i32 %x, i8* %p) {
define dso_local void @trunc_i32_to_i8(i32 %x, i8* %p) {
; CHECK-LABEL: trunc_i32_to_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, (%rsi)
Expand All @@ -465,7 +465,7 @@ define void @trunc_i32_to_i8(i32 %x, i8* %p) {
ret void
}

define void @trunc_i32_to_i16(i32 %x, i16* %p) {
define dso_local void @trunc_i32_to_i16(i32 %x, i16* %p) {
; CHECK-LABEL: trunc_i32_to_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: movl %edi, (%rsi)
Expand All @@ -479,7 +479,7 @@ define void @trunc_i32_to_i16(i32 %x, i16* %p) {
ret void
}

define void @be_i32_to_i16(i32 %x, i16* %p0) {
define dso_local void @be_i32_to_i16(i32 %x, i16* %p0) {
; CHECK-LABEL: be_i32_to_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: rorl $16, %edi
Expand All @@ -494,7 +494,7 @@ define void @be_i32_to_i16(i32 %x, i16* %p0) {
ret void
}

define void @be_i32_to_i16_order(i32 %x, i16* %p0) {
define dso_local void @be_i32_to_i16_order(i32 %x, i16* %p0) {
; CHECK-LABEL: be_i32_to_i16_order:
; CHECK: # %bb.0:
; CHECK-NEXT: rorl $16, %edi
Expand All @@ -509,7 +509,7 @@ define void @be_i32_to_i16_order(i32 %x, i16* %p0) {
ret void
}

define void @trunc_i64_to_i8(i64 %x, i8* %p) {
define dso_local void @trunc_i64_to_i8(i64 %x, i8* %p) {
; CHECK-LABEL: trunc_i64_to_i8:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, (%rsi)
Expand Down Expand Up @@ -547,7 +547,7 @@ define void @trunc_i64_to_i8(i64 %x, i8* %p) {
ret void
}

define void @trunc_i64_to_i16(i64 %x, i16* %p) {
define dso_local void @trunc_i64_to_i16(i64 %x, i16* %p) {
; CHECK-LABEL: trunc_i64_to_i16:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, (%rsi)
Expand All @@ -569,7 +569,7 @@ define void @trunc_i64_to_i16(i64 %x, i16* %p) {
ret void
}

define void @trunc_i64_to_i32(i64 %x, i32* %p) {
define dso_local void @trunc_i64_to_i32(i64 %x, i32* %p) {
; CHECK-LABEL: trunc_i64_to_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: movq %rdi, (%rsi)
Expand All @@ -583,7 +583,7 @@ define void @trunc_i64_to_i32(i64 %x, i32* %p) {
ret void
}

define void @be_i64_to_i32(i64 %x, i32* %p0) {
define dso_local void @be_i64_to_i32(i64 %x, i32* %p0) {
; CHECK-LABEL: be_i64_to_i32:
; CHECK: # %bb.0:
; CHECK-NEXT: rorq $32, %rdi
Expand All @@ -598,7 +598,7 @@ define void @be_i64_to_i32(i64 %x, i32* %p0) {
ret void
}

define void @be_i64_to_i32_order(i64 %x, i32* %p0) {
define dso_local void @be_i64_to_i32_order(i64 %x, i32* %p0) {
; CHECK-LABEL: be_i64_to_i32_order:
; CHECK: # %bb.0:
; CHECK-NEXT: rorq $32, %rdi
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/X86/subvector-broadcast.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -797,10 +797,10 @@ define <16 x i32> @test_broadcast_4i32_16i32_chain(<4 x i32>* %p0, <4 x float>*
; Fallback to the broadcast should be done
;

@ga4 = global <4 x i64> zeroinitializer, align 8
@gb4 = global <8 x i64> zeroinitializer, align 8
@ga4 = dso_local global <4 x i64> zeroinitializer, align 8
@gb4 = dso_local global <8 x i64> zeroinitializer, align 8

define void @fallback_broadcast_v4i64_to_v8i64(<4 x i64> %a, <8 x i64> %b) {
define dso_local void @fallback_broadcast_v4i64_to_v8i64(<4 x i64> %a, <8 x i64> %b) {
; X86-AVX1-LABEL: fallback_broadcast_v4i64_to_v8i64:
; X86-AVX1: # %bb.0: # %entry
; X86-AVX1-NEXT: vmovdqa {{.*#+}} xmm3 = [1,0,2,0]
Expand Down Expand Up @@ -912,10 +912,10 @@ entry:
}


@ga2 = global <4 x double> zeroinitializer, align 8
@gb2 = global <8 x double> zeroinitializer, align 8
@ga2 = dso_local global <4 x double> zeroinitializer, align 8
@gb2 = dso_local global <8 x double> zeroinitializer, align 8

define void @fallback_broadcast_v4f64_to_v8f64(<4 x double> %a, <8 x double> %b) {
define dso_local void @fallback_broadcast_v4f64_to_v8f64(<4 x double> %a, <8 x double> %b) {
; X86-AVX-LABEL: fallback_broadcast_v4f64_to_v8f64:
; X86-AVX: # %bb.0: # %entry
; X86-AVX-NEXT: vmovapd {{.*#+}} ymm3 = [1.0E+0,2.0E+0,3.0E+0,4.0E+0]
Expand Down Expand Up @@ -976,11 +976,11 @@ entry:
ret void
}

@ha4 = global <4 x i32> zeroinitializer, align 8
@hb4 = global <8 x i32> zeroinitializer, align 8
@hc4 = global <16 x i32> zeroinitializer, align 8
@ha4 = dso_local global <4 x i32> zeroinitializer, align 8
@hb4 = dso_local global <8 x i32> zeroinitializer, align 8
@hc4 = dso_local global <16 x i32> zeroinitializer, align 8

define void @fallback_broadcast_v4i32_v8i32_v16i32(<4 x i32> %a, <8 x i32> %b, <16 x i32> %c) nounwind {
define dso_local void @fallback_broadcast_v4i32_v8i32_v16i32(<4 x i32> %a, <8 x i32> %b, <16 x i32> %c) nounwind {
; X86-AVX1-LABEL: fallback_broadcast_v4i32_v8i32_v16i32:
; X86-AVX1: # %bb.0: # %entry
; X86-AVX1-NEXT: pushl %ebp
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/X86/swift-return.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
; RUN: llc -verify-machineinstrs < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
; RUN: llc -verify-machineinstrs < %s -mtriple=x86_64-unknown-unknown -O0 | FileCheck --check-prefix=CHECK-O0 %s

@var = global i32 0
@var = dso_local global i32 0

; Test how llvm handles return type of {i16, i8}. The return value will be
; passed in %eax and %dl.
Expand Down Expand Up @@ -54,7 +54,7 @@ declare swiftcc { i16, i8 } @gen(i32)
; If we can't pass every return value in register, we will pass everything
; in memroy. The caller provides space for the return value and passes
; the address in %rax. The first input argument will be in %rdi.
define i32 @test2(i32 %key) #0 {
define dso_local i32 @test2(i32 %key) #0 {
; CHECK-LABEL: test2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subq $24, %rsp
Expand Down Expand Up @@ -140,7 +140,7 @@ define swiftcc { i32, i32, i32, i32, i32 } @gen2(i32 %key) {

; The return value {i32, i32, i32, i32} will be returned via registers %eax,
; %edx, %ecx, %r8d.
define i32 @test3(i32 %key) #0 {
define dso_local i32 @test3(i32 %key) #0 {
; CHECK-LABEL: test3:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
Expand Down Expand Up @@ -188,7 +188,7 @@ declare swiftcc { i32, i32, i32, i32 } @gen3(i32 %key)

; The return value {float, float, float, float} will be returned via registers
; %xmm0, %xmm1, %xmm2, %xmm3.
define float @test4(float %key) #0 {
define dso_local float @test4(float %key) #0 {
; CHECK-LABEL: test4:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
Expand Down Expand Up @@ -234,7 +234,7 @@ entry:

declare swiftcc { float, float, float, float } @gen4(float %key)

define void @consume_i1_ret() {
define dso_local void @consume_i1_ret() {
; CHECK-LABEL: consume_i1_ret:
; CHECK: # %bb.0:
; CHECK-NEXT: pushq %rax
Expand Down
30 changes: 15 additions & 15 deletions llvm/test/CodeGen/X86/tail-opts.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,13 +8,13 @@ declare dso_local void @ear(i32)
declare dso_local void @far(i32)
declare i1 @qux()

@GHJK = global i32 0
@HABC = global i32 0
@GHJK = dso_local global i32 0
@HABC = dso_local global i32 0

; BranchFolding should tail-merge the stores since they all precede
; direct branches to the same place.

define void @tail_merge_me() nounwind {
define dso_local void @tail_merge_me() nounwind {
; CHECK-LABEL: tail_merge_me:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
Expand Down Expand Up @@ -92,7 +92,7 @@ declare i8* @choose(i8*, i8*)
; BranchFolding should tail-duplicate the indirect jump to avoid
; redundant branching.

define void @tail_duplicate_me() nounwind {
define dso_local void @tail_duplicate_me() nounwind {
; CHECK-LABEL: tail_duplicate_me:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %r14
Expand Down Expand Up @@ -401,7 +401,7 @@ declare fastcc %union.tree_node* @default_conversion(%union.tree_node*) nounwind
; instructions are involved. This function should have only
; one ret instruction.

define void @foo(i1* %V) nounwind {
define dso_local void @foo(i1* %V) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testq %rdi, %rdi
Expand Down Expand Up @@ -432,7 +432,7 @@ declare dso_local void @func()

declare dso_local void @tail_call_me()

define void @one(i32 %v) nounwind optsize {
define dso_local void @one(i32 %v) nounwind optsize {
; CHECK-LABEL: one:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testl %edi, %edi
Expand Down Expand Up @@ -473,7 +473,7 @@ return:
ret void
}

define void @one_pgso(i32 %v) nounwind !prof !14 {
define dso_local void @one_pgso(i32 %v) nounwind !prof !14 {
; CHECK-LABEL: one_pgso:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testl %edi, %edi
Expand Down Expand Up @@ -518,7 +518,7 @@ return:
; tail instead of one. This is too much to be merged, given
; the optsize attribute.

define void @two() nounwind optsize {
define dso_local void @two() nounwind optsize {
; CHECK-LABEL: two:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
Expand Down Expand Up @@ -559,7 +559,7 @@ return:
ret void
}

define void @two_pgso() nounwind !prof !14 {
define dso_local void @two_pgso() nounwind !prof !14 {
; CHECK-LABEL: two_pgso:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
Expand Down Expand Up @@ -602,7 +602,7 @@ return:

; two_minsize - Same as two, but with minsize instead of optsize.

define void @two_minsize() nounwind minsize {
define dso_local void @two_minsize() nounwind minsize {
; CHECK-LABEL: two_minsize:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: xorl %eax, %eax
Expand Down Expand Up @@ -646,7 +646,7 @@ return:
; two_nosize - Same as two, but without the optsize attribute.
; Now two instructions are enough to be tail-duplicated.

define void @two_nosize(i32 %x, i32 %y, i32 %z) nounwind {
define dso_local void @two_nosize(i32 %x, i32 %y, i32 %z) nounwind {
; CHECK-LABEL: two_nosize:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testl %edi, %edi
Expand Down Expand Up @@ -729,7 +729,7 @@ for.end: ; preds = %entry
; them as possible.

declare dso_local void @abort()
define void @merge_aborts() {
define dso_local void @merge_aborts() {
; CHECK-LABEL: merge_aborts:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
Expand Down Expand Up @@ -789,7 +789,7 @@ cont4:

declare dso_local void @alt_abort()

define void @merge_alternating_aborts() {
define dso_local void @merge_alternating_aborts() {
; CHECK-LABEL: merge_alternating_aborts:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
Expand Down Expand Up @@ -848,8 +848,8 @@ cont4:

; This triggers a situation where a new block (bb4 is split) is created and then
; would be passed to the PGSO interface llvm::shouldOptimizeForSize().
@GV = global i32 0
define void @bfi_new_block_pgso(i32 %c) nounwind {
@GV = dso_local global i32 0
define dso_local void @bfi_new_block_pgso(i32 %c) nounwind {
; CHECK-LABEL: bfi_new_block_pgso:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testl %edi, %edi
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/tailcall-disable.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,12 +4,12 @@
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"

define i32 @helper() nounwind {
define dso_local i32 @helper() nounwind {
entry:
ret i32 7
}

define i32 @test1() nounwind {
define dso_local i32 @test1() nounwind {
entry:
%call = tail call i32 @helper()
ret i32 %call
Expand All @@ -24,7 +24,7 @@ entry:
; JMP-NOT: ret
; JMP: jmp helper # TAILCALL

define i32 @test2() nounwind {
define dso_local i32 @test2() nounwind {
entry:
%call = tail call i32 @test2()
ret i32 %call
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/X86/tailcall-tailcc.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@

declare dso_local tailcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4)

define tailcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind {
define dso_local tailcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind {
; X64-LABEL: tailcaller:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
Expand Down Expand Up @@ -48,7 +48,7 @@ define tailcc noalias i8* @noalias_caller() nounwind {

declare dso_local tailcc noalias i8* @noalias_callee()

define tailcc i8* @alias_caller() nounwind {
define dso_local tailcc i8* @alias_caller() nounwind {
; X64-LABEL: alias_caller:
; X64: # %bb.0:
; X64-NEXT: pushq %rax
Expand All @@ -64,7 +64,7 @@ define tailcc i8* @alias_caller() nounwind {

declare dso_local tailcc i32 @i32_callee()

define tailcc i32 @ret_undef() nounwind {
define dso_local tailcc i32 @ret_undef() nounwind {
; X64-LABEL: ret_undef:
; X64: # %bb.0:
; X64-NEXT: pushq %rax
Expand All @@ -80,7 +80,7 @@ define tailcc i32 @ret_undef() nounwind {

declare dso_local tailcc void @does_not_return()

define tailcc i32 @noret() nounwind {
define dso_local tailcc i32 @noret() nounwind {
; X64-LABEL: noret:
; X64: # %bb.0:
; X64-NEXT: pushq %rax
Expand All @@ -94,7 +94,7 @@ define tailcc i32 @noret() nounwind {
unreachable
}

define tailcc void @void_test(i32, i32, i32, i32) {
define dso_local tailcc void @void_test(i32, i32, i32, i32) {
; X64-LABEL: void_test:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
Expand Down Expand Up @@ -124,7 +124,7 @@ define tailcc void @void_test(i32, i32, i32, i32) {
ret void
}

define tailcc i1 @i1test(i32, i32, i32, i32) {
define dso_local tailcc i1 @i1test(i32, i32, i32, i32) {
; X64-LABEL: i1test:
; X64: # %bb.0: # %entry
; X64-NEXT: pushq %rax
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/X86/tailcall.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,7 @@

declare fastcc i32 @tailcallee(i32 %a1, i32 %a2, i32 %a3, i32 %a4)

define fastcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind {
define dso_local fastcc i32 @tailcaller(i32 %in1, i32 %in2) nounwind {
; CHECK-LABEL: tailcaller:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: subl $16, %esp
Expand All @@ -33,7 +33,7 @@ define fastcc noalias i8* @noalias_caller() nounwind {

declare fastcc noalias i8* @noalias_callee()

define fastcc i8* @alias_caller() nounwind {
define dso_local fastcc i8* @alias_caller() nounwind {
; CHECK-LABEL: alias_caller:
; CHECK: # %bb.0:
; CHECK-NEXT: jmp noalias_callee@PLT # TAILCALL
Expand All @@ -43,7 +43,7 @@ define fastcc i8* @alias_caller() nounwind {

declare fastcc i32 @i32_callee()

define fastcc i32 @ret_undef() nounwind {
define dso_local fastcc i32 @ret_undef() nounwind {
; CHECK-LABEL: ret_undef:
; CHECK: # %bb.0:
; CHECK-NEXT: jmp i32_callee@PLT # TAILCALL
Expand All @@ -53,15 +53,15 @@ define fastcc i32 @ret_undef() nounwind {

declare fastcc void @does_not_return()

define fastcc i32 @noret() nounwind {
define dso_local fastcc i32 @noret() nounwind {
; CHECK-LABEL: noret:
; CHECK: # %bb.0:
; CHECK-NEXT: jmp does_not_return@PLT # TAILCALL
tail call fastcc void @does_not_return()
unreachable
}

define fastcc void @void_test(i32, i32, i32, i32) {
define dso_local fastcc void @void_test(i32, i32, i32, i32) {
; CHECK-LABEL: void_test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %esi
Expand All @@ -83,7 +83,7 @@ define fastcc void @void_test(i32, i32, i32, i32) {
ret void
}

define fastcc i1 @i1test(i32, i32, i32, i32) {
define dso_local fastcc i1 @i1test(i32, i32, i32, i32) {
; CHECK-LABEL: i1test:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushl %esi
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/test-shrink-bug.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2,11 +2,11 @@
; RUN: llc < %s -mtriple=i386-apple-darwin10.0 | FileCheck %s --check-prefix=CHECK-X86
; RUN: llc < %s -mtriple=x86_64-grtev4-linux-gnu | FileCheck %s --check-prefix=CHECK-X64

@g_14 = global i8 -6, align 1 ; <i8*> [#uses=1]
@g_14 = dso_local global i8 -6, align 1 ; <i8*> [#uses=1]

declare i32 @func_16(i8 signext %p_19, i32 %p_20) nounwind

define i32 @func_35(i64 %p_38) nounwind ssp {
define dso_local i32 @func_35(i64 %p_38) nounwind ssp {
; CHECK-X86-LABEL: func_35:
; CHECK-X86: ## %bb.0: ## %entry
; CHECK-X86-NEXT: subl $12, %esp
Expand Down Expand Up @@ -43,7 +43,7 @@ entry:
ret i32 1
}

define void @fail(i16 %a, <2 x i8> %b) {
define dso_local void @fail(i16 %a, <2 x i8> %b) {
; CHECK-X86-LABEL: fail:
; CHECK-X86: ## %bb.0:
; CHECK-X86-NEXT: subl $12, %esp
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/X86/tls-pie.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,10 +3,10 @@
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux-gnux32 -relocation-model=pic | FileCheck %s --check-prefix=X32
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-linux-gnu -relocation-model=pic | FileCheck %s --check-prefix=X64

@i = thread_local global i32 15
@i = dso_local thread_local global i32 15
@i2 = external thread_local global i32

define i32 @f1() {
define dso_local i32 @f1() {
; X86-LABEL: f1:
; X86: # %bb.0: # %entry
; X86-NEXT: movl %gs:i@NTPOFF, %eax
Expand All @@ -26,7 +26,7 @@ entry:
ret i32 %tmp1
}

define i32* @f2() {
define dso_local i32* @f2() {
; X86-LABEL: f2:
; X86: # %bb.0: # %entry
; X86-NEXT: movl %gs:0, %eax
Expand All @@ -48,7 +48,7 @@ entry:
ret i32* @i
}

define i32 @f3() {
define dso_local i32 @f3() {
; X86-LABEL: f3:
; X86: # %bb.0: # %entry
; X86-NEXT: calll .L2$pb
Expand Down Expand Up @@ -79,7 +79,7 @@ entry:
ret i32 %tmp1
}

define i32* @f4() {
define dso_local i32* @f4() {
; X86-LABEL: f4:
; X86: # %bb.0: # %entry
; X86-NEXT: calll .L3$pb
Expand Down
42 changes: 21 additions & 21 deletions llvm/test/CodeGen/X86/tls.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,17 +7,17 @@
; RUN: llc < %s -mtriple=i686-pc-windows-gnu | FileCheck -check-prefix=MINGW32 %s
; RUN: llc < %s -mtriple=x86_64-pc-windows-gnu | FileCheck -check-prefix=X64_WIN %s

@i1 = thread_local global i32 15
@i1 = dso_local thread_local global i32 15
@i2 = external thread_local global i32
@i3 = internal thread_local global i32 15
@i4 = hidden thread_local global i32 15
@i5 = external hidden thread_local global i32
@i6 = external protected thread_local global i32
@s1 = thread_local global i16 15
@b1 = thread_local global i8 0
@b2 = thread_local(localexec) global i8 0
@s1 = dso_local thread_local global i16 15
@b1 = dso_local thread_local global i8 0
@b2 = dso_local thread_local(localexec) global i8 0

define i32 @f1() {
define dso_local i32 @f1() {
; X86_LINUX-LABEL: f1:
; X86_LINUX: movl %gs:i1@NTPOFF, %eax
; X86_LINUX-NEXT: ret
Expand Down Expand Up @@ -48,7 +48,7 @@ entry:
ret i32 %tmp1
}

define i32* @f2() {
define dso_local i32* @f2() {
; X86_LINUX-LABEL: f2:
; X86_LINUX: movl %gs:0, %eax
; X86_LINUX-NEXT: leal i1@NTPOFF(%eax), %eax
Expand Down Expand Up @@ -80,7 +80,7 @@ entry:
ret i32* @i1
}

define i32 @f3() nounwind {
define dso_local i32 @f3() nounwind {
; X86_LINUX-LABEL: f3:
; X86_LINUX: movl i2@INDNTPOFF, %eax
; X86_LINUX-NEXT: movl %gs:(%eax), %eax
Expand Down Expand Up @@ -113,7 +113,7 @@ entry:
ret i32 %tmp1
}

define i32* @f4() {
define dso_local i32* @f4() {
; X86_LINUX-LABEL: f4:
; X86_LINUX: movl %gs:0, %eax
; X86_LINUX-NEXT: addl i2@INDNTPOFF, %eax
Expand Down Expand Up @@ -145,7 +145,7 @@ entry:
ret i32* @i2
}

define i32 @f5() nounwind {
define dso_local i32 @f5() nounwind {
; X86_LINUX-LABEL: f5:
; X86_LINUX: movl %gs:i3@NTPOFF, %eax
; X86_LINUX-NEXT: ret
Expand Down Expand Up @@ -176,7 +176,7 @@ entry:
ret i32 %tmp1
}

define i32* @f6() {
define dso_local i32* @f6() {
; X86_LINUX-LABEL: f6:
; X86_LINUX: movl %gs:0, %eax
; X86_LINUX-NEXT: leal i3@NTPOFF(%eax), %eax
Expand Down Expand Up @@ -208,7 +208,7 @@ entry:
ret i32* @i3
}

define i32 @f7() {
define dso_local i32 @f7() {
; X86_LINUX-LABEL: f7:
; X86_LINUX: movl %gs:i4@NTPOFF, %eax
; X86_LINUX-NEXT: ret
Expand All @@ -227,7 +227,7 @@ entry:
ret i32 %tmp1
}

define i32* @f8() {
define dso_local i32* @f8() {
; X86_LINUX-LABEL: f8:
; X86_LINUX: movl %gs:0, %eax
; X86_LINUX-NEXT: leal i4@NTPOFF(%eax), %eax
Expand All @@ -247,7 +247,7 @@ entry:
ret i32* @i4
}

define i32 @f9() {
define dso_local i32 @f9() {
; X86_LINUX-LABEL: f9:
; X86_LINUX: movl %gs:i5@NTPOFF, %eax
; X86_LINUX-NEXT: ret
Expand All @@ -266,7 +266,7 @@ entry:
ret i32 %tmp1
}

define i32* @f10() {
define dso_local i32* @f10() {
; X86_LINUX-LABEL: f10:
; X86_LINUX: movl %gs:0, %eax
; X86_LINUX-NEXT: leal i5@NTPOFF(%eax), %eax
Expand Down Expand Up @@ -317,7 +317,7 @@ entry:
ret i16 %tmp1
}

define i32 @f12() {
define dso_local i32 @f12() {
; X86_LINUX-LABEL: f12:
; X86_LINUX: movswl %gs:s1@NTPOFF, %eax
; X86_LINUX-NEXT: ret
Expand Down Expand Up @@ -350,7 +350,7 @@ entry:
ret i32 %tmp2
}

define i8 @f13() {
define dso_local i8 @f13() {
; X86_LINUX-LABEL: f13:
; X86_LINUX: movb %gs:b1@NTPOFF, %al
; X86_LINUX-NEXT: ret
Expand Down Expand Up @@ -381,7 +381,7 @@ entry:
ret i8 %tmp1
}

define i32 @f14() {
define dso_local i32 @f14() {
; X86_LINUX-LABEL: f14:
; X86_LINUX: movsbl %gs:b1@NTPOFF, %eax
; X86_LINUX-NEXT: ret
Expand Down Expand Up @@ -413,7 +413,7 @@ entry:
ret i32 %tmp2
}

define i8* @f15() {
define dso_local i8* @f15() {
; X86_LINUX-LABEL: f15:
; X86_LINUX: movl %gs:0, %eax
; X86_LINUX-NEXT: leal b2@NTPOFF(%eax), %eax
Expand Down Expand Up @@ -442,7 +442,7 @@ entry:
}


define i32* @f16() {
define dso_local i32* @f16() {
; X86_LINUX-LABEL: f16:
; X86_LINUX: movl %gs:0, %eax
; X86_LINUX-NEXT: leal i6@NTPOFF(%eax), %eax
Expand All @@ -457,7 +457,7 @@ define i32* @f16() {
}

; NOTE: Similar to f1() but with direct TLS segment access disabled
define i32 @f17() #0 {
define dso_local i32 @f17() #0 {
; X86_LINUX-LABEL: f17:
; X86_LINUX: movl %gs:0, %eax
; X86_LINUX-NEXT: movl i1@NTPOFF(%eax), %eax
Expand All @@ -481,7 +481,7 @@ entry:
}

; NOTE: Similar to f3() but with direct TLS segment access disabled
define i32 @f18() #1 {
define dso_local i32 @f18() #1 {
; X86_LINUX-LABEL: f18:
; X86_LINUX: movl i2@INDNTPOFF, %eax
; X86_LINUX-NEXT: movl %gs:0, %ecx
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/trunc-and.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -28,9 +28,9 @@ declare <2 x double> @llvm.fabs.v2f64(<2 x double>)

%struct.anon = type { [9 x i8], [3 x i8] }

@b = common local_unnamed_addr global %struct.anon zeroinitializer, align 4
@b = common dso_local local_unnamed_addr global %struct.anon zeroinitializer, align 4

define i32 @d() {
define dso_local i32 @d() {
; CHECK-LABEL: d:
; CHECK: # %bb.0:
; CHECK-NEXT: movzbl b+{{.*}}(%rip), %ecx
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/undef-label.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,9 +4,9 @@
; This is a case where we would incorrectly conclude that LBB0_1 could only
; be reached via fall through and would therefore omit the label.

@g = global i32 0
@g = dso_local global i32 0

define void @xyz() {
define dso_local void @xyz() {
; CHECK-LABEL: xyz:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl $g, %eax
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/vec-loadsingles-alignment.ll
View file
Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s

@e = global [8 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8], align 16
@d = global [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 16
@e = dso_local global [8 x i32] [i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8], align 16
@d = dso_local global [8 x i32] [i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1], align 16

; The global 'e' has 16 byte alignment, so make sure we don't generate an
; aligned 32-byte load instruction when we combine the load+insert sequence.

define i32 @subb() nounwind ssp {
define dso_local i32 @subb() nounwind ssp {
; CHECK-LABEL: subb:
; CHECK: vmovups e(%rip), %ymm
entry:
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/widen_load-1.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,11 +13,11 @@
; AVX: vmovaps %xmm0, (%rsp)
; AVX: callq killcommon

@compl = linkonce global [20 x i64] zeroinitializer, align 64 ; <[20 x i64]*> [#uses=1]
@compl = linkonce dso_local global [20 x i64] zeroinitializer, align 64 ; <[20 x i64]*> [#uses=1]

declare void @killcommon(i32* noalias)

define void @reset(<2 x float>* noalias %garbage1) {
define dso_local void @reset(<2 x float>* noalias %garbage1) {
"file complex.c, line 27, bb1":
%changed = alloca i32, align 4 ; <i32*> [#uses=3]
br label %"file complex.c, line 27, bb13"
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/X86/x86-64-intrcc.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,8 @@

%struct.interrupt_frame = type { i64, i64, i64, i64, i64 }

@sink_address = global i64* null
@sink_i32 = global i64 0
@sink_address = dso_local global i64* null
@sink_i32 = dso_local global i64 0

; Spills rax, putting original esp at +8.
; No stack adjustment if declared with no error code
Expand Down Expand Up @@ -90,7 +90,7 @@ define x86_intrcc void @test_isr_clobbers(%struct.interrupt_frame* byval(%struct
ret void
}

@f80 = common global x86_fp80 0xK00000000000000000000, align 4
@f80 = common dso_local global x86_fp80 0xK00000000000000000000, align 4

; Test that the presence of x87 does not crash the FP stackifier
define x86_intrcc void @test_isr_x87(%struct.interrupt_frame* byval(%struct.interrupt_frame) %frame) {
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/X86/xor-select-i1-combine.ll
View file
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
;RUN: llc < %s -O2 -mattr=+avx512f -mtriple=x86_64-unknown | FileCheck %s

@n = common global i32 0, align 4
@m = common global i32 0, align 4
@n = common dso_local global i32 0, align 4
@m = common dso_local global i32 0, align 4

define i32 @main(i8 %small) {
define dso_local i32 @main(i8 %small) {
; CHECK-LABEL: main:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testb $1, %dil
Expand All @@ -22,7 +22,7 @@ entry:
}


define i32 @main2(i8 %small) {
define dso_local i32 @main2(i8 %small) {
; CHECK-LABEL: main2:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: movl $m, %eax
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/X86/xray-tail-call-sled.ll
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
; RUN: llc -verify-machineinstrs -filetype=asm -o - -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
; RUN: llc -verify-machineinstrs -filetype=asm -o - -mtriple=x86_64-darwin-unknown < %s | FileCheck %s

define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" {
define dso_local i32 @callee() nounwind noinline uwtable "function-instrument"="xray-always" {
; CHECK: .p2align 1, 0x90
; CHECK-LABEL: Lxray_sled_0:
; CHECK: .ascii "\353\t"
Expand All @@ -21,7 +21,7 @@ define i32 @callee() nounwind noinline uwtable "function-instrument"="xray-alway
; CHECK: .quad {{.*}}xray_sleds_start0
; CHECK-NEXT: .quad {{.*}}xray_sleds_end0

define i32 @caller() nounwind noinline uwtable "function-instrument"="xray-always" {
define dso_local i32 @caller() nounwind noinline uwtable "function-instrument"="xray-always" {
; CHECK: .p2align 1, 0x90
; CHECK-LABEL: Lxray_sled_2:
; CHECK: .ascii "\353\t"
Expand Down