68 changes: 34 additions & 34 deletions clang/test/CodeGen/SystemZ/zvector.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ volatile vector double fd, fd2;

volatile int cnt;

// CHECK-LABEL: define void @test_assign() #0 {
// CHECK-LABEL: define{{.*}} void @test_assign() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: store volatile <16 x i8> [[TMP0]], <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @uc2, align 8
Expand Down Expand Up @@ -57,7 +57,7 @@ void test_assign(void) {
fd = fd2;
}

// CHECK-LABEL: define void @test_pos() #0 {
// CHECK-LABEL: define{{.*}} void @test_pos() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: store volatile <16 x i8> [[TMP0]], <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @uc2, align 8
Expand Down Expand Up @@ -94,7 +94,7 @@ void test_pos(void) {
fd = +fd2;
}

// CHECK-LABEL: define void @test_neg() #0 {
// CHECK-LABEL: define{{.*}} void @test_neg() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[SUB:%.*]] = sub <16 x i8> zeroinitializer, [[TMP0]]
// CHECK: store volatile <16 x i8> [[SUB]], <16 x i8>* @sc, align 8
Expand All @@ -120,7 +120,7 @@ void test_neg(void) {
fd = -fd2;
}

// CHECK-LABEL: define void @test_preinc() #0 {
// CHECK-LABEL: define{{.*}} void @test_preinc() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[INC:%.*]] = add <16 x i8> [[TMP0]], <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
// CHECK: store volatile <16 x i8> [[INC]], <16 x i8>* @sc2, align 8
Expand Down Expand Up @@ -166,7 +166,7 @@ void test_preinc(void) {
++fd2;
}

// CHECK-LABEL: define void @test_postinc() #0 {
// CHECK-LABEL: define{{.*}} void @test_postinc() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[INC:%.*]] = add <16 x i8> [[TMP0]], <i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
// CHECK: store volatile <16 x i8> [[INC]], <16 x i8>* @sc2, align 8
Expand Down Expand Up @@ -212,7 +212,7 @@ void test_postinc(void) {
fd2++;
}

// CHECK-LABEL: define void @test_predec() #0 {
// CHECK-LABEL: define{{.*}} void @test_predec() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[DEC:%.*]] = add <16 x i8> [[TMP0]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: store volatile <16 x i8> [[DEC]], <16 x i8>* @sc2, align 8
Expand Down Expand Up @@ -258,7 +258,7 @@ void test_predec(void) {
--fd2;
}

// CHECK-LABEL: define void @test_postdec() #0 {
// CHECK-LABEL: define{{.*}} void @test_postdec() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[DEC:%.*]] = add <16 x i8> [[TMP0]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: store volatile <16 x i8> [[DEC]], <16 x i8>* @sc2, align 8
Expand Down Expand Up @@ -304,7 +304,7 @@ void test_postdec(void) {
fd2--;
}

// CHECK-LABEL: define void @test_add() #0 {
// CHECK-LABEL: define{{.*}} void @test_add() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[ADD:%.*]] = add <16 x i8> [[TMP0]], [[TMP1]]
Expand Down Expand Up @@ -439,7 +439,7 @@ void test_add(void) {
fd = fd + fd2;
}

// CHECK-LABEL: define void @test_add_assign() #0 {
// CHECK-LABEL: define{{.*}} void @test_add_assign() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[ADD:%.*]] = add <16 x i8> [[TMP1]], [[TMP0]]
Expand Down Expand Up @@ -534,7 +534,7 @@ void test_add_assign(void) {
fd += fd2;
}

// CHECK-LABEL: define void @test_sub() #0 {
// CHECK-LABEL: define{{.*}} void @test_sub() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[SUB:%.*]] = sub <16 x i8> [[TMP0]], [[TMP1]]
Expand Down Expand Up @@ -669,7 +669,7 @@ void test_sub(void) {
fd = fd - fd2;
}

// CHECK-LABEL: define void @test_sub_assign() #0 {
// CHECK-LABEL: define{{.*}} void @test_sub_assign() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[SUB:%.*]] = sub <16 x i8> [[TMP1]], [[TMP0]]
Expand Down Expand Up @@ -764,7 +764,7 @@ void test_sub_assign(void) {
fd -= fd2;
}

// CHECK-LABEL: define void @test_mul() #0 {
// CHECK-LABEL: define{{.*}} void @test_mul() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[MUL:%.*]] = mul <16 x i8> [[TMP0]], [[TMP1]]
Expand Down Expand Up @@ -819,7 +819,7 @@ void test_mul(void) {
fd = fd * fd2;
}

// CHECK-LABEL: define void @test_mul_assign() #0 {
// CHECK-LABEL: define{{.*}} void @test_mul_assign() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[MUL:%.*]] = mul <16 x i8> [[TMP1]], [[TMP0]]
Expand Down Expand Up @@ -874,7 +874,7 @@ void test_mul_assign(void) {
fd *= fd2;
}

// CHECK-LABEL: define void @test_div() #0 {
// CHECK-LABEL: define{{.*}} void @test_div() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[DIV:%.*]] = sdiv <16 x i8> [[TMP0]], [[TMP1]]
Expand Down Expand Up @@ -929,7 +929,7 @@ void test_div(void) {
fd = fd / fd2;
}

// CHECK-LABEL: define void @test_div_assign() #0 {
// CHECK-LABEL: define{{.*}} void @test_div_assign() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[DIV:%.*]] = sdiv <16 x i8> [[TMP1]], [[TMP0]]
Expand Down Expand Up @@ -984,7 +984,7 @@ void test_div_assign(void) {
fd /= fd2;
}

// CHECK-LABEL: define void @test_rem() #0 {
// CHECK-LABEL: define{{.*}} void @test_rem() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[REM:%.*]] = srem <16 x i8> [[TMP0]], [[TMP1]]
Expand Down Expand Up @@ -1033,7 +1033,7 @@ void test_rem(void) {
ul = ul % ul2;
}

// CHECK-LABEL: define void @test_rem_assign() #0 {
// CHECK-LABEL: define{{.*}} void @test_rem_assign() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[REM:%.*]] = srem <16 x i8> [[TMP1]], [[TMP0]]
Expand Down Expand Up @@ -1082,7 +1082,7 @@ void test_rem_assign(void) {
ul %= ul2;
}

// CHECK-LABEL: define void @test_not() #0 {
// CHECK-LABEL: define{{.*}} void @test_not() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[NEG:%.*]] = xor <16 x i8> [[TMP0]], <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
// CHECK: store volatile <16 x i8> [[NEG]], <16 x i8>* @sc, align 8
Expand Down Expand Up @@ -1139,7 +1139,7 @@ void test_not(void) {
bl = ~bl2;
}

// CHECK-LABEL: define void @test_and() #0 {
// CHECK-LABEL: define{{.*}} void @test_and() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[AND:%.*]] = and <16 x i8> [[TMP0]], [[TMP1]]
Expand Down Expand Up @@ -1288,7 +1288,7 @@ void test_and(void) {
bl = bl & bl2;
}

// CHECK-LABEL: define void @test_and_assign() #0 {
// CHECK-LABEL: define{{.*}} void @test_and_assign() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[AND:%.*]] = and <16 x i8> [[TMP1]], [[TMP0]]
Expand Down Expand Up @@ -1397,7 +1397,7 @@ void test_and_assign(void) {
bl &= bl2;
}

// CHECK-LABEL: define void @test_or() #0 {
// CHECK-LABEL: define{{.*}} void @test_or() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[OR:%.*]] = or <16 x i8> [[TMP0]], [[TMP1]]
Expand Down Expand Up @@ -1546,7 +1546,7 @@ void test_or(void) {
bl = bl | bl2;
}

// CHECK-LABEL: define void @test_or_assign() #0 {
// CHECK-LABEL: define{{.*}} void @test_or_assign() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[OR:%.*]] = or <16 x i8> [[TMP1]], [[TMP0]]
Expand Down Expand Up @@ -1655,7 +1655,7 @@ void test_or_assign(void) {
bl |= bl2;
}

// CHECK-LABEL: define void @test_xor() #0 {
// CHECK-LABEL: define{{.*}} void @test_xor() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[XOR:%.*]] = xor <16 x i8> [[TMP0]], [[TMP1]]
Expand Down Expand Up @@ -1804,7 +1804,7 @@ void test_xor(void) {
bl = bl ^ bl2;
}

// CHECK-LABEL: define void @test_xor_assign() #0 {
// CHECK-LABEL: define{{.*}} void @test_xor_assign() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[XOR:%.*]] = xor <16 x i8> [[TMP1]], [[TMP0]]
Expand Down Expand Up @@ -1913,7 +1913,7 @@ void test_xor_assign(void) {
bl ^= bl2;
}

// CHECK-LABEL: define void @test_sl() #0 {
// CHECK-LABEL: define{{.*}} void @test_sl() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[SHL:%.*]] = shl <16 x i8> [[TMP0]], [[TMP1]]
Expand Down Expand Up @@ -2096,7 +2096,7 @@ void test_sl(void) {
ul = ul << 5;
}

// CHECK-LABEL: define void @test_sl_assign() #0 {
// CHECK-LABEL: define{{.*}} void @test_sl_assign() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[SHL:%.*]] = shl <16 x i8> [[TMP1]], [[TMP0]]
Expand Down Expand Up @@ -2279,7 +2279,7 @@ void test_sl_assign(void) {
ul <<= 5;
}

// CHECK-LABEL: define void @test_sr() #0 {
// CHECK-LABEL: define{{.*}} void @test_sr() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[SHR:%.*]] = ashr <16 x i8> [[TMP0]], [[TMP1]]
Expand Down Expand Up @@ -2462,7 +2462,7 @@ void test_sr(void) {
ul = ul >> 5;
}

// CHECK-LABEL: define void @test_sr_assign() #0 {
// CHECK-LABEL: define{{.*}} void @test_sr_assign() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[SHR:%.*]] = ashr <16 x i8> [[TMP1]], [[TMP0]]
Expand Down Expand Up @@ -2646,7 +2646,7 @@ void test_sr_assign(void) {
}


// CHECK-LABEL: define void @test_cmpeq() #0 {
// CHECK-LABEL: define{{.*}} void @test_cmpeq() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[CMP:%.*]] = icmp eq <16 x i8> [[TMP0]], [[TMP1]]
Expand Down Expand Up @@ -2830,7 +2830,7 @@ void test_cmpeq(void) {
bl = fd == fd2;
}

// CHECK-LABEL: define void @test_cmpne() #0 {
// CHECK-LABEL: define{{.*}} void @test_cmpne() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[CMP:%.*]] = icmp ne <16 x i8> [[TMP0]], [[TMP1]]
Expand Down Expand Up @@ -3014,7 +3014,7 @@ void test_cmpne(void) {
bl = fd != fd2;
}

// CHECK-LABEL: define void @test_cmpge() #0 {
// CHECK-LABEL: define{{.*}} void @test_cmpge() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[CMP:%.*]] = icmp sge <16 x i8> [[TMP0]], [[TMP1]]
Expand Down Expand Up @@ -3102,7 +3102,7 @@ void test_cmpge(void) {
bl = fd >= fd2;
}

// CHECK-LABEL: define void @test_cmpgt() #0 {
// CHECK-LABEL: define{{.*}} void @test_cmpgt() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[CMP:%.*]] = icmp sgt <16 x i8> [[TMP0]], [[TMP1]]
Expand Down Expand Up @@ -3190,7 +3190,7 @@ void test_cmpgt(void) {
bl = fd > fd2;
}

// CHECK-LABEL: define void @test_cmple() #0 {
// CHECK-LABEL: define{{.*}} void @test_cmple() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[CMP:%.*]] = icmp sle <16 x i8> [[TMP0]], [[TMP1]]
Expand Down Expand Up @@ -3278,7 +3278,7 @@ void test_cmple(void) {
bl = fd <= fd2;
}

// CHECK-LABEL: define void @test_cmplt() #0 {
// CHECK-LABEL: define{{.*}} void @test_cmplt() #0 {
// CHECK: [[TMP0:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc, align 8
// CHECK: [[TMP1:%.*]] = load volatile <16 x i8>, <16 x i8>* @sc2, align 8
// CHECK: [[CMP:%.*]] = icmp slt <16 x i8> [[TMP0]], [[TMP1]]
Expand Down
100 changes: 50 additions & 50 deletions clang/test/CodeGen/X86/3dnow-builtins.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,176 +5,176 @@
#include <x86intrin.h>

__m64 test_m_pavgusb(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pavgusb
// GCC-LABEL: define double @test_m_pavgusb
// PS4-LABEL: define{{.*}} i64 @test_m_pavgusb
// GCC-LABEL: define{{.*}} double @test_m_pavgusb
// CHECK: @llvm.x86.3dnow.pavgusb
return _m_pavgusb(m1, m2);
}

__m64 test_m_pf2id(__m64 m) {
// PS4-LABEL: define i64 @test_m_pf2id
// GCC-LABEL: define double @test_m_pf2id
// PS4-LABEL: define{{.*}} i64 @test_m_pf2id
// GCC-LABEL: define{{.*}} double @test_m_pf2id
// CHECK: @llvm.x86.3dnow.pf2id
return _m_pf2id(m);
}

__m64 test_m_pfacc(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pfacc
// GCC-LABEL: define double @test_m_pfacc
// PS4-LABEL: define{{.*}} i64 @test_m_pfacc
// GCC-LABEL: define{{.*}} double @test_m_pfacc
// CHECK: @llvm.x86.3dnow.pfacc
return _m_pfacc(m1, m2);
}

__m64 test_m_pfadd(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pfadd
// GCC-LABEL: define double @test_m_pfadd
// PS4-LABEL: define{{.*}} i64 @test_m_pfadd
// GCC-LABEL: define{{.*}} double @test_m_pfadd
// CHECK: @llvm.x86.3dnow.pfadd
return _m_pfadd(m1, m2);
}

__m64 test_m_pfcmpeq(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pfcmpeq
// GCC-LABEL: define double @test_m_pfcmpeq
// PS4-LABEL: define{{.*}} i64 @test_m_pfcmpeq
// GCC-LABEL: define{{.*}} double @test_m_pfcmpeq
// CHECK: @llvm.x86.3dnow.pfcmpeq
return _m_pfcmpeq(m1, m2);
}

__m64 test_m_pfcmpge(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pfcmpge
// GCC-LABEL: define double @test_m_pfcmpge
// PS4-LABEL: define{{.*}} i64 @test_m_pfcmpge
// GCC-LABEL: define{{.*}} double @test_m_pfcmpge
// CHECK: @llvm.x86.3dnow.pfcmpge
return _m_pfcmpge(m1, m2);
}

__m64 test_m_pfcmpgt(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pfcmpgt
// GCC-LABEL: define double @test_m_pfcmpgt
// PS4-LABEL: define{{.*}} i64 @test_m_pfcmpgt
// GCC-LABEL: define{{.*}} double @test_m_pfcmpgt
// CHECK: @llvm.x86.3dnow.pfcmpgt
return _m_pfcmpgt(m1, m2);
}

__m64 test_m_pfmax(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pfmax
// GCC-LABEL: define double @test_m_pfmax
// PS4-LABEL: define{{.*}} i64 @test_m_pfmax
// GCC-LABEL: define{{.*}} double @test_m_pfmax
// CHECK: @llvm.x86.3dnow.pfmax
return _m_pfmax(m1, m2);
}

__m64 test_m_pfmin(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pfmin
// GCC-LABEL: define double @test_m_pfmin
// PS4-LABEL: define{{.*}} i64 @test_m_pfmin
// GCC-LABEL: define{{.*}} double @test_m_pfmin
// CHECK: @llvm.x86.3dnow.pfmin
return _m_pfmin(m1, m2);
}

__m64 test_m_pfmul(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pfmul
// GCC-LABEL: define double @test_m_pfmul
// PS4-LABEL: define{{.*}} i64 @test_m_pfmul
// GCC-LABEL: define{{.*}} double @test_m_pfmul
// CHECK: @llvm.x86.3dnow.pfmul
return _m_pfmul(m1, m2);
}

__m64 test_m_pfrcp(__m64 m) {
// PS4-LABEL: define i64 @test_m_pfrcp
// GCC-LABEL: define double @test_m_pfrcp
// PS4-LABEL: define{{.*}} i64 @test_m_pfrcp
// GCC-LABEL: define{{.*}} double @test_m_pfrcp
// CHECK: @llvm.x86.3dnow.pfrcp
return _m_pfrcp(m);
}

__m64 test_m_pfrcpit1(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pfrcpit1
// GCC-LABEL: define double @test_m_pfrcpit1
// PS4-LABEL: define{{.*}} i64 @test_m_pfrcpit1
// GCC-LABEL: define{{.*}} double @test_m_pfrcpit1
// CHECK: @llvm.x86.3dnow.pfrcpit1
return _m_pfrcpit1(m1, m2);
}

__m64 test_m_pfrcpit2(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pfrcpit2
// GCC-LABEL: define double @test_m_pfrcpit2
// PS4-LABEL: define{{.*}} i64 @test_m_pfrcpit2
// GCC-LABEL: define{{.*}} double @test_m_pfrcpit2
// CHECK: @llvm.x86.3dnow.pfrcpit2
return _m_pfrcpit2(m1, m2);
}

__m64 test_m_pfrsqrt(__m64 m) {
// PS4-LABEL: define i64 @test_m_pfrsqrt
// GCC-LABEL: define double @test_m_pfrsqrt
// PS4-LABEL: define{{.*}} i64 @test_m_pfrsqrt
// GCC-LABEL: define{{.*}} double @test_m_pfrsqrt
// CHECK: @llvm.x86.3dnow.pfrsqrt
return _m_pfrsqrt(m);
}

__m64 test_m_pfrsqrtit1(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pfrsqrtit1
// GCC-LABEL: define double @test_m_pfrsqrtit1
// PS4-LABEL: define{{.*}} i64 @test_m_pfrsqrtit1
// GCC-LABEL: define{{.*}} double @test_m_pfrsqrtit1
// CHECK: @llvm.x86.3dnow.pfrsqit1
return _m_pfrsqrtit1(m1, m2);
}

__m64 test_m_pfsub(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pfsub
// GCC-LABEL: define double @test_m_pfsub
// PS4-LABEL: define{{.*}} i64 @test_m_pfsub
// GCC-LABEL: define{{.*}} double @test_m_pfsub
// CHECK: @llvm.x86.3dnow.pfsub
return _m_pfsub(m1, m2);
}

__m64 test_m_pfsubr(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pfsubr
// GCC-LABEL: define double @test_m_pfsubr
// PS4-LABEL: define{{.*}} i64 @test_m_pfsubr
// GCC-LABEL: define{{.*}} double @test_m_pfsubr
// CHECK: @llvm.x86.3dnow.pfsubr
return _m_pfsubr(m1, m2);
}

__m64 test_m_pi2fd(__m64 m) {
// PS4-LABEL: define i64 @test_m_pi2fd
// GCC-LABEL: define double @test_m_pi2fd
// PS4-LABEL: define{{.*}} i64 @test_m_pi2fd
// GCC-LABEL: define{{.*}} double @test_m_pi2fd
// CHECK: @llvm.x86.3dnow.pi2fd
return _m_pi2fd(m);
}

__m64 test_m_pmulhrw(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pmulhrw
// GCC-LABEL: define double @test_m_pmulhrw
// PS4-LABEL: define{{.*}} i64 @test_m_pmulhrw
// GCC-LABEL: define{{.*}} double @test_m_pmulhrw
// CHECK: @llvm.x86.3dnow.pmulhrw
return _m_pmulhrw(m1, m2);
}

__m64 test_m_pf2iw(__m64 m) {
// PS4-LABEL: define i64 @test_m_pf2iw
// GCC-LABEL: define double @test_m_pf2iw
// PS4-LABEL: define{{.*}} i64 @test_m_pf2iw
// GCC-LABEL: define{{.*}} double @test_m_pf2iw
// CHECK: @llvm.x86.3dnowa.pf2iw
return _m_pf2iw(m);
}

__m64 test_m_pfnacc(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pfnacc
// GCC-LABEL: define double @test_m_pfnacc
// PS4-LABEL: define{{.*}} i64 @test_m_pfnacc
// GCC-LABEL: define{{.*}} double @test_m_pfnacc
// CHECK: @llvm.x86.3dnowa.pfnacc
return _m_pfnacc(m1, m2);
}

__m64 test_m_pfpnacc(__m64 m1, __m64 m2) {
// PS4-LABEL: define i64 @test_m_pfpnacc
// GCC-LABEL: define double @test_m_pfpnacc
// PS4-LABEL: define{{.*}} i64 @test_m_pfpnacc
// GCC-LABEL: define{{.*}} double @test_m_pfpnacc
// CHECK: @llvm.x86.3dnowa.pfpnacc
return _m_pfpnacc(m1, m2);
}

__m64 test_m_pi2fw(__m64 m) {
// PS4-LABEL: define i64 @test_m_pi2fw
// GCC-LABEL: define double @test_m_pi2fw
// PS4-LABEL: define{{.*}} i64 @test_m_pi2fw
// GCC-LABEL: define{{.*}} double @test_m_pi2fw
// CHECK: @llvm.x86.3dnowa.pi2fw
return _m_pi2fw(m);
}

__m64 test_m_pswapdsf(__m64 m) {
// PS4-LABEL: define i64 @test_m_pswapdsf
// GCC-LABEL: define double @test_m_pswapdsf
// PS4-LABEL: define{{.*}} i64 @test_m_pswapdsf
// GCC-LABEL: define{{.*}} double @test_m_pswapdsf
// CHECK: @llvm.x86.3dnowa.pswapd
return _m_pswapdsf(m);
}

__m64 test_m_pswapdsi(__m64 m) {
// PS4-LABEL: define i64 @test_m_pswapdsi
// GCC-LABEL: define double @test_m_pswapdsi
// PS4-LABEL: define{{.*}} i64 @test_m_pswapdsi
// GCC-LABEL: define{{.*}} double @test_m_pswapdsi
// CHECK: @llvm.x86.3dnowa.pswapd
return _m_pswapdsi(m);
}
2 changes: 1 addition & 1 deletion clang/test/CodeGen/X86/avx-union.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ extern void foo1(union M256 A);
extern void foo2(union M512 A);
union M256 m1;
union M512 m2;
// CHECK-LABEL: define void @test()
// CHECK-LABEL: define{{.*}} void @test()
// CHECK: call void @foo1(<4 x double>
// CHECK-LEGACY: call void @foo1(%union.M256* byval(%union.M256) align 32
// AVX: call void @foo2(%union.M512* byval(%union.M512) align 64
Expand Down
4 changes: 2 additions & 2 deletions clang/test/CodeGen/X86/prefetchw-builtins.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,12 +5,12 @@

void test_m_prefetch(void *p) {
return _m_prefetch(p);
// CHECK-LABEL: define void @test_m_prefetch
// CHECK-LABEL: define{{.*}} void @test_m_prefetch
// CHECK: call void @llvm.prefetch.p0i8({{.*}}, i32 0, i32 3, i32 1)
}

void test_m_prefetch_w(void *p) {
return _m_prefetchw(p);
// CHECK-LABEL: define void @test_m_prefetch_w
// CHECK-LABEL: define{{.*}} void @test_m_prefetch_w
// CHECK: call void @llvm.prefetch.p0i8({{.*}}, i32 1, i32 3, i32 1)
}
12 changes: 6 additions & 6 deletions clang/test/CodeGen/X86/x86-inline-asm-min-vector-width.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,38 +4,38 @@ typedef long long __m128i __attribute__ ((vector_size (16)));
typedef long long __m256i __attribute__ ((vector_size (32)));
typedef long long __m512i __attribute__ ((vector_size (64)));

// CHECK: define <2 x i64> @testXMMout(<2 x i64>* %p) #0
// CHECK: define{{.*}} <2 x i64> @testXMMout(<2 x i64>* %p) #0
__m128i testXMMout(__m128i *p) {
__m128i xmm0;
__asm__("vmovdqu %1, %0" :"=v"(xmm0) : "m"(*(__m128i*)p));
return xmm0;
}

// CHECK: define <4 x i64> @testYMMout(<4 x i64>* %p) #1
// CHECK: define{{.*}} <4 x i64> @testYMMout(<4 x i64>* %p) #1
__m256i testYMMout(__m256i *p) {
__m256i ymm0;
__asm__("vmovdqu %1, %0" :"=v"(ymm0) : "m"(*(__m256i*)p));
return ymm0;
}

// CHECK: define <8 x i64> @testZMMout(<8 x i64>* %p) #2
// CHECK: define{{.*}} <8 x i64> @testZMMout(<8 x i64>* %p) #2
__m512i testZMMout(__m512i *p) {
__m512i zmm0;
__asm__("vmovdqu64 %1, %0" :"=v"(zmm0) : "m"(*(__m512i*)p));
return zmm0;
}

// CHECK: define void @testXMMin(<2 x i64> %xmm0, <2 x i64>* %p) #0
// CHECK: define{{.*}} void @testXMMin(<2 x i64> %xmm0, <2 x i64>* %p) #0
void testXMMin(__m128i xmm0, __m128i *p) {
__asm__("vmovdqu %0, %1" : : "v"(xmm0), "m"(*(__m128i*)p));
}

// CHECK: define void @testYMMin(<4 x i64> %ymm0, <4 x i64>* %p) #1
// CHECK: define{{.*}} void @testYMMin(<4 x i64> %ymm0, <4 x i64>* %p) #1
void testYMMin(__m256i ymm0, __m256i *p) {
__asm__("vmovdqu %0, %1" : : "v"(ymm0), "m"(*(__m256i*)p));
}

// CHECK: define void @testZMMin(<8 x i64> %zmm0, <8 x i64>* %p) #2
// CHECK: define{{.*}} void @testZMMin(<8 x i64> %zmm0, <8 x i64>* %p) #2
void testZMMin(__m512i zmm0, __m512i *p) {
__asm__("vmovdqu64 %0, %1" : : "v"(zmm0), "m"(*(__m512i*)p));
}
Expand Down
4 changes: 2 additions & 2 deletions clang/test/CodeGen/X86/x86-soft-float.c
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// RUN: %clang_cc1 -triple i386-unknown-unknown -mregparm 3 -emit-llvm %s -o - | FileCheck %s -check-prefix=HARD
// RUN: %clang_cc1 -triple i386-unknown-unknown -mregparm 3 -mfloat-abi soft -emit-llvm %s -o - | FileCheck %s -check-prefix=SOFT

// HARD: define void @f1(float %a)
// SOFT: define void @f1(float inreg %a)
// HARD: define{{.*}} void @f1(float %a)
// SOFT: define{{.*}} void @f1(float inreg %a)
void f1(float a) {}
32 changes: 16 additions & 16 deletions clang/test/CodeGen/X86/x86_32-arguments-iamcu.c
View file
Original file line number Diff line number Diff line change
@@ -1,18 +1,18 @@
// RUN: %clang_cc1 -w -triple i386-pc-elfiamcu -mfloat-abi soft -emit-llvm -o - %s | FileCheck %s

// CHECK-LABEL: define void @ints(i32 %a, i32 %b, i32 %c, i32 %d)
// CHECK-LABEL: define{{.*}} void @ints(i32 %a, i32 %b, i32 %c, i32 %d)
void ints(int a, int b, int c, int d) {}

// CHECK-LABEL: define void @floats(float %a, float %b, float %c, float %d)
// CHECK-LABEL: define{{.*}} void @floats(float %a, float %b, float %c, float %d)
void floats(float a, float b, float c, float d) {}

// CHECK-LABEL: define void @mixed(i32 %a, float %b, i32 %c, float %d)
// CHECK-LABEL: define{{.*}} void @mixed(i32 %a, float %b, i32 %c, float %d)
void mixed(int a, float b, int c, float d) {}

// CHECK-LABEL: define void @doubles(double %d1, double %d2)
// CHECK-LABEL: define{{.*}} void @doubles(double %d1, double %d2)
void doubles(double d1, double d2) {}

// CHECK-LABEL: define void @mixedDoubles(i32 %a, double %d1)
// CHECK-LABEL: define{{.*}} void @mixedDoubles(i32 %a, double %d1)
void mixedDoubles(int a, double d1) {}

typedef struct st3_t {
Expand All @@ -34,36 +34,36 @@ typedef struct st12_t {
int c;
} st12_t;

// CHECK-LABEL: define void @smallStructs(i32 %st1.coerce, i32 %st2.coerce, i32 %st3.coerce)
// CHECK-LABEL: define{{.*}} void @smallStructs(i32 %st1.coerce, i32 %st2.coerce, i32 %st3.coerce)
void smallStructs(st4_t st1, st4_t st2, st4_t st3) {}

// CHECK-LABEL: define void @paddedStruct(i32 %i1, i32 %st.coerce0, i32 %st.coerce1, i32 %st4.0)
// CHECK-LABEL: define{{.*}} void @paddedStruct(i32 %i1, i32 %st.coerce0, i32 %st.coerce1, i32 %st4.0)
void paddedStruct(int i1, st5_t st, st4_t st4) {}

// CHECK-LABEL: define void @largeStructBegin(%struct.st12_t* byval(%struct.st12_t) align 4 %st)
// CHECK-LABEL: define{{.*}} void @largeStructBegin(%struct.st12_t* byval(%struct.st12_t) align 4 %st)
void largeStructBegin(st12_t st) {}

// CHECK-LABEL: define void @largeStructMiddle(i32 %i1, %struct.st12_t* byval(%struct.st12_t) align 4 %st, i32 %i2, i32 %i3)
// CHECK-LABEL: define{{.*}} void @largeStructMiddle(i32 %i1, %struct.st12_t* byval(%struct.st12_t) align 4 %st, i32 %i2, i32 %i3)
void largeStructMiddle(int i1, st12_t st, int i2, int i3) {}

// CHECK-LABEL: define void @largeStructEnd(i32 %i1, i32 %i2, i32 %i3, i32 %st.0, i32 %st.1, i32 %st.2)
// CHECK-LABEL: define{{.*}} void @largeStructEnd(i32 %i1, i32 %i2, i32 %i3, i32 %st.0, i32 %st.1, i32 %st.2)
void largeStructEnd(int i1, int i2, int i3, st12_t st) {}

// CHECK-LABEL: define i24 @retNonPow2Struct(i32 %r.coerce)
// CHECK-LABEL: define{{.*}} i24 @retNonPow2Struct(i32 %r.coerce)
st3_t retNonPow2Struct(st3_t r) { return r; }

// CHECK-LABEL: define i32 @retSmallStruct(i32 %r.coerce)
// CHECK-LABEL: define{{.*}} i32 @retSmallStruct(i32 %r.coerce)
st4_t retSmallStruct(st4_t r) { return r; }

// CHECK-LABEL: define i64 @retPaddedStruct(i32 %r.coerce0, i32 %r.coerce1)
// CHECK-LABEL: define{{.*}} i64 @retPaddedStruct(i32 %r.coerce0, i32 %r.coerce1)
st5_t retPaddedStruct(st5_t r) { return r; }

// CHECK-LABEL: define void @retLargeStruct(%struct.st12_t* noalias sret(%struct.st12_t) align 4 %agg.result, i32 %i1, %struct.st12_t* byval(%struct.st12_t) align 4 %r)
// CHECK-LABEL: define{{.*}} void @retLargeStruct(%struct.st12_t* noalias sret(%struct.st12_t) align 4 %agg.result, i32 %i1, %struct.st12_t* byval(%struct.st12_t) align 4 %r)
st12_t retLargeStruct(int i1, st12_t r) { return r; }

// CHECK-LABEL: define i32 @varArgs(i32 %i1, ...)
// CHECK-LABEL: define{{.*}} i32 @varArgs(i32 %i1, ...)
int varArgs(int i1, ...) { return i1; }

// CHECK-LABEL: define double @longDoubleArg(double %ld1)
// CHECK-LABEL: define{{.*}} double @longDoubleArg(double %ld1)
long double longDoubleArg(long double ld1) { return ld1; }

2 changes: 1 addition & 1 deletion clang/test/CodeGen/X86/x86_32-arguments-linux.c
View file
Original file line number Diff line number Diff line change
@@ -1,7 +1,7 @@
// RUN: %clang_cc1 -w -fblocks -triple i386-pc-linux-gnu -target-cpu pentium4 -emit-llvm -o %t %s
// RUN: FileCheck < %t %s

// CHECK-LABEL: define void @f56(
// CHECK-LABEL: define{{.*}} void @f56(
// CHECK: i8 signext %a0, %struct.s56_0* byval(%struct.s56_0) align 4 %a1,
// CHECK: i64 %a2.coerce, %struct.s56_1* byval(%struct.s56_1) align 4 %0,
// CHECK: <1 x double> %a4, %struct.s56_2* byval(%struct.s56_2) align 4 %1,
Expand Down
4 changes: 2 additions & 2 deletions clang/test/CodeGen/X86/x86_32-arguments-nommx.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,9 +3,9 @@
// no-mmx should put mmx into memory
typedef int __attribute__((vector_size (8))) i32v2;
int a(i32v2 x) { return x[0]; }
// CHECK-LABEL: define i32 @a(i64 %x.coerce)
// CHECK-LABEL: define{{.*}} i32 @a(i64 %x.coerce)

// but SSE2 vectors should still go into an SSE2 register
typedef int __attribute__((vector_size (16))) i32v4;
int b(i32v4 x) { return x[0]; }
// CHECK-LABEL: define i32 @b(<4 x i32> %x)
// CHECK-LABEL: define{{.*}} i32 @b(<4 x i32> %x)
26 changes: 13 additions & 13 deletions clang/test/CodeGen/X86/x86_64-arguments-nacl.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,60 +15,60 @@ struct PP_Var {
union PP_VarValue value;
};

// CHECK: define { i64, i64 } @f0()
// CHECK: define{{.*}} { i64, i64 } @f0()
struct PP_Var f0() {
struct PP_Var result = { 0, 0, 0 };
return result;
}

// CHECK-LABEL: define void @f1(i64 %p1.coerce0, i64 %p1.coerce1)
// CHECK-LABEL: define{{.*}} void @f1(i64 %p1.coerce0, i64 %p1.coerce1)
void f1(struct PP_Var p1) { while(1) {} }

// long doubles are 64 bits on NaCl
// CHECK-LABEL: define double @f5()
// CHECK-LABEL: define{{.*}} double @f5()
long double f5(void) {
return 0;
}

// CHECK-LABEL: define void @f6(i8 signext %a0, i16 signext %a1, i32 %a2, i64 %a3, i8* %a4)
// CHECK-LABEL: define{{.*}} void @f6(i8 signext %a0, i16 signext %a1, i32 %a2, i64 %a3, i8* %a4)
void f6(char a0, short a1, int a2, long long a3, void *a4) {
}

// CHECK-LABEL: define i64 @f8_1()
// CHECK-LABEL: define void @f8_2(i64 %a0.coerce)
// CHECK-LABEL: define{{.*}} i64 @f8_1()
// CHECK-LABEL: define{{.*}} void @f8_2(i64 %a0.coerce)
union u8 {
long double a;
int b;
};
union u8 f8_1() { while (1) {} }
void f8_2(union u8 a0) {}

// CHECK-LABEL: define i64 @f9()
// CHECK-LABEL: define{{.*}} i64 @f9()
struct s9 { int a; int b; int : 0; } f9(void) { while (1) {} }

// CHECK-LABEL: define void @f10(i64 %a0.coerce)
// CHECK-LABEL: define{{.*}} void @f10(i64 %a0.coerce)
struct s10 { int a; int b; int : 0; };
void f10(struct s10 a0) {}

// CHECK-LABEL: define double @f11()
// CHECK-LABEL: define{{.*}} double @f11()
union { long double a; float b; } f11() { while (1) {} }

// CHECK-LABEL: define i32 @f12_0()
// CHECK-LABEL: define void @f12_1(i32 %a0.coerce)
// CHECK-LABEL: define{{.*}} i32 @f12_0()
// CHECK-LABEL: define{{.*}} void @f12_1(i32 %a0.coerce)
struct s12 { int a __attribute__((aligned(16))); };
struct s12 f12_0(void) { while (1) {} }
void f12_1(struct s12 a0) {}

// Check that sret parameter is accounted for when checking available integer
// registers.
// CHECK: define void @f13(%struct.s13_0* noalias sret(%struct.s13_0) align 8 %agg.result, i32 %a, i32 %b, i32 %c, i32 %d, {{.*}}* byval({{.*}}) align 8 %e, i32 %f)
// CHECK: define{{.*}} void @f13(%struct.s13_0* noalias sret(%struct.s13_0) align 8 %agg.result, i32 %a, i32 %b, i32 %c, i32 %d, {{.*}}* byval({{.*}}) align 8 %e, i32 %f)

struct s13_0 { long long f0[3]; };
struct s13_1 { long long f0[2]; };
struct s13_0 f13(int a, int b, int c, int d,
struct s13_1 e, int f) { while (1) {} }

// CHECK-LABEL: define void @f20(%struct.s20* byval(%struct.s20) align 32 %x)
// CHECK-LABEL: define{{.*}} void @f20(%struct.s20* byval(%struct.s20) align 32 %x)
struct __attribute__((aligned(32))) s20 {
int x;
int y;
Expand Down
92 changes: 46 additions & 46 deletions clang/test/CodeGen/X86/x86_64-arguments.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,111 +6,111 @@
// RUN: FileCheck %s -check-prefix=CHECK -check-prefix=AVX -check-prefix=AVX512
#include <stdarg.h>

// CHECK-LABEL: define signext i8 @f0()
// CHECK-LABEL: define{{.*}} signext i8 @f0()
char f0(void) {
return 0;
}

// CHECK-LABEL: define signext i16 @f1()
// CHECK-LABEL: define{{.*}} signext i16 @f1()
short f1(void) {
return 0;
}

// CHECK-LABEL: define i32 @f2()
// CHECK-LABEL: define{{.*}} i32 @f2()
int f2(void) {
return 0;
}

// CHECK-LABEL: define float @f3()
// CHECK-LABEL: define{{.*}} float @f3()
float f3(void) {
return 0;
}

// CHECK-LABEL: define double @f4()
// CHECK-LABEL: define{{.*}} double @f4()
double f4(void) {
return 0;
}

// CHECK-LABEL: define x86_fp80 @f5()
// CHECK-LABEL: define{{.*}} x86_fp80 @f5()
long double f5(void) {
return 0;
}

// CHECK-LABEL: define void @f6(i8 signext %a0, i16 signext %a1, i32 %a2, i64 %a3, i8* %a4)
// CHECK-LABEL: define{{.*}} void @f6(i8 signext %a0, i16 signext %a1, i32 %a2, i64 %a3, i8* %a4)
void f6(char a0, short a1, int a2, long long a3, void *a4) {
}

// CHECK-LABEL: define void @f7(i32 %a0)
// CHECK-LABEL: define{{.*}} void @f7(i32 %a0)
typedef enum { A, B, C } e7;
void f7(e7 a0) {
}

// Test merging/passing of upper eightbyte with X87 class.
//
// CHECK-LABEL: define void @f8_1(%union.u8* noalias sret(%union.u8) align 16 %agg.result)
// CHECK-LABEL: define void @f8_2(%union.u8* byval(%union.u8) align 16 %a0)
// CHECK-LABEL: define{{.*}} void @f8_1(%union.u8* noalias sret(%union.u8) align 16 %agg.result)
// CHECK-LABEL: define{{.*}} void @f8_2(%union.u8* byval(%union.u8) align 16 %a0)
union u8 {
long double a;
int b;
};
union u8 f8_1() { while (1) {} }
void f8_2(union u8 a0) {}

// CHECK-LABEL: define i64 @f9()
// CHECK-LABEL: define{{.*}} i64 @f9()
struct s9 { int a; int b; int : 0; } f9(void) { while (1) {} }

// CHECK-LABEL: define void @f10(i64 %a0.coerce)
// CHECK-LABEL: define{{.*}} void @f10(i64 %a0.coerce)
struct s10 { int a; int b; int : 0; };
void f10(struct s10 a0) {}

// CHECK-LABEL: define void @f11(%union.anon* noalias sret(%union.anon) align 16 %agg.result)
// CHECK-LABEL: define{{.*}} void @f11(%union.anon* noalias sret(%union.anon) align 16 %agg.result)
union { long double a; float b; } f11() { while (1) {} }

// CHECK-LABEL: define i32 @f12_0()
// CHECK-LABEL: define void @f12_1(i32 %a0.coerce)
// CHECK-LABEL: define{{.*}} i32 @f12_0()
// CHECK-LABEL: define{{.*}} void @f12_1(i32 %a0.coerce)
struct s12 { int a __attribute__((aligned(16))); };
struct s12 f12_0(void) { while (1) {} }
void f12_1(struct s12 a0) {}

// Check that sret parameter is accounted for when checking available integer
// registers.
// CHECK: define void @f13(%struct.s13_0* noalias sret(%struct.s13_0) align 8 %agg.result, i32 %a, i32 %b, i32 %c, i32 %d, {{.*}}* byval({{.*}}) align 8 %e, i32 %f)
// CHECK: define{{.*}} void @f13(%struct.s13_0* noalias sret(%struct.s13_0) align 8 %agg.result, i32 %a, i32 %b, i32 %c, i32 %d, {{.*}}* byval({{.*}}) align 8 %e, i32 %f)

struct s13_0 { long long f0[3]; };
struct s13_1 { long long f0[2]; };
struct s13_0 f13(int a, int b, int c, int d,
struct s13_1 e, int f) { while (1) {} }

// CHECK: define void @f14({{.*}}, i8 signext %X)
// CHECK: define{{.*}} void @f14({{.*}}, i8 signext %X)
void f14(int a, int b, int c, int d, int e, int f, char X) {}

// CHECK: define void @f15({{.*}}, i8* %X)
// CHECK: define{{.*}} void @f15({{.*}}, i8* %X)
void f15(int a, int b, int c, int d, int e, int f, void *X) {}

// CHECK: define void @f16({{.*}}, float %X)
// CHECK: define{{.*}} void @f16({{.*}}, float %X)
void f16(float a, float b, float c, float d, float e, float f, float g, float h,
float X) {}

// CHECK: define void @f17({{.*}}, x86_fp80 %X)
// CHECK: define{{.*}} void @f17({{.*}}, x86_fp80 %X)
void f17(float a, float b, float c, float d, float e, float f, float g, float h,
long double X) {}

// Check for valid coercion. The struct should be passed/returned as i32, not
// as i64 for better code quality.
// rdar://8135035
// CHECK-LABEL: define void @f18(i32 %a, i32 %f18_arg1.coerce)
// CHECK-LABEL: define{{.*}} void @f18(i32 %a, i32 %f18_arg1.coerce)
struct f18_s0 { int f0; };
void f18(int a, struct f18_s0 f18_arg1) { while (1) {} }

// Check byval alignment.

// CHECK-LABEL: define void @f19(%struct.s19* byval(%struct.s19) align 16 %x)
// CHECK-LABEL: define{{.*}} void @f19(%struct.s19* byval(%struct.s19) align 16 %x)
struct s19 {
long double a;
};
void f19(struct s19 x) {}

// CHECK-LABEL: define void @f20(%struct.s20* byval(%struct.s20) align 32 %x)
// CHECK-LABEL: define{{.*}} void @f20(%struct.s20* byval(%struct.s20) align 32 %x)
struct __attribute__((aligned(32))) s20 {
int x;
int y;
Expand All @@ -123,7 +123,7 @@ struct StringRef {
};

// rdar://7375902
// CHECK-LABEL: define i8* @f21(i64 %S.coerce0, i8* %S.coerce1)
// CHECK-LABEL: define{{.*}} i8* @f21(i64 %S.coerce0, i8* %S.coerce1)
const char *f21(struct StringRef S) { return S.x+S.Ptr; }

// PR7567
Expand All @@ -144,21 +144,21 @@ struct f23S {


void f23(int A, struct f23S B) {
// CHECK-LABEL: define void @f23(i32 %A, i64 %B.coerce0, i32 %B.coerce1)
// CHECK-LABEL: define{{.*}} void @f23(i32 %A, i64 %B.coerce0, i32 %B.coerce1)
}

struct f24s { long a; int b; };

struct f23S f24(struct f23S *X, struct f24s *P2) {
return *X;

// CHECK: define { i64, i32 } @f24(%struct.f23S* %X, %struct.f24s* %P2)
// CHECK: define{{.*}} { i64, i32 } @f24(%struct.f23S* %X, %struct.f24s* %P2)
}

// rdar://8248065
typedef float v4f32 __attribute__((__vector_size__(16)));
v4f32 f25(v4f32 X) {
// CHECK-LABEL: define <4 x float> @f25(<4 x float> %X)
// CHECK-LABEL: define{{.*}} <4 x float> @f25(<4 x float> %X)
// CHECK-NOT: alloca
// CHECK: alloca <4 x float>
// CHECK-NOT: alloca
Expand All @@ -174,7 +174,7 @@ struct foo26 {
};

struct foo26 f26(struct foo26 *P) {
// CHECK: define { i32*, float* } @f26(%struct.foo26* %P)
// CHECK: define{{.*}} { i32*, float* } @f26(%struct.foo26* %P)
return *P;
}

Expand All @@ -184,7 +184,7 @@ struct v4f32wrapper {
};

struct v4f32wrapper f27(struct v4f32wrapper X) {
// CHECK-LABEL: define <4 x float> @f27(<4 x float> %X.coerce)
// CHECK-LABEL: define{{.*}} <4 x float> @f27(<4 x float> %X.coerce)
return X;
}

Expand All @@ -197,7 +197,7 @@ struct v8f32wrapper {
};

struct v8f32wrapper f27a(struct v8f32wrapper X) {
// AVX-LABEL: define <8 x float> @f27a(<8 x float> %X.coerce)
// AVX-LABEL: define{{.*}} <8 x float> @f27a(<8 x float> %X.coerce)
return X;
}

Expand All @@ -206,7 +206,7 @@ struct v8f32wrapper_wrapper {
};

struct v8f32wrapper_wrapper f27b(struct v8f32wrapper_wrapper X) {
// AVX-LABEL: define <8 x float> @f27b(<8 x float> %X.coerce)
// AVX-LABEL: define{{.*}} <8 x float> @f27b(<8 x float> %X.coerce)
return X;
}

Expand All @@ -216,7 +216,7 @@ struct f28c {
int y;
};
void f28(struct f28c C) {
// CHECK-LABEL: define void @f28(double %C.coerce0, i32 %C.coerce1)
// CHECK-LABEL: define{{.*}} void @f28(double %C.coerce0, i32 %C.coerce1)
}

struct f29a {
Expand All @@ -227,26 +227,26 @@ struct f29a {
};

void f29a(struct f29a A) {
// CHECK-LABEL: define void @f29a(double %A.coerce0, i32 %A.coerce1)
// CHECK-LABEL: define{{.*}} void @f29a(double %A.coerce0, i32 %A.coerce1)
}

// rdar://8249586
struct S0 { char f0[8]; char f2; char f3; char f4; };
void f30(struct S0 p_4) {
// CHECK-LABEL: define void @f30(i64 %p_4.coerce0, i24 %p_4.coerce1)
// CHECK-LABEL: define{{.*}} void @f30(i64 %p_4.coerce0, i24 %p_4.coerce1)
}

// Pass the third element as a float when followed by tail padding.
// rdar://8251384
struct f31foo { float a, b, c; };
float f31(struct f31foo X) {
// CHECK-LABEL: define float @f31(<2 x float> %X.coerce0, float %X.coerce1)
// CHECK-LABEL: define{{.*}} float @f31(<2 x float> %X.coerce0, float %X.coerce1)
return X.c;
}

_Complex float f32(_Complex float A, _Complex float B) {
// rdar://6379669
// CHECK-LABEL: define <2 x float> @f32(<2 x float> %A.coerce, <2 x float> %B.coerce)
// CHECK-LABEL: define{{.*}} <2 x float> @f32(<2 x float> %A.coerce, <2 x float> %B.coerce)
return A+B;
}

Expand All @@ -261,12 +261,12 @@ void f33(va_list X) {
typedef unsigned long long v1i64 __attribute__((__vector_size__(8)));

// rdar://8359248
// CHECK-LABEL: define double @f34(double %arg.coerce)
// CHECK-LABEL: define{{.*}} double @f34(double %arg.coerce)
v1i64 f34(v1i64 arg) { return arg; }


// rdar://8358475
// CHECK-LABEL: define double @f35(double %arg.coerce)
// CHECK-LABEL: define{{.*}} double @f35(double %arg.coerce)
typedef unsigned long v1i64_2 __attribute__((__vector_size__(8)));
v1i64_2 f35(v1i64_2 arg) { return arg+arg; }

Expand All @@ -286,7 +286,7 @@ void f9122143()
func(ss);
}

// CHECK-LABEL: define double @f36(double %arg.coerce)
// CHECK-LABEL: define{{.*}} double @f36(double %arg.coerce)
typedef unsigned v2i32 __attribute((__vector_size__(8)));
v2i32 f36(v2i32 arg) { return arg; }

Expand Down Expand Up @@ -334,7 +334,7 @@ void func43(SA s) {
func42(s);
}

// CHECK-LABEL: define i32 @f44
// CHECK-LABEL: define{{.*}} i32 @f44
// CHECK: ptrtoint
// CHECK-NEXT: add i64 %{{[0-9]+}}, 31
// CHECK-NEXT: and i64 %{{[0-9]+}}, -32
Expand All @@ -350,7 +350,7 @@ int f44(int i, ...) {
}

// Text that vec3 returns the correct LLVM IR type.
// AVX-LABEL: define i32 @foo(<3 x i64> %X)
// AVX-LABEL: define{{.*}} i32 @foo(<3 x i64> %X)
typedef long long3 __attribute((ext_vector_type(3)));
int foo(long3 X)
{
Expand Down Expand Up @@ -406,7 +406,7 @@ void test49_helper(double, ...);
void test49(double d, double e) {
test49_helper(d, e);
}
// CHECK-LABEL: define void @test49(
// CHECK-LABEL: define{{.*}} void @test49(
// CHECK: [[T0:%.*]] = load double, double*
// CHECK-NEXT: [[T1:%.*]] = load double, double*
// CHECK-NEXT: call void (double, ...) @test49_helper(double [[T0]], double [[T1]])
Expand All @@ -415,7 +415,7 @@ void test50_helper();
void test50(double d, double e) {
test50_helper(d, e);
}
// CHECK-LABEL: define void @test50(
// CHECK-LABEL: define{{.*}} void @test50(
// CHECK: [[T0:%.*]] = load double, double*
// CHECK-NEXT: [[T1:%.*]] = load double, double*
// CHECK-NEXT: call void (double, double, ...) bitcast (void (...)* @test50_helper to void (double, double, ...)*)(double [[T0]], double [[T1]])
Expand All @@ -425,7 +425,7 @@ void test51(struct test51_s *s, __builtin_va_list argList) {
*s = __builtin_va_arg(argList, struct test51_s);
}

// CHECK-LABEL: define void @test51
// CHECK-LABEL: define{{.*}} void @test51
// CHECK: [[TMP_ADDR:%.*]] = alloca [[STRUCT_TEST51:%.*]], align 16
// CHECK: br i1
// CHECK: [[REG_SAVE_AREA_PTR:%.*]] = getelementptr inbounds {{.*}}, i32 0, i32 3
Expand All @@ -449,7 +449,7 @@ void test52() {
void test53(__m256 *m, __builtin_va_list argList) {
*m = __builtin_va_arg(argList, __m256);
}
// AVX-LABEL: define void @test53
// AVX-LABEL: define{{.*}} void @test53
// AVX-NOT: br i1
// AVX: ret void

Expand Down Expand Up @@ -521,7 +521,7 @@ void f62() {
// Like for __m256 on AVX, we always pass __m512 in memory, and don't
// need to use the register save area.
//
// AVX512-LABEL: define void @f63
// AVX512-LABEL: define{{.*}} void @f63
// AVX512-NOT: br i1
// AVX512: ret void
void f63(__m512 *m, __builtin_va_list argList) {
Expand Down
14 changes: 7 additions & 7 deletions clang/test/CodeGen/X86/x86_64-floatvectors.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ double Vec3FTest(__builtin_va_list ap) {
vec3f vec = __builtin_va_arg(ap, vec3f);
return vec.x + vec.y + vec.z;
}
// CHECK: define double @Vec3FTest
// CHECK: define{{.*}} double @Vec3FTest
// CHECK: vaarg.in_reg:
// CHECK: [[Vec3FLoad1:%.*]] = load <2 x float>, <2 x float>*
// CHECK: [[Vec3FGEP1:%.*]] = getelementptr inbounds { <2 x float>, float }, { <2 x float>, float }* {{%.*}}, i32 0, i32 0
Expand All @@ -28,7 +28,7 @@ double Vec4FTest(__builtin_va_list ap) {
vec4f vec = __builtin_va_arg(ap, vec4f);
return vec.x + vec.y + vec.z + vec.q;
}
// CHECK: define double @Vec4FTest
// CHECK: define{{.*}} double @Vec4FTest
// CHECK: vaarg.in_reg:
// CHECK: [[Vec4FLoad1:%.*]] = load <2 x float>, <2 x float>*
// CHECK: [[Vec4FGEP1:%.*]] = getelementptr inbounds { <2 x float>, <2 x float> }, { <2 x float>, <2 x float> }* {{%.*}}, i32 0, i32 0
Expand All @@ -44,7 +44,7 @@ double Vec2DTest(__builtin_va_list ap) {
vec2d vec = __builtin_va_arg(ap, vec2d);
return vec.x + vec.y;
}
// CHECK: define double @Vec2DTest
// CHECK: define{{.*}} double @Vec2DTest
// CHECK: vaarg.in_reg:
// CHECK: [[Vec2DLoad1:%.*]] = load double, double*
// CHECK: [[Vec2DGEP1:%.*]] = getelementptr inbounds { double, double }, { double, double }* {{%.*}}, i32 0, i32 0
Expand All @@ -63,7 +63,7 @@ double Vec2F1DTest(__builtin_va_list ap) {
vec2f1d vec = __builtin_va_arg(ap, vec2f1d);
return vec.x + vec.y + vec.z;
}
// CHECK: define double @Vec2F1DTest
// CHECK: define{{.*}} double @Vec2F1DTest
// CHECK: vaarg.in_reg:
// CHECK: [[Vec2F1DLoad1:%.*]] = load <2 x float>, <2 x float>*
// CHECK: [[Vec2F1DGEP1:%.*]] = getelementptr inbounds { <2 x float>, double }, { <2 x float>, double }* {{%.*}}, i32 0, i32 0
Expand All @@ -82,7 +82,7 @@ double Vec1D2FTest(__builtin_va_list ap) {
vec1d2f vec = __builtin_va_arg(ap, vec1d2f);
return vec.x + vec.y + vec.z;
}
// CHECK: define double @Vec1D2FTest
// CHECK: define{{.*}} double @Vec1D2FTest
// CHECK: vaarg.in_reg:
// CHECK: [[Vec1D2FLoad1:%.*]] = load double, double*
// CHECK: [[Vec1D2FGEP1:%.*]] = getelementptr inbounds { double, <2 x float> }, { double, <2 x float> }* {{%.*}}, i32 0, i32 0
Expand All @@ -101,7 +101,7 @@ double Vec1F1DTest(__builtin_va_list ap) {
vec1f1d vec = __builtin_va_arg(ap, vec1f1d);
return vec.x + vec.z;
}
// CHECK: define double @Vec1F1DTest
// CHECK: define{{.*}} double @Vec1F1DTest
// CHECK: vaarg.in_reg:
// CHECK: [[Vec1F1DLoad1:%.*]] = load float, float*
// CHECK: [[Vec1F1DGEP1:%.*]] = getelementptr inbounds { float, double }, { float, double }* {{%.*}}, i32 0, i32 0
Expand All @@ -120,7 +120,7 @@ double Vec1D1FTest(__builtin_va_list ap) {
vec1d1f vec = __builtin_va_arg(ap, vec1d1f);
return vec.x + vec.z;
}
// CHECK: define double @Vec1D1FTest
// CHECK: define{{.*}} double @Vec1D1FTest
// CHECK: vaarg.in_reg:
// CHECK: [[Vec1D1FLoad1:%.*]] = load double, double*
// CHECK: [[Vec1D1FGEP1:%.*]] = getelementptr inbounds { double, float }, { double, float }* {{%.*}}, i32 0, i32 0
Expand Down
54 changes: 27 additions & 27 deletions clang/test/CodeGen/X86/x86_64-longdouble.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,33 +11,33 @@
// Android uses fp128 for long double but other x86_64 targets use x86_fp80.

long double dataLD = 1.0L;
// ANDROID: @dataLD = local_unnamed_addr global fp128 0xL00000000000000003FFF000000000000, align 16
// GNU: @dataLD = local_unnamed_addr global x86_fp80 0xK3FFF8000000000000000, align 16
// ANDROID: @dataLD ={{.*}} local_unnamed_addr global fp128 0xL00000000000000003FFF000000000000, align 16
// GNU: @dataLD ={{.*}} local_unnamed_addr global x86_fp80 0xK3FFF8000000000000000, align 16

long double _Complex dataLDC = {1.0L, 1.0L};
// ANDROID: @dataLDC = local_unnamed_addr global { fp128, fp128 } { fp128 0xL00000000000000003FFF000000000000, fp128 0xL00000000000000003FFF000000000000 }, align 16
// GNU: @dataLDC = local_unnamed_addr global { x86_fp80, x86_fp80 } { x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000 }, align 16
// ANDROID: @dataLDC ={{.*}} local_unnamed_addr global { fp128, fp128 } { fp128 0xL00000000000000003FFF000000000000, fp128 0xL00000000000000003FFF000000000000 }, align 16
// GNU: @dataLDC ={{.*}} local_unnamed_addr global { x86_fp80, x86_fp80 } { x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000 }, align 16

long double TestLD(long double x) {
return x * x;
// ANDROID: define fp128 @TestLD(fp128 %x)
// GNU: define x86_fp80 @TestLD(x86_fp80 %x)
// NACL: define double @TestLD(double %x)
// ANDROID: define{{.*}} fp128 @TestLD(fp128 %x)
// GNU: define{{.*}} x86_fp80 @TestLD(x86_fp80 %x)
// NACL: define{{.*}} double @TestLD(double %x)
}

long double _Complex TestLDC(long double _Complex x) {
return x * x;
// ANDROID: define void @TestLDC({ fp128, fp128 }* {{.*}}, { fp128, fp128 }* {{.*}} %x)
// GNU: define { x86_fp80, x86_fp80 } @TestLDC({ x86_fp80, x86_fp80 }* {{.*}} %x)
// NACL: define { double, double } @TestLDC(double %x{{.*}}, double %x{{.*}})
// ANDROID: define{{.*}} void @TestLDC({ fp128, fp128 }* {{.*}}, { fp128, fp128 }* {{.*}} %x)
// GNU: define{{.*}} { x86_fp80, x86_fp80 } @TestLDC({ x86_fp80, x86_fp80 }* {{.*}} %x)
// NACL: define{{.*}} { double, double } @TestLDC(double %x{{.*}}, double %x{{.*}})
}

typedef __builtin_va_list va_list;

int TestGetVarInt(va_list ap) {
return __builtin_va_arg(ap, int);
// Since int can be passed in memory or register there are two branches.
// CHECK: define i32 @TestGetVarInt(
// CHECK: define{{.*}} i32 @TestGetVarInt(
// CHECK: br label
// CHECK: br label
// CHECK: = phi
Expand All @@ -47,7 +47,7 @@ int TestGetVarInt(va_list ap) {
double TestGetVarDouble(va_list ap) {
return __builtin_va_arg(ap, double);
// Since double can be passed in memory or register there are two branches.
// CHECK: define double @TestGetVarDouble(
// CHECK: define{{.*}} double @TestGetVarDouble(
// CHECK: br label
// CHECK: br label
// CHECK: = phi
Expand All @@ -58,9 +58,9 @@ long double TestGetVarLD(va_list ap) {
return __builtin_va_arg(ap, long double);
// fp128 and double can be passed in memory or in register, but x86_fp80 is in
// memory.
// ANDROID: define fp128 @TestGetVarLD(
// GNU: define x86_fp80 @TestGetVarLD(
// NACL: define double @TestGetVarLD(
// ANDROID: define{{.*}} fp128 @TestGetVarLD(
// GNU: define{{.*}} x86_fp80 @TestGetVarLD(
// NACL: define{{.*}} double @TestGetVarLD(
// ANDROID: br label
// ANDROID: br label
// NACL: br
Expand All @@ -75,10 +75,10 @@ long double TestGetVarLD(va_list ap) {
long double _Complex TestGetVarLDC(va_list ap) {
return __builtin_va_arg(ap, long double _Complex);
// Pair of fp128 or x86_fp80 are passed as struct in memory.
// ANDROID: define void @TestGetVarLDC({ fp128, fp128 }* {{.*}}, %struct.__va_list_tag*
// GNU: define { x86_fp80, x86_fp80 } @TestGetVarLDC(
// ANDROID: define{{.*}} void @TestGetVarLDC({ fp128, fp128 }* {{.*}}, %struct.__va_list_tag*
// GNU: define{{.*}} { x86_fp80, x86_fp80 } @TestGetVarLDC(
// Pair of double can go in SSE registers or memory
// NACL: define { double, double } @TestGetVarLDC(
// NACL: define{{.*}} { double, double } @TestGetVarLDC(
// ANDROID-NOT: br
// GNU-NOT: br
// NACL: br
Expand All @@ -94,42 +94,42 @@ void TestVarArg(const char *s, ...);

void TestPassVarInt(int x) {
TestVarArg("A", x);
// CHECK: define void @TestPassVarInt(i32 %x)
// CHECK: define{{.*}} void @TestPassVarInt(i32 %x)
// CHECK: call {{.*}} @TestVarArg(i8* {{.*}}, i32 %x)
}

void TestPassVarFloat(float x) {
TestVarArg("A", x);
// CHECK: define void @TestPassVarFloat(float %x)
// CHECK: define{{.*}} void @TestPassVarFloat(float %x)
// CHECK: call {{.*}} @TestVarArg(i8* {{.*}}, double %
}

void TestPassVarDouble(double x) {
TestVarArg("A", x);
// CHECK: define void @TestPassVarDouble(double %x)
// CHECK: define{{.*}} void @TestPassVarDouble(double %x)
// CHECK: call {{.*}} @TestVarArg(i8* {{.*}}, double %x
}

void TestPassVarLD(long double x) {
TestVarArg("A", x);
// ANDROID: define void @TestPassVarLD(fp128 %x)
// ANDROID: define{{.*}} void @TestPassVarLD(fp128 %x)
// ANDROID: call {{.*}} @TestVarArg(i8* {{.*}}, fp128 %x
// GNU: define void @TestPassVarLD(x86_fp80 %x)
// GNU: define{{.*}} void @TestPassVarLD(x86_fp80 %x)
// GNU: call {{.*}} @TestVarArg(i8* {{.*}}, x86_fp80 %x
// NACL: define void @TestPassVarLD(double %x)
// NACL: define{{.*}} void @TestPassVarLD(double %x)
// NACL: call {{.*}} @TestVarArg(i8* {{.*}}, double %x
}

void TestPassVarLDC(long double _Complex x) {
TestVarArg("A", x);
// ANDROID: define void @TestPassVarLDC({ fp128, fp128 }* {{.*}} %x)
// ANDROID: define{{.*}} void @TestPassVarLDC({ fp128, fp128 }* {{.*}} %x)
// ANDROID: store fp128 %{{.*}}, fp128* %
// ANDROID-NEXT: store fp128 %{{.*}}, fp128* %
// ANDROID-NEXT: call {{.*}} @TestVarArg(i8* {{.*}}, { fp128, fp128 }* {{.*}} %
// GNU: define void @TestPassVarLDC({ x86_fp80, x86_fp80 }* {{.*}} %x)
// GNU: define{{.*}} void @TestPassVarLDC({ x86_fp80, x86_fp80 }* {{.*}} %x)
// GNU: store x86_fp80 %{{.*}}, x86_fp80* %
// GNU-NEXT: store x86_fp80 %{{.*}}, x86_fp80* %
// GNU-NEXT: call {{.*}} @TestVarArg(i8* {{.*}}, { x86_fp80, x86_fp80 }* {{.*}} %
// NACL: define void @TestPassVarLDC(double %x{{.*}}, double %x{{.*}})
// NACL: define{{.*}} void @TestPassVarLDC(double %x{{.*}}, double %x{{.*}})
// NACL: call {{.*}} @TestVarArg(i8* {{.*}}, double %x{{.*}}, double %x{{.*}})
}
2 changes: 1 addition & 1 deletion clang/test/CodeGen/_Bool-conversion.c
View file
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// RUN: %clang_cc1 -triple i386 -emit-llvm -O2 -o - %s | FileCheck %s

// CHECK-LABEL: define i32 @f0()
// CHECK-LABEL: define{{.*}} i32 @f0()
// CHECK: ret i32 1
// CHECK: }

Expand Down
14 changes: 7 additions & 7 deletions clang/test/CodeGen/aapcs-align.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ void g0() {
f0(1, s);
f0m(1, 2, 3, 4, 5, s);
}
// CHECK: define void @g0
// CHECK: define{{.*}} void @g0
// CHECK: call void @f0(i32 1, [2 x i32] [i32 6, i32 7]
// CHECK: call void @f0m(i32 1, i32 2, i32 3, i32 4, i32 5, [2 x i32] [i32 6, i32 7]
// CHECK: declare void @f0(i32, [2 x i32])
Expand All @@ -36,7 +36,7 @@ void g1() {
f1(1, s);
f1m(1, 2, 3, 4, 5, s);
}
// CHECK: define void @g1
// CHECK: define{{.*}} void @g1
// CHECK: call void @f1(i32 1, [2 x i32] [i32 6, i32 7]
// CHECK: call void @f1m(i32 1, i32 2, i32 3, i32 4, i32 5, [2 x i32] [i32 6, i32 7]
// CHECK: declare void @f1(i32, [2 x i32])
Expand All @@ -55,7 +55,7 @@ void g2() {
f2(1, s);
f2m(1, 2, 3, 4, 5, s);
}
// CHECK: define void @g2
// CHECK: define{{.*}} void @g2
// CHECK: call void @f2(i32 1, [4 x i32] [i32 6, i32 7
// CHECK: call void @f2m(i32 1, i32 2, i32 3, i32 4, i32 5, [4 x i32] [i32 6, i32 7
// CHECK: declare void @f2(i32, [4 x i32])
Expand All @@ -74,7 +74,7 @@ void g3() {
f3(1, s);
f3m(1, 2, 3, 4, 5, s);
}
// CHECK: define void @g3
// CHECK: define{{.*}} void @g3
// CHECK: call void @f3(i32 1, [1 x i64] [i64 30064771078]
// CHECK: call void @f3m(i32 1, i32 2, i32 3, i32 4, i32 5, [1 x i64] [i64 30064771078]
// CHECK: declare void @f3(i32, [1 x i64])
Expand All @@ -94,7 +94,7 @@ void g4() {
f4(1, s);
f4m(1, 2, 3, 4, 5, s);
}
// CHECK: define void @g4
// CHECK: define{{.*}} void @g4
// CHECK: call void @f4(i32 1, %struct.SF16* nonnull byval(%struct.SF16) align 8
// CHECK: call void @f4m(i32 1, i32 2, i32 3, i32 4, i32 5, %struct.SF16* nonnull byval(%struct.SF16) align 8
// CHECK: declare void @f4(i32, %struct.SF16* byval(%struct.SF16) align 8)
Expand All @@ -113,7 +113,7 @@ void g5() {
f5(1, s);
f5m(1, 2, 3, 4, 5, s);
}
// CHECK: define void @g5
// CHECK: define{{.*}} void @g5
// CHECK: call void @f5(i32 1, [3 x i32] [i32 6, i32 7, i32 0])
// CHECK: call void @f5m(i32 1, i32 2, i32 3, i32 4, i32 5, [3 x i32] [i32 6, i32 7, i32 0])
// CHECK: declare void @f5(i32, [3 x i32])
Expand All @@ -133,7 +133,7 @@ void g6() {
f6(1, s);
f6m(1, 2, 3, 4, 5, s);
}
// CHECK: define void @g6
// CHECK: define{{.*}} void @g6
// CHECK: call void @f6(i32 1, [4 x i32] [i32 6, i32 7, i32 0, i32 0])
// CHECK: call void @f6m(i32 1, i32 2, i32 3, i32 4, i32 5, [4 x i32] [i32 6, i32 7, i32 0, i32 0])
// CHECK: declare void @f6(i32, [4 x i32])
Expand Down
10 changes: 5 additions & 5 deletions clang/test/CodeGen/aapcs64-align.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ void g0() {
f0(1, s);
f0m(1, 2, 3, 4, 5, s);
}
// CHECK: define void @g0
// CHECK: define{{.*}} void @g0
// CHECK: call void @f0(i64 1, [2 x i64] [i64 6, i64 7]
// CHECK: call void @f0m{{.*}}[2 x i64] [i64 6, i64 7]
// CHECK: declare void @f0(i64, [2 x i64])
Expand All @@ -35,7 +35,7 @@ void g1() {
f1(1, s);
f1m(1, 2, 3, 4, 5, s);
}
// CHECK: define void @g1
// CHECK: define{{.*}} void @g1
// CHECK: call void @f1{{.*}}[2 x i64] [i64 6, i64 7]
// CHECK: call void @f1m{{.*}}[2 x i64] [i64 6, i64 7]
// CHECK: declare void @f1(i64, [2 x i64])
Expand All @@ -54,7 +54,7 @@ void g3() {
f3(1, s);
f3m(1, 2, 3, 4, 5, s);
}
// CHECK: define void @g3
// CHECK: define{{.*}} void @g3
// CHECK: call void @f3(i64 1, i128 129127208515966861318)
// CHECK: call void @f3m(i64 1, i64 2, i64 3, i64 4, i64 5, i128 129127208515966861318)
// CHECK: declare void @f3(i64, i128)
Expand All @@ -74,7 +74,7 @@ void g4() {
f4(1, s);
f4m(1, 2, 3, 4, 5, s);
}
// CHECK: define void @g4()
// CHECK: define{{.*}} void @g4()
// CHECK: call void @f4(i32 1, [2 x i64] [i64 30064771078, i64 0])
// CHECK: void @f4m(i32 1, i32 2, i32 3, i32 4, i32 5, [2 x i64] [i64 30064771078, i64 0])
// CHECK: declare void @f4(i32, [2 x i64])
Expand All @@ -94,7 +94,7 @@ void f5m(int, int, int, int, int, P16);
f5(1, s);
f5m(1, 2, 3, 4, 5, s);
}
// CHECK: define void @g5()
// CHECK: define{{.*}} void @g5()
// CHECK: call void @f5(i32 1, [2 x i64] [i64 30064771078, i64 0])
// CHECK: void @f5m(i32 1, i32 2, i32 3, i32 4, i32 5, [2 x i64] [i64 30064771078, i64 0])
// CHECK: declare void @f5(i32, [2 x i64])
Expand Down
22 changes: 11 additions & 11 deletions clang/test/CodeGen/aarch64-branch-protection-attr.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,47 +4,47 @@

__attribute__ ((target("branch-protection=none")))
void none() {}
// CHECK: define void @none() #[[#NONE:]]
// CHECK: define{{.*}} void @none() #[[#NONE:]]

__attribute__ ((target("branch-protection=standard")))
void std() {}
// CHECK: define void @std() #[[#STD:]]
// CHECK: define{{.*}} void @std() #[[#STD:]]

__attribute__ ((target("branch-protection=bti")))
void btionly() {}
// CHECK: define void @btionly() #[[#BTI:]]
// CHECK: define{{.*}} void @btionly() #[[#BTI:]]

__attribute__ ((target("branch-protection=pac-ret")))
void paconly() {}
// CHECK: define void @paconly() #[[#PAC:]]
// CHECK: define{{.*}} void @paconly() #[[#PAC:]]

__attribute__ ((target("branch-protection=pac-ret+bti")))
void pacbti0() {}
// CHECK: define void @pacbti0() #[[#PACBTI:]]
// CHECK: define{{.*}} void @pacbti0() #[[#PACBTI:]]

__attribute__ ((target("branch-protection=bti+pac-ret")))
void pacbti1() {}
// CHECK: define void @pacbti1() #[[#PACBTI]]
// CHECK: define{{.*}} void @pacbti1() #[[#PACBTI]]

__attribute__ ((target("branch-protection=pac-ret+leaf")))
void leaf() {}
// CHECK: define void @leaf() #[[#PACLEAF:]]
// CHECK: define{{.*}} void @leaf() #[[#PACLEAF:]]

__attribute__ ((target("branch-protection=pac-ret+b-key")))
void bkey() {}
// CHECK: define void @bkey() #[[#PACBKEY:]]
// CHECK: define{{.*}} void @bkey() #[[#PACBKEY:]]

__attribute__ ((target("branch-protection=pac-ret+b-key+leaf")))
void bkeyleaf0() {}
// CHECK: define void @bkeyleaf0() #[[#PACBKEYLEAF:]]
// CHECK: define{{.*}} void @bkeyleaf0() #[[#PACBKEYLEAF:]]

__attribute__ ((target("branch-protection=pac-ret+leaf+b-key")))
void bkeyleaf1() {}
// CHECK: define void @bkeyleaf1() #[[#PACBKEYLEAF]]
// CHECK: define{{.*}} void @bkeyleaf1() #[[#PACBKEYLEAF]]

__attribute__ ((target("branch-protection=pac-ret+leaf+bti")))
void btileaf() {}
// CHECK: define void @btileaf() #[[#BTIPACLEAF:]]
// CHECK: define{{.*}} void @btileaf() #[[#BTIPACLEAF:]]

// CHECK-DAG: attributes #[[#NONE]] = { {{.*}} "branch-target-enforcement"="false" {{.*}} "sign-return-address"="none"

Expand Down
4 changes: 2 additions & 2 deletions clang/test/CodeGen/aarch64-byval-temp.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ void example() {
pass_large(l);
pass_large(l);
}
// CHECK-O0-LABEL: define void @example(
// CHECK-O0-LABEL: define{{.*}} void @example(
// The alloca for the struct on the stack.
// CHECK-O0: %[[l:[0-9A-Za-z-]+]] = alloca %struct.large, align 8
// The alloca for the temporary stack space that we use to pass the argument.
Expand All @@ -42,7 +42,7 @@ void example() {
//
// At O3, we should have lifetime markers to help the optimizer re-use the temporary allocas.
//
// CHECK-O3-LABEL: define void @example(
// CHECK-O3-LABEL: define{{.*}} void @example(
// The alloca for the struct on the stack.
// CHECK-O3: %[[l:[0-9A-Za-z-]+]] = alloca %struct.large, align 8
// The alloca for the temporary stack space that we use to pass the argument.
Expand Down
2 changes: 1 addition & 1 deletion clang/test/CodeGen/aarch64-matmul.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,6 +3,6 @@
#ifdef __ARM_FEATURE_MATMUL_INT8
extern "C" void arm_feature_matmulint8_defined() {}
#endif
// CHECK: define void @arm_feature_matmulint8_defined()
// CHECK: define{{.*}} void @arm_feature_matmulint8_defined()


160 changes: 80 additions & 80 deletions clang/test/CodeGen/aarch64-neon-3v.c
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88 changes: 44 additions & 44 deletions clang/test/CodeGen/aarch64-neon-across.c
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24 changes: 12 additions & 12 deletions clang/test/CodeGen/aarch64-neon-dot-product.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,35 +8,35 @@
#include <arm_neon.h>

uint32x2_t test_vdot_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) {
// CHECK-LABEL: define <2 x i32> @test_vdot_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.aarch64.neon.udot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK: ret <2 x i32> [[RESULT]]
return vdot_u32(a, b, c);
}

uint32x4_t test_vdotq_u32(uint32x4_t a, uint8x16_t b, uint8x16_t c) {
// CHECK-LABEL: define <4 x i32> @test_vdotq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.aarch64.neon.udot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK: ret <4 x i32> [[RESULT]]
return vdotq_u32(a, b, c);
}

int32x2_t test_vdot_s32(int32x2_t a, int8x8_t b, int8x8_t c) {
// CHECK-LABEL: define <2 x i32> @test_vdot_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK: [[RESULT:%.*]] = call <2 x i32> @llvm.aarch64.neon.sdot.v2i32.v8i8(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK: ret <2 x i32> [[RESULT]]
return vdot_s32(a, b, c);
}

int32x4_t test_vdotq_s32(int32x4_t a, int8x16_t b, int8x16_t c) {
// CHECK-LABEL: define <4 x i32> @test_vdotq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK: [[RESULT:%.*]] = call <4 x i32> @llvm.aarch64.neon.sdot.v4i32.v16i8(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK: ret <4 x i32> [[RESULT]]
return vdotq_s32(a, b, c);
}

uint32x2_t test_vdot_lane_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) {
// CHECK-LABEL: define <2 x i32> @test_vdot_lane_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_u32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> undef, <2 x i32> <i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
Expand All @@ -46,7 +46,7 @@ uint32x2_t test_vdot_lane_u32(uint32x2_t a, uint8x8_t b, uint8x8_t c) {
}

uint32x4_t test_vdotq_lane_u32(uint32x4_t a, uint8x16_t b, uint8x8_t c) {
// CHECK-LABEL: define <4 x i32> @test_vdotq_lane_u32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_u32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c)
// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8>
Expand All @@ -56,7 +56,7 @@ uint32x4_t test_vdotq_lane_u32(uint32x4_t a, uint8x16_t b, uint8x8_t c) {
}

uint32x2_t test_vdot_laneq_u32(uint32x2_t a, uint8x8_t b, uint8x16_t c) {
// CHECK-LABEL: define <2 x i32> @test_vdot_laneq_u32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c)
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_laneq_u32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c)
// CHECK: [[CAST1:%.*]] = bitcast <16 x i8> %c to <4 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[CAST1]], <4 x i32> undef, <2 x i32> <i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
Expand All @@ -66,7 +66,7 @@ uint32x2_t test_vdot_laneq_u32(uint32x2_t a, uint8x8_t b, uint8x16_t c) {
}

uint32x4_t test_vdotq_laneq_u32(uint32x4_t a, uint8x16_t b, uint8x16_t c) {
// CHECK-LABEL: define <4 x i32> @test_vdotq_laneq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_laneq_u32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK: [[CAST1:%.*]] = bitcast <16 x i8> %c to <4 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[CAST1]], <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8>
Expand All @@ -76,7 +76,7 @@ uint32x4_t test_vdotq_laneq_u32(uint32x4_t a, uint8x16_t b, uint8x16_t c) {
}

int32x2_t test_vdot_lane_s32(int32x2_t a, int8x8_t b, int8x8_t c) {
// CHECK-LABEL: define <2 x i32> @test_vdot_lane_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_lane_s32(<2 x i32> %a, <8 x i8> %b, <8 x i8> %c)
// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> undef, <2 x i32> <i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
Expand All @@ -86,7 +86,7 @@ int32x2_t test_vdot_lane_s32(int32x2_t a, int8x8_t b, int8x8_t c) {
}

int32x4_t test_vdotq_lane_s32(int32x4_t a, int8x16_t b, int8x8_t c) {
// CHECK-LABEL: define <4 x i32> @test_vdotq_lane_s32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c)
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_lane_s32(<4 x i32> %a, <16 x i8> %b, <8 x i8> %c)
// CHECK: [[CAST1:%.*]] = bitcast <8 x i8> %c to <2 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <2 x i32> [[CAST1]], <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8>
Expand All @@ -96,7 +96,7 @@ int32x4_t test_vdotq_lane_s32(int32x4_t a, int8x16_t b, int8x8_t c) {
}

int32x2_t test_vdot_laneq_s32(int32x2_t a, int8x8_t b, int8x16_t c) {
// CHECK-LABEL: define <2 x i32> @test_vdot_laneq_s32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c)
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vdot_laneq_s32(<2 x i32> %a, <8 x i8> %b, <16 x i8> %c)
// CHECK: [[CAST1:%.*]] = bitcast <16 x i8> %c to <4 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[CAST1]], <4 x i32> undef, <2 x i32> <i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <2 x i32> [[SHUFFLE]] to <8 x i8>
Expand All @@ -106,7 +106,7 @@ int32x2_t test_vdot_laneq_s32(int32x2_t a, int8x8_t b, int8x16_t c) {
}

int32x4_t test_vdotq_laneq_s32(int32x4_t a, int8x16_t b, int8x16_t c) {
// CHECK-LABEL: define <4 x i32> @test_vdotq_laneq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vdotq_laneq_s32(<4 x i32> %a, <16 x i8> %b, <16 x i8> %c)
// CHECK: [[CAST1:%.*]] = bitcast <16 x i8> %c to <4 x i32>
// CHECK: [[SHUFFLE:%.*]] = shufflevector <4 x i32> [[CAST1]], <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
// CHECK: [[CAST2:%.*]] = bitcast <4 x i32> [[SHUFFLE]] to <16 x i8>
Expand Down
48 changes: 24 additions & 24 deletions clang/test/CodeGen/aarch64-neon-extract.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,14 +6,14 @@

#include <arm_neon.h>

// CHECK-LABEL: define <8 x i8> @test_vext_s8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vext_s8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK: [[VEXT:%.*]] = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
// CHECK: ret <8 x i8> [[VEXT]]
int8x8_t test_vext_s8(int8x8_t a, int8x8_t b) {
return vext_s8(a, b, 2);
}

// CHECK-LABEL: define <4 x i16> @test_vext_s16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vext_s16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
Expand All @@ -24,7 +24,7 @@ int16x4_t test_vext_s16(int16x4_t a, int16x4_t b) {
return vext_s16(a, b, 3);
}

// CHECK-LABEL: define <2 x i32> @test_vext_s32(<2 x i32> %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vext_s32(<2 x i32> %a, <2 x i32> %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
Expand All @@ -35,7 +35,7 @@ int32x2_t test_vext_s32(int32x2_t a, int32x2_t b) {
return vext_s32(a, b, 1);
}

// CHECK-LABEL: define <1 x i64> @test_vext_s64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vext_s64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
Expand All @@ -46,14 +46,14 @@ int64x1_t test_vext_s64(int64x1_t a, int64x1_t b) {
return vext_s64(a, b, 0);
}

// CHECK-LABEL: define <16 x i8> @test_vextq_s8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vextq_s8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK: [[VEXT:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
// CHECK: ret <16 x i8> [[VEXT]]
int8x16_t test_vextq_s8(int8x16_t a, int8x16_t b) {
return vextq_s8(a, b, 2);
}

// CHECK-LABEL: define <8 x i16> @test_vextq_s16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vextq_s16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
Expand All @@ -64,7 +64,7 @@ int16x8_t test_vextq_s16(int16x8_t a, int16x8_t b) {
return vextq_s16(a, b, 3);
}

// CHECK-LABEL: define <4 x i32> @test_vextq_s32(<4 x i32> %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vextq_s32(<4 x i32> %a, <4 x i32> %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <4 x i32> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
Expand All @@ -75,7 +75,7 @@ int32x4_t test_vextq_s32(int32x4_t a, int32x4_t b) {
return vextq_s32(a, b, 1);
}

// CHECK-LABEL: define <2 x i64> @test_vextq_s64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vextq_s64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
Expand All @@ -86,14 +86,14 @@ int64x2_t test_vextq_s64(int64x2_t a, int64x2_t b) {
return vextq_s64(a, b, 1);
}

// CHECK-LABEL: define <8 x i8> @test_vext_u8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vext_u8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK: [[VEXT:%.*]] = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
// CHECK: ret <8 x i8> [[VEXT]]
uint8x8_t test_vext_u8(uint8x8_t a, uint8x8_t b) {
return vext_u8(a, b, 2);
}

// CHECK-LABEL: define <4 x i16> @test_vext_u16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vext_u16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
Expand All @@ -104,7 +104,7 @@ uint16x4_t test_vext_u16(uint16x4_t a, uint16x4_t b) {
return vext_u16(a, b, 3);
}

// CHECK-LABEL: define <2 x i32> @test_vext_u32(<2 x i32> %a, <2 x i32> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x i32> @test_vext_u32(<2 x i32> %a, <2 x i32> %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i32> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <2 x i32> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32>
Expand All @@ -115,7 +115,7 @@ uint32x2_t test_vext_u32(uint32x2_t a, uint32x2_t b) {
return vext_u32(a, b, 1);
}

// CHECK-LABEL: define <1 x i64> @test_vext_u64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x i64> @test_vext_u64(<1 x i64> %a, <1 x i64> %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <1 x i64> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <1 x i64> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64>
Expand All @@ -126,14 +126,14 @@ uint64x1_t test_vext_u64(uint64x1_t a, uint64x1_t b) {
return vext_u64(a, b, 0);
}

// CHECK-LABEL: define <16 x i8> @test_vextq_u8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vextq_u8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK: [[VEXT:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
// CHECK: ret <16 x i8> [[VEXT]]
uint8x16_t test_vextq_u8(uint8x16_t a, uint8x16_t b) {
return vextq_u8(a, b, 2);
}

// CHECK-LABEL: define <8 x i16> @test_vextq_u16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vextq_u16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
Expand All @@ -144,7 +144,7 @@ uint16x8_t test_vextq_u16(uint16x8_t a, uint16x8_t b) {
return vextq_u16(a, b, 3);
}

// CHECK-LABEL: define <4 x i32> @test_vextq_u32(<4 x i32> %a, <4 x i32> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x i32> @test_vextq_u32(<4 x i32> %a, <4 x i32> %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x i32> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <4 x i32> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32>
Expand All @@ -155,7 +155,7 @@ uint32x4_t test_vextq_u32(uint32x4_t a, uint32x4_t b) {
return vextq_u32(a, b, 1);
}

// CHECK-LABEL: define <2 x i64> @test_vextq_u64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x i64> @test_vextq_u64(<2 x i64> %a, <2 x i64> %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x i64> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <2 x i64> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64>
Expand All @@ -166,7 +166,7 @@ uint64x2_t test_vextq_u64(uint64x2_t a, uint64x2_t b) {
return vextq_u64(a, b, 1);
}

// CHECK-LABEL: define <2 x float> @test_vext_f32(<2 x float> %a, <2 x float> %b) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vext_f32(<2 x float> %a, <2 x float> %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <2 x float> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
Expand All @@ -177,7 +177,7 @@ float32x2_t test_vext_f32(float32x2_t a, float32x2_t b) {
return vext_f32(a, b, 1);
}

// CHECK-LABEL: define <1 x double> @test_vext_f64(<1 x double> %a, <1 x double> %b) #0 {
// CHECK-LABEL: define{{.*}} <1 x double> @test_vext_f64(<1 x double> %a, <1 x double> %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <1 x double> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <1 x double> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x double>
Expand All @@ -188,7 +188,7 @@ float64x1_t test_vext_f64(float64x1_t a, float64x1_t b) {
return vext_f64(a, b, 0);
}

// CHECK-LABEL: define <4 x float> @test_vextq_f32(<4 x float> %a, <4 x float> %b) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vextq_f32(<4 x float> %a, <4 x float> %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <4 x float> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
Expand All @@ -199,7 +199,7 @@ float32x4_t test_vextq_f32(float32x4_t a, float32x4_t b) {
return vextq_f32(a, b, 1);
}

// CHECK-LABEL: define <2 x double> @test_vextq_f64(<2 x double> %a, <2 x double> %b) #1 {
// CHECK-LABEL: define{{.*}} <2 x double> @test_vextq_f64(<2 x double> %a, <2 x double> %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x double> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <2 x double> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x double>
Expand All @@ -210,14 +210,14 @@ float64x2_t test_vextq_f64(float64x2_t a, float64x2_t b) {
return vextq_f64(a, b, 1);
}

// CHECK-LABEL: define <8 x i8> @test_vext_p8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK-LABEL: define{{.*}} <8 x i8> @test_vext_p8(<8 x i8> %a, <8 x i8> %b) #0 {
// CHECK: [[VEXT:%.*]] = shufflevector <8 x i8> %a, <8 x i8> %b, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9>
// CHECK: ret <8 x i8> [[VEXT]]
poly8x8_t test_vext_p8(poly8x8_t a, poly8x8_t b) {
return vext_p8(a, b, 2);
}

// CHECK-LABEL: define <4 x i16> @test_vext_p16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK-LABEL: define{{.*}} <4 x i16> @test_vext_p16(<4 x i16> %a, <4 x i16> %b) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x i16> %a to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <4 x i16> %b to <8 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16>
Expand All @@ -228,14 +228,14 @@ poly16x4_t test_vext_p16(poly16x4_t a, poly16x4_t b) {
return vext_p16(a, b, 3);
}

// CHECK-LABEL: define <16 x i8> @test_vextq_p8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK-LABEL: define{{.*}} <16 x i8> @test_vextq_p8(<16 x i8> %a, <16 x i8> %b) #1 {
// CHECK: [[VEXT:%.*]] = shufflevector <16 x i8> %a, <16 x i8> %b, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17>
// CHECK: ret <16 x i8> [[VEXT]]
poly8x16_t test_vextq_p8(poly8x16_t a, poly8x16_t b) {
return vextq_p8(a, b, 2);
}

// CHECK-LABEL: define <8 x i16> @test_vextq_p16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK-LABEL: define{{.*}} <8 x i16> @test_vextq_p16(<8 x i16> %a, <8 x i16> %b) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <8 x i16> %a to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i16> %b to <16 x i8>
// CHECK: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16>
Expand Down
42 changes: 21 additions & 21 deletions clang/test/CodeGen/aarch64-neon-fcvt-intrinsics.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,147 +5,147 @@

#include <arm_neon.h>

// CHECK-LABEL: define float @test_vcvtxd_f32_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} float @test_vcvtxd_f32_f64(double %a) #0 {
// CHECK: [[VCVTXD_F32_F64_I:%.*]] = call float @llvm.aarch64.sisd.fcvtxn(double %a) #2
// CHECK: ret float [[VCVTXD_F32_F64_I]]
float32_t test_vcvtxd_f32_f64(float64_t a) {
return (float32_t)vcvtxd_f32_f64(a);
}

// CHECK-LABEL: define i32 @test_vcvtas_s32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvtas_s32_f32(float %a) #0 {
// CHECK: [[VCVTAS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtas.i32.f32(float %a) #2
// CHECK: ret i32 [[VCVTAS_S32_F32_I]]
int32_t test_vcvtas_s32_f32(float32_t a) {
return (int32_t)vcvtas_s32_f32(a);
}

// CHECK-LABEL: define i64 @test_test_vcvtad_s64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_test_vcvtad_s64_f64(double %a) #0 {
// CHECK: [[VCVTAD_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtas.i64.f64(double %a) #2
// CHECK: ret i64 [[VCVTAD_S64_F64_I]]
int64_t test_test_vcvtad_s64_f64(float64_t a) {
return (int64_t)vcvtad_s64_f64(a);
}

// CHECK-LABEL: define i32 @test_vcvtas_u32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvtas_u32_f32(float %a) #0 {
// CHECK: [[VCVTAS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtau.i32.f32(float %a) #2
// CHECK: ret i32 [[VCVTAS_U32_F32_I]]
uint32_t test_vcvtas_u32_f32(float32_t a) {
return (uint32_t)vcvtas_u32_f32(a);
}

// CHECK-LABEL: define i64 @test_vcvtad_u64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtad_u64_f64(double %a) #0 {
// CHECK: [[VCVTAD_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtau.i64.f64(double %a) #2
// CHECK: ret i64 [[VCVTAD_U64_F64_I]]
uint64_t test_vcvtad_u64_f64(float64_t a) {
return (uint64_t)vcvtad_u64_f64(a);
}

// CHECK-LABEL: define i32 @test_vcvtms_s32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvtms_s32_f32(float %a) #0 {
// CHECK: [[VCVTMS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtms.i32.f32(float %a) #2
// CHECK: ret i32 [[VCVTMS_S32_F32_I]]
int32_t test_vcvtms_s32_f32(float32_t a) {
return (int32_t)vcvtms_s32_f32(a);
}

// CHECK-LABEL: define i64 @test_vcvtmd_s64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtmd_s64_f64(double %a) #0 {
// CHECK: [[VCVTMD_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtms.i64.f64(double %a) #2
// CHECK: ret i64 [[VCVTMD_S64_F64_I]]
int64_t test_vcvtmd_s64_f64(float64_t a) {
return (int64_t)vcvtmd_s64_f64(a);
}

// CHECK-LABEL: define i32 @test_vcvtms_u32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvtms_u32_f32(float %a) #0 {
// CHECK: [[VCVTMS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtmu.i32.f32(float %a) #2
// CHECK: ret i32 [[VCVTMS_U32_F32_I]]
uint32_t test_vcvtms_u32_f32(float32_t a) {
return (uint32_t)vcvtms_u32_f32(a);
}

// CHECK-LABEL: define i64 @test_vcvtmd_u64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtmd_u64_f64(double %a) #0 {
// CHECK: [[VCVTMD_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtmu.i64.f64(double %a) #2
// CHECK: ret i64 [[VCVTMD_U64_F64_I]]
uint64_t test_vcvtmd_u64_f64(float64_t a) {
return (uint64_t)vcvtmd_u64_f64(a);
}

// CHECK-LABEL: define i32 @test_vcvtns_s32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvtns_s32_f32(float %a) #0 {
// CHECK: [[VCVTNS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtns.i32.f32(float %a) #2
// CHECK: ret i32 [[VCVTNS_S32_F32_I]]
int32_t test_vcvtns_s32_f32(float32_t a) {
return (int32_t)vcvtns_s32_f32(a);
}

// CHECK-LABEL: define i64 @test_vcvtnd_s64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtnd_s64_f64(double %a) #0 {
// CHECK: [[VCVTND_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtns.i64.f64(double %a) #2
// CHECK: ret i64 [[VCVTND_S64_F64_I]]
int64_t test_vcvtnd_s64_f64(float64_t a) {
return (int64_t)vcvtnd_s64_f64(a);
}

// CHECK-LABEL: define i32 @test_vcvtns_u32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvtns_u32_f32(float %a) #0 {
// CHECK: [[VCVTNS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtnu.i32.f32(float %a) #2
// CHECK: ret i32 [[VCVTNS_U32_F32_I]]
uint32_t test_vcvtns_u32_f32(float32_t a) {
return (uint32_t)vcvtns_u32_f32(a);
}

// CHECK-LABEL: define i64 @test_vcvtnd_u64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtnd_u64_f64(double %a) #0 {
// CHECK: [[VCVTND_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtnu.i64.f64(double %a) #2
// CHECK: ret i64 [[VCVTND_U64_F64_I]]
uint64_t test_vcvtnd_u64_f64(float64_t a) {
return (uint64_t)vcvtnd_u64_f64(a);
}

// CHECK-LABEL: define i32 @test_vcvtps_s32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvtps_s32_f32(float %a) #0 {
// CHECK: [[VCVTPS_S32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtps.i32.f32(float %a) #2
// CHECK: ret i32 [[VCVTPS_S32_F32_I]]
int32_t test_vcvtps_s32_f32(float32_t a) {
return (int32_t)vcvtps_s32_f32(a);
}

// CHECK-LABEL: define i64 @test_vcvtpd_s64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtpd_s64_f64(double %a) #0 {
// CHECK: [[VCVTPD_S64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtps.i64.f64(double %a) #2
// CHECK: ret i64 [[VCVTPD_S64_F64_I]]
int64_t test_vcvtpd_s64_f64(float64_t a) {
return (int64_t)vcvtpd_s64_f64(a);
}

// CHECK-LABEL: define i32 @test_vcvtps_u32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvtps_u32_f32(float %a) #0 {
// CHECK: [[VCVTPS_U32_F32_I:%.*]] = call i32 @llvm.aarch64.neon.fcvtpu.i32.f32(float %a) #2
// CHECK: ret i32 [[VCVTPS_U32_F32_I]]
uint32_t test_vcvtps_u32_f32(float32_t a) {
return (uint32_t)vcvtps_u32_f32(a);
}

// CHECK-LABEL: define i64 @test_vcvtpd_u64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtpd_u64_f64(double %a) #0 {
// CHECK: [[VCVTPD_U64_F64_I:%.*]] = call i64 @llvm.aarch64.neon.fcvtpu.i64.f64(double %a) #2
// CHECK: ret i64 [[VCVTPD_U64_F64_I]]
uint64_t test_vcvtpd_u64_f64(float64_t a) {
return (uint64_t)vcvtpd_u64_f64(a);
}

// CHECK-LABEL: define i32 @test_vcvts_s32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvts_s32_f32(float %a) #0 {
// CHECK: [[TMP0:%.*]] = call i32 @llvm.aarch64.neon.fcvtzs.i32.f32(float %a)
// CHECK: ret i32 [[TMP0]]
int32_t test_vcvts_s32_f32(float32_t a) {
return (int32_t)vcvts_s32_f32(a);
}

// CHECK-LABEL: define i64 @test_vcvtd_s64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtd_s64_f64(double %a) #0 {
// CHECK: [[TMP0:%.*]] = call i64 @llvm.aarch64.neon.fcvtzs.i64.f64(double %a)
// CHECK: ret i64 [[TMP0]]
int64_t test_vcvtd_s64_f64(float64_t a) {
return (int64_t)vcvtd_s64_f64(a);
}

// CHECK-LABEL: define i32 @test_vcvts_u32_f32(float %a) #0 {
// CHECK-LABEL: define{{.*}} i32 @test_vcvts_u32_f32(float %a) #0 {
// CHECK: [[TMP0:%.*]] = call i32 @llvm.aarch64.neon.fcvtzu.i32.f32(float %a)
// CHECK: ret i32 [[TMP0]]
uint32_t test_vcvts_u32_f32(float32_t a) {
return (uint32_t)vcvts_u32_f32(a);
}

// CHECK-LABEL: define i64 @test_vcvtd_u64_f64(double %a) #0 {
// CHECK-LABEL: define{{.*}} i64 @test_vcvtd_u64_f64(double %a) #0 {
// CHECK: [[TMP0:%.*]] = call i64 @llvm.aarch64.neon.fcvtzu.i64.f64(double %a)
// CHECK: ret i64 [[TMP0]]
uint64_t test_vcvtd_u64_f64(float64_t a) {
Expand Down
44 changes: 22 additions & 22 deletions clang/test/CodeGen/aarch64-neon-fma.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,7 +4,7 @@

#include <arm_neon.h>

// CHECK-LABEL: define <2 x float> @test_vmla_n_f32(<2 x float> %a, <2 x float> %b, float %c) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_n_f32(<2 x float> %a, <2 x float> %b, float %c) #0 {
// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %c, i32 0
// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %c, i32 1
// CHECK: [[MUL_I:%.*]] = fmul <2 x float> %b, [[VECINIT1_I]]
Expand All @@ -14,7 +14,7 @@ float32x2_t test_vmla_n_f32(float32x2_t a, float32x2_t b, float32_t c) {
return vmla_n_f32(a, b, c);
}

// CHECK-LABEL: define <4 x float> @test_vmlaq_n_f32(<4 x float> %a, <4 x float> %b, float %c) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_n_f32(<4 x float> %a, <4 x float> %b, float %c) #1 {
// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %c, i32 0
// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %c, i32 1
// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %c, i32 2
Expand All @@ -26,7 +26,7 @@ float32x4_t test_vmlaq_n_f32(float32x4_t a, float32x4_t b, float32_t c) {
return vmlaq_n_f32(a, b, c);
}

// CHECK-LABEL: define <4 x float> @test_vmlsq_n_f32(<4 x float> %a, <4 x float> %b, float %c) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_n_f32(<4 x float> %a, <4 x float> %b, float %c) #1 {
// CHECK: [[VECINIT_I:%.*]] = insertelement <4 x float> undef, float %c, i32 0
// CHECK: [[VECINIT1_I:%.*]] = insertelement <4 x float> [[VECINIT_I]], float %c, i32 1
// CHECK: [[VECINIT2_I:%.*]] = insertelement <4 x float> [[VECINIT1_I]], float %c, i32 2
Expand All @@ -38,7 +38,7 @@ float32x4_t test_vmlsq_n_f32(float32x4_t a, float32x4_t b, float32_t c) {
return vmlsq_n_f32(a, b, c);
}

// CHECK-LABEL: define <2 x float> @test_vmls_n_f32(<2 x float> %a, <2 x float> %b, float %c) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_n_f32(<2 x float> %a, <2 x float> %b, float %c) #0 {
// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x float> undef, float %c, i32 0
// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x float> [[VECINIT_I]], float %c, i32 1
// CHECK: [[MUL_I:%.*]] = fmul <2 x float> %b, [[VECINIT1_I]]
Expand All @@ -48,7 +48,7 @@ float32x2_t test_vmls_n_f32(float32x2_t a, float32x2_t b, float32_t c) {
return vmls_n_f32(a, b, c);
}

// CHECK-LABEL: define <2 x float> @test_vmla_lane_f32_0(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_lane_f32_0(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> zeroinitializer
Expand All @@ -59,7 +59,7 @@ float32x2_t test_vmla_lane_f32_0(float32x2_t a, float32x2_t b, float32x2_t v) {
return vmla_lane_f32(a, b, v, 0);
}

// CHECK-LABEL: define <4 x float> @test_vmlaq_lane_f32_0(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_lane_f32_0(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <4 x i32> zeroinitializer
Expand All @@ -70,7 +70,7 @@ float32x4_t test_vmlaq_lane_f32_0(float32x4_t a, float32x4_t b, float32x2_t v) {
return vmlaq_lane_f32(a, b, v, 0);
}

// CHECK-LABEL: define <2 x float> @test_vmla_laneq_f32_0(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_laneq_f32_0(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <2 x i32> zeroinitializer
Expand All @@ -81,7 +81,7 @@ float32x2_t test_vmla_laneq_f32_0(float32x2_t a, float32x2_t b, float32x4_t v) {
return vmla_laneq_f32(a, b, v, 0);
}

// CHECK-LABEL: define <4 x float> @test_vmlaq_laneq_f32_0(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_laneq_f32_0(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> zeroinitializer
Expand All @@ -92,7 +92,7 @@ float32x4_t test_vmlaq_laneq_f32_0(float32x4_t a, float32x4_t b, float32x4_t v)
return vmlaq_laneq_f32(a, b, v, 0);
}

// CHECK-LABEL: define <2 x float> @test_vmls_lane_f32_0(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_lane_f32_0(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> zeroinitializer
Expand All @@ -103,7 +103,7 @@ float32x2_t test_vmls_lane_f32_0(float32x2_t a, float32x2_t b, float32x2_t v) {
return vmls_lane_f32(a, b, v, 0);
}

// CHECK-LABEL: define <4 x float> @test_vmlsq_lane_f32_0(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_lane_f32_0(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <4 x i32> zeroinitializer
Expand All @@ -114,7 +114,7 @@ float32x4_t test_vmlsq_lane_f32_0(float32x4_t a, float32x4_t b, float32x2_t v) {
return vmlsq_lane_f32(a, b, v, 0);
}

// CHECK-LABEL: define <2 x float> @test_vmls_laneq_f32_0(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_laneq_f32_0(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <2 x i32> zeroinitializer
Expand All @@ -125,7 +125,7 @@ float32x2_t test_vmls_laneq_f32_0(float32x2_t a, float32x2_t b, float32x4_t v) {
return vmls_laneq_f32(a, b, v, 0);
}

// CHECK-LABEL: define <4 x float> @test_vmlsq_laneq_f32_0(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_laneq_f32_0(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> zeroinitializer
Expand All @@ -136,7 +136,7 @@ float32x4_t test_vmlsq_laneq_f32_0(float32x4_t a, float32x4_t b, float32x4_t v)
return vmlsq_laneq_f32(a, b, v, 0);
}

// CHECK-LABEL: define <2 x float> @test_vmla_lane_f32(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_lane_f32(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> <i32 1, i32 1>
Expand All @@ -147,7 +147,7 @@ float32x2_t test_vmla_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v) {
return vmla_lane_f32(a, b, v, 1);
}

// CHECK-LABEL: define <4 x float> @test_vmlaq_lane_f32(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_lane_f32(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>
Expand All @@ -158,7 +158,7 @@ float32x4_t test_vmlaq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v) {
return vmlaq_lane_f32(a, b, v, 1);
}

// CHECK-LABEL: define <2 x float> @test_vmla_laneq_f32(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmla_laneq_f32(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <2 x i32> <i32 3, i32 3>
Expand All @@ -169,7 +169,7 @@ float32x2_t test_vmla_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v) {
return vmla_laneq_f32(a, b, v, 3);
}

// CHECK-LABEL: define <4 x float> @test_vmlaq_laneq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlaq_laneq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>
Expand All @@ -180,7 +180,7 @@ float32x4_t test_vmlaq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v) {
return vmlaq_laneq_f32(a, b, v, 3);
}

// CHECK-LABEL: define <2 x float> @test_vmls_lane_f32(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_lane_f32(<2 x float> %a, <2 x float> %b, <2 x float> %v) #0 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <2 x i32> <i32 1, i32 1>
Expand All @@ -191,7 +191,7 @@ float32x2_t test_vmls_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v) {
return vmls_lane_f32(a, b, v, 1);
}

// CHECK-LABEL: define <4 x float> @test_vmlsq_lane_f32(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_lane_f32(<4 x float> %a, <4 x float> %b, <2 x float> %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <2 x float> [[V:%.*]] to <8 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x float>
// CHECK: [[LANE:%.*]] = shufflevector <2 x float> [[TMP1]], <2 x float> [[TMP1]], <4 x i32> <i32 1, i32 1, i32 1, i32 1>
Expand All @@ -202,7 +202,7 @@ float32x2_t test_vmls_lane_f32(float32x2_t a, float32x2_t b, float32x2_t v) {
float32x4_t test_vmlsq_lane_f32(float32x4_t a, float32x4_t b, float32x2_t v) {
return vmlsq_lane_f32(a, b, v, 1);
}
// CHECK-LABEL: define <2 x float> @test_vmls_laneq_f32(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <2 x float> @test_vmls_laneq_f32(<2 x float> %a, <2 x float> %b, <4 x float> %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <2 x i32> <i32 3, i32 3>
Expand All @@ -213,7 +213,7 @@ float32x2_t test_vmls_laneq_f32(float32x2_t a, float32x2_t b, float32x4_t v) {
return vmls_laneq_f32(a, b, v, 3);
}

// CHECK-LABEL: define <4 x float> @test_vmlsq_laneq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 {
// CHECK-LABEL: define{{.*}} <4 x float> @test_vmlsq_laneq_f32(<4 x float> %a, <4 x float> %b, <4 x float> %v) #1 {
// CHECK: [[TMP0:%.*]] = bitcast <4 x float> [[V:%.*]] to <16 x i8>
// CHECK: [[TMP1:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x float>
// CHECK: [[LANE:%.*]] = shufflevector <4 x float> [[TMP1]], <4 x float> [[TMP1]], <4 x i32> <i32 3, i32 3, i32 3, i32 3>
Expand All @@ -224,7 +224,7 @@ float32x4_t test_vmlsq_laneq_f32(float32x4_t a, float32x4_t b, float32x4_t v) {
return vmlsq_laneq_f32(a, b, v, 3);
}

// CHECK-LABEL: define <2 x double> @test_vfmaq_n_f64(<2 x double> %a, <2 x double> %b, double %c) #1 {
// CHECK-LABEL: define{{.*}} <2 x double> @test_vfmaq_n_f64(<2 x double> %a, <2 x double> %b, double %c) #1 {
// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, i32 0
// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %c, i32 1
// CHECK: [[TMP6:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> %b, <2 x double> [[VECINIT1_I]], <2 x double> %a)
Expand All @@ -233,7 +233,7 @@ float64x2_t test_vfmaq_n_f64(float64x2_t a, float64x2_t b, float64_t c) {
return vfmaq_n_f64(a, b, c);
}

// CHECK-LABEL: define <2 x double> @test_vfmsq_n_f64(<2 x double> %a, <2 x double> %b, double %c) #1 {
// CHECK-LABEL: define{{.*}} <2 x double> @test_vfmsq_n_f64(<2 x double> %a, <2 x double> %b, double %c) #1 {
// CHECK: [[SUB_I:%.*]] = fneg <2 x double> %b
// CHECK: [[VECINIT_I:%.*]] = insertelement <2 x double> undef, double %c, i32 0
// CHECK: [[VECINIT1_I:%.*]] = insertelement <2 x double> [[VECINIT_I]], double %c, i32 1
Expand Down
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