136 changes: 68 additions & 68 deletions clang/test/CodeGen/PowerPC/builtins-ppc-32bit-vec-ll.c
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec \
// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec \
// RUN: -target-feature +power8-vector -triple powerpc-unknown-unknown -emit-llvm %s -o - | FileCheck %s

#include <altivec.h>
Expand All @@ -14,282 +14,282 @@ void test() {
vec_abs(vsll1);
// CHECK: call <2 x i64> @llvm.ppc.altivec.vmaxsd
dummy();
// CHECK-NEXT: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK-NEXT: call void @dummy()
vec_add(vsll1, vsll2);
// CHECK: add <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_and(vsll1, vsll2);
// CHECK: and <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_vand(vsll1, vsll2);
// CHECK: and <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_andc(vsll1, vsll2);
// CHECK: xor <2 x i64>
// CHECK: and <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_vandc(vsll1, vsll2);
// CHECK: xor <2 x i64>
// CHECK: and <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_cmpeq(vsll1, vsll2);
// CHECK: call <2 x i64> @llvm.ppc.altivec.vcmpequd
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_cmpne(vsll1, vsll2);
// CHECK: call <2 x i64> @llvm.ppc.altivec.vcmpequd
// CHECK: xor <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_cmpgt(vsll1, vsll2);
// CHECK: call <2 x i64> @llvm.ppc.altivec.vcmpgtsd
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_cmpge(vsll1, vsll2);
// CHECK: call <2 x i64> @llvm.ppc.altivec.vcmpgtsd
// CHECK: xor <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_cmple(vsll1, vsll2);
// CHECK: call <2 x i64> @llvm.ppc.altivec.vcmpgtsd
// CHECK: xor <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_cmplt(vsll1, vsll2);
// CHECK: call <2 x i64> @llvm.ppc.altivec.vcmpgtsd
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_popcnt(vsll1);
// CHECK: call <2 x i64> @llvm.ctpop.v2i64
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_cntlz(vsll1);
// CHECK: call <2 x i64> @llvm.ctlz.v2i64
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_float2(vsll1, vsll2);
// CHECK: sitofp i64 %{{.*}} to float
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_floate(vsll1);
// CHECK: call <4 x float> @llvm.ppc.vsx.xvcvsxdsp
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_floato(vsll1);
// CHECK: call <4 x float> @llvm.ppc.vsx.xvcvsxdsp
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_double(vsll1);
// CHECK: sitofp <2 x i64> %{{.*}} to <2 x double>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_div(vsll1, vsll2);
// CHECK: sdiv <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_eqv(vsll1, vsll2);
// CHECK: call <4 x i32> @llvm.ppc.vsx.xxleqv
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_max(vsll1, vsll2);
// CHECK: call <2 x i64> @llvm.ppc.altivec.vmaxsd
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_mergeh(vsll1, vsll2);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_mergel(vsll1, vsll2);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_mergee(vsll1, vsll2);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_mergeo(vsll1, vsll2);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_min(vsll1, vsll2);
// CHECK: call <2 x i64> @llvm.ppc.altivec.vminsd
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_mul(vsll1, vsll2);
// CHECK: mul <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_nand(vsll1, vsll2);
// CHECK: and <2 x i64>
// CHECK: xor <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_nor(vsll1, vsll2);
// CHECK: or <2 x i64>
// CHECK: xor <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_or(vsll1, vsll2);
// CHECK: or <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_orc(vsll1, vsll2);
// CHECK: xor <2 x i64>
// CHECK: or <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_vor(vsll1, vsll2);
// CHECK: or <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_pack(vsll1, vsll2);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_vpkudum(vsll1, vsll2);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_packs(vsll1, vsll2);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vpksdss
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_vpkudus(vull1, vull2);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vpkudus
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_packsu(vsll1, vsll2);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vpksdus
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_rl(vull1, vull2);
// CHECK: call <2 x i64> @llvm.ppc.altivec.vrld
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_sel(vsll1, vsll2, vbll);
// CHECK: xor <2 x i64>
// CHECK: and <2 x i64>
// CHECK: and <2 x i64>
// CHECK: or <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_sl(vull1, vull2);
// CHECK: shl <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_sld(vsll1, vsll2, 2);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_sldw(vsll1, vsll2, 2);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_sll(vsll1, vuc);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vsl
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_slo(vsll1, vsc);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vslo
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_splat(vsll1, 2);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_sr(vull1, vull2);
// CHECK: lshr <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_sra(vsll1, vull2);
// CHECK: ashr <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_srl(vsll1, vuc);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vsr
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_sro(vsll1, vsc);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vsro
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_sub(vsll1, vsll2);
// CHECK: sub <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_xor(vsll1, vsll2);
// CHECK: xor <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_vxor(vsll1, vsll2);
// CHECK: xor <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_extract(vsll1, 2);
// CHECK: extractelement <2 x i64>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_all_eq(vsll1, vsll2);
// CHECK: call i32 @llvm.ppc.altivec.vcmpequd.p
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_all_ge(vsll1, vsll2);
// CHECK: call i32 @llvm.ppc.altivec.vcmpgtsd.p
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_all_gt(vsll1, vsll2);
// CHECK: call i32 @llvm.ppc.altivec.vcmpgtsd.p
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_all_le(vsll1, vsll2);
// CHECK: call i32 @llvm.ppc.altivec.vcmpgtsd.p
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_all_lt(vsll1, vsll2);
// CHECK: call i32 @llvm.ppc.altivec.vcmpgtsd.p
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_all_ne(vsll1, vsll2);
// CHECK: call i32 @llvm.ppc.altivec.vcmpequd.p
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_any_eq(vsll1, vsll2);
// CHECK: call i32 @llvm.ppc.altivec.vcmpequd.p
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_any_ge(vsll1, vsll2);
// CHECK: call i32 @llvm.ppc.altivec.vcmpgtsd.p
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_any_gt(vsll1, vsll2);
// CHECK: call i32 @llvm.ppc.altivec.vcmpgtsd.p
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_any_le(vsll1, vsll2);
// CHECK: call i32 @llvm.ppc.altivec.vcmpgtsd.p
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_any_lt(vsll1, vsll2);
// CHECK: call i32 @llvm.ppc.altivec.vcmpgtsd.p
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_any_ne(vsll1, vsll2);
// CHECK: call i32 @llvm.ppc.altivec.vcmpequd.p
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_gbb(vsll1);
// CHECK: call <16 x i8> @llvm.ppc.altivec.vgbbd
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_reve(vsll1);
// CHECK: shufflevector <2 x i64> %{{.*}}, <2 x i64> %{{.*}}, <2 x i32> <i32 1, i32 0>
dummy();
// CHECK: call void bitcast (void (...)* @dummy to void ()*)()
// CHECK: call void @dummy()
vec_revb(vsll1);
// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm
}
16 changes: 6 additions & 10 deletions clang/test/CodeGen/PowerPC/builtins-ppc-build-pair-mma.c
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Original file line number Diff line number Diff line change
@@ -1,21 +1,19 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -no-opaque-pointers -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
// RUN: %clang_cc1 -O3 -triple powerpc64le-unknown-unknown -target-cpu pwr10 \
// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-LE
// RUN: %clang_cc1 -no-opaque-pointers -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
// RUN: %clang_cc1 -O3 -triple powerpc64-unknown-unknown -target-cpu pwr10 \
// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK-BE

// CHECK-LE-LABEL: @test1(
// CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC4:%.*]], <16 x i8> [[VC3:%.*]], <16 x i8> [[VC2:%.*]], <16 x i8> [[VC1:%.*]])
// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
// CHECK-LE-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2:![0-9]+]]
// CHECK-LE-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2:![0-9]+]]
// CHECK-LE-NEXT: ret void
//
// CHECK-BE-LABEL: @test1(
// CHECK-BE-NEXT: entry:
// CHECK-BE-NEXT: [[TMP0:%.*]] = tail call <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8> [[VC1:%.*]], <16 x i8> [[VC2:%.*]], <16 x i8> [[VC3:%.*]], <16 x i8> [[VC4:%.*]])
// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <512 x i1>*
// CHECK-BE-NEXT: store <512 x i1> [[TMP0]], <512 x i1>* [[TMP1]], align 64, !tbaa [[TBAA2:![0-9]+]]
// CHECK-BE-NEXT: store <512 x i1> [[TMP0]], ptr [[RESP:%.*]], align 64, !tbaa [[TBAA2:![0-9]+]]
// CHECK-BE-NEXT: ret void
//
void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1, vector unsigned char vc2,
Expand All @@ -30,15 +28,13 @@ void test1(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1, vec
// CHECK-LE-LABEL: @test2(
// CHECK-LE-NEXT: entry:
// CHECK-LE-NEXT: [[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC2:%.*]], <16 x i8> [[VC1:%.*]])
// CHECK-LE-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>*
// CHECK-LE-NEXT: store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa [[TBAA6:![0-9]+]]
// CHECK-LE-NEXT: store <256 x i1> [[TMP0]], ptr [[RESP:%.*]], align 32, !tbaa [[TBAA6:![0-9]+]]
// CHECK-LE-NEXT: ret void
//
// CHECK-BE-LABEL: @test2(
// CHECK-BE-NEXT: entry:
// CHECK-BE-NEXT: [[TMP0:%.*]] = tail call <256 x i1> @llvm.ppc.vsx.assemble.pair(<16 x i8> [[VC1:%.*]], <16 x i8> [[VC2:%.*]])
// CHECK-BE-NEXT: [[TMP1:%.*]] = bitcast i8* [[RESP:%.*]] to <256 x i1>*
// CHECK-BE-NEXT: store <256 x i1> [[TMP0]], <256 x i1>* [[TMP1]], align 32, !tbaa [[TBAA6:![0-9]+]]
// CHECK-BE-NEXT: store <256 x i1> [[TMP0]], ptr [[RESP:%.*]], align 32, !tbaa [[TBAA6:![0-9]+]]
// CHECK-BE-NEXT: ret void
//
void test2(unsigned char *vqp, unsigned char *vpp, vector unsigned char vc1,
Expand Down
26 changes: 13 additions & 13 deletions clang/test/CodeGen/PowerPC/builtins-ppc-cache.c
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Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-linux-gnu -emit-llvm \
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm \
// RUN: -o - %s | FileCheck %s

int A;
Expand All @@ -10,38 +10,38 @@ double F[5];

void func(int a, int b[], float c, float d[], double e, double f[]) {
__builtin_dcbf (&a);
// CHECK: @llvm.ppc.dcbf(i8*
// CHECK: @llvm.ppc.dcbf(ptr

__builtin_dcbf (&A);
// CHECK: @llvm.ppc.dcbf(i8*
// CHECK: @llvm.ppc.dcbf(ptr

__builtin_dcbf (&b[2]);
// CHECK: @llvm.ppc.dcbf(i8*
// CHECK: @llvm.ppc.dcbf(ptr

__builtin_dcbf (&B[2]);
// CHECK: @llvm.ppc.dcbf(i8*
// CHECK: @llvm.ppc.dcbf(ptr

__builtin_dcbf (&c);
// CHECK: @llvm.ppc.dcbf(i8*
// CHECK: @llvm.ppc.dcbf(ptr

__builtin_dcbf (&C);
// CHECK: @llvm.ppc.dcbf(i8*
// CHECK: @llvm.ppc.dcbf(ptr

__builtin_dcbf (&d[2]);
// CHECK: @llvm.ppc.dcbf(i8*
// CHECK: @llvm.ppc.dcbf(ptr

__builtin_dcbf (&D[2]);
// CHECK: @llvm.ppc.dcbf(i8*
// CHECK: @llvm.ppc.dcbf(ptr

__builtin_dcbf (&e);
// CHECK: @llvm.ppc.dcbf(i8*
// CHECK: @llvm.ppc.dcbf(ptr

__builtin_dcbf (&E);
// CHECK: @llvm.ppc.dcbf(i8*
// CHECK: @llvm.ppc.dcbf(ptr

__builtin_dcbf (&f[0]);
// CHECK: @llvm.ppc.dcbf(i8*
// CHECK: @llvm.ppc.dcbf(ptr

__builtin_dcbf (&F[0]);
// CHECK: @llvm.ppc.dcbf(i8*
// CHECK: @llvm.ppc.dcbf(ptr
}
28 changes: 14 additions & 14 deletions clang/test/CodeGen/PowerPC/builtins-ppc-fastmath.c
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Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-unknown \
// RUN: %clang_cc1 -triple powerpc64-unknown-unknown \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-unknown \
// RUN: %clang_cc1 -triple powerpc64le-unknown-unknown \
// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-aix \
// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-aix \
// RUN: %clang_cc1 -triple powerpc-unknown-aix \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s

extern vector float a;
Expand All @@ -16,10 +16,10 @@ extern vector double e;
extern vector double f;

// CHECK-LABEL: @test_flags_recipdivf(
// CHECK: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @a, align 16
// CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, <4 x float>* @b, align 16
// CHECK: [[TMP0:%.*]] = load <4 x float>, ptr @a, align 16
// CHECK-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @b, align 16
// CHECK-NEXT: [[RECIPDIV:%.*]] = fdiv fast <4 x float> [[TMP0]], [[TMP1]]
// CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, <4 x float>* @c, align 16
// CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr @c, align 16
// CHECK-NEXT: [[ADD:%.*]] = fadd <4 x float> [[RECIPDIV]], [[TMP2]]
// CHECK-NEXT: ret <4 x float> [[ADD]]
//
Expand All @@ -28,10 +28,10 @@ vector float test_flags_recipdivf() {
}

// CHECK-LABEL: @test_flags_recipdivd(
// CHECK: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @d, align 16
// CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, <2 x double>* @e, align 16
// CHECK: [[TMP0:%.*]] = load <2 x double>, ptr @d, align 16
// CHECK-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @e, align 16
// CHECK-NEXT: [[RECIPDIV:%.*]] = fdiv fast <2 x double> [[TMP0]], [[TMP1]]
// CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, <2 x double>* @f, align 16
// CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @f, align 16
// CHECK-NEXT: [[ADD:%.*]] = fadd <2 x double> [[RECIPDIV]], [[TMP2]]
// CHECK-NEXT: ret <2 x double> [[ADD]]
//
Expand All @@ -40,10 +40,10 @@ vector double test_flags_recipdivd() {
}

// CHECK-LABEL: @test_flags_rsqrtf(
// CHECK: [[TMP0:%.*]] = load <4 x float>, <4 x float>* @a, align 16
// CHECK: [[TMP0:%.*]] = load <4 x float>, ptr @a, align 16
// CHECK-NEXT: [[TMP1:%.*]] = call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> [[TMP0]])
// CHECK-NEXT: [[RSQRT:%.*]] = fdiv fast <4 x float> <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, [[TMP1]]
// CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, <4 x float>* @b, align 16
// CHECK-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr @b, align 16
// CHECK-NEXT: [[ADD:%.*]] = fadd <4 x float> [[RSQRT]], [[TMP2]]
// CHECK-NEXT: ret <4 x float> [[ADD]]
//
Expand All @@ -52,10 +52,10 @@ vector float test_flags_rsqrtf() {
}

// CHECK-LABEL: @test_flags_rsqrtd(
// CHECK: [[TMP0:%.*]] = load <2 x double>, <2 x double>* @d, align 16
// CHECK: [[TMP0:%.*]] = load <2 x double>, ptr @d, align 16
// CHECK-NEXT: [[TMP1:%.*]] = call fast <2 x double> @llvm.sqrt.v2f64(<2 x double> [[TMP0]])
// CHECK-NEXT: [[RSQRT:%.*]] = fdiv fast <2 x double> <double 1.000000e+00, double 1.000000e+00>, [[TMP1]]
// CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, <2 x double>* @e, align 16
// CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @e, align 16
// CHECK-NEXT: [[ADD:%.*]] = fadd <2 x double> [[RSQRT]], [[TMP2]]
// CHECK-NEXT: ret <2 x double> [[ADD]]
//
Expand Down
1 change: 0 additions & 1 deletion clang/test/CodeGen/PowerPC/builtins-ppc-int128.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,6 @@ void testVectorInt128Pack(){
res_vslll = __builtin_pack_vector_int128(aull[0], aull[1]);
// CHECK: %[[V1:[0-9]+]] = insertelement <2 x i64> poison, i64 %{{[0-9]+}}, i64 0
// CHECK-NEXT: %[[V2:[0-9]+]] = insertelement <2 x i64> %[[V1]], i64 %{{[0-9]+}}, i64 1
// CHECK-NEXT: bitcast <2 x i64> %[[V2]] to <1 x i128>

// CHECK-LE: %[[V1:[0-9]+]] = insertelement <2 x i64> poison, i64 %{{[0-9]+}}, i64 1
// CHECK-NEXT-LE: %[[V2:[0-9]+]] = insertelement <2 x i64> %[[V1]], i64 %{{[0-9]+}}, i64 0
Expand Down
2,614 changes: 1,268 additions & 1,346 deletions clang/test/CodeGen/PowerPC/builtins-ppc-ld-st-rmb.c
View file

Large diffs are not rendered by default.

11 changes: 0 additions & 11 deletions clang/test/CodeGen/PowerPC/builtins-ppc-p8vector.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -233,7 +233,6 @@ void test1() {
// CHECK: [[T1:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
// CHECK: [[T2:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
// CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
// CHECK: bitcast <4 x i32> [[T3]] to <16 x i8>
// CHECK-LE: [[T1:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
// CHECK-LE: [[T2:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
// CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
Expand All @@ -244,7 +243,6 @@ void test1() {
// CHECK: [[T1:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
// CHECK: [[T2:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
// CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
// CHECK: bitcast <4 x i32> [[T3]] to <16 x i8>
// CHECK-LE: [[T1:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
// CHECK-LE: [[T2:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
// CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
Expand All @@ -255,7 +253,6 @@ void test1() {
// CHECK: [[T1:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
// CHECK: [[T2:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
// CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
// CHECK: bitcast <4 x i32> [[T3]] to <16 x i8>
// CHECK-LE: [[T1:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
// CHECK-LE: [[T2:%.+]] = bitcast <16 x i8> {{.+}} to <4 x i32>
// CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
Expand All @@ -266,7 +263,6 @@ void test1() {
// CHECK: [[T1:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
// CHECK: [[T2:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
// CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
// CHECK: bitcast <4 x i32> [[T3]] to <8 x i16>
// CHECK-LE: [[T1:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
// CHECK-LE: [[T2:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
// CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
Expand All @@ -277,7 +273,6 @@ void test1() {
// CHECK: [[T1:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
// CHECK: [[T2:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
// CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
// CHECK: bitcast <4 x i32> [[T3]] to <8 x i16>
// CHECK-LE: [[T1:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
// CHECK-LE: [[T2:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
// CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
Expand All @@ -288,7 +283,6 @@ void test1() {
// CHECK: [[T1:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
// CHECK: [[T2:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
// CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
// CHECK: bitcast <4 x i32> [[T3]] to <8 x i16>
// CHECK-LE: [[T1:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
// CHECK-LE: [[T2:%.+]] = bitcast <8 x i16> {{.+}} to <4 x i32>
// CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
Expand All @@ -314,7 +308,6 @@ void test1() {
// CHECK: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
// CHECK: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
// CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
// CHECK: bitcast <4 x i32> [[T3]] to <2 x i64>
// CHECK-LE: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
// CHECK-LE: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
// CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
Expand All @@ -325,7 +318,6 @@ void test1() {
// CHECK: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
// CHECK: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
// CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
// CHECK: bitcast <4 x i32> [[T3]] to <2 x i64>
// CHECK-LE: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
// CHECK-LE: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
// CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
Expand All @@ -336,7 +328,6 @@ void test1() {
// CHECK: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
// CHECK: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
// CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
// CHECK: bitcast <4 x i32> [[T3]] to <2 x i64>
// CHECK-LE: [[T1:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
// CHECK-LE: [[T2:%.+]] = bitcast <2 x i64> {{.+}} to <4 x i32>
// CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
Expand All @@ -347,7 +338,6 @@ void test1() {
// CHECK: [[T1:%.+]] = bitcast <4 x float> {{.+}} to <4 x i32>
// CHECK: [[T2:%.+]] = bitcast <4 x float> {{.+}} to <4 x i32>
// CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
// CHECK: bitcast <4 x i32> [[T3]] to <4 x float>
// CHECK-LE: [[T1:%.+]] = bitcast <4 x float> {{.+}} to <4 x i32>
// CHECK-LE: [[T2:%.+]] = bitcast <4 x float> {{.+}} to <4 x i32>
// CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
Expand All @@ -358,7 +348,6 @@ void test1() {
// CHECK: [[T1:%.+]] = bitcast <2 x double> {{.+}} to <4 x i32>
// CHECK: [[T2:%.+]] = bitcast <2 x double> {{.+}} to <4 x i32>
// CHECK: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
// CHECK: bitcast <4 x i32> [[T3]] to <2 x double>
// CHECK-LE: [[T1:%.+]] = bitcast <2 x double> {{.+}} to <4 x i32>
// CHECK-LE: [[T2:%.+]] = bitcast <2 x double> {{.+}} to <4 x i32>
// CHECK-LE: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxleqv(<4 x i32> [[T1]], <4 x i32> [[T2]])
Expand Down
120 changes: 59 additions & 61 deletions clang/test/CodeGen/PowerPC/builtins-ppc-p9vector.c
View file
Original file line number Diff line number Diff line change
@@ -1,15 +1,15 @@
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +power9-vector \
// RUN: %clang_cc1 -target-feature +altivec -target-feature +power9-vector \
// RUN: -triple powerpc64-unknown-unknown -emit-llvm %s \
// RUN: -flax-vector-conversions=integer \
// RUN: -o - | FileCheck %s -check-prefix=CHECK-BE

// RUN: %clang_cc1 -no-opaque-pointers -target-feature +altivec -target-feature +power9-vector \
// RUN: %clang_cc1 -target-feature +altivec -target-feature +power9-vector \
// RUN: -triple powerpc64le-unknown-unknown -emit-llvm %s \
// RUN: -flax-vector-conversions=integer \
// RUN: -o - | FileCheck %s

// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +power9-vector \
// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +power9-vector \
// RUN: -triple powerpc64-unknown-unknown -emit-llvm %s \
// RUN: -o - | FileCheck %s -check-prefix=CHECK-BE

Expand Down Expand Up @@ -995,185 +995,185 @@ vector bool long long test87(void) {
return vec_test_data_class(vda, __VEC_CLASS_FP_NOT_NORMAL);
}
vector unsigned char test88(void) {
// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-BE-NEXT-NEXT: ret <16 x i8>
// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-NEXT-NEXT: ret <16 x i8>
return vec_xl_len(uc,0);
}
vector signed char test89(void) {
// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-BE-NEXT-NEXT: ret <16 x i8>
// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-NEXT-NEXT: ret <16 x i8>
return vec_xl_len(sc,0);
}
vector unsigned short test90(void) {
// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-BE-NEXT-NEXT: ret <8 x i16>
// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-NEXT-NEXT: ret <8 x i16>
return vec_xl_len(us,0);
}
vector signed short test91(void) {
// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-BE-NEXT-NEXT: ret <8 x i16>
// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-NEXT-NEXT: ret <8 x i16>
return vec_xl_len(ss,0);
}
vector unsigned int test92(void) {
// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-BE-NEXT: ret <4 x i32>
// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-NEXT: ret <4 x i32>
return vec_xl_len(ui,0);
}

vector signed int test93(void) {
// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-BE-NEXT: ret <4 x i32>
// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-NEXT: ret <4 x i32>
return vec_xl_len(si,0);
}

vector float test94(void) {
// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-BE-NEXT-NEXT: ret <4 x i32>
// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-NEXT-NEXT: ret <4 x i32>
return vec_xl_len(f,0);
}

vector unsigned long long test95(void) {
// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-BE-NEXT-NEXT: ret <2 x i64>
// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-NEXT-NEXT: ret <2 x i64>
return vec_xl_len(ull,0);
}

vector signed long long test96(void) {
// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-BE-NEXT-NEXT: ret <2 x i64>
// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-NEXT-NEXT: ret <2 x i64>
return vec_xl_len(sll,0);
}

vector double test97(void) {
// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-BE-NEXT-NEXT: ret <2 x i64>
// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-NEXT-NEXT: ret <2 x i64>
return vec_xl_len(d,0);
}

vector unsigned __int128 test98(void) {
// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-BE-NEXT-NEXT: ret <1 x i128>
// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-NEXT-NEXT: ret <1 x i128>
return vec_xl_len(uint128,0);
}

vector signed __int128 test99(void) {
// CHECK-BE: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-BE-NEXT-NEXT: ret <1 x i128>
// CHECK: @llvm.ppc.vsx.lxvl(i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.lxvl(ptr %{{.+}}, i64
// CHECK-NEXT-NEXT: ret <1 x i128>
return vec_xl_len(sint128,0);
}

void test100(void) {
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
return vec_xst_len(vuca,uc,0);
}

void test101(void) {
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
return vec_xst_len(vsca,sc,0);
}

void test102(void) {
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
return vec_xst_len(vusa,us,0);
}

void test103(void) {
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
return vec_xst_len(vssa,ss,0);
}

void test104(void) {
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
return vec_xst_len(vuia,ui,0);
}

void test105(void) {
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
return vec_xst_len(vsia,si,0);
}

void test106(void) {
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
return vec_xst_len(vfa,f,0);
}

void test107(void) {
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
return vec_xst_len(vula,ull,0);
}

void test108(void) {
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
return vec_xst_len(vsla,sll,0);
}

void test109(void) {
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
return vec_xst_len(vda,d,0);
}

void test110(void) {
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
return vec_xst_len(vui128a,uint128,0);
}

void test111(void) {
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvl(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
return vec_xst_len(vsi128a,sint128,0);
}

vector unsigned char test112(void) {
// CHECK-BE: @llvm.ppc.vsx.lxvll(i8* %{{.+}}, i64
// CHECK-BE: @llvm.ppc.altivec.lvsr(i8* %{{.+}}
// CHECK-BE: @llvm.ppc.vsx.lxvll(ptr %{{.+}}, i64
// CHECK-BE: @llvm.ppc.altivec.lvsr(ptr %{{.+}}
// CHECK-BE: @llvm.ppc.altivec.vperm
// CHECK: @llvm.ppc.vsx.lxvll(i8* %{{.+}}, i64
// CHECK: @llvm.ppc.altivec.lvsr(i8* %{{.+}}
// CHECK: @llvm.ppc.vsx.lxvll(ptr %{{.+}}, i64
// CHECK: @llvm.ppc.altivec.lvsr(ptr %{{.+}}
// CHECK: @llvm.ppc.altivec.vperm
return vec_xl_len_r(uc,0);
}
void test113(void) {
// CHECK-BE: @llvm.ppc.altivec.lvsl(i8* %{{.+}}
// CHECK-BE: @llvm.ppc.altivec.lvsl(ptr %{{.+}}
// CHECK-BE: @llvm.ppc.altivec.vperm
// CHECK-BE: @llvm.ppc.vsx.stxvll(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK: @llvm.ppc.altivec.lvsl(i8* %{{.+}}
// CHECK-BE: @llvm.ppc.vsx.stxvll(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
// CHECK: @llvm.ppc.altivec.lvsl(ptr %{{.+}}
// CHECK: @llvm.ppc.altivec.vperm
// CHECK: @llvm.ppc.vsx.stxvll(<4 x i32> %{{.+}}, i8* %{{.+}}, i64
// CHECK: @llvm.ppc.vsx.stxvll(<4 x i32> %{{.+}}, ptr %{{.+}}, i64
return vec_xst_len_r(vuca,uc,0);
}
vector float test114(void) {
Expand All @@ -1200,7 +1200,6 @@ vector unsigned char test116(void) {
// CHECK: [[T1:%.+]] = shufflevector <2 x i64> {{.+}}, <2 x i64> {{.+}}, <2 x i32> <i32 1, i32 0>
// CHECK-NEXT: [[T2:%.+]] = bitcast <2 x i64> [[T1]] to <4 x i32>
// CHECK-NEXT: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> [[T2]], <2 x i64> {{.+}}, i32 5)
// CHECK-NEXT: bitcast <4 x i32> [[T3]] to <16 x i8>
return vec_insert4b(vuia, vuca, 7);
}
vector unsigned char test117(void) {
Expand All @@ -1209,7 +1208,6 @@ vector unsigned char test117(void) {
// CHECK: [[T1:%.+]] = shufflevector <2 x i64> {{.+}}, <2 x i64> {{.+}}, <2 x i32> <i32 1, i32 0>
// CHECK-NEXT: [[T2:%.+]] = bitcast <2 x i64> [[T1]] to <4 x i32>
// CHECK-NEXT: [[T3:%.+]] = call <4 x i32> @llvm.ppc.vsx.xxinsertw(<4 x i32> [[T2]], <2 x i64> {{.+}}, i32 0)
// CHECK-NEXT: bitcast <4 x i32> [[T3]] to <16 x i8>
return vec_insert4b(vuia, vuca, 13);
}
vector unsigned long long test118(void) {
Expand Down
272 changes: 132 additions & 140 deletions clang/test/CodeGen/PowerPC/builtins-ppc-pair-mma-types.c
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6 changes: 3 additions & 3 deletions clang/test/CodeGen/PowerPC/builtins-ppc-quadword-char.c
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Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \
// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -target-feature +altivec -target-feature +power8-vector \
// RUN: -triple powerpc64-unknown-linux -emit-llvm %s -o - | FileCheck %s
//
// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \
// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -target-feature +altivec -target-feature +power8-vector \
// RUN: -triple powerpc64le-unknown-linux -emit-llvm %s -o - | FileCheck %s

// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \
// RUN: %clang_cc1 -flax-vector-conversions=none -O2 -target-feature +altivec -target-feature +power8-vector \
// RUN: -triple powerpc64-unknown-aix -emit-llvm %s -o - | FileCheck %s
#include <altivec.h>

Expand Down
44 changes: 22 additions & 22 deletions clang/test/CodeGen/PowerPC/builtins-ppc-quadword.c
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Original file line number Diff line number Diff line change
@@ -1,12 +1,12 @@
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \
// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +power8-vector \
// RUN: -triple powerpc64-unknown-unknown -emit-llvm %s -o - | FileCheck %s

// RUN: %clang_cc1 -flax-vector-conversions=none -no-opaque-pointers -target-feature +altivec -target-feature +power8-vector \
// RUN: %clang_cc1 -flax-vector-conversions=none -target-feature +altivec -target-feature +power8-vector \
// RUN: -triple powerpc64le-unknown-unknown -emit-llvm %s -o - \
// RUN: | FileCheck %s -check-prefix=CHECK-LE

// RUN: not %clang_cc1 -no-opaque-pointers -target-feature +altivec -triple powerpc-unknown-unknown \
// RUN: not %clang_cc1 -target-feature +altivec -triple powerpc-unknown-unknown \
// RUN: -emit-llvm %s -o - 2>&1 | FileCheck %s -check-prefix=CHECK-PPC
#include <altivec.h>

Expand Down Expand Up @@ -213,55 +213,55 @@ void test1() {
// CHECK-LE: @llvm.ppc.altivec.vsubecuq

res_vulll = vec_revb(vulll);
// CHECK: store <16 x i8> <i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, <16 x i8>* {{%.+}}, align 16
// CHECK: store <16 x i8> <i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, ptr {{%.+}}, align 16
// CHECK: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
// CHECK-LE: store <16 x i8> <i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, <16 x i8>* {{%.+}}, align 16
// CHECK-LE: store <16 x i8> <i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>, ptr {{%.+}}, align 16
// CHECK-LE: store <16 x i8> <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>, ptr {{%.+}}, align 16
// CHECK-LE: xor <16 x i8>
// CHECK-LE: call <4 x i32> @llvm.ppc.altivec.vperm(<4 x i32> {{%.+}}, <4 x i32> {{%.+}}, <16 x i8> {{%.+}})
// CHECK_PPC: error: call to 'vec_revb' is ambiguous

/* vec_xl */
res_vlll = vec_xl(param_sll, &param_lll);
// CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 1
// CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 1
// CHECK: load <1 x i128>, ptr %{{[0-9]+}}, align 1
// CHECK-LE: load <1 x i128>, ptr %{{[0-9]+}}, align 1
// CHECK-PPC: error: call to 'vec_xl' is ambiguous

res_vulll = vec_xl(param_sll, &param_ulll);
// CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 1
// CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 1
// CHECK: load <1 x i128>, ptr %{{[0-9]+}}, align 1
// CHECK-LE: load <1 x i128>, ptr %{{[0-9]+}}, align 1
// CHECK-PPC: error: call to 'vec_xl' is ambiguous

/* vec_xst */
vec_xst(vlll, param_sll, &param_lll);
// CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 1
// CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 1
// CHECK: store <1 x i128> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1
// CHECK-LE: store <1 x i128> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1
// CHECK-PPC: error: call to 'vec_xst' is ambiguous

vec_xst(vulll, param_sll, &param_ulll);
// CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 1
// CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 1
// CHECK: store <1 x i128> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1
// CHECK-LE: store <1 x i128> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1
// CHECK-PPC: error: call to 'vec_xst' is ambiguous

/* vec_xl_be */
res_vlll = vec_xl_be(param_sll, &param_lll);
// CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 1
// CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 1
// CHECK: load <1 x i128>, ptr %{{[0-9]+}}, align 1
// CHECK-LE: load <1 x i128>, ptr %{{[0-9]+}}, align 1
// CHECK-PPC: error: call to 'vec_xl' is ambiguous

res_vulll = vec_xl_be(param_sll, &param_ulll);
// CHECK: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 1
// CHECK-LE: load <1 x i128>, <1 x i128>* %{{[0-9]+}}, align 1
// CHECK: load <1 x i128>, ptr %{{[0-9]+}}, align 1
// CHECK-LE: load <1 x i128>, ptr %{{[0-9]+}}, align 1
// CHECK-PPC: error: call to 'vec_xl' is ambiguous

/* vec_xst_be */
vec_xst_be(vlll, param_sll, &param_lll);
// CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 1
// CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 1
// CHECK: store <1 x i128> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1
// CHECK-LE: store <1 x i128> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1
// CHECK-PPC: error: call to 'vec_xst' is ambiguous

vec_xst_be(vulll, param_sll, &param_ulll);
// CHECK: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 1
// CHECK-LE: store <1 x i128> %{{[0-9]+}}, <1 x i128>* %{{[0-9]+}}, align 1
// CHECK: store <1 x i128> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1
// CHECK-LE: store <1 x i128> %{{[0-9]+}}, ptr %{{[0-9]+}}, align 1
// CHECK-PPC: error: call to 'vec_xst' is ambiguous
}
10 changes: 5 additions & 5 deletions clang/test/CodeGen/PowerPC/builtins-ppc-stmtexpr-argument.c
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Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-linux-gnu \
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-linux-gnu \
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s

// The argument expression must not be emitted multiple times
Expand All @@ -11,9 +11,9 @@
// CHECK-NEXT: entry:
// CHECK-NEXT: [[D:%.*]] = alloca double, align 8
// CHECK-NEXT: [[TMP:%.*]] = alloca double, align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[D]], align 8
// CHECK-NEXT: store double [[TMP0]], double* [[TMP]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[TMP]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[D]], align 8
// CHECK-NEXT: store double [[TMP0]], ptr [[TMP]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[TMP]], align 8
// CHECK-NEXT: [[TMP2:%.*]] = call double @llvm.rint.f64(double [[TMP1]])
// CHECK-NEXT: ret void
//
Expand Down
724 changes: 342 additions & 382 deletions clang/test/CodeGen/PowerPC/builtins-ppc-xl-xst.c
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13 changes: 6 additions & 7 deletions clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-LoadReseve-StoreCond-64bit-only.c
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Original file line number Diff line number Diff line change
@@ -1,24 +1,23 @@
// REQUIRES: powerpc-registered-target
// RUN: not %clang_cc1 -no-opaque-pointers -triple=powerpc-unknown-aix -emit-llvm %s -o - 2>&1 |\
// RUN: not %clang_cc1 -triple=powerpc-unknown-aix -emit-llvm %s -o - 2>&1 |\
// RUN: FileCheck %s --check-prefix=CHECK32-ERROR
// RUN: %clang_cc1 -no-opaque-pointers -O2 -triple=powerpc64-unknown-aix -emit-llvm %s -o - | \
// RUN: %clang_cc1 -O2 -triple=powerpc64-unknown-aix -emit-llvm %s -o - | \
// RUN: FileCheck %s --check-prefix=CHECK64
// RUN: %clang_cc1 -no-opaque-pointers -O2 -triple=powerpc64le-unknown-linux-gnu -emit-llvm %s \
// RUN: %clang_cc1 -O2 -triple=powerpc64le-unknown-linux-gnu -emit-llvm %s \
// RUN: -o - | FileCheck %s --check-prefix=CHECK64
// RUN: %clang_cc1 -no-opaque-pointers -O2 -triple=powerpc64-unknown-linux-gnu -emit-llvm %s \
// RUN: %clang_cc1 -O2 -triple=powerpc64-unknown-linux-gnu -emit-llvm %s \
// RUN: -o - | FileCheck %s --check-prefix=CHECK64

long test_ldarx(volatile long* a) {
// CHECK64-LABEL: @test_ldarx
// CHECK64: %0 = tail call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(i64* elementtype(i64) %a)
// CHECK64: %0 = tail call i64 asm sideeffect "ldarx $0, ${1:y}", "=r,*Z,~{memory}"(ptr elementtype(i64) %a)
// CHECK32-ERROR: error: this builtin is only available on 64-bit targets
return __ldarx(a);
}

int test_stdcx(volatile long* addr, long val) {
// CHECK64-LABEL: @test_stdcx
// CHECK64: %0 = bitcast i64* %addr to i8*
// CHECK64: %1 = tail call i32 @llvm.ppc.stdcx(i8* %0, i64 %val)
// CHECK64: %0 = tail call i32 @llvm.ppc.stdcx(ptr %addr, i64 %val)
// CHECK32-ERROR: error: this builtin is only available on 64-bit targets
return __stdcx(addr, val);
}
32 changes: 16 additions & 16 deletions clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cas.c
View file
Original file line number Diff line number Diff line change
@@ -1,8 +1,8 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-linux-gnu \
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-linux-gnu \
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s


Expand All @@ -11,15 +11,15 @@
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[C_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// CHECK-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
// CHECK-NEXT: store i32 [[C:%.*]], i32* [[C_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* [[C_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = cmpxchg weak volatile i32* [[A_ADDR]], i32 [[TMP0]], i32 [[TMP1]] monotonic monotonic, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
// CHECK-NEXT: store i32 [[C:%.*]], ptr [[C_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[C_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = cmpxchg weak volatile ptr [[A_ADDR]], i32 [[TMP0]], i32 [[TMP1]] monotonic monotonic, align 4
// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i32, i1 } [[TMP2]], 0
// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i32, i1 } [[TMP2]], 1
// CHECK-NEXT: store i32 [[TMP3]], i32* [[B_ADDR]], align 4
// CHECK-NEXT: store i32 [[TMP3]], ptr [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP5:%.*]] = zext i1 [[TMP4]] to i32
// CHECK-NEXT: ret i32 [[TMP5]]
//
Expand All @@ -33,15 +33,15 @@ int test_builtin_ppc_compare_and_swap(int a, int b, int c) {
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[C_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
// CHECK-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
// CHECK-NEXT: store i64 [[C:%.*]], i64* [[C_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load i64, i64* [[C_ADDR]], align 8
// CHECK-NEXT: [[TMP2:%.*]] = cmpxchg weak volatile i64* [[A_ADDR]], i64 [[TMP0]], i64 [[TMP1]] monotonic monotonic, align 8
// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// CHECK-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR]], align 8
// CHECK-NEXT: store i64 [[C:%.*]], ptr [[C_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[C_ADDR]], align 8
// CHECK-NEXT: [[TMP2:%.*]] = cmpxchg weak volatile ptr [[A_ADDR]], i64 [[TMP0]], i64 [[TMP1]] monotonic monotonic, align 8
// CHECK-NEXT: [[TMP3:%.*]] = extractvalue { i64, i1 } [[TMP2]], 0
// CHECK-NEXT: [[TMP4:%.*]] = extractvalue { i64, i1 } [[TMP2]], 1
// CHECK-NEXT: store i64 [[TMP3]], i64* [[B_ADDR]], align 8
// CHECK-NEXT: store i64 [[TMP3]], ptr [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP5:%.*]] = zext i1 [[TMP4]] to i32
// CHECK-NEXT: ret i32 [[TMP5]]
//
Expand Down
420 changes: 210 additions & 210 deletions clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-cmplx.c
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24 changes: 12 additions & 12 deletions clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-compare.c
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Original file line number Diff line number Diff line change
@@ -1,30 +1,30 @@
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-linux-gnu \
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix=CHECK-64B
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-linux-gnu \
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s --check-prefix=CHECK-64B
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-aix \
// RUN: %clang_cc1 -triple powerpc-unknown-aix \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix=CHECK-32B
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-aix \
// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefix=CHECK-64B

// CHECK-64B-LABEL: @test_builtin_ppc_cmpb(
// CHECK-64B: [[LLA_ADDR:%.*]] = alloca i64, align 8
// CHECK-64B-NEXT: [[LLB_ADDR:%.*]] = alloca i64, align 8
// CHECK-64B-NEXT: store i64 [[LLA:%.*]], i64* [[LLA_ADDR]], align 8
// CHECK-64B-NEXT: store i64 [[LLB:%.*]], i64* [[LLB_ADDR]], align 8
// CHECK-64B-NEXT: [[TMP0:%.*]] = load i64, i64* [[LLA_ADDR]], align 8
// CHECK-64B-NEXT: [[TMP1:%.*]] = load i64, i64* [[LLB_ADDR]], align 8
// CHECK-64B-NEXT: store i64 [[LLA:%.*]], ptr [[LLA_ADDR]], align 8
// CHECK-64B-NEXT: store i64 [[LLB:%.*]], ptr [[LLB_ADDR]], align 8
// CHECK-64B-NEXT: [[TMP0:%.*]] = load i64, ptr [[LLA_ADDR]], align 8
// CHECK-64B-NEXT: [[TMP1:%.*]] = load i64, ptr [[LLB_ADDR]], align 8
// CHECK-64B-NEXT: [[CMPB:%.*]] = call i64 @llvm.ppc.cmpb.i64.i64.i64(i64 [[TMP0]], i64 [[TMP1]])
// CHECK-64B-NEXT: ret i64 [[CMPB]]
//
// CHECK-32B-LABEL: @test_builtin_ppc_cmpb(
// CHECK-32B: [[LLA_ADDR:%.*]] = alloca i64, align 8
// CHECK-32B-NEXT: [[LLB_ADDR:%.*]] = alloca i64, align 8
// CHECK-32B-NEXT: store i64 [[LLA:%.*]], i64* [[LLA_ADDR]], align 8
// CHECK-32B-NEXT: store i64 [[LLB:%.*]], i64* [[LLB_ADDR]], align 8
// CHECK-32B-NEXT: [[TMP0:%.*]] = load i64, i64* [[LLA_ADDR]], align 8
// CHECK-32B-NEXT: [[TMP1:%.*]] = load i64, i64* [[LLB_ADDR]], align 8
// CHECK-32B-NEXT: store i64 [[LLA:%.*]], ptr [[LLA_ADDR]], align 8
// CHECK-32B-NEXT: store i64 [[LLB:%.*]], ptr [[LLB_ADDR]], align 8
// CHECK-32B-NEXT: [[TMP0:%.*]] = load i64, ptr [[LLA_ADDR]], align 8
// CHECK-32B-NEXT: [[TMP1:%.*]] = load i64, ptr [[LLB_ADDR]], align 8
// CHECK-32B-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP0]] to i32
// CHECK-32B-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP1]] to i32
// CHECK-32B-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP0]], 32
Expand Down
68 changes: 34 additions & 34 deletions clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fetch.c
View file
Original file line number Diff line number Diff line change
@@ -1,18 +1,18 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-linux-gnu \
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-linux-gnu \
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s

// CHECK-LABEL: @test_builtin_ppc_fetch_and_add(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// CHECK-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw add i32* [[A_ADDR]], i32 [[TMP0]] monotonic, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw add ptr [[A_ADDR]], i32 [[TMP0]] monotonic, align 4
// CHECK-NEXT: ret void
//
void test_builtin_ppc_fetch_and_add(int a, int b) {
Expand All @@ -23,10 +23,10 @@ void test_builtin_ppc_fetch_and_add(int a, int b) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
// CHECK-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw add i64* [[A_ADDR]], i64 [[TMP0]] monotonic, align 8
// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// CHECK-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw add ptr [[A_ADDR]], i64 [[TMP0]] monotonic, align 8
// CHECK-NEXT: ret void
//
void test_builtin_ppc_fetch_and_addlp(long a, long b) {
Expand All @@ -36,10 +36,10 @@ void test_builtin_ppc_fetch_and_addlp(long a, long b) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// CHECK-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw and i32* [[A_ADDR]], i32 [[TMP0]] monotonic, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw and ptr [[A_ADDR]], i32 [[TMP0]] monotonic, align 4
// CHECK-NEXT: ret void
//
void test_builtin_ppc_fetch_and_and(unsigned int a, unsigned int b) {
Expand All @@ -49,10 +49,10 @@ void test_builtin_ppc_fetch_and_and(unsigned int a, unsigned int b) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
// CHECK-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw and i64* [[A_ADDR]], i64 [[TMP0]] monotonic, align 8
// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// CHECK-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw and ptr [[A_ADDR]], i64 [[TMP0]] monotonic, align 8
// CHECK-NEXT: ret void
//
void test_builtin_ppc_fetch_and_andlp(unsigned long a, unsigned long b) {
Expand All @@ -62,10 +62,10 @@ void test_builtin_ppc_fetch_and_andlp(unsigned long a, unsigned long b) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// CHECK-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw or i32* [[A_ADDR]], i32 [[TMP0]] monotonic, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw or ptr [[A_ADDR]], i32 [[TMP0]] monotonic, align 4
// CHECK-NEXT: ret void
//
void test_builtin_ppc_fetch_and_or(unsigned int a, unsigned int b) {
Expand All @@ -75,10 +75,10 @@ void test_builtin_ppc_fetch_and_or(unsigned int a, unsigned int b) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
// CHECK-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw or i64* [[A_ADDR]], i64 [[TMP0]] monotonic, align 8
// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// CHECK-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw or ptr [[A_ADDR]], i64 [[TMP0]] monotonic, align 8
// CHECK-NEXT: ret void
//
void test_builtin_ppc_fetch_and_orlp(unsigned long a, unsigned long b) {
Expand All @@ -88,10 +88,10 @@ void test_builtin_ppc_fetch_and_orlp(unsigned long a, unsigned long b) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4
// CHECK-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// CHECK-NEXT: store i32 [[B:%.*]], i32* [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, i32* [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg i32* [[A_ADDR]], i32 [[TMP0]] monotonic, align 4
// CHECK-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// CHECK-NEXT: store i32 [[B:%.*]], ptr [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[B_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[A_ADDR]], i32 [[TMP0]] monotonic, align 4
// CHECK-NEXT: ret void
//
void test_builtin_ppc_fetch_and_swap(unsigned int a, unsigned int b) {
Expand All @@ -101,10 +101,10 @@ void test_builtin_ppc_fetch_and_swap(unsigned int a, unsigned int b) {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8
// CHECK-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
// CHECK-NEXT: store i64 [[B:%.*]], i64* [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i64, i64* [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg i64* [[A_ADDR]], i64 [[TMP0]] monotonic, align 8
// CHECK-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// CHECK-NEXT: store i64 [[B:%.*]], ptr [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[B_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = atomicrmw xchg ptr [[A_ADDR]], i64 [[TMP0]] monotonic, align 8
// CHECK-NEXT: ret void
//
void test_builtin_ppc_fetch_and_swaplp(unsigned long a, unsigned long b) {
Expand Down
82 changes: 41 additions & 41 deletions clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-fp.c
View file
Original file line number Diff line number Diff line change
@@ -1,9 +1,9 @@
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-linux-gnu \
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-aix \
// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-aix \
// RUN: %clang_cc1 -triple powerpc-unknown-aix \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s

extern double a;
Expand All @@ -14,7 +14,7 @@ extern float e;
extern float f;

// CHECK-LABEL: @test_fric(
// CHECK: [[TMP0:%.*]] = load double, double* @a, align 8
// CHECK: [[TMP0:%.*]] = load double, ptr @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.rint.f64(double [[TMP0]])
// CHECK-NEXT: ret double [[TMP1]]
//
Expand All @@ -23,7 +23,7 @@ double test_fric() {
}

// CHECK-LABEL: @test_frim(
// CHECK: [[TMP0:%.*]] = load double, double* @a, align 8
// CHECK: [[TMP0:%.*]] = load double, ptr @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.floor.f64(double [[TMP0]])
// CHECK-NEXT: ret double [[TMP1]]
//
Expand All @@ -32,7 +32,7 @@ double test_frim() {
}

// CHECK-LABEL: @test_frims(
// CHECK: [[TMP0:%.*]] = load float, float* @d, align 4
// CHECK: [[TMP0:%.*]] = load float, ptr @d, align 4
// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.floor.f32(float [[TMP0]])
// CHECK-NEXT: ret float [[TMP1]]
//
Expand All @@ -41,7 +41,7 @@ float test_frims() {
}

// CHECK-LABEL: @test_frin(
// CHECK: [[TMP0:%.*]] = load double, double* @a, align 8
// CHECK: [[TMP0:%.*]] = load double, ptr @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.round.f64(double [[TMP0]])
// CHECK-NEXT: ret double [[TMP1]]
//
Expand All @@ -50,7 +50,7 @@ double test_frin() {
}

// CHECK-LABEL: @test_frins(
// CHECK: [[TMP0:%.*]] = load float, float* @d, align 4
// CHECK: [[TMP0:%.*]] = load float, ptr @d, align 4
// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.round.f32(float [[TMP0]])
// CHECK-NEXT: ret float [[TMP1]]
//
Expand All @@ -59,7 +59,7 @@ float test_frins() {
}

// CHECK-LABEL: @test_frip(
// CHECK: [[TMP0:%.*]] = load double, double* @a, align 8
// CHECK: [[TMP0:%.*]] = load double, ptr @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.ceil.f64(double [[TMP0]])
// CHECK-NEXT: ret double [[TMP1]]
//
Expand All @@ -68,7 +68,7 @@ double test_frip() {
}

// CHECK-LABEL: @test_frips(
// CHECK: [[TMP0:%.*]] = load float, float* @d, align 4
// CHECK: [[TMP0:%.*]] = load float, ptr @d, align 4
// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.ceil.f32(float [[TMP0]])
// CHECK-NEXT: ret float [[TMP1]]
//
Expand All @@ -77,7 +77,7 @@ float test_frips() {
}

// CHECK-LABEL: @test_friz(
// CHECK: [[TMP0:%.*]] = load double, double* @a, align 8
// CHECK: [[TMP0:%.*]] = load double, ptr @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.trunc.f64(double [[TMP0]])
// CHECK-NEXT: ret double [[TMP1]]
//
Expand All @@ -86,7 +86,7 @@ double test_friz() {
}

// CHECK-LABEL: @test_frizs(
// CHECK: [[TMP0:%.*]] = load float, float* @d, align 4
// CHECK: [[TMP0:%.*]] = load float, ptr @d, align 4
// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.trunc.f32(float [[TMP0]])
// CHECK-NEXT: ret float [[TMP1]]
//
Expand All @@ -95,9 +95,9 @@ float test_frizs() {
}

// CHECK-LABEL: @test_fsel(
// CHECK: [[TMP0:%.*]] = load double, double* @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = load double, double* @b, align 8
// CHECK-NEXT: [[TMP2:%.*]] = load double, double* @c, align 8
// CHECK: [[TMP0:%.*]] = load double, ptr @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = load double, ptr @b, align 8
// CHECK-NEXT: [[TMP2:%.*]] = load double, ptr @c, align 8
// CHECK-NEXT: [[TMP3:%.*]] = call double @llvm.ppc.fsel(double [[TMP0]], double [[TMP1]], double [[TMP2]])
// CHECK-NEXT: ret double [[TMP3]]
//
Expand All @@ -106,9 +106,9 @@ double test_fsel() {
}

// CHECK-LABEL: @test_fsels(
// CHECK: [[TMP0:%.*]] = load float, float* @d, align 4
// CHECK-NEXT: [[TMP1:%.*]] = load float, float* @e, align 4
// CHECK-NEXT: [[TMP2:%.*]] = load float, float* @f, align 4
// CHECK: [[TMP0:%.*]] = load float, ptr @d, align 4
// CHECK-NEXT: [[TMP1:%.*]] = load float, ptr @e, align 4
// CHECK-NEXT: [[TMP2:%.*]] = load float, ptr @f, align 4
// CHECK-NEXT: [[TMP3:%.*]] = call float @llvm.ppc.fsels(float [[TMP0]], float [[TMP1]], float [[TMP2]])
// CHECK-NEXT: ret float [[TMP3]]
//
Expand All @@ -117,7 +117,7 @@ float test_fsels() {
}

// CHECK-LABEL: @test_frsqrte(
// CHECK: [[TMP0:%.*]] = load double, double* @a, align 8
// CHECK: [[TMP0:%.*]] = load double, ptr @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.ppc.frsqrte(double [[TMP0]])
// CHECK-NEXT: ret double [[TMP1]]
//
Expand All @@ -126,7 +126,7 @@ double test_frsqrte() {
}

// CHECK-LABEL: @test_frsqrtes(
// CHECK: [[TMP0:%.*]] = load float, float* @d, align 4
// CHECK: [[TMP0:%.*]] = load float, ptr @d, align 4
// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.ppc.frsqrtes(float [[TMP0]])
// CHECK-NEXT: ret float [[TMP1]]
//
Expand All @@ -135,7 +135,7 @@ float test_frsqrtes() {
}

// CHECK-LABEL: @test_fsqrt(
// CHECK: [[TMP0:%.*]] = load double, double* @a, align 8
// CHECK: [[TMP0:%.*]] = load double, ptr @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.sqrt.f64(double [[TMP0]])
// CHECK-NEXT: ret double [[TMP1]]
//
Expand All @@ -144,7 +144,7 @@ double test_fsqrt() {
}

// CHECK-LABEL: @test_fsqrts(
// CHECK: [[TMP0:%.*]] = load float, float* @d, align 4
// CHECK: [[TMP0:%.*]] = load float, ptr @d, align 4
// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.sqrt.f32(float [[TMP0]])
// CHECK-NEXT: ret float [[TMP1]]
//
Expand All @@ -153,7 +153,7 @@ float test_fsqrts() {
}

// CHECK-LABEL: @test_builtin_ppc_fric(
// CHECK: [[TMP0:%.*]] = load double, double* @a, align 8
// CHECK: [[TMP0:%.*]] = load double, ptr @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.rint.f64(double [[TMP0]])
// CHECK-NEXT: ret double [[TMP1]]
//
Expand All @@ -162,7 +162,7 @@ double test_builtin_ppc_fric() {
}

// CHECK-LABEL: @test_builtin_ppc_frim(
// CHECK: [[TMP0:%.*]] = load double, double* @a, align 8
// CHECK: [[TMP0:%.*]] = load double, ptr @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.floor.f64(double [[TMP0]])
// CHECK-NEXT: ret double [[TMP1]]
//
Expand All @@ -171,7 +171,7 @@ double test_builtin_ppc_frim() {
}

// CHECK-LABEL: @test_builtin_ppc_frims(
// CHECK: [[TMP0:%.*]] = load float, float* @d, align 4
// CHECK: [[TMP0:%.*]] = load float, ptr @d, align 4
// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.floor.f32(float [[TMP0]])
// CHECK-NEXT: ret float [[TMP1]]
//
Expand All @@ -180,7 +180,7 @@ float test_builtin_ppc_frims() {
}

// CHECK-LABEL: @test_builtin_ppc_frin(
// CHECK: [[TMP0:%.*]] = load double, double* @a, align 8
// CHECK: [[TMP0:%.*]] = load double, ptr @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.round.f64(double [[TMP0]])
// CHECK-NEXT: ret double [[TMP1]]
//
Expand All @@ -189,7 +189,7 @@ double test_builtin_ppc_frin() {
}

// CHECK-LABEL: @test_builtin_ppc_frins(
// CHECK: [[TMP0:%.*]] = load float, float* @d, align 4
// CHECK: [[TMP0:%.*]] = load float, ptr @d, align 4
// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.round.f32(float [[TMP0]])
// CHECK-NEXT: ret float [[TMP1]]
//
Expand All @@ -198,7 +198,7 @@ float test_builtin_ppc_frins() {
}

// CHECK-LABEL: @test_builtin_ppc_frip(
// CHECK: [[TMP0:%.*]] = load double, double* @a, align 8
// CHECK: [[TMP0:%.*]] = load double, ptr @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.ceil.f64(double [[TMP0]])
// CHECK-NEXT: ret double [[TMP1]]
//
Expand All @@ -207,7 +207,7 @@ double test_builtin_ppc_frip() {
}

// CHECK-LABEL: @test_builtin_ppc_frips(
// CHECK: [[TMP0:%.*]] = load float, float* @d, align 4
// CHECK: [[TMP0:%.*]] = load float, ptr @d, align 4
// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.ceil.f32(float [[TMP0]])
// CHECK-NEXT: ret float [[TMP1]]
//
Expand All @@ -216,7 +216,7 @@ float test_builtin_ppc_frips() {
}

// CHECK-LABEL: @test_builtin_ppc_friz(
// CHECK: [[TMP0:%.*]] = load double, double* @a, align 8
// CHECK: [[TMP0:%.*]] = load double, ptr @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.trunc.f64(double [[TMP0]])
// CHECK-NEXT: ret double [[TMP1]]
//
Expand All @@ -225,7 +225,7 @@ double test_builtin_ppc_friz() {
}

// CHECK-LABEL: @test_builtin_ppc_frizs(
// CHECK: [[TMP0:%.*]] = load float, float* @d, align 4
// CHECK: [[TMP0:%.*]] = load float, ptr @d, align 4
// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.trunc.f32(float [[TMP0]])
// CHECK-NEXT: ret float [[TMP1]]
//
Expand All @@ -234,9 +234,9 @@ float test_builtin_ppc_frizs() {
}

// CHECK-LABEL: @test_builtin_ppc_fsel(
// CHECK: [[TMP0:%.*]] = load double, double* @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = load double, double* @b, align 8
// CHECK-NEXT: [[TMP2:%.*]] = load double, double* @c, align 8
// CHECK: [[TMP0:%.*]] = load double, ptr @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = load double, ptr @b, align 8
// CHECK-NEXT: [[TMP2:%.*]] = load double, ptr @c, align 8
// CHECK-NEXT: [[TMP3:%.*]] = call double @llvm.ppc.fsel(double [[TMP0]], double [[TMP1]], double [[TMP2]])
// CHECK-NEXT: ret double [[TMP3]]
//
Expand All @@ -245,9 +245,9 @@ double test_builtin_ppc_fsel() {
}

// CHECK-LABEL: @test_builtin_ppc_fsels(
// CHECK: [[TMP0:%.*]] = load float, float* @d, align 4
// CHECK-NEXT: [[TMP1:%.*]] = load float, float* @e, align 4
// CHECK-NEXT: [[TMP2:%.*]] = load float, float* @f, align 4
// CHECK: [[TMP0:%.*]] = load float, ptr @d, align 4
// CHECK-NEXT: [[TMP1:%.*]] = load float, ptr @e, align 4
// CHECK-NEXT: [[TMP2:%.*]] = load float, ptr @f, align 4
// CHECK-NEXT: [[TMP3:%.*]] = call float @llvm.ppc.fsels(float [[TMP0]], float [[TMP1]], float [[TMP2]])
// CHECK-NEXT: ret float [[TMP3]]
//
Expand All @@ -256,7 +256,7 @@ float test_builtin_ppc_fsels() {
}

// CHECK-LABEL: @test_builtin_ppc_frsqrte(
// CHECK: [[TMP0:%.*]] = load double, double* @a, align 8
// CHECK: [[TMP0:%.*]] = load double, ptr @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.ppc.frsqrte(double [[TMP0]])
// CHECK-NEXT: ret double [[TMP1]]
//
Expand All @@ -265,7 +265,7 @@ double test_builtin_ppc_frsqrte() {
}

// CHECK-LABEL: @test_builtin_ppc_frsqrtes(
// CHECK: [[TMP0:%.*]] = load float, float* @d, align 4
// CHECK: [[TMP0:%.*]] = load float, ptr @d, align 4
// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.ppc.frsqrtes(float [[TMP0]])
// CHECK-NEXT: ret float [[TMP1]]
//
Expand All @@ -274,7 +274,7 @@ float test_builtin_ppc_frsqrtes() {
}

// CHECK-LABEL: @test_builtin_ppc_fsqrt(
// CHECK: [[TMP0:%.*]] = load double, double* @a, align 8
// CHECK: [[TMP0:%.*]] = load double, ptr @a, align 8
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.sqrt.f64(double [[TMP0]])
// CHECK-NEXT: ret double [[TMP1]]
//
Expand All @@ -283,7 +283,7 @@ double test_builtin_ppc_fsqrt() {
}

// CHECK-LABEL: @test_builtin_ppc_fsqrts(
// CHECK: [[TMP0:%.*]] = load float, float* @d, align 4
// CHECK: [[TMP0:%.*]] = load float, ptr @d, align 4
// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.sqrt.f32(float [[TMP0]])
// CHECK-NEXT: ret float [[TMP1]]
//
Expand Down
12 changes: 5 additions & 7 deletions clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed-64bit-only.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,10 +12,9 @@ extern unsigned long long ull;
extern unsigned long long *ull_addr;

// CHECK-LABEL: @test_builtin_ppc_store8r(
// CHECK: [[TMP0:%.*]] = load i64, i64* @ull, align 8
// CHECK-NEXT: [[TMP1:%.*]] = load i64*, i64** @ull_addr, align 8
// CHECK-NEXT: [[TMP2:%.*]] = bitcast i64* [[TMP1]] to i8*
// CHECK-NEXT: call void @llvm.ppc.store8r(i64 [[TMP0]], i8* [[TMP2]])
// CHECK: [[TMP0:%.*]] = load i64, ptr @ull, align 8
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr @ull_addr, align 8
// CHECK-NEXT: call void @llvm.ppc.store8r(i64 [[TMP0]], ptr [[TMP1]])
// CHECK-NEXT: ret void

// CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
Expand All @@ -24,9 +23,8 @@ void test_builtin_ppc_store8r() {
}

// CHECK-LABEL: @test_builtin_ppc_load8r(
// CHECK: [[TMP0:%.*]] = load i64*, i64** @ull_addr, align 8
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i64* [[TMP0]] to i8*
// CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.ppc.load8r(i8* [[TMP1]])
// CHECK: [[TMP0:%.*]] = load ptr, ptr @ull_addr, align 8
// CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.ppc.load8r(ptr [[TMP0]])
// CHECK-NEXT: ret i64 [[TMP2]]

// CHECK-32-ERROR: error: this builtin is only available on 64-bit targets
Expand Down
56 changes: 24 additions & 32 deletions clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-load-store-reversed.c
View file
Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-linux-gnu \
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-linux-gnu \
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-aix \
// RUN: %clang_cc1 -triple powerpc-unknown-aix \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefixes=CHECK-32B
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-aix \
// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s

extern unsigned short us;
Expand All @@ -14,54 +14,48 @@ extern unsigned short *us_addr;
extern unsigned int *ui_addr;

// CHECK-LABEL: @test_builtin_ppc_store2r(
// CHECK: [[TMP0:%.*]] = load i16, i16* @us, align 2
// CHECK: [[TMP0:%.*]] = load i16, ptr @us, align 2
// CHECK-NEXT: [[CONV:%.*]] = zext i16 [[TMP0]] to i32
// CHECK-NEXT: [[TMP1:%.*]] = load i16*, i16** @us_addr, align 8
// CHECK-NEXT: [[TMP2:%.*]] = bitcast i16* [[TMP1]] to i8*
// CHECK-NEXT: call void @llvm.ppc.store2r(i32 [[CONV]], i8* [[TMP2]])
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr @us_addr, align 8
// CHECK-NEXT: call void @llvm.ppc.store2r(i32 [[CONV]], ptr [[TMP1]])
// CHECK-NEXT: ret void
//
// CHECK-32B-LABEL: @test_builtin_ppc_store2r(
// CHECK-32B: [[TMP0:%.*]] = load i16, i16* @us, align 2
// CHECK-32B: [[TMP0:%.*]] = load i16, ptr @us, align 2
// CHECK-32B-NEXT: [[CONV:%.*]] = zext i16 [[TMP0]] to i32
// CHECK-32B-NEXT: [[TMP1:%.*]] = load i16*, i16** @us_addr, align 4
// CHECK-32B-NEXT: [[TMP2:%.*]] = bitcast i16* [[TMP1]] to i8*
// CHECK-32B-NEXT: call void @llvm.ppc.store2r(i32 [[CONV]], i8* [[TMP2]])
// CHECK-32B-NEXT: [[TMP1:%.*]] = load ptr, ptr @us_addr, align 4
// CHECK-32B-NEXT: call void @llvm.ppc.store2r(i32 [[CONV]], ptr [[TMP1]])
// CHECK-32B-NEXT: ret void
//
void test_builtin_ppc_store2r() {
__builtin_ppc_store2r(us, us_addr);
}

// CHECK-LABEL: @test_builtin_ppc_store4r(
// CHECK: [[TMP0:%.*]] = load i32, i32* @ui, align 4
// CHECK-NEXT: [[TMP1:%.*]] = load i32*, i32** @ui_addr, align 8
// CHECK-NEXT: [[TMP2:%.*]] = bitcast i32* [[TMP1]] to i8*
// CHECK-NEXT: call void @llvm.ppc.store4r(i32 [[TMP0]], i8* [[TMP2]])
// CHECK: [[TMP0:%.*]] = load i32, ptr @ui, align 4
// CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr @ui_addr, align 8
// CHECK-NEXT: call void @llvm.ppc.store4r(i32 [[TMP0]], ptr [[TMP1]])
// CHECK-NEXT: ret void
//
// CHECK-32B-LABEL: @test_builtin_ppc_store4r(
// CHECK-32B: [[TMP0:%.*]] = load i32, i32* @ui, align 4
// CHECK-32B-NEXT: [[TMP1:%.*]] = load i32*, i32** @ui_addr, align 4
// CHECK-32B-NEXT: [[TMP2:%.*]] = bitcast i32* [[TMP1]] to i8*
// CHECK-32B-NEXT: call void @llvm.ppc.store4r(i32 [[TMP0]], i8* [[TMP2]])
// CHECK-32B: [[TMP0:%.*]] = load i32, ptr @ui, align 4
// CHECK-32B-NEXT: [[TMP1:%.*]] = load ptr, ptr @ui_addr, align 4
// CHECK-32B-NEXT: call void @llvm.ppc.store4r(i32 [[TMP0]], ptr [[TMP1]])
// CHECK-32B-NEXT: ret void
//
void test_builtin_ppc_store4r() {
__builtin_ppc_store4r(ui, ui_addr);
}

// CHECK-LABEL: @test_builtin_ppc_load2r(
// CHECK: [[TMP0:%.*]] = load i16*, i16** @us_addr, align 8
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i16* [[TMP0]] to i8*
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.load2r(i8* [[TMP1]])
// CHECK: [[TMP0:%.*]] = load ptr, ptr @us_addr, align 8
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.load2r(ptr [[TMP0]])
// CHECK-NEXT: [[CONV:%.*]] = trunc i32 [[TMP2]] to i16
// CHECK-NEXT: ret i16 [[CONV]]
//
// CHECK-32B-LABEL: @test_builtin_ppc_load2r(
// CHECK-32B: [[TMP0:%.*]] = load i16*, i16** @us_addr, align 4
// CHECK-32B-NEXT: [[TMP1:%.*]] = bitcast i16* [[TMP0]] to i8*
// CHECK-32B-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.load2r(i8* [[TMP1]])
// CHECK-32B: [[TMP0:%.*]] = load ptr, ptr @us_addr, align 4
// CHECK-32B-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.load2r(ptr [[TMP0]])
// CHECK-32B-NEXT: [[CONV:%.*]] = trunc i32 [[TMP2]] to i16
// CHECK-32B-NEXT: ret i16 [[CONV]]
//
Expand All @@ -70,15 +64,13 @@ unsigned short test_builtin_ppc_load2r() {
}

// CHECK-LABEL: @test_builtin_ppc_load4r(
// CHECK: [[TMP0:%.*]] = load i32*, i32** @ui_addr, align 8
// CHECK-NEXT: [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8*
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.load4r(i8* [[TMP1]])
// CHECK: [[TMP0:%.*]] = load ptr, ptr @ui_addr, align 8
// CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.load4r(ptr [[TMP0]])
// CHECK-NEXT: ret i32 [[TMP2]]
//
// CHECK-32B-LABEL: @test_builtin_ppc_load4r(
// CHECK-32B: [[TMP0:%.*]] = load i32*, i32** @ui_addr, align 4
// CHECK-32B-NEXT: [[TMP1:%.*]] = bitcast i32* [[TMP0]] to i8*
// CHECK-32B-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.load4r(i8* [[TMP1]])
// CHECK-32B: [[TMP0:%.*]] = load ptr, ptr @ui_addr, align 4
// CHECK-32B-NEXT: [[TMP2:%.*]] = call i32 @llvm.ppc.load4r(ptr [[TMP0]])
// CHECK-32B-NEXT: ret i32 [[TMP2]]
//
unsigned int test_builtin_ppc_load4r() {
Expand Down
48 changes: 24 additions & 24 deletions clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-macros.c
View file
Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-linux-gnu \
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefixes=64BIT --check-prefix=BOTH
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-linux-gnu \
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu \
// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s --check-prefixes=64BIT --check-prefix=BOTH
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-aix \
// RUN: %clang_cc1 -triple powerpc-unknown-aix \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefixes=32BIT --check-prefix=BOTH
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-aix \
// RUN: %clang_cc1 -triple powerpc64-unknown-aix \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s --check-prefixes=64BIT --check-prefix=BOTH

// Will not be adding include files to avoid any dependencies on the system.
Expand All @@ -15,8 +15,8 @@ typedef __SIZE_TYPE__ size_t;
// BOTH-LABEL: @testabs(
// BOTH-NEXT: entry:
// BOTH-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// BOTH-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// BOTH-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// BOTH-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// BOTH-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// BOTH-NEXT: [[NEG:%.*]] = sub nsw i32 0, [[TMP0]]
// BOTH-NEXT: [[ABSCOND:%.*]] = icmp slt i32 [[TMP0]], 0
// BOTH-NEXT: [[ABS:%.*]] = select i1 [[ABSCOND]], i32 [[NEG]], i32 [[TMP0]]
Expand All @@ -28,8 +28,8 @@ signed int testabs(signed int a) {
// 64BIT-LABEL: @testlabs(
// 64BIT-NEXT: entry:
// 64BIT-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// 64BIT-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
// 64BIT-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
// 64BIT-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// 64BIT-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// 64BIT-NEXT: [[NEG:%.*]] = sub nsw i64 0, [[TMP0]]
// 64BIT-NEXT: [[ABSCOND:%.*]] = icmp slt i64 [[TMP0]], 0
// 64BIT-NEXT: [[ABS:%.*]] = select i1 [[ABSCOND]], i64 [[NEG]], i64 [[TMP0]]
Expand All @@ -38,8 +38,8 @@ signed int testabs(signed int a) {
// 32BIT-LABEL: @testlabs(
// 32BIT-NEXT: entry:
// 32BIT-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// 32BIT-NEXT: store i32 [[A:%.*]], i32* [[A_ADDR]], align 4
// 32BIT-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
// 32BIT-NEXT: store i32 [[A:%.*]], ptr [[A_ADDR]], align 4
// 32BIT-NEXT: [[TMP0:%.*]] = load i32, ptr [[A_ADDR]], align 4
// 32BIT-NEXT: [[NEG:%.*]] = sub nsw i32 0, [[TMP0]]
// 32BIT-NEXT: [[ABSCOND:%.*]] = icmp slt i32 [[TMP0]], 0
// 32BIT-NEXT: [[ABS:%.*]] = select i1 [[ABSCOND]], i32 [[NEG]], i32 [[TMP0]]
Expand All @@ -52,8 +52,8 @@ signed long testlabs(signed long a) {
// 64BIT-LABEL: @testllabs(
// 64BIT-NEXT: entry:
// 64BIT-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// 64BIT-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
// 64BIT-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
// 64BIT-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// 64BIT-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// 64BIT-NEXT: [[NEG:%.*]] = sub nsw i64 0, [[TMP0]]
// 64BIT-NEXT: [[ABSCOND:%.*]] = icmp slt i64 [[TMP0]], 0
// 64BIT-NEXT: [[ABS:%.*]] = select i1 [[ABSCOND]], i64 [[NEG]], i64 [[TMP0]]
Expand All @@ -62,8 +62,8 @@ signed long testlabs(signed long a) {
// 32BIT-LABEL: @testllabs(
// 32BIT-NEXT: entry:
// 32BIT-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// 32BIT-NEXT: store i64 [[A:%.*]], i64* [[A_ADDR]], align 8
// 32BIT-NEXT: [[TMP0:%.*]] = load i64, i64* [[A_ADDR]], align 8
// 32BIT-NEXT: store i64 [[A:%.*]], ptr [[A_ADDR]], align 8
// 32BIT-NEXT: [[TMP0:%.*]] = load i64, ptr [[A_ADDR]], align 8
// 32BIT-NEXT: [[NEG:%.*]] = sub nsw i64 0, [[TMP0]]
// 32BIT-NEXT: [[ABSCOND:%.*]] = icmp slt i64 [[TMP0]], 0
// 32BIT-NEXT: [[ABS:%.*]] = select i1 [[ABSCOND]], i64 [[NEG]], i64 [[TMP0]]
Expand All @@ -75,11 +75,11 @@ signed long long testllabs(signed long long a) {

// 64BIT-LABEL: @testalloca(
// 64BIT: [[TMP1:%.*]] = alloca i8, i64
// 64BIT-NEXT: ret i8* [[TMP1]]
// 64BIT-NEXT: ret ptr [[TMP1]]
//
// 32BIT-LABEL: @testalloca(
// 32BIT: [[TMP1:%.*]] = alloca i8, i32
// 32BIT-NEXT: ret i8* [[TMP1]]
// 32BIT-NEXT: ret ptr [[TMP1]]
//
void *testalloca(size_t size) {
return __alloca(size);
Expand Down Expand Up @@ -155,47 +155,47 @@ extern void bcopy(const void *__src, void *__dest, size_t __n);
extern void bzero(void *__s, size_t __n);

// 64BIT-LABEL: @testalignx(
// 64BIT: call void @llvm.assume(i1 true) [ "align"(i8* {{%.*}}, i64 16) ]
// 64BIT: call void @llvm.assume(i1 true) [ "align"(ptr {{%.*}}, i64 16) ]
// 64BIT-NEXT: ret void
//
// 32BIT-LABEL: @testalignx(
// 32BIT: call void @llvm.assume(i1 true) [ "align"(i8* {{%.*}}, i32 16) ]
// 32BIT: call void @llvm.assume(i1 true) [ "align"(ptr {{%.*}}, i32 16) ]
// 32BIT-NEXT: ret void
//
void testalignx(const void *pointer) {
__alignx(16, pointer);
}

// 64BIT-LABEL: @testbcopy(
// 64BIT: call void @bcopy(i8* noundef {{%.*}}, i8* noundef {{%.*}}, i64 noundef {{%.*}})
// 64BIT: call void @bcopy(ptr noundef {{%.*}}, ptr noundef {{%.*}}, i64 noundef {{%.*}})
// 64BIT-NEXT: ret void
//
// 32BIT-LABEL: @testbcopy(
// 32BIT: call void @bcopy(i8* noundef {{%.*}}, i8* noundef {{%.*}}, i32 noundef {{%.*}})
// 32BIT: call void @bcopy(ptr noundef {{%.*}}, ptr noundef {{%.*}}, i32 noundef {{%.*}})
// 32BIT-NEXT: ret void
//
void testbcopy(const void *src, void *dest, size_t n) {
__bcopy(src, dest, n);
}

// 64BIT-LABEL: @testbzero(
// 64BIT: call void @llvm.memset.p0i8.i64(i8* align 1 {{%.*}}, i8 0, i64 {{%.*}}, i1 false)
// 64BIT: call void @llvm.memset.p0.i64(ptr align 1 {{%.*}}, i8 0, i64 {{%.*}}, i1 false)
// 64BIT-NEXT: ret void
//
// 32BIT-LABEL: @testbzero(
// 32BIT: call void @llvm.memset.p0i8.i32(i8* align 1 {{%.*}}, i8 0, i32 {{%.*}}, i1 false)
// 32BIT: call void @llvm.memset.p0.i32(ptr align 1 {{%.*}}, i8 0, i32 {{%.*}}, i1 false)
// 32BIT-NEXT: ret void
//
void testbzero(void *s, size_t n) {
bzero(s, n);
}

// 64BIT-LABEL: @testdcbf(
// 64BIT: call void @llvm.ppc.dcbf(i8* {{%.*}})
// 64BIT: call void @llvm.ppc.dcbf(ptr {{%.*}})
// 64BIT-NEXT: ret void
//
// 32BIT-LABEL: @testdcbf(
// 32BIT: call void @llvm.ppc.dcbf(i8* {{%.*}})
// 32BIT: call void @llvm.ppc.dcbf(ptr {{%.*}})
// 32BIT-NEXT: ret void
//
void testdcbf(const void *addr) {
Expand Down
64 changes: 32 additions & 32 deletions clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-math.c
View file
Original file line number Diff line number Diff line change
@@ -1,10 +1,10 @@
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-linux-gnu -emit-llvm %s \
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm %s \
// RUN: -target-cpu pwr7 -o - | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-linux-gnu -emit-llvm %s \
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm %s \
// RUN: -target-cpu pwr8 -o - | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-aix -emit-llvm %s \
// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
// RUN: -target-cpu pwr7 -o - | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-aix -emit-llvm %s \
// RUN: %clang_cc1 -triple powerpc-unknown-aix -emit-llvm %s \
// RUN: -target-cpu pwr7 -o - | FileCheck %s

// CHECK-LABEL: @mtfsb0(
Expand Down Expand Up @@ -42,10 +42,10 @@ void mtfsfi (void) {

// CHECK-LABEL: @fmsub(
// CHECK: [[D_ADDR:%.*]] = alloca double, align 8
// CHECK-NEXT: store double [[D:%.*]], double* [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP2:%.*]] = load double, double* [[D_ADDR]], align 8
// CHECK-NEXT: store double [[D:%.*]], ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP2:%.*]] = load double, ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP3:%.*]] = call double @llvm.ppc.fmsub(double [[TMP0]], double [[TMP1]], double [[TMP2]])
// CHECK-NEXT: ret double [[TMP3]]
//
Expand All @@ -55,10 +55,10 @@ double fmsub (double d) {

// CHECK-LABEL: @fmsubs(
// CHECK: [[F_ADDR:%.*]] = alloca float, align 4
// CHECK-NEXT: store float [[F:%.*]], float* [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load float, float* [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load float, float* [[F_ADDR]], align 4
// CHECK-NEXT: store float [[F:%.*]], ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = call float @llvm.ppc.fmsubs(float [[TMP0]], float [[TMP1]], float [[TMP2]])
// CHECK-NEXT: ret float [[TMP3]]
//
Expand All @@ -68,10 +68,10 @@ float fmsubs (float f) {

// CHECK-LABEL: @fnmadd(
// CHECK: [[D_ADDR:%.*]] = alloca double, align 8
// CHECK-NEXT: store double [[D:%.*]], double* [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP2:%.*]] = load double, double* [[D_ADDR]], align 8
// CHECK-NEXT: store double [[D:%.*]], ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP2:%.*]] = load double, ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP3:%.*]] = call double @llvm.ppc.fnmadd(double [[TMP0]], double [[TMP1]], double [[TMP2]])
// CHECK-NEXT: ret double [[TMP3]]
//
Expand All @@ -81,10 +81,10 @@ double fnmadd (double d) {

// CHECK-LABEL: @fnmadds(
// CHECK: [[F_ADDR:%.*]] = alloca float, align 4
// CHECK-NEXT: store float [[F:%.*]], float* [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load float, float* [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load float, float* [[F_ADDR]], align 4
// CHECK-NEXT: store float [[F:%.*]], ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = call float @llvm.ppc.fnmadds(float [[TMP0]], float [[TMP1]], float [[TMP2]])
// CHECK-NEXT: ret float [[TMP3]]
//
Expand All @@ -94,10 +94,10 @@ float fnmadds (float f) {

// CHECK-LABEL: @fnmsub(
// CHECK: [[D_ADDR:%.*]] = alloca double, align 8
// CHECK-NEXT: store double [[D:%.*]], double* [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load double, double* [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP2:%.*]] = load double, double* [[D_ADDR]], align 8
// CHECK-NEXT: store double [[D:%.*]], ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = load double, ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP2:%.*]] = load double, ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP3:%.*]] = call double @llvm.ppc.fnmsub.f64(double [[TMP0]], double [[TMP1]], double [[TMP2]])
// CHECK-NEXT: ret double [[TMP3]]
//
Expand All @@ -107,10 +107,10 @@ double fnmsub (double d) {

// CHECK-LABEL: @fnmsubs(
// CHECK: [[F_ADDR:%.*]] = alloca float, align 4
// CHECK-NEXT: store float [[F:%.*]], float* [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load float, float* [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load float, float* [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load float, float* [[F_ADDR]], align 4
// CHECK-NEXT: store float [[F:%.*]], ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP2:%.*]] = load float, ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP3:%.*]] = call float @llvm.ppc.fnmsub.f32(float [[TMP0]], float [[TMP1]], float [[TMP2]])
// CHECK-NEXT: ret float [[TMP3]]
//
Expand All @@ -120,8 +120,8 @@ float fnmsubs (float f) {

// CHECK-LABEL: @fre(
// CHECK: [[D_ADDR:%.*]] = alloca double, align 8
// CHECK-NEXT: store double [[D:%.*]], double* [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, double* [[D_ADDR]], align 8
// CHECK-NEXT: store double [[D:%.*]], ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP0:%.*]] = load double, ptr [[D_ADDR]], align 8
// CHECK-NEXT: [[TMP1:%.*]] = call double @llvm.ppc.fre(double [[TMP0]])
// CHECK-NEXT: ret double [[TMP1]]
//
Expand All @@ -131,8 +131,8 @@ double fre (double d) {

// CHECK-LABEL: @fres(
// CHECK: [[F_ADDR:%.*]] = alloca float, align 4
// CHECK-NEXT: store float [[F:%.*]], float* [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load float, float* [[F_ADDR]], align 4
// CHECK-NEXT: store float [[F:%.*]], ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP0:%.*]] = load float, ptr [[F_ADDR]], align 4
// CHECK-NEXT: [[TMP1:%.*]] = call float @llvm.ppc.fres(float [[TMP0]])
// CHECK-NEXT: ret float [[TMP1]]
//
Expand Down
16 changes: 8 additions & 8 deletions clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-prefetch.c
View file
Original file line number Diff line number Diff line change
@@ -1,26 +1,26 @@
// RUN: %clang_cc1 -no-opaque-pointers -O2 -triple powerpc64-unknown-linux-gnu \
// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-linux-gnu \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -O2 -triple powerpc64le-unknown-linux-gnu \
// RUN: %clang_cc1 -O2 -triple powerpc64le-unknown-linux-gnu \
// RUN: -emit-llvm %s -o - -target-cpu pwr8 | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -O2 -triple powerpc-unknown-aix \
// RUN: %clang_cc1 -O2 -triple powerpc-unknown-aix \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s
// RUN: %clang_cc1 -no-opaque-pointers -O2 -triple powerpc64-unknown-aix \
// RUN: %clang_cc1 -O2 -triple powerpc64-unknown-aix \
// RUN: -emit-llvm %s -o - -target-cpu pwr7 | FileCheck %s

extern void *vpa;

void test_dcbtstt(void) {
// CHECK-LABEL: @test_dcbtstt
// CHECK: %0 = load i8*, i8** @vpa
// CHECK: tail call void @llvm.ppc.dcbtstt(i8* %0)
// CHECK: %0 = load ptr, ptr @vpa
// CHECK: tail call void @llvm.ppc.dcbtstt(ptr %0)
// CHECK: ret void
__dcbtstt(vpa);
}

void test_dcbtt(void) {
// CHECK-LABEL: @test_dcbt
// CHECK: %0 = load i8*, i8** @vpa
// CHECK: tail call void @llvm.ppc.dcbtt(i8* %0)
// CHECK: %0 = load ptr, ptr @vpa
// CHECK: tail call void @llvm.ppc.dcbtt(ptr %0)
// CHECK: ret void
__dcbtt(vpa);
}
24 changes: 12 additions & 12 deletions clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat-pwr8.c
View file
Original file line number Diff line number Diff line change
@@ -1,17 +1,17 @@
// REQUIRES: powerpc-registered-target
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-linux-gnu -emit-llvm %s \
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm %s \
// RUN: -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64le-unknown-linux-gnu -emit-llvm %s \
// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -emit-llvm %s \
// RUN: -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-aix -emit-llvm %s \
// RUN: %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
// RUN: -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8
// RUN: %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-aix %s -emit-llvm %s \
// RUN: %clang_cc1 -triple powerpc-unknown-aix %s -emit-llvm %s \
// RUN: -target-cpu pwr8 -o - | FileCheck %s -check-prefix=CHECK-PWR8
// RUN: not %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-linux-gnu -emit-llvm %s \
// RUN: not %clang_cc1 -triple powerpc64-unknown-linux-gnu -emit-llvm %s \
// RUN: -target-cpu pwr7 -o - 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8
// RUN: not %clang_cc1 -no-opaque-pointers -triple powerpc64-unknown-aix -emit-llvm %s \
// RUN: not %clang_cc1 -triple powerpc64-unknown-aix -emit-llvm %s \
// RUN: -target-cpu pwr7 -o - 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8
// RUN: not %clang_cc1 -no-opaque-pointers -triple powerpc-unknown-aix %s -emit-llvm %s \
// RUN: not %clang_cc1 -triple powerpc-unknown-aix %s -emit-llvm %s \
// RUN: -target-cpu pwr7 -o - 2>&1 | FileCheck %s -check-prefix=CHECK-NOPWR8

extern void *a;
Expand All @@ -22,24 +22,24 @@ void test_icbt() {
// CHECK-LABEL: @test_icbt(

__icbt(a);
// CHECK-PWR8: call void @llvm.ppc.icbt(i8* %0)
// CHECK-PWR8: call void @llvm.ppc.icbt(ptr %0)
// CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs
}

void test_builtin_ppc_icbt() {
// CHECK-LABEL: @test_builtin_ppc_icbt(

__builtin_ppc_icbt(a);
// CHECK-PWR8: call void @llvm.ppc.icbt(i8* %0)
// CHECK-PWR8: call void @llvm.ppc.icbt(ptr %0)
// CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs
}

int test_builtin_ppc_stbcx() {
// CHECK-PWR8-LABEL: @test_builtin_ppc_stbcx(
// CHECK-PWR8: [[TMP0:%.*]] = load i8*, i8** @c_addr, align {{[0-9]+}}
// CHECK-PWR8-NEXT: [[TMP1:%.*]] = load i8, i8* @c, align 1
// CHECK-PWR8: [[TMP0:%.*]] = load ptr, ptr @c_addr, align {{[0-9]+}}
// CHECK-PWR8-NEXT: [[TMP1:%.*]] = load i8, ptr @c, align 1
// CHECK-PWR8-NEXT: [[TMP2:%.*]] = sext i8 [[TMP1]] to i32
// CHECK-PWR8-NEXT: [[TMP3:%.*]] = call i32 @llvm.ppc.stbcx(i8* [[TMP0]], i32 [[TMP2]])
// CHECK-PWR8-NEXT: [[TMP3:%.*]] = call i32 @llvm.ppc.stbcx(ptr [[TMP0]], i32 [[TMP2]])
// CHECK-PWR8-NEXT: ret i32 [[TMP3]]
// CHECK-NOPWR8: error: this builtin is only valid on POWER8 or later CPUs
return __builtin_ppc_stbcx(c_addr, c);
Expand Down
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