diff --git a/llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll b/llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll
@@ -1,6 +1,25 @@
-; RUN: llc < %s -mtriple=x86_64-- | not grep "movzbl	%[abcd]h,"
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 
 define void @BZ2_bzDecompress_bb5_2E_outer_bb35_2E_i_bb54_2E_i(i32*, i32 %c_nblock_used.2.i, i32 %.reload51, i32* %.out, i32* %.out1, i32* %.out2, i32* %.out3) nounwind {
+; CHECK-LABEL: BZ2_bzDecompress_bb5_2E_outer_bb35_2E_i_bb54_2E_i:
+; CHECK:       # %bb.0: # %newFuncRoot
+; CHECK-NEXT:    movq {{[0-9]+}}(%rsp), %r10
+; CHECK-NEXT:    movl %edx, %edx
+; CHECK-NEXT:    movl (%rdi,%rdx,4), %edx
+; CHECK-NEXT:    movzbl %dl, %eax
+; CHECK-NEXT:    shrq $6, %rdx
+; CHECK-NEXT:    andl $67108860, %edx # imm = 0x3FFFFFC
+; CHECK-NEXT:    addl $4, %eax
+; CHECK-NEXT:    movl (%rdi,%rdx), %edx
+; CHECK-NEXT:    movzbl %dl, %edi
+; CHECK-NEXT:    shrl $8, %edx
+; CHECK-NEXT:    addl $5, %esi
+; CHECK-NEXT:    movl %eax, (%rcx)
+; CHECK-NEXT:    movl %edi, (%r8)
+; CHECK-NEXT:    movl %edx, (%r9)
+; CHECK-NEXT:    movl %esi, (%r10)
+; CHECK-NEXT:    retq
 newFuncRoot:
 	br label %bb54.i
 

diff --git a/llvm/test/CodeGen/X86/2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll b/llvm/test/CodeGen/X86/2009-06-12-x86_64-tail-call-conv-out-of-sync-bug.ll
@@ -1,13 +1,24 @@
-; RUN: llc < %s -tailcallopt -mattr=+sse2 -mtriple=x86_64-apple-darwin | grep fstpt
-; RUN: llc < %s -tailcallopt -mattr=+sse2 -mtriple=x86_64-apple-darwin | grep xmm
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -tailcallopt -mattr=+sse2 -mtriple=x86_64-apple-darwin | FileCheck %s
 
 ; Check that x86-64 tail calls support x86_fp80 and v2f32 types. (Tail call
 ; calling convention out of sync with standard c calling convention on x86_64)
 ; Bug 4278.
 
-declare fastcc double @tailcallee(x86_fp80, <2 x float>) 
-	
+declare fastcc double @tailcallee(x86_fp80, <2 x float>)
+
 define fastcc double @tailcall() {
+; CHECK-LABEL: tailcall:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    subq $40, %rsp
+; CHECK-NEXT:    .cfi_def_cfa_offset 48
+; CHECK-NEXT:    movq {{[0-9]+}}(%rsp), %rax
+; CHECK-NEXT:    movq %rax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    fld1
+; CHECK-NEXT:    fstpt {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movaps {{.*#+}} xmm0 = <1.0E+0,1.0E+0,u,u>
+; CHECK-NEXT:    addq $24, %rsp
+; CHECK-NEXT:    jmp _tailcallee ## TAILCALL
 entry:
   %tmp = fpext float 1.000000e+00 to x86_fp80
 	%tmp2 = tail call fastcc double @tailcallee( x86_fp80 %tmp,  <2 x float> <float 1.000000e+00, float 1.000000e+00>)

diff --git a/llvm/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll b/llvm/test/CodeGen/X86/2009-06-15-not-a-tail-call.ll
@@ -1,10 +1,25 @@
-; RUN: llc < %s -mtriple=i686-- -tailcallopt | not grep TAILCALL
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- -tailcallopt | FileCheck %s
 
 ; Bug 4396. This tail call can NOT be optimized.
 
 declare fastcc i8* @_D3gcx2GC12mallocNoSyncMFmkZPv() nounwind
 
 define fastcc i8* @_D3gcx2GC12callocNoSyncMFmkZPv() nounwind {
+; CHECK-LABEL: _D3gcx2GC12callocNoSyncMFmkZPv:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    calll _D3gcx2GC12mallocNoSyncMFmkZPv
+; CHECK-NEXT:    movl %eax, %esi
+; CHECK-NEXT:    pushl $0
+; CHECK-NEXT:    pushl $2
+; CHECK-NEXT:    pushl $0
+; CHECK-NEXT:    pushl %eax
+; CHECK-NEXT:    calll memset
+; CHECK-NEXT:    addl $16, %esp
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    retl
 entry:
 	%tmp6 = tail call fastcc i8* @_D3gcx2GC12mallocNoSyncMFmkZPv()		; <i8*> [#uses=2]
 	%tmp9 = tail call i8* @memset(i8* %tmp6, i32 0, i64 2)		; <i8*> [#uses=0]

diff --git a/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll b/llvm/test/CodeGen/X86/2009-08-12-badswitch.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s | grep LJT
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-apple-darwin10"
 
@@ -30,6 +31,153 @@ declare void @f25() nounwind readnone
 declare void @f26() nounwind readnone
 
 define internal fastcc i32 @foo(i64 %bar) nounwind ssp {
+; CHECK-LABEL: foo:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    addq $-2, %rdi
+; CHECK-NEXT:    cmpq $25, %rdi
+; CHECK-NEXT:    ja LBB0_2
+; CHECK-NEXT:  ## %bb.1: ## %bb49
+; CHECK-NEXT:    leaq {{.*}}(%rip), %rax
+; CHECK-NEXT:    movslq (%rax,%rdi,4), %rcx
+; CHECK-NEXT:    addq %rax, %rcx
+; CHECK-NEXT:    jmpq *%rcx
+; CHECK-NEXT:  LBB0_3: ## %RRETURN_6
+; CHECK-NEXT:    callq _f2
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_2: ## %RETURN
+; CHECK-NEXT:    callq _f1
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_4: ## %RRETURN_7
+; CHECK-NEXT:    callq _f3
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_5: ## %RRETURN_14
+; CHECK-NEXT:    callq _f4
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_6: ## %RRETURN_15
+; CHECK-NEXT:    callq _f5
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_7: ## %RRETURN_16
+; CHECK-NEXT:    callq _f6
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_8: ## %RRETURN_17
+; CHECK-NEXT:    callq _f7
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_9: ## %RRETURN_18
+; CHECK-NEXT:    callq _f8
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_10: ## %RRETURN_19
+; CHECK-NEXT:    callq _f9
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_11: ## %RRETURN_20
+; CHECK-NEXT:    callq _f10
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_12: ## %RRETURN_21
+; CHECK-NEXT:    callq _f11
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_13: ## %RRETURN_22
+; CHECK-NEXT:    callq _f12
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_14: ## %RRETURN_24
+; CHECK-NEXT:    callq _f13
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_15: ## %RRETURN_26
+; CHECK-NEXT:    callq _f14
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_16: ## %RRETURN_27
+; CHECK-NEXT:    callq _f15
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_17: ## %RRETURN_28
+; CHECK-NEXT:    callq _f16
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_18: ## %RRETURN_29
+; CHECK-NEXT:    callq _f17
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_19: ## %RRETURN_30
+; CHECK-NEXT:    callq _f18
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_20: ## %RRETURN_31
+; CHECK-NEXT:    callq _f19
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_21: ## %RRETURN_38
+; CHECK-NEXT:    callq _f20
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_22: ## %RRETURN_40
+; CHECK-NEXT:    callq _f21
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_23: ## %RRETURN_42
+; CHECK-NEXT:    callq _f22
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_24: ## %RRETURN_44
+; CHECK-NEXT:    callq _f23
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_25: ## %RRETURN_48
+; CHECK-NEXT:    callq _f24
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_26: ## %RRETURN_52
+; CHECK-NEXT:    callq _f25
+; CHECK-NEXT:    jmp LBB0_28
+; CHECK-NEXT:  LBB0_27: ## %RRETURN_1
+; CHECK-NEXT:    callq _f26
+; CHECK-NEXT:  LBB0_28: ## %EXIT
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    popq %rcx
+; CHECK-NEXT:    retq
+; CHECK-NEXT:    .p2align 2, 0x90
+; CHECK-NEXT:    .data_region jt32
+; CHECK-NEXT:  .set L0_0_set_3, LBB0_3-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_4, LBB0_4-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_5, LBB0_5-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_6, LBB0_6-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_7, LBB0_7-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_8, LBB0_8-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_9, LBB0_9-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_10, LBB0_10-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_11, LBB0_11-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_12, LBB0_12-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_13, LBB0_13-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_14, LBB0_14-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_15, LBB0_15-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_16, LBB0_16-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_17, LBB0_17-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_18, LBB0_18-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_19, LBB0_19-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_20, LBB0_20-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_21, LBB0_21-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_22, LBB0_22-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_23, LBB0_23-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_24, LBB0_24-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_25, LBB0_25-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_26, LBB0_26-LJTI0_0
+; CHECK-NEXT:  .set L0_0_set_27, LBB0_27-LJTI0_0
+; CHECK-NEXT:  LJTI0_0:
+; CHECK-NEXT:    .long L0_0_set_3
+; CHECK-NEXT:    .long L0_0_set_3
+; CHECK-NEXT:    .long L0_0_set_4
+; CHECK-NEXT:    .long L0_0_set_5
+; CHECK-NEXT:    .long L0_0_set_6
+; CHECK-NEXT:    .long L0_0_set_7
+; CHECK-NEXT:    .long L0_0_set_8
+; CHECK-NEXT:    .long L0_0_set_9
+; CHECK-NEXT:    .long L0_0_set_10
+; CHECK-NEXT:    .long L0_0_set_11
+; CHECK-NEXT:    .long L0_0_set_12
+; CHECK-NEXT:    .long L0_0_set_13
+; CHECK-NEXT:    .long L0_0_set_14
+; CHECK-NEXT:    .long L0_0_set_15
+; CHECK-NEXT:    .long L0_0_set_16
+; CHECK-NEXT:    .long L0_0_set_17
+; CHECK-NEXT:    .long L0_0_set_18
+; CHECK-NEXT:    .long L0_0_set_19
+; CHECK-NEXT:    .long L0_0_set_20
+; CHECK-NEXT:    .long L0_0_set_21
+; CHECK-NEXT:    .long L0_0_set_22
+; CHECK-NEXT:    .long L0_0_set_23
+; CHECK-NEXT:    .long L0_0_set_24
+; CHECK-NEXT:    .long L0_0_set_25
+; CHECK-NEXT:    .long L0_0_set_26
+; CHECK-NEXT:    .long L0_0_set_27
+; CHECK-NEXT:    .end_data_region
 entry:
         br label %bb49
 

diff --git a/llvm/test/CodeGen/X86/20090313-signext.ll b/llvm/test/CodeGen/X86/20090313-signext.ll
@@ -1,11 +1,19 @@
-; RUN: llc < %s -mtriple=x86_64-- -relocation-model=pic > %t
-; RUN: grep "movswl	%ax, %edi" %t
-; RUN: grep "movw	(%rax), %ax" %t
-; XFAIL: *
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -relocation-model=pic | FileCheck %s
 
 @x = common global i16 0
 
 define signext i16 @f() nounwind {
+; CHECK-LABEL: f:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    callq h@PLT
+; CHECK-NEXT:    movswl %ax, %edi
+; CHECK-NEXT:    callq g@PLT
+; CHECK-NEXT:    movq x@{{.*}}(%rip), %rax
+; CHECK-NEXT:    movzwl (%rax), %eax
+; CHECK-NEXT:    popq %rcx
+; CHECK-NEXT:    retq
 entry:
 	%0 = tail call signext i16 @h() nounwind
 	%1 = sext i16 %0 to i32

diff --git a/llvm/test/CodeGen/X86/SwitchLowering.ll b/llvm/test/CodeGen/X86/SwitchLowering.ll
@@ -1,7 +1,43 @@
-; RUN: llc < %s -mtriple=i686-- | grep cmp | count 1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 ; PR964
 
 define i8* @FindChar(i8* %CurPtr) {
+; CHECK-LABEL: FindChar:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushl %edi
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    .cfi_def_cfa_offset 12
+; CHECK-NEXT:    .cfi_offset %esi, -12
+; CHECK-NEXT:    .cfi_offset %edi, -8
+; CHECK-NEXT:    xorl %edi, %edi
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB0_1: # %bb
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    movzbl (%esi,%edi), %eax
+; CHECK-NEXT:    incl %edi
+; CHECK-NEXT:    cmpb $120, %al
+; CHECK-NEXT:    je .LBB0_3
+; CHECK-NEXT:  # %bb.2: # %bb
+; CHECK-NEXT:    # in Loop: Header=BB0_1 Depth=1
+; CHECK-NEXT:    testb %al, %al
+; CHECK-NEXT:    jne .LBB0_1
+; CHECK-NEXT:  .LBB0_3: # %bb7
+; CHECK-NEXT:    movzbl %al, %eax
+; CHECK-NEXT:    pushl %eax
+; CHECK-NEXT:    .cfi_adjust_cfa_offset 4
+; CHECK-NEXT:    calll foo
+; CHECK-NEXT:    addl $4, %esp
+; CHECK-NEXT:    .cfi_adjust_cfa_offset -4
+; CHECK-NEXT:    addl %edi, %esi
+; CHECK-NEXT:    movl %esi, %eax
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    popl %edi
+; CHECK-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-NEXT:    retl
 entry:
         br label %bb
 

diff --git a/llvm/test/CodeGen/X86/addr-label-difference.ll b/llvm/test/CodeGen/X86/addr-label-difference.ll
@@ -1,5 +1,8 @@
-; RUN: llc %s -o - | grep "__TEXT,__const"
+; RUN: llc < %s | FileCheck %s
 ; PR5929
+
+; CHECK: .section        __TEXT,__const
+
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128-n8:16:32"
 target triple = "i386-apple-darwin10.0"
 

diff --git a/llvm/test/CodeGen/X86/aligned-comm.ll b/llvm/test/CodeGen/X86/aligned-comm.ll
@@ -1,6 +1,11 @@
-; RUN: llc < %s -mtriple=i686--
-; RUN: llc < %s -mtriple=i386-apple-darwin10 | grep "array,16512,7"
-; RUN: llc < %s -mtriple=i386-apple-darwin9 | grep "array,16512,7"
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefix=i686
+; RUN: llc < %s -mtriple=i386-apple-darwin10 | FileCheck %s --check-prefix=DARWIN
+; RUN: llc < %s -mtriple=i386-apple-darwin9 | FileCheck %s --check-prefix=DARWIN
+; RUN: llc < %s -mtriple=i386-apple-darwin8 | FileCheck %s --check-prefix=DARWIN8
+
+; i686: array,16512
+; DARWIN8: array,16512
+; DARWIN: array,16512,7
 
 ; Darwin 9+ should get alignment on common symbols.
 @array = common global [4128 x i32] zeroinitializer, align 128
diff --git a/llvm/test/CodeGen/X86/arg-cast.ll b/llvm/test/CodeGen/X86/arg-cast.ll
@@ -1,13 +1,17 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; This should compile to movl $2147483647, %eax + andl only.
-; RUN: llc < %s | grep andl
-; RUN: llc < %s | not grep movsd
-; RUN: llc < %s | grep esp | not grep add
+; RUN: llc < %s | FileCheck %s
 ; rdar://5736574
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i686-apple-darwin8"
 
 define i32 @foo(double %x) nounwind  {
+; CHECK-LABEL: foo:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    movl $2147483647, %eax ## imm = 0x7FFFFFFF
+; CHECK-NEXT:    andl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    retl
 entry:
 	%x15 = bitcast double %x to i64		; <i64> [#uses=1]
 	%tmp713 = lshr i64 %x15, 32		; <i64> [#uses=1]

diff --git a/llvm/test/CodeGen/X86/bitcast2.ll b/llvm/test/CodeGen/X86/bitcast2.ll
@@ -1,12 +1,20 @@
-; RUN: llc < %s -mtriple=x86_64-- -mattr=-avx | grep movq | count 2
-; RUN: llc < %s -mtriple=x86_64-- -mattr=-avx | not grep rsp
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mattr=-avx | FileCheck %s
 
 define i64 @test1(double %A) {
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %xmm0, %rax
+; CHECK-NEXT:    retq
    %B = bitcast double %A to i64
    ret i64 %B
 }
 
 define double @test2(i64 %A) {
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rdi, %xmm0
+; CHECK-NEXT:    retq
    %B = bitcast i64 %A to double
    ret double %B
 }

diff --git a/llvm/test/CodeGen/X86/break-anti-dependencies.ll b/llvm/test/CodeGen/X86/break-anti-dependencies.ll
@@ -1,14 +1,58 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; Without list-burr scheduling we may not see the difference in codegen here.
 ; Use a subtarget that has post-RA scheduling enabled because the anti-dependency
 ; breaker requires liveness information to be kept.
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=atom -enable-misched=false -post-RA-scheduler -pre-RA-sched=list-burr -break-anti-dependencies=none > %t
-; RUN:   grep "%xmm0" %t | count 14
-; RUN:   not grep "%xmm1" %t
-; RUN: llc < %s -mtriple=x86_64-- -mcpu=atom -post-RA-scheduler -break-anti-dependencies=critical > %t
-; RUN:   grep "%xmm0" %t | count 7
-; RUN:   grep "%xmm1" %t | count 7
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=atom -enable-misched=false -post-RA-scheduler -pre-RA-sched=list-burr -break-anti-dependencies=none | FileCheck %s --check-prefix=none
+; RUN: llc < %s -mtriple=x86_64-- -mcpu=atom -post-RA-scheduler -break-anti-dependencies=critical | FileCheck %s --check-prefix=critical
 
 define void @goo(double* %r, double* %p, double* %q) nounwind {
+; none-LABEL: goo:
+; none:       # %bb.0: # %entry
+; none-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; none-NEXT:    addsd {{.*}}(%rip), %xmm0
+; none-NEXT:    mulsd {{.*}}(%rip), %xmm0
+; none-NEXT:    addsd {{.*}}(%rip), %xmm0
+; none-NEXT:    mulsd {{.*}}(%rip), %xmm0
+; none-NEXT:    addsd {{.*}}(%rip), %xmm0
+; none-NEXT:    cvttsd2si %xmm0, %eax
+; none-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; none-NEXT:    addsd {{.*}}(%rip), %xmm0
+; none-NEXT:    mulsd {{.*}}(%rip), %xmm0
+; none-NEXT:    addsd {{.*}}(%rip), %xmm0
+; none-NEXT:    mulsd {{.*}}(%rip), %xmm0
+; none-NEXT:    addsd {{.*}}(%rip), %xmm0
+; none-NEXT:    cvttsd2si %xmm0, %ecx
+; none-NEXT:    cmpl %eax, %ecx
+; none-NEXT:    jge .LBB0_2
+; none-NEXT:  # %bb.1: # %bb
+; none-NEXT:    movabsq $4621425052621576602, %rax # imm = 0x402299999999999A
+; none-NEXT:    movq %rax, (%rdx)
+; none-NEXT:  .LBB0_2: # %return
+; none-NEXT:    retq
+;
+; critical-LABEL: goo:
+; critical:       # %bb.0: # %entry
+; critical-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; critical-NEXT:    movsd {{.*#+}} xmm1 = mem[0],zero
+; critical-NEXT:    addsd {{.*}}(%rip), %xmm0
+; critical-NEXT:    addsd {{.*}}(%rip), %xmm1
+; critical-NEXT:    mulsd {{.*}}(%rip), %xmm0
+; critical-NEXT:    mulsd {{.*}}(%rip), %xmm1
+; critical-NEXT:    addsd {{.*}}(%rip), %xmm0
+; critical-NEXT:    addsd {{.*}}(%rip), %xmm1
+; critical-NEXT:    mulsd {{.*}}(%rip), %xmm0
+; critical-NEXT:    mulsd {{.*}}(%rip), %xmm1
+; critical-NEXT:    addsd {{.*}}(%rip), %xmm0
+; critical-NEXT:    addsd {{.*}}(%rip), %xmm1
+; critical-NEXT:    cvttsd2si %xmm0, %eax
+; critical-NEXT:    cvttsd2si %xmm1, %ecx
+; critical-NEXT:    cmpl %ecx, %eax
+; critical-NEXT:    jge .LBB0_2
+; critical-NEXT:  # %bb.1: # %bb
+; critical-NEXT:    movabsq $4621425052621576602, %rax # imm = 0x402299999999999A
+; critical-NEXT:    movq %rax, (%rdx)
+; critical-NEXT:  .LBB0_2: # %return
+; critical-NEXT:    retq
 entry:
 	%0 = load double, double* %p, align 8
 	%1 = fadd double %0, 1.100000e+00

diff --git a/llvm/test/CodeGen/X86/byval6.ll b/llvm/test/CodeGen/X86/byval6.ll
@@ -1,11 +1,50 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mcpu=generic -mtriple=i686-- | grep add | not grep 16
+; RUN: llc < %s -mcpu=generic -mtriple=i686-- | FileCheck %s
 
 	%struct.W = type { x86_fp80, x86_fp80 }
 @B = global %struct.W { x86_fp80 0xK4001A000000000000000, x86_fp80 0xK4001C000000000000000 }, align 32
 @.cpx = internal constant %struct.W { x86_fp80 0xK4001E000000000000000, x86_fp80 0xK40028000000000000000 }
 
 define i32 @main() nounwind  {
+; CHECK-LABEL: main:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushl %ebx
+; CHECK-NEXT:    pushl %edi
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    movl .cpx+20, %eax
+; CHECK-NEXT:    movl .cpx+16, %ecx
+; CHECK-NEXT:    movl .cpx+12, %edx
+; CHECK-NEXT:    movl .cpx+8, %esi
+; CHECK-NEXT:    movl .cpx+4, %edi
+; CHECK-NEXT:    movl .cpx, %ebx
+; CHECK-NEXT:    pushl %eax
+; CHECK-NEXT:    pushl %ecx
+; CHECK-NEXT:    pushl %edx
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    pushl %edi
+; CHECK-NEXT:    pushl %ebx
+; CHECK-NEXT:    pushl $3
+; CHECK-NEXT:    calll bar
+; CHECK-NEXT:    addl $28, %esp
+; CHECK-NEXT:    movl B+20, %eax
+; CHECK-NEXT:    movl B+16, %ecx
+; CHECK-NEXT:    movl B+12, %edx
+; CHECK-NEXT:    movl B+8, %esi
+; CHECK-NEXT:    movl B+4, %edi
+; CHECK-NEXT:    movl B, %ebx
+; CHECK-NEXT:    pushl %eax
+; CHECK-NEXT:    pushl %ecx
+; CHECK-NEXT:    pushl %edx
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    pushl %edi
+; CHECK-NEXT:    pushl %ebx
+; CHECK-NEXT:    pushl $3
+; CHECK-NEXT:    calll baz
+; CHECK-NEXT:    addl $28, %esp
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    popl %edi
+; CHECK-NEXT:    popl %ebx
+; CHECK-NEXT:    retl
 entry:
 	tail call void (i32, ...) @bar( i32 3, %struct.W* byval  @.cpx ) nounwind
 	tail call void (i32, ...) @baz( i32 3, %struct.W* byval  @B ) nounwind

diff --git a/llvm/test/CodeGen/X86/coalesce-esp.ll b/llvm/test/CodeGen/X86/coalesce-esp.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s | grep "movl	%esp, %ebp"
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
 ; PR4572
 
 ; Don't coalesce with %esp if it would end up putting %esp in
@@ -11,6 +12,33 @@ target triple = "i386-pc-mingw32"
 	%"struct.std::valarray<unsigned int>" = type { i32, i32* }
 
 define void @_ZSt17__gslice_to_indexjRKSt8valarrayIjES2_RS0_(i32 %__o, %"struct.std::valarray<unsigned int>"* nocapture %__l, %"struct.std::valarray<unsigned int>"* nocapture %__s, %"struct.std::valarray<unsigned int>"* nocapture %__i) nounwind {
+; CHECK-LABEL: _ZSt17__gslice_to_indexjRKSt8valarrayIjES2_RS0_:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushl %ebp
+; CHECK-NEXT:    movl %esp, %ebp
+; CHECK-NEXT:    movl %esp, %eax
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    testb %cl, %cl
+; CHECK-NEXT:    je .LBB0_1
+; CHECK-NEXT:  # %bb.5: # %return
+; CHECK-NEXT:    movl %ebp, %esp
+; CHECK-NEXT:    popl %ebp
+; CHECK-NEXT:    retl
+; CHECK-NEXT:  .LBB0_1: # %bb4.preheader
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:    jmp .LBB0_2
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB0_4: # %bb7.backedge
+; CHECK-NEXT:    # in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT:    addl $-4, %edx
+; CHECK-NEXT:  .LBB0_2: # %bb4
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    testb %cl, %cl
+; CHECK-NEXT:    jne .LBB0_4
+; CHECK-NEXT:  # %bb.3: # %bb5
+; CHECK-NEXT:    # in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT:    movl $0, (%eax,%edx)
+; CHECK-NEXT:    jmp .LBB0_4
 entry:
 	%0 = alloca i32, i32 undef, align 4		; <i32*> [#uses=1]
 	br i1 undef, label %return, label %bb4

diff --git a/llvm/test/CodeGen/X86/coalescer-commute1.ll b/llvm/test/CodeGen/X86/coalescer-commute1.ll
@@ -1,10 +1,30 @@
-; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx -mattr=+sse2 | not grep movaps
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-apple-darwin -mcpu=corei7-avx -mattr=+sse2 | FileCheck %s
 ; PR1877
 
 @NNTOT = weak global i32 0		; <i32*> [#uses=1]
 @G = weak global float 0.000000e+00		; <float*> [#uses=1]
 
 define void @runcont(i32* %source) nounwind  {
+; CHECK-LABEL: runcont:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl L_NNTOT$non_lazy_ptr, %ecx
+; CHECK-NEXT:    movl (%ecx), %ecx
+; CHECK-NEXT:    vxorps %xmm0, %xmm0, %xmm0
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  LBB0_1: ## %bb
+; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    vcvtsi2ssl (%eax,%edx,4), %xmm2, %xmm1
+; CHECK-NEXT:    vaddss %xmm0, %xmm1, %xmm0
+; CHECK-NEXT:    incl %edx
+; CHECK-NEXT:    cmpl %edx, %ecx
+; CHECK-NEXT:    jne LBB0_1
+; CHECK-NEXT:  ## %bb.2: ## %bb13
+; CHECK-NEXT:    movl L_G$non_lazy_ptr, %eax
+; CHECK-NEXT:    vmovss %xmm0, (%eax)
+; CHECK-NEXT:    retl
 entry:
 	%tmp10 = load i32, i32* @NNTOT, align 4		; <i32> [#uses=1]
 	br label %bb

diff --git a/llvm/test/CodeGen/X86/coalescer-commute3.ll b/llvm/test/CodeGen/X86/coalescer-commute3.ll
@@ -1,8 +1,35 @@
-; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -no-x86-call-frame-opt | grep mov | count 6
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 -no-x86-call-frame-opt | FileCheck %s
 
 	%struct.quad_struct = type { i32, i32, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct*, %struct.quad_struct* }
 
 define  i32 @perimeter(%struct.quad_struct* %tree, i32 %size) nounwind  {
+; CHECK-LABEL: perimeter:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    subl $8, %esp
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    testl %eax, %eax
+; CHECK-NEXT:    je LBB0_3
+; CHECK-NEXT:  ## %bb.1: ## %entry
+; CHECK-NEXT:    cmpl $2, %eax
+; CHECK-NEXT:    jne LBB0_3
+; CHECK-NEXT:  ## %bb.2: ## %bb
+; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl $0, (%esp)
+; CHECK-NEXT:    calll _perimeter
+; CHECK-NEXT:    movl %eax, %esi
+; CHECK-NEXT:    movl $0, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl $0, (%esp)
+; CHECK-NEXT:    calll _perimeter
+; CHECK-NEXT:    addl %esi, %eax
+; CHECK-NEXT:    jmp LBB0_4
+; CHECK-NEXT:  LBB0_3: ## %UnifiedReturnBlock
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:  LBB0_4: ## %UnifiedReturnBlock
+; CHECK-NEXT:    addl $8, %esp
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    retl
 entry:
 	switch i32 %size, label %UnifiedReturnBlock [
 		 i32 2, label %bb

diff --git a/llvm/test/CodeGen/X86/coalescer-commute4.ll b/llvm/test/CodeGen/X86/coalescer-commute4.ll
@@ -1,7 +1,39 @@
-; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s
 ; PR1501
 
 define float @foo(i32* %x, float* %y, i32 %c) nounwind  {
+; CHECK-LABEL: foo:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    pushl %eax
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    testl %eax, %eax
+; CHECK-NEXT:    je LBB0_1
+; CHECK-NEXT:  ## %bb.2: ## %bb.preheader
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; CHECK-NEXT:    xorps %xmm0, %xmm0
+; CHECK-NEXT:    xorl %esi, %esi
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  LBB0_3: ## %bb
+; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    xorps %xmm1, %xmm1
+; CHECK-NEXT:    cvtsi2ssl (%edx,%esi,4), %xmm1
+; CHECK-NEXT:    mulss (%ecx,%esi,4), %xmm1
+; CHECK-NEXT:    addss %xmm1, %xmm0
+; CHECK-NEXT:    incl %esi
+; CHECK-NEXT:    cmpl %eax, %esi
+; CHECK-NEXT:    jb LBB0_3
+; CHECK-NEXT:    jmp LBB0_4
+; CHECK-NEXT:  LBB0_1:
+; CHECK-NEXT:    xorps %xmm0, %xmm0
+; CHECK-NEXT:  LBB0_4: ## %bb23
+; CHECK-NEXT:    movss %xmm0, (%esp)
+; CHECK-NEXT:    flds (%esp)
+; CHECK-NEXT:    addl $4, %esp
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    retl
 entry:
 	%tmp2132 = icmp eq i32 %c, 0		; <i1> [#uses=2]
 	br i1 %tmp2132, label %bb23, label %bb.preheader

diff --git a/llvm/test/CodeGen/X86/coalescer-commute5.ll b/llvm/test/CodeGen/X86/coalescer-commute5.ll
@@ -1,6 +1,11 @@
-; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | not grep movaps
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-apple-darwin -mattr=+sse2 | FileCheck %s
 
 define i32 @t() {
+; CHECK-LABEL: t:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    retl
 entry:
 	br i1 true, label %bb1664, label %bb1656
 bb1656:		; preds = %entry
@@ -18,4 +23,4 @@ bb5310:		; preds = %bb4743, %bb1664
 	ret i32 0
 }
 
-declare <16 x i8> @llvm.x86.sse2.pcmpeq.b(<16 x i8>, <16 x i8>) nounwind readnone 
+declare <16 x i8> @llvm.x86.sse2.pcmpeq.b(<16 x i8>, <16 x i8>) nounwind readnone
diff --git a/llvm/test/CodeGen/X86/coalescer-remat.ll b/llvm/test/CodeGen/X86/coalescer-remat.ll
@@ -1,9 +1,23 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep xor | count 3
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
 
 @val = internal global i64 0
 @"\01LC" = internal constant [7 x i8] c"0x%lx\0A\00"
 
 define i32 @main() nounwind {
+; CHECK-LABEL: main:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    movl $1, %ecx
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    lock cmpxchgq %rcx, {{.*}}(%rip)
+; CHECK-NEXT:    leaq {{.*}}(%rip), %rdi
+; CHECK-NEXT:    movq %rax, %rsi
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    callq _printf
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    popq %rcx
+; CHECK-NEXT:    retq
 entry:
   %t0 = cmpxchg i64* @val, i64 0, i64 1 monotonic monotonic
   %0 = extractvalue { i64, i1 } %t0, 0

diff --git a/llvm/test/CodeGen/X86/compare-add.ll b/llvm/test/CodeGen/X86/compare-add.ll
@@ -1,6 +1,12 @@
-; RUN: llc < %s -mtriple=i686-- | not grep add
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 
 define i1 @X(i32 %X) {
+; CHECK-LABEL: X:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    cmpl $12331, {{[0-9]+}}(%esp) # imm = 0x302B
+; CHECK-NEXT:    setne %al
+; CHECK-NEXT:    retl
         %Y = add i32 %X, 14             ; <i32> [#uses=1]
         %Z = icmp ne i32 %Y, 12345              ; <i1> [#uses=1]
         ret i1 %Z

diff --git a/llvm/test/CodeGen/X86/compare_folding.ll b/llvm/test/CodeGen/X86/compare_folding.ll
@@ -1,10 +1,14 @@
-; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | \
-; RUN:   grep movsd | count 1
-; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | \
-; RUN:   grep ucomisd
-declare i1 @llvm.isunordered.f64(double, double)
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | FileCheck %s
 
+declare i1 @llvm.isunordered.f64(double, double)
 define i1 @test1(double %X, double %Y) {
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT:    ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-NEXT:    setp %al
+; CHECK-NEXT:    retl
         %COM = fcmp uno double %X, %Y           ; <i1> [#uses=1]
         ret i1 %COM
 }

diff --git a/llvm/test/CodeGen/X86/cstring.ll b/llvm/test/CodeGen/X86/cstring.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin | not grep comm
+; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
 ; rdar://6479858
 
+; CHECK-NOT: comm
 @str1 = internal constant [1 x i8] zeroinitializer
diff --git a/llvm/test/CodeGen/X86/empty-struct-return-type.ll b/llvm/test/CodeGen/X86/empty-struct-return-type.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s | grep call
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
 ; PR4688
 
 ; Return types can be empty structs, which can be awkward.
@@ -7,6 +8,14 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-unknown-linux-gnu"
 
 define void @_ZN15QtSharedPointer22internalSafetyCheckAddEPVKv(i8* %ptr) {
+; CHECK-LABEL: _ZN15QtSharedPointer22internalSafetyCheckAddEPVKv:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    callq _ZNK5QHashIPv15QHashDummyValueE5valueERKS0_
+; CHECK-NEXT:    popq %rax
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    retq
 entry:
 	%0 = call { } @_ZNK5QHashIPv15QHashDummyValueE5valueERKS0_(i8** undef)		; <{ }> [#uses=0]
         ret void

diff --git a/llvm/test/CodeGen/X86/extend.ll b/llvm/test/CodeGen/X86/extend.ll
@@ -1,16 +1,26 @@
-; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | grep movzx | count 1
-; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | grep movsx | count 1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | FileCheck %s
 
 @G1 = internal global i8 0              ; <i8*> [#uses=1]
 @G2 = internal global i8 0              ; <i8*> [#uses=1]
 
 define i16 @test1() {
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movzx eax, byte ptr [G1]
+; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT:    ret
         %tmp.0 = load i8, i8* @G1           ; <i8> [#uses=1]
         %tmp.3 = zext i8 %tmp.0 to i16          ; <i16> [#uses=1]
         ret i16 %tmp.3
 }
 
 define i16 @test2() {
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movsx eax, byte ptr [G2]
+; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT:    ret
         %tmp.0 = load i8, i8* @G2           ; <i8> [#uses=1]
         %tmp.3 = sext i8 %tmp.0 to i16          ; <i16> [#uses=1]
         ret i16 %tmp.3

diff --git a/llvm/test/CodeGen/X86/extmul128.ll b/llvm/test/CodeGen/X86/extmul128.ll
@@ -1,12 +1,23 @@
-; RUN: llc < %s -mtriple=x86_64-- | grep mul | count 2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 
 define i128 @i64_sext_i128(i64 %a, i64 %b) {
+; CHECK-LABEL: i64_sext_i128:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    imulq %rsi
+; CHECK-NEXT:    retq
   %aa = sext i64 %a to i128
   %bb = sext i64 %b to i128
   %cc = mul i128 %aa, %bb
   ret i128 %cc
 }
 define i128 @i64_zext_i128(i64 %a, i64 %b) {
+; CHECK-LABEL: i64_zext_i128:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    mulq %rsi
+; CHECK-NEXT:    retq
   %aa = zext i64 %a to i128
   %bb = zext i64 %b to i128
   %cc = mul i128 %aa, %bb

diff --git a/llvm/test/CodeGen/X86/extmul64.ll b/llvm/test/CodeGen/X86/extmul64.ll
@@ -1,12 +1,23 @@
-; RUN: llc < %s -mtriple=i686-- | grep mul | count 2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 
 define i64 @i32_sext_i64(i32 %a, i32 %b) {
+; CHECK-LABEL: i32_sext_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    imull {{[0-9]+}}(%esp)
+; CHECK-NEXT:    retl
   %aa = sext i32 %a to i64
   %bb = sext i32 %b to i64
   %cc = mul i64 %aa, %bb
   ret i64 %cc
 }
 define i64 @i32_zext_i64(i32 %a, i32 %b) {
+; CHECK-LABEL: i32_zext_i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    mull {{[0-9]+}}(%esp)
+; CHECK-NEXT:    retl
   %aa = zext i32 %a to i64
   %bb = zext i32 %b to i64
   %cc = mul i64 %aa, %bb

diff --git a/llvm/test/CodeGen/X86/extractps.ll b/llvm/test/CodeGen/X86/extractps.ll
@@ -1,20 +1,31 @@
-; RUN: llc < %s -mtriple=i686-- -mcpu=penryn > %t
-; RUN: not grep movd %t
-; RUN: grep "movss	%xmm" %t | count 1
-; RUN: grep "extractps	\$1, %xmm0, " %t | count 1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- -mcpu=penryn | FileCheck %s
 ; PR2647
 
 @0 = external global float, align 16         ; <float*>:0 [#uses=2]
 
-define internal void @""() nounwind {
+define internal void @a() nounwind {
+; CHECK-LABEL: a:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:    rsqrtss %xmm0, %xmm0
+; CHECK-NEXT:    movss %xmm0, __unnamed_1
+; CHECK-NEXT:    retl
         load float, float* @0, align 16                ; <float>:1 [#uses=1]
         insertelement <4 x float> undef, float %1, i32 0                ; <<4 x float>>:2 [#uses=1]
         call <4 x float> @llvm.x86.sse.rsqrt.ss( <4 x float> %2 )              ; <<4 x float>>:3 [#uses=1]
         extractelement <4 x float> %3, i32 0            ; <float>:4 [#uses=1]
         store float %4, float* @0, align 16
         ret void
 }
-define internal void @""() nounwind {
+define internal void @b() nounwind {
+; CHECK-LABEL: b:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:    movsldup {{.*#+}} xmm0 = xmm0[0,0,2,2]
+; CHECK-NEXT:    rsqrtss %xmm0, %xmm0
+; CHECK-NEXT:    extractps $1, %xmm0, __unnamed_1
+; CHECK-NEXT:    retl
         load float, float* @0, align 16                ; <float>:1 [#uses=1]
         insertelement <4 x float> undef, float %1, i32 1                ; <<4 x float>>:2 [#uses=1]
         call <4 x float> @llvm.x86.sse.rsqrt.ss( <4 x float> %2 )              ; <<4 x float>>:3 [#uses=1]

diff --git a/llvm/test/CodeGen/X86/field-extract-use-trunc.ll b/llvm/test/CodeGen/X86/field-extract-use-trunc.ll
@@ -1,38 +1,107 @@
-; RUN: llc < %s -mtriple=i686-- | grep sar | count 1
-; RUN: llc < %s -mtriple=x86_64-- | not grep sar
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefix=i686
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefix=x86_64
 
 define i32 @test(i32 %f12) nounwind {
-	%tmp7.25 = lshr i32 %f12, 16		
+; i686-LABEL: test:
+; i686:       # %bb.0:
+; i686-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
+; i686-NEXT:    retl
+;
+; x86_64-LABEL: test:
+; x86_64:       # %bb.0:
+; x86_64-NEXT:    shrl $16, %edi
+; x86_64-NEXT:    movsbl %dil, %eax
+; x86_64-NEXT:    retq
+	%tmp7.25 = lshr i32 %f12, 16
 	%tmp7.26 = trunc i32 %tmp7.25 to i8
 	%tmp78.2 = sext i8 %tmp7.26 to i32
 	ret i32 %tmp78.2
 }
 
 define i32 @test2(i32 %f12) nounwind {
+; i686-LABEL: test2:
+; i686:       # %bb.0:
+; i686-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
+; i686-NEXT:    retl
+;
+; x86_64-LABEL: test2:
+; x86_64:       # %bb.0:
+; x86_64-NEXT:    shrl $16, %edi
+; x86_64-NEXT:    movsbl %dil, %eax
+; x86_64-NEXT:    retq
 	%f11 = shl i32 %f12, 8
 	%tmp7.25 = ashr i32 %f11, 24
 	ret i32 %tmp7.25
 }
 
 define i32 @test3(i32 %f12) nounwind {
+; i686-LABEL: test3:
+; i686:       # %bb.0:
+; i686-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; i686-NEXT:    shrl $11, %eax
+; i686-NEXT:    movsbl %al, %eax
+; i686-NEXT:    retl
+;
+; x86_64-LABEL: test3:
+; x86_64:       # %bb.0:
+; x86_64-NEXT:    shrl $11, %edi
+; x86_64-NEXT:    movsbl %dil, %eax
+; x86_64-NEXT:    retq
 	%f11 = shl i32 %f12, 13
 	%tmp7.25 = ashr i32 %f11, 24
 	ret i32 %tmp7.25
 }
 
 define i64 @test4(i64 %f12) nounwind {
+; i686-LABEL: test4:
+; i686:       # %bb.0:
+; i686-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; i686-NEXT:    movl %eax, %edx
+; i686-NEXT:    sarl $31, %edx
+; i686-NEXT:    retl
+;
+; x86_64-LABEL: test4:
+; x86_64:       # %bb.0:
+; x86_64-NEXT:    movslq %edi, %rax
+; x86_64-NEXT:    retq
 	%f11 = shl i64 %f12, 32
 	%tmp7.25 = ashr i64 %f11, 32
 	ret i64 %tmp7.25
 }
 
 define i16 @test5(i16 %f12) nounwind {
+; i686-LABEL: test5:
+; i686:       # %bb.0:
+; i686-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; i686-NEXT:    shrl $6, %eax
+; i686-NEXT:    movsbl %al, %eax
+; i686-NEXT:    # kill: def $ax killed $ax killed $eax
+; i686-NEXT:    retl
+;
+; x86_64-LABEL: test5:
+; x86_64:       # %bb.0:
+; x86_64-NEXT:    shrl $6, %edi
+; x86_64-NEXT:    movsbl %dil, %eax
+; x86_64-NEXT:    # kill: def $ax killed $ax killed $eax
+; x86_64-NEXT:    retq
 	%f11 = shl i16 %f12, 2
 	%tmp7.25 = ashr i16 %f11, 8
 	ret i16 %tmp7.25
 }
 
 define i16 @test6(i16 %f12) nounwind {
+; i686-LABEL: test6:
+; i686:       # %bb.0:
+; i686-NEXT:    movsbl {{[0-9]+}}(%esp), %eax
+; i686-NEXT:    # kill: def $ax killed $ax killed $eax
+; i686-NEXT:    retl
+;
+; x86_64-LABEL: test6:
+; x86_64:       # %bb.0:
+; x86_64-NEXT:    movsbl %dil, %eax
+; x86_64-NEXT:    # kill: def $ax killed $ax killed $eax
+; x86_64-NEXT:    retq
 	%f11 = shl i16 %f12, 8
 	%tmp7.25 = ashr i16 %f11, 8
 	ret i16 %tmp7.25

diff --git a/llvm/test/CodeGen/X86/fildll.ll b/llvm/test/CodeGen/X86/fildll.ll
@@ -1,11 +1,50 @@
-; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=att -mattr=-sse2 | grep fildll | count 2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=att -mattr=-sse2 | FileCheck %s
 
 define fastcc double @sint64_to_fp(i64 %X) {
+; CHECK-LABEL: sint64_to_fp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushl %ebp
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    .cfi_offset %ebp, -8
+; CHECK-NEXT:    movl %esp, %ebp
+; CHECK-NEXT:    .cfi_def_cfa_register %ebp
+; CHECK-NEXT:    andl $-8, %esp
+; CHECK-NEXT:    subl $8, %esp
+; CHECK-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl %ecx, (%esp)
+; CHECK-NEXT:    fildll (%esp)
+; CHECK-NEXT:    movl %ebp, %esp
+; CHECK-NEXT:    popl %ebp
+; CHECK-NEXT:    .cfi_def_cfa %esp, 4
+; CHECK-NEXT:    retl
         %R = sitofp i64 %X to double            ; <double> [#uses=1]
         ret double %R
 }
 
 define fastcc double @uint64_to_fp(i64 %X) {
+; CHECK-LABEL: uint64_to_fp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    pushl %ebp
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    .cfi_offset %ebp, -8
+; CHECK-NEXT:    movl %esp, %ebp
+; CHECK-NEXT:    .cfi_def_cfa_register %ebp
+; CHECK-NEXT:    andl $-8, %esp
+; CHECK-NEXT:    subl $16, %esp
+; CHECK-NEXT:    movl %edx, {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl %ecx, (%esp)
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    testl %edx, %edx
+; CHECK-NEXT:    setns %al
+; CHECK-NEXT:    fildll (%esp)
+; CHECK-NEXT:    fadds {{\.LCPI.*}}(,%eax,4)
+; CHECK-NEXT:    fstpl {{[0-9]+}}(%esp)
+; CHECK-NEXT:    fldl {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movl %ebp, %esp
+; CHECK-NEXT:    popl %ebp
+; CHECK-NEXT:    .cfi_def_cfa %esp, 4
+; CHECK-NEXT:    retl
         %R = uitofp i64 %X to double            ; <double> [#uses=1]
         ret double %R
 }

diff --git a/llvm/test/CodeGen/X86/fold-call-2.ll b/llvm/test/CodeGen/X86/fold-call-2.ll
@@ -1,8 +1,17 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin | grep mov | count 1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-apple-darwin | FileCheck %s
 
 @f = external global void ()*		; <void ()**> [#uses=1]
 
 define i32 @main() nounwind {
+; CHECK-LABEL: main:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    subl $12, %esp
+; CHECK-NEXT:    movl L_f$non_lazy_ptr, %eax
+; CHECK-NEXT:    calll *(%eax)
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    addl $12, %esp
+; CHECK-NEXT:    retl
 entry:
 	load void ()*, void ()** @f, align 8		; <void ()*>:0 [#uses=1]
 	tail call void %0( ) nounwind

diff --git a/llvm/test/CodeGen/X86/fold-call-3.ll b/llvm/test/CodeGen/X86/fold-call-3.ll
@@ -1,7 +1,8 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | grep call | grep 560
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
 ; rdar://6522427
 ; This command line used to crash due to dangling nodes left after PreprocessISelDAG
-; RUN: llc < %s -mtriple=x86_64-apple-darwin -pre-RA-sched=linearize
+; RUN: llc < %s -mtriple=x86_64-apple-darwin -pre-RA-sched=linearize | FileCheck %s --check-prefix=pre-RA
 
 	%"struct.clang::Action" = type { %"struct.clang::ActionBase" }
 	%"struct.clang::ActionBase" = type { i32 (...)** }
@@ -10,6 +11,63 @@
 @llvm.used = appending global [1 x i8*] [ i8* bitcast (void (i8*, %"struct.clang::Action"*)* @_Z25RawPointerPerformanceTestPvRN5clang6ActionE to i8*) ], section "llvm.metadata"		; <[1 x i8*]*> [#uses=0]
 
 define void @_Z25RawPointerPerformanceTestPvRN5clang6ActionE(i8* %Val, %"struct.clang::Action"* %Actions) nounwind {
+; CHECK-LABEL: _Z25RawPointerPerformanceTestPvRN5clang6ActionE:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    pushq %rbp
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    subq $24, %rsp
+; CHECK-NEXT:    cmpl $0, {{.*}}(%rip)
+; CHECK-NEXT:    je LBB0_3
+; CHECK-NEXT:  ## %bb.1: ## %bb.nph
+; CHECK-NEXT:    movq %rsi, %rbx
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    xorl %ebp, %ebp
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  LBB0_2: ## %bb
+; CHECK-NEXT:    ## =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    movq (%rbx), %rcx
+; CHECK-NEXT:    movq %rbx, %rdi
+; CHECK-NEXT:    movq %rax, %rsi
+; CHECK-NEXT:    callq *560(%rcx)
+; CHECK-NEXT:    movq %rax, {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    movq %rdx, {{[0-9]+}}(%rsp)
+; CHECK-NEXT:    incl %ebp
+; CHECK-NEXT:    cmpl {{.*}}(%rip), %ebp
+; CHECK-NEXT:    jb LBB0_2
+; CHECK-NEXT:  LBB0_3: ## %return
+; CHECK-NEXT:    addq $24, %rsp
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    popq %rbp
+; CHECK-NEXT:    retq
+;
+; pre-RA-LABEL: _Z25RawPointerPerformanceTestPvRN5clang6ActionE:
+; pre-RA:       ## %bb.0: ## %entry
+; pre-RA-NEXT:    pushq %rbp
+; pre-RA-NEXT:    pushq %rbx
+; pre-RA-NEXT:    subq $24, %rsp
+; pre-RA-NEXT:    cmpl $0, {{.*}}(%rip)
+; pre-RA-NEXT:    je LBB0_3
+; pre-RA-NEXT:  ## %bb.1: ## %bb.nph
+; pre-RA-NEXT:    movq %rsi, %rbx
+; pre-RA-NEXT:    movq %rdi, %rax
+; pre-RA-NEXT:    xorl %ebp, %ebp
+; pre-RA-NEXT:    .p2align 4, 0x90
+; pre-RA-NEXT:  LBB0_2: ## %bb
+; pre-RA-NEXT:    ## =>This Inner Loop Header: Depth=1
+; pre-RA-NEXT:    movq (%rbx), %rcx
+; pre-RA-NEXT:    movq %rbx, %rdi
+; pre-RA-NEXT:    movq %rax, %rsi
+; pre-RA-NEXT:    callq *560(%rcx)
+; pre-RA-NEXT:    incl %ebp
+; pre-RA-NEXT:    movq %rax, {{[0-9]+}}(%rsp)
+; pre-RA-NEXT:    movq %rdx, {{[0-9]+}}(%rsp)
+; pre-RA-NEXT:    cmpl {{.*}}(%rip), %ebp
+; pre-RA-NEXT:    jb LBB0_2
+; pre-RA-NEXT:  LBB0_3: ## %return
+; pre-RA-NEXT:    addq $24, %rsp
+; pre-RA-NEXT:    popq %rbx
+; pre-RA-NEXT:    popq %rbp
+; pre-RA-NEXT:    retq
 entry:
 	%0 = alloca %"struct.clang::ActionBase::ActionResult<0u>", align 8		; <%"struct.clang::ActionBase::ActionResult<0u>"*> [#uses=3]
 	%1 = load i32, i32* @NumTrials, align 4		; <i32> [#uses=1]

diff --git a/llvm/test/CodeGen/X86/fold-sext-trunc.ll b/llvm/test/CodeGen/X86/fold-sext-trunc.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=x86_64-- | grep movslq | count 1
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 ; RUN: llc < %s -O0 -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -stop-after livedebugvalues -o - | FileCheck %s -check-prefix=MIR
 ; PR4050
 
@@ -9,6 +9,7 @@
 
 declare void @func_28(i64, i64)
 
+; CHECK: movslq  g_10+4(%rip), %rdi
 define void @int322(i32 %foo) !dbg !5 {
 entry:
   %val = load i64, i64* getelementptr (%0, %0* bitcast (%struct.S1* @g_10 to %0*), i32 0, i32 0), !dbg !16

diff --git a/llvm/test/CodeGen/X86/fp-stack-2results.ll b/llvm/test/CodeGen/X86/fp-stack-2results.ll
@@ -1,11 +1,18 @@
-; RUN: llc < %s -mtriple=i686-- | grep fldz
-; RUN: llc < %s -mtriple=x86_64-- | grep fld1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefixes=ALL,i686
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s -check-prefixes=ALL,x86_64
+
 
 %0 = type { x86_fp80, x86_fp80 }
 
 ; This is basically this code on x86-64:
 ; _Complex long double test() { return 1.0; }
 define %0 @test() {
+; ALL-LABEL: test:
+; ALL:       # %bb.0:
+; ALL-NEXT:    fldz
+; ALL-NEXT:    fld1
+; ALL-NEXT:    ret{{[l|q]}}
   %A = fpext double 1.0 to x86_fp80
   %B = fpext double 0.0 to x86_fp80
   %mrv = insertvalue %0 undef, x86_fp80 %A, 0
@@ -19,6 +26,11 @@ define %0 @test() {
 ;	fld	%st(0)
 ;	ret
 define %0 @test2() {
+; ALL-LABEL: test2:
+; ALL:       # %bb.0:
+; ALL-NEXT:    fld1
+; ALL-NEXT:    fld %st(0)
+; ALL-NEXT:    ret{{[l|q]}}
   %A = fpext double 1.0 to x86_fp80
   %mrv = insertvalue %0 undef, x86_fp80 %A, 0
   %mrv1 = insertvalue %0 %mrv, x86_fp80 %A, 1
@@ -27,6 +39,47 @@ define %0 @test2() {
 
 ; Uses both values.
 define void @call1(x86_fp80 *%P1, x86_fp80 *%P2) {
+; i686-LABEL: call1:
+; i686:       # %bb.0:
+; i686-NEXT:    pushl %edi
+; i686-NEXT:    .cfi_def_cfa_offset 8
+; i686-NEXT:    pushl %esi
+; i686-NEXT:    .cfi_def_cfa_offset 12
+; i686-NEXT:    .cfi_offset %esi, -12
+; i686-NEXT:    .cfi_offset %edi, -8
+; i686-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; i686-NEXT:    movl {{[0-9]+}}(%esp), %edi
+; i686-NEXT:    calll test
+; i686-NEXT:    fstpt (%edi)
+; i686-NEXT:    fstpt (%esi)
+; i686-NEXT:    popl %esi
+; i686-NEXT:    .cfi_def_cfa_offset 8
+; i686-NEXT:    popl %edi
+; i686-NEXT:    .cfi_def_cfa_offset 4
+; i686-NEXT:    retl
+;
+; x86_64-LABEL: call1:
+; x86_64:       # %bb.0:
+; x86_64-NEXT:    pushq %r14
+; x86_64-NEXT:    .cfi_def_cfa_offset 16
+; x86_64-NEXT:    pushq %rbx
+; x86_64-NEXT:    .cfi_def_cfa_offset 24
+; x86_64-NEXT:    pushq %rax
+; x86_64-NEXT:    .cfi_def_cfa_offset 32
+; x86_64-NEXT:    .cfi_offset %rbx, -24
+; x86_64-NEXT:    .cfi_offset %r14, -16
+; x86_64-NEXT:    movq %rsi, %r14
+; x86_64-NEXT:    movq %rdi, %rbx
+; x86_64-NEXT:    callq test
+; x86_64-NEXT:    fstpt (%rbx)
+; x86_64-NEXT:    fstpt (%r14)
+; x86_64-NEXT:    addq $8, %rsp
+; x86_64-NEXT:    .cfi_def_cfa_offset 24
+; x86_64-NEXT:    popq %rbx
+; x86_64-NEXT:    .cfi_def_cfa_offset 16
+; x86_64-NEXT:    popq %r14
+; x86_64-NEXT:    .cfi_def_cfa_offset 8
+; x86_64-NEXT:    retq
   %a = call %0 @test()
   %b = extractvalue %0 %a, 0
   store x86_fp80 %b, x86_fp80* %P1
@@ -38,6 +91,49 @@ define void @call1(x86_fp80 *%P1, x86_fp80 *%P2) {
 
 ; Uses both values, requires fxch
 define void @call2(x86_fp80 *%P1, x86_fp80 *%P2) {
+; i686-LABEL: call2:
+; i686:       # %bb.0:
+; i686-NEXT:    pushl %edi
+; i686-NEXT:    .cfi_def_cfa_offset 8
+; i686-NEXT:    pushl %esi
+; i686-NEXT:    .cfi_def_cfa_offset 12
+; i686-NEXT:    .cfi_offset %esi, -12
+; i686-NEXT:    .cfi_offset %edi, -8
+; i686-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; i686-NEXT:    movl {{[0-9]+}}(%esp), %edi
+; i686-NEXT:    calll test
+; i686-NEXT:    fxch %st(1)
+; i686-NEXT:    fstpt (%edi)
+; i686-NEXT:    fstpt (%esi)
+; i686-NEXT:    popl %esi
+; i686-NEXT:    .cfi_def_cfa_offset 8
+; i686-NEXT:    popl %edi
+; i686-NEXT:    .cfi_def_cfa_offset 4
+; i686-NEXT:    retl
+;
+; x86_64-LABEL: call2:
+; x86_64:       # %bb.0:
+; x86_64-NEXT:    pushq %r14
+; x86_64-NEXT:    .cfi_def_cfa_offset 16
+; x86_64-NEXT:    pushq %rbx
+; x86_64-NEXT:    .cfi_def_cfa_offset 24
+; x86_64-NEXT:    pushq %rax
+; x86_64-NEXT:    .cfi_def_cfa_offset 32
+; x86_64-NEXT:    .cfi_offset %rbx, -24
+; x86_64-NEXT:    .cfi_offset %r14, -16
+; x86_64-NEXT:    movq %rsi, %r14
+; x86_64-NEXT:    movq %rdi, %rbx
+; x86_64-NEXT:    callq test
+; x86_64-NEXT:    fxch %st(1)
+; x86_64-NEXT:    fstpt (%rbx)
+; x86_64-NEXT:    fstpt (%r14)
+; x86_64-NEXT:    addq $8, %rsp
+; x86_64-NEXT:    .cfi_def_cfa_offset 24
+; x86_64-NEXT:    popq %rbx
+; x86_64-NEXT:    .cfi_def_cfa_offset 16
+; x86_64-NEXT:    popq %r14
+; x86_64-NEXT:    .cfi_def_cfa_offset 8
+; x86_64-NEXT:    retq
   %a = call %0 @test()
   %b = extractvalue %0 %a, 1
   store x86_fp80 %b, x86_fp80* %P1
@@ -49,6 +145,31 @@ define void @call2(x86_fp80 *%P1, x86_fp80 *%P2) {
 
 ; Uses ST(0), ST(1) is dead but must be popped.
 define void @call3(x86_fp80 *%P1, x86_fp80 *%P2) {
+; i686-LABEL: call3:
+; i686:       # %bb.0:
+; i686-NEXT:    pushl %esi
+; i686-NEXT:    .cfi_def_cfa_offset 8
+; i686-NEXT:    .cfi_offset %esi, -8
+; i686-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; i686-NEXT:    calll test
+; i686-NEXT:    fstp %st(1)
+; i686-NEXT:    fstpt (%esi)
+; i686-NEXT:    popl %esi
+; i686-NEXT:    .cfi_def_cfa_offset 4
+; i686-NEXT:    retl
+;
+; x86_64-LABEL: call3:
+; x86_64:       # %bb.0:
+; x86_64-NEXT:    pushq %rbx
+; x86_64-NEXT:    .cfi_def_cfa_offset 16
+; x86_64-NEXT:    .cfi_offset %rbx, -16
+; x86_64-NEXT:    movq %rdi, %rbx
+; x86_64-NEXT:    callq test
+; x86_64-NEXT:    fstp %st(1)
+; x86_64-NEXT:    fstpt (%rbx)
+; x86_64-NEXT:    popq %rbx
+; x86_64-NEXT:    .cfi_def_cfa_offset 8
+; x86_64-NEXT:    retq
   %a = call %0 @test()
   %b = extractvalue %0 %a, 0
   store x86_fp80 %b, x86_fp80* %P1
@@ -57,6 +178,31 @@ define void @call3(x86_fp80 *%P1, x86_fp80 *%P2) {
 
 ; Uses ST(1), ST(0) is dead and must be popped.
 define void @call4(x86_fp80 *%P1, x86_fp80 *%P2) {
+; i686-LABEL: call4:
+; i686:       # %bb.0:
+; i686-NEXT:    pushl %esi
+; i686-NEXT:    .cfi_def_cfa_offset 8
+; i686-NEXT:    .cfi_offset %esi, -8
+; i686-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; i686-NEXT:    calll test
+; i686-NEXT:    fstp %st(0)
+; i686-NEXT:    fstpt (%esi)
+; i686-NEXT:    popl %esi
+; i686-NEXT:    .cfi_def_cfa_offset 4
+; i686-NEXT:    retl
+;
+; x86_64-LABEL: call4:
+; x86_64:       # %bb.0:
+; x86_64-NEXT:    pushq %rbx
+; x86_64-NEXT:    .cfi_def_cfa_offset 16
+; x86_64-NEXT:    .cfi_offset %rbx, -16
+; x86_64-NEXT:    movq %rsi, %rbx
+; x86_64-NEXT:    callq test
+; x86_64-NEXT:    fstp %st(0)
+; x86_64-NEXT:    fstpt (%rbx)
+; x86_64-NEXT:    popq %rbx
+; x86_64-NEXT:    .cfi_def_cfa_offset 8
+; x86_64-NEXT:    retq
   %a = call %0 @test()
 
   %c = extractvalue %0 %a, 1

diff --git a/llvm/test/CodeGen/X86/fp-stack-direct-ret.ll b/llvm/test/CodeGen/X86/fp-stack-direct-ret.ll
@@ -1,9 +1,13 @@
-; RUN: llc < %s -mtriple=i686-- | not grep fstp
-; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | not grep movsd
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefixes=ALL,GENERIC
+; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | FileCheck %s --check-prefixes=ALL,YONAH
 
 declare double @foo()
 
 define double @bar() {
+; ALL-LABEL: bar:
+; ALL:       # %bb.0: # %entry
+; ALL-NEXT:    jmp foo # TAILCALL
 entry:
 	%tmp5 = tail call double @foo()
 	ret double %tmp5

diff --git a/llvm/test/CodeGen/X86/fp-stack-ret-conv.ll b/llvm/test/CodeGen/X86/fp-stack-ret-conv.ll
@@ -1,11 +1,26 @@
-; RUN: llc < %s -mcpu=yonah | grep cvtss2sd
-; RUN: llc < %s -mcpu=yonah | grep fstps
-; RUN: llc < %s -mcpu=yonah | not grep cvtsd2ss
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mcpu=yonah | FileCheck %s
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64"
 target triple = "i686-apple-darwin8"
 
 define void @test(double *%b) {
+; CHECK-LABEL: test:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    subl $8, %esp
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %esi, -8
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT:    calll _foo
+; CHECK-NEXT:    fstps {{[0-9]+}}(%esp)
+; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:    cvtss2sd %xmm0, %xmm0
+; CHECK-NEXT:    movsd %xmm0, (%esi)
+; CHECK-NEXT:    addl $8, %esp
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    retl
 entry:
 	%tmp13 = tail call double @foo()
 	%tmp1314 = fptrunc double %tmp13 to float		; <float> [#uses=1]

diff --git a/llvm/test/CodeGen/X86/fp-stack-ret-store.ll b/llvm/test/CodeGen/X86/fp-stack-ret-store.ll
@@ -1,11 +1,26 @@
-; RUN: llc < %s -mcpu=yonah | not grep movss
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mcpu=yonah | FileCheck %s
+
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
 target triple = "i686-apple-darwin8"
 
 ; This should store directly into P from the FP stack.  It should not
 ; go through a stack slot to get there.
 
 define void @bar(double* %P) {
+; CHECK-LABEL: bar:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    subl $8, %esp
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %esi, -8
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT:    calll _foo
+; CHECK-NEXT:    fstpl (%esi)
+; CHECK-NEXT:    addl $8, %esp
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    retl
 entry:
 	%tmp = tail call double (...) @foo( )		; <double> [#uses=1]
 	store double %tmp, double* %P, align 8
@@ -15,6 +30,19 @@ entry:
 declare double @foo(...)
 
 define void @bar2(float* %P) {
+; CHECK-LABEL: bar2:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    subl $8, %esp
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %esi, -8
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT:    calll _foo2
+; CHECK-NEXT:    fstps (%esi)
+; CHECK-NEXT:    addl $8, %esp
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    retl
 entry:
 	%tmp = tail call double (...) @foo2( )		; <double> [#uses=1]
 	%tmp1 = fptrunc double %tmp to float		; <float> [#uses=1]

diff --git a/llvm/test/CodeGen/X86/fp-stack-retcopy.ll b/llvm/test/CodeGen/X86/fp-stack-retcopy.ll
@@ -1,10 +1,14 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; This should not copy the result of foo into an xmm register.
-; RUN: llc < %s -mcpu=yonah -mtriple=i686-apple-darwin9 | not grep xmm
+; RUN: llc < %s -mcpu=yonah -mtriple=i686-apple-darwin9 | FileCheck %s
 ; rdar://5689903
 
 declare double @foo()
 
 define double @carg({ double, double }* byval  %z) nounwind  {
+; CHECK-LABEL: carg:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    jmp _foo ## TAILCALL
 entry:
 	%tmp5 = tail call double @foo() nounwind 		; <double> [#uses=1]
 	ret double %tmp5

diff --git a/llvm/test/CodeGen/X86/fp-stack-set-st1.ll b/llvm/test/CodeGen/X86/fp-stack-set-st1.ll
@@ -1,6 +1,23 @@
-; RUN: llc < %s -mtriple=i686-- | grep fxch | count 2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 
 define i32 @main() nounwind {
+; CHECK-LABEL: main:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    fldl {{\.LCPI.*}}
+; CHECK-NEXT:    fldl {{\.LCPI.*}}
+; CHECK-NEXT:    fxch %st(1)
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    fmul %st(1), %st
+; CHECK-NEXT:    fst %st(1)
+; CHECK-NEXT:    frndint
+; CHECK-NEXT:    fxch %st(1)
+; CHECK-NEXT:    fsub %st(1), %st
+; CHECK-NEXT:    f2xm1
+; CHECK-EMPTY:
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    fstp %st(0)
+; CHECK-NEXT:    fstp %st(0)
 entry:
 	%asmtmp = tail call { double, double } asm sideeffect "fmul\09%st(1),%st\0A\09fst\09%st(1)\0A\09frndint\0A\09fxch  %st(1)\0A\09fsub\09%st(1),%st\0A\09f2xm1\0A\09", "={st},={st(1)},0,1,~{dirflag},~{fpsr},~{flags}"(double 0x4030FEFBD582097D, double 4.620000e+01) nounwind		; <{ double, double }> [#uses=0]
 	unreachable

diff --git a/llvm/test/CodeGen/X86/fp2sint.ll b/llvm/test/CodeGen/X86/fp2sint.ll
@@ -1,8 +1,15 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ;; LowerFP_TO_SINT should not create a stack object if it's not needed.
 
-; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | not grep add
+; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 | FileCheck %s
 
 define i32 @main(i32 %argc, i8** %argv) {
+; CHECK-LABEL: main:
+; CHECK:       # %bb.0: # %cond_false.i.i.i
+; CHECK-NEXT:    cvttsd2si 0, %eax
+; CHECK-NEXT:    movl %eax, 0
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    retl
 cond_false.i.i.i:               ; preds = %bb.i5
        %tmp35.i = load double, double* null, align 8           ; <double> [#uses=1]
        %tmp3536.i = fptosi double %tmp35.i to i32              ; <i32> [#uses=1]

diff --git a/llvm/test/CodeGen/X86/fp_load_fold.ll b/llvm/test/CodeGen/X86/fp_load_fold.ll
@@ -1,39 +1,75 @@
-; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | \
-; RUN:   grep -i ST | not grep "fadd\|fsub\|fdiv\|fmul"
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- -x86-asm-syntax=intel | FileCheck %s
 
 ; Test that the load of the memory location is folded into the operation.
 
 define double @test_add(double %X, double* %P) {
+; CHECK-LABEL: test_add:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mov eax, dword ptr [esp + 12]
+; CHECK-NEXT:    fld qword ptr [esp + 4]
+; CHECK-NEXT:    fadd qword ptr [eax]
+; CHECK-NEXT:    ret
 	%Y = load double, double* %P		; <double> [#uses=1]
 	%R = fadd double %X, %Y		; <double> [#uses=1]
 	ret double %R
 }
 
 define double @test_mul(double %X, double* %P) {
+; CHECK-LABEL: test_mul:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mov eax, dword ptr [esp + 12]
+; CHECK-NEXT:    fld qword ptr [esp + 4]
+; CHECK-NEXT:    fmul qword ptr [eax]
+; CHECK-NEXT:    ret
 	%Y = load double, double* %P		; <double> [#uses=1]
 	%R = fmul double %X, %Y		; <double> [#uses=1]
 	ret double %R
 }
 
 define double @test_sub(double %X, double* %P) {
+; CHECK-LABEL: test_sub:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mov eax, dword ptr [esp + 12]
+; CHECK-NEXT:    fld qword ptr [esp + 4]
+; CHECK-NEXT:    fsub qword ptr [eax]
+; CHECK-NEXT:    ret
 	%Y = load double, double* %P		; <double> [#uses=1]
 	%R = fsub double %X, %Y		; <double> [#uses=1]
 	ret double %R
 }
 
 define double @test_subr(double %X, double* %P) {
+; CHECK-LABEL: test_subr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mov eax, dword ptr [esp + 12]
+; CHECK-NEXT:    fld qword ptr [eax]
+; CHECK-NEXT:    fsub qword ptr [esp + 4]
+; CHECK-NEXT:    ret
 	%Y = load double, double* %P		; <double> [#uses=1]
 	%R = fsub double %Y, %X		; <double> [#uses=1]
 	ret double %R
 }
 
 define double @test_div(double %X, double* %P) {
+; CHECK-LABEL: test_div:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mov eax, dword ptr [esp + 12]
+; CHECK-NEXT:    fld qword ptr [esp + 4]
+; CHECK-NEXT:    fdiv qword ptr [eax]
+; CHECK-NEXT:    ret
 	%Y = load double, double* %P		; <double> [#uses=1]
 	%R = fdiv double %X, %Y		; <double> [#uses=1]
 	ret double %R
 }
 
 define double @test_divr(double %X, double* %P) {
+; CHECK-LABEL: test_divr:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    mov eax, dword ptr [esp + 12]
+; CHECK-NEXT:    fld qword ptr [eax]
+; CHECK-NEXT:    fdiv qword ptr [esp + 4]
+; CHECK-NEXT:    ret
 	%Y = load double, double* %P		; <double> [#uses=1]
 	%R = fdiv double %Y, %X		; <double> [#uses=1]
 	ret double %R

diff --git a/llvm/test/CodeGen/X86/fsxor-alignment.ll b/llvm/test/CodeGen/X86/fsxor-alignment.ll
@@ -1,11 +1,23 @@
-; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 -enable-unsafe-fp-math | \
-; RUN:  grep -v sp | grep xorps | count 2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 -enable-unsafe-fp-math | FileCheck %s
 
 ; Don't fold the incoming stack arguments into the xorps instructions used
 ; to do floating-point negations, because the arguments aren't vectors
 ; and aren't vector-aligned.
 
 define void @foo(float* %p, float* %q, float %s, float %y) {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:    movaps {{.*#+}} xmm1 = [-0.0E+0,-0.0E+0,-0.0E+0,-0.0E+0]
+; CHECK-NEXT:    xorps %xmm1, %xmm0
+; CHECK-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
+; CHECK-NEXT:    xorps %xmm1, %xmm2
+; CHECK-NEXT:    movss %xmm0, (%ecx)
+; CHECK-NEXT:    movss %xmm2, (%eax)
+; CHECK-NEXT:    retl
   %ss = fsub float -0.0, %s
   %yy = fsub float -0.0, %y
   store float %ss, float* %p

diff --git a/llvm/test/CodeGen/X86/hidden-vis-2.ll b/llvm/test/CodeGen/X86/hidden-vis-2.ll
@@ -1,9 +1,19 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin9   | grep mov | count 1
-; RUN: llc < %s -mtriple=x86_64-apple-darwin9 | not grep GOT
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-apple-darwin9   | FileCheck %s --check-prefix=i386-darwin9
+; RUN: llc < %s -mtriple=x86_64-apple-darwin9 | FileCheck %s --check-prefix=x86_64-darwin9
 
 @x = weak hidden global i32 0		; <i32*> [#uses=1]
 
 define i32 @t() nounwind readonly {
+; i386-darwin9-LABEL: t:
+; i386-darwin9:       ## %bb.0: ## %entry
+; i386-darwin9-NEXT:    movl _x, %eax
+; i386-darwin9-NEXT:    retl
+;
+; x86_64-darwin9-LABEL: t:
+; x86_64-darwin9:       ## %bb.0: ## %entry
+; x86_64-darwin9-NEXT:    movl {{.*}}(%rip), %eax
+; x86_64-darwin9-NEXT:    retq
 entry:
 	%0 = load i32, i32* @x, align 4		; <i32> [#uses=1]
 	ret i32 %0

diff --git a/llvm/test/CodeGen/X86/i128-and-beyond.ll b/llvm/test/CodeGen/X86/i128-and-beyond.ll
@@ -1,8 +1,21 @@
-; RUN: llc < %s -mtriple=i686-pc-linux-gnu | grep -- -1 | count 14
+; RUN: llc < %s -mtriple=i686-pc-linux-gnu | FileCheck %s
 
 ; These static initializers are too big to hand off to assemblers
 ; as monolithic blobs.
 
+; CHECK: -1
+; CHECK-NEXT: -1
+; CHECK: -1
+; CHECK-NEXT: -1
+; CHECK-NEXT: -1
+; CHECK-NEXT: -1
+; CHECK: -1
+; CHECK-NEXT: -1
+; CHECK-NEXT: -1
+; CHECK-NEXT: -1
+; CHECK-NEXT: -1
+; CHECK-NEXT: -1
+; CHECK-NEXT: -1
 @x = global i128 -1
 @y = global i256 -1
 @z = global i512 -1
diff --git a/llvm/test/CodeGen/X86/i128-immediate.ll b/llvm/test/CodeGen/X86/i128-immediate.ll
@@ -1,5 +1,11 @@
-; RUN: llc < %s -mtriple=x86_64-- | grep movq | count 2
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 
 define i128 @__addvti3() {
+; CHECK-LABEL: __addvti3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq $-1, %rax
+; CHECK-NEXT:    movq $-1, %rdx
+; CHECK-NEXT:    retq
           ret i128 -1
 }
diff --git a/llvm/test/CodeGen/X86/illegal-vector-args-return.ll b/llvm/test/CodeGen/X86/illegal-vector-args-return.ll
@@ -1,16 +1,24 @@
-; RUN: llc < %s -mattr=+sse2 -mcpu=nehalem | grep "mulpd	%xmm3, %xmm1"
-; RUN: llc < %s -mattr=+sse2 -mcpu=nehalem | grep "mulpd	%xmm2, %xmm0"
-; RUN: llc < %s -mattr=+sse2 -mcpu=nehalem | grep "addps	%xmm3, %xmm1"
-; RUN: llc < %s -mattr=+sse2 -mcpu=nehalem | grep "addps	%xmm2, %xmm0"
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mattr=+sse2 -mcpu=nehalem | FileCheck %s
 
 target triple = "i686-apple-darwin8"
 
 define <4 x double> @foo(<4 x double> %x, <4 x double> %z) {
+; CHECK-LABEL: foo:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    mulpd %xmm2, %xmm0
+; CHECK-NEXT:    mulpd %xmm3, %xmm1
+; CHECK-NEXT:    retl
   %y = fmul <4 x double> %x, %z
   ret <4 x double> %y
 }
 
 define <8 x float> @bar(<8 x float> %x, <8 x float> %z) {
+; CHECK-LABEL: bar:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    addps %xmm2, %xmm0
+; CHECK-NEXT:    addps %xmm3, %xmm1
+; CHECK-NEXT:    retl
   %y = fadd <8 x float> %x, %z
   ret <8 x float> %y
 }
diff --git a/llvm/test/CodeGen/X86/inline-asm-modifier-n.ll b/llvm/test/CodeGen/X86/inline-asm-modifier-n.ll
@@ -1,7 +1,14 @@
-; RUN: llc < %s -mtriple=i686-- -no-integrated-as | grep " 37"
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- -no-integrated-as | FileCheck %s
 ; rdar://7008959
 
 define void @bork() nounwind {
+; CHECK-LABEL: bork:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    #APP
+; CHECK-NEXT:    BORK 37
+; CHECK-NEXT:    #NO_APP
+; CHECK-NEXT:    retl
 entry:
 	tail call void asm sideeffect "BORK ${0:n}", "i,~{dirflag},~{fpsr},~{flags}"(i32 -37) nounwind
 	ret void

diff --git a/llvm/test/CodeGen/X86/inline-asm-mrv.ll b/llvm/test/CodeGen/X86/inline-asm-mrv.ll
@@ -1,13 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -no-integrated-as | FileCheck %s
 ; PR2094
-; RUN: llc < %s -no-integrated-as | grep movslq
-; RUN: llc < %s -no-integrated-as | grep addps
-; RUN: llc < %s -no-integrated-as | grep paddd
-; RUN: llc < %s -no-integrated-as | not grep movq
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
 target triple = "x86_64-apple-darwin8"
 
 define i32 @test1(i8* %v, i8* %blk2, i8* %blk1, i32 %stride, i32 %h) nounwind  {
+; CHECK-LABEL: test1:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movslq %ecx, %rax
+; CHECK-NEXT:    ## InlineAsm Start
+; CHECK-NEXT:    %eax %rcx %rdx %rax %r8d %rdx %rsi
+; CHECK-NEXT:    ## InlineAsm End
+; CHECK-NEXT:    ## InlineAsm Start
+; CHECK-NEXT:    set %eax
+; CHECK-NEXT:    ## InlineAsm End
+; CHECK-NEXT:    retq
 	%tmp12 = sext i32 %stride to i64		; <i64> [#uses=1]
 	%mrv = call {i32, i8*, i8*} asm sideeffect "$0 $1 $2 $3 $4 $5 $6",
          "=r,=r,=r,r,r,r,r"( i64 %tmp12, i32 %h, i8* %blk1, i8* %blk2 ) nounwind
@@ -18,6 +26,13 @@ define i32 @test1(i8* %v, i8* %blk2, i8* %blk1, i32 %stride, i32 %h) nounwind  {
 }
 
 define <4 x float> @test2() nounwind {
+; CHECK-LABEL: test2:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    ## InlineAsm Start
+; CHECK-NEXT:    set %xmm0, %xmm1
+; CHECK-NEXT:    ## InlineAsm End
+; CHECK-NEXT:    addps %xmm1, %xmm0
+; CHECK-NEXT:    retq
 	%mrv = call {<4 x float>, <4 x float>} asm "set $0, $1", "=x,=x"()
 	%a = extractvalue {<4 x float>, <4 x float>} %mrv, 0
 	%b = extractvalue {<4 x float>, <4 x float>} %mrv, 1
@@ -26,6 +41,13 @@ define <4 x float> @test2() nounwind {
 }
 
 define <4 x i32> @test3() nounwind {
+; CHECK-LABEL: test3:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    ## InlineAsm Start
+; CHECK-NEXT:    set %xmm0, %xmm1
+; CHECK-NEXT:    ## InlineAsm End
+; CHECK-NEXT:    paddd %xmm1, %xmm0
+; CHECK-NEXT:    retq
 	%mrv = call {<4 x i32>, <4 x i32>} asm "set $0, $1", "=x,=x"()
 	%a = extractvalue {<4 x i32>, <4 x i32>} %mrv, 0
 	%b = extractvalue {<4 x i32>, <4 x i32>} %mrv, 1

diff --git a/llvm/test/CodeGen/X86/inline-asm-pic.ll b/llvm/test/CodeGen/X86/inline-asm-pic.ll
@@ -1,9 +1,19 @@
-; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic | grep lea
-; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic | grep call
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i386-apple-darwin -relocation-model=pic | FileCheck %s
 
 @main_q = internal global i8* null		; <i8**> [#uses=1]
 
 define void @func2() nounwind {
+; CHECK-LABEL: func2:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    calll L0$pb
+; CHECK-NEXT:  L0$pb:
+; CHECK-NEXT:    popl %eax
+; CHECK-NEXT:    leal _main_q-L0$pb(%eax), %eax
+; CHECK-NEXT:    ## InlineAsm Start
+; CHECK-NEXT:    movl %eax, %gs:152
+; CHECK-NEXT:    ## InlineAsm End
+; CHECK-NEXT:    retl
 entry:
 	tail call void asm "mov $1,%gs:$0", "=*m,ri,~{dirflag},~{fpsr},~{flags}"(i8** inttoptr (i32 152 to i8**), i8* bitcast (i8** @main_q to i8*)) nounwind
 	ret void

diff --git a/llvm/test/CodeGen/X86/ins_subreg_coalesce-2.ll b/llvm/test/CodeGen/X86/ins_subreg_coalesce-2.ll
@@ -1,6 +1,13 @@
-; RUN: llc < %s -mtriple=x86_64-- | not grep movw
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 
 define i16 @test5(i16 %f12) nounwind {
+; CHECK-LABEL: test5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    shrl $6, %edi
+; CHECK-NEXT:    movsbl %dil, %eax
+; CHECK-NEXT:    # kill: def $ax killed $ax killed $eax
+; CHECK-NEXT:    retq
 	%f11 = shl i16 %f12, 2		; <i16> [#uses=1]
 	%tmp7.25 = ashr i16 %f11, 8		; <i16> [#uses=1]
 	ret i16 %tmp7.25

diff --git a/llvm/test/CodeGen/X86/ins_subreg_coalesce-3.ll b/llvm/test/CodeGen/X86/ins_subreg_coalesce-3.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -mtriple=x86_64-- | grep mov | count 3
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 
 	%struct.COMPOSITE = type { i8, i16, i16 }
 	%struct.FILE = type { i8*, i32, i32, i16, i16, %struct.__sbuf, i32, i8*, i32 (i8*)*, i32 (i8*, i8*, i32)*, i64 (i8*, i64, i32)*, i32 (i8*, i8*, i32)*, %struct.__sbuf, %struct.__sFILEX*, i32, [3 x i8], [1 x i8], %struct.__sbuf, i32, i64 }
@@ -18,6 +19,44 @@
 	%struct.rec = type { %struct.head_type }
 
 define void @FontChange(i1 %foo) nounwind {
+; CHECK-LABEL: FontChange:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    testb $1, %dil
+; CHECK-NEXT:    je .LBB0_9
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB0_1: # %bb366
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    testb $1, %dil
+; CHECK-NEXT:    jne .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %bb428
+; CHECK-NEXT:    testb $1, %dil
+; CHECK-NEXT:    je .LBB0_9
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB0_3: # %bb650
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    cmpb $0, 0
+; CHECK-NEXT:    je .LBB0_3
+; CHECK-NEXT:  # %bb.4: # %bb662
+; CHECK-NEXT:    movl 0, %eax
+; CHECK-NEXT:    movl %eax, %ecx
+; CHECK-NEXT:    andl $57344, %ecx # imm = 0xE000
+; CHECK-NEXT:    cmpl $8192, %ecx # imm = 0x2000
+; CHECK-NEXT:    jne .LBB0_9
+; CHECK-NEXT:  # %bb.5: # %bb4884
+; CHECK-NEXT:    andl $7168, %eax # imm = 0x1C00
+; CHECK-NEXT:    cmpl $1024, %eax # imm = 0x400
+; CHECK-NEXT:    jne .LBB0_9
+; CHECK-NEXT:  # %bb.6: # %bb4932
+; CHECK-NEXT:    testb $1, %dil
+; CHECK-NEXT:    jne .LBB0_9
+; CHECK-NEXT:  # %bb.7: # %bb4940
+; CHECK-NEXT:    movl 0, %eax
+; CHECK-NEXT:    cmpl $160, %eax
+; CHECK-NEXT:    je .LBB0_9
+; CHECK-NEXT:  # %bb.8: # %bb4940
+; CHECK-NEXT:    cmpl $159, %eax
+; CHECK-NEXT:  .LBB0_9: # %bb4897
+; CHECK-NEXT:    retq
 entry:
 	br i1 %foo, label %bb298, label %bb49
 bb49:		; preds = %entry

diff --git a/llvm/test/CodeGen/X86/isel-sink2.ll b/llvm/test/CodeGen/X86/isel-sink2.ll
@@ -1,8 +1,18 @@
-; RUN: llc < %s -mtriple=i686-- > %t
-; RUN: grep "movb.7(%...)" %t
-; RUN: not grep leal %t
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 
 define i8 @test(i32 *%P) nounwind {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    cmpb $0, 4(%eax)
+; CHECK-NEXT:    je .LBB0_1
+; CHECK-NEXT:  # %bb.2: # %F
+; CHECK-NEXT:    movb 7(%eax), %al
+; CHECK-NEXT:    retl
+; CHECK-NEXT:  .LBB0_1: # %TB
+; CHECK-NEXT:    movb $4, %al
+; CHECK-NEXT:    retl
   %Q = getelementptr i32, i32* %P, i32 1
   %R = bitcast i32* %Q to i8*
   %S = load i8, i8* %R

diff --git a/llvm/test/CodeGen/X86/isnan.ll b/llvm/test/CodeGen/X86/isnan.ll
@@ -1,8 +1,18 @@
-; RUN: llc < %s -mtriple=i686-- | not grep call
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 
 declare i1 @llvm.isunordered.f64(double)
 
 define i1 @test_isnan(double %X) {
+; CHECK-LABEL: test_isnan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fldl {{[0-9]+}}(%esp)
+; CHECK-NEXT:    fucomp %st(0)
+; CHECK-NEXT:    fnstsw %ax
+; CHECK-NEXT:    # kill: def $ah killed $ah killed $ax
+; CHECK-NEXT:    sahf
+; CHECK-NEXT:    setp %al
+; CHECK-NEXT:    retl
         %R = fcmp uno double %X, %X             ; <i1> [#uses=1]
         ret i1 %R
 }

diff --git a/llvm/test/CodeGen/X86/isnan2.ll b/llvm/test/CodeGen/X86/isnan2.ll
@@ -1,8 +1,16 @@
-; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | not grep pxor
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- -mcpu=yonah | FileCheck %s
 
 ; This should not need to materialize 0.0 to evaluate the condition.
 
 define i32 @test(double %X) nounwind  {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    ucomisd %xmm0, %xmm0
+; CHECK-NEXT:    setp %al
+; CHECK-NEXT:    retl
 entry:
 	%tmp6 = fcmp uno double %X, 0.000000e+00		; <i1> [#uses=1]
 	%tmp67 = zext i1 %tmp6 to i32		; <i32> [#uses=1]

diff --git a/llvm/test/CodeGen/X86/ispositive.ll b/llvm/test/CodeGen/X86/ispositive.ll
@@ -1,6 +1,12 @@
-; RUN: llc < %s -mtriple=i686-- | grep "shrl.*31"
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 
 define i32 @test1(i32 %X) {
+; CHECK-LABEL: test1:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    shrl $31, %eax
+; CHECK-NEXT:    retl
 entry:
         icmp slt i32 %X, 0              ; <i1>:0 [#uses=1]
         zext i1 %0 to i32               ; <i32>:1 [#uses=1]

diff --git a/llvm/test/CodeGen/X86/large-constants.ll b/llvm/test/CodeGen/X86/large-constants.ll
@@ -1,6 +1,35 @@
-; RUN: llc < %s -mtriple=x86_64-darwin -mcpu=corei7 | grep movabsq | count 3
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-darwin -mcpu=corei7 | FileCheck %s
 
 define i64 @constant_hoisting(i64 %o0, i64 %o1, i64 %o2, i64 %o3, i64 %o4, i64 %o5) {
+; CHECK-LABEL: constant_hoisting:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    movabsq $-281474976710654, %rax ## imm = 0xFFFF000000000002
+; CHECK-NEXT:    testq %rax, %rdi
+; CHECK-NEXT:    jne LBB0_7
+; CHECK-NEXT:  ## %bb.1: ## %bb1
+; CHECK-NEXT:    testq %rax, %rsi
+; CHECK-NEXT:    jne LBB0_7
+; CHECK-NEXT:  ## %bb.2: ## %bb2
+; CHECK-NEXT:    testq %rax, %rdx
+; CHECK-NEXT:    jne LBB0_7
+; CHECK-NEXT:  ## %bb.3: ## %bb3
+; CHECK-NEXT:    testq %rax, %rcx
+; CHECK-NEXT:    jne LBB0_7
+; CHECK-NEXT:  ## %bb.4: ## %bb4
+; CHECK-NEXT:    leaq 1(%rax), %rcx
+; CHECK-NEXT:    testq %rcx, %r8
+; CHECK-NEXT:    jne LBB0_7
+; CHECK-NEXT:  ## %bb.5: ## %bb5
+; CHECK-NEXT:    addq $2, %rax
+; CHECK-NEXT:    andq %rax, %r9
+; CHECK-NEXT:    je LBB0_6
+; CHECK-NEXT:  LBB0_7: ## %fail
+; CHECK-NEXT:    movq $-1, %rax
+; CHECK-NEXT:    retq
+; CHECK-NEXT:  LBB0_6: ## %bb6
+; CHECK-NEXT:    movq %r9, %rax
+; CHECK-NEXT:    retq
 entry:
   %l0 = and i64 %o0, -281474976710654
   %c0 = icmp ne i64 %l0, 0
@@ -39,6 +68,16 @@ fail:
 }
 
 define void @constant_expressions() {
+; CHECK-LABEL: constant_expressions:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    movabsq $51250129900, %rax ## imm = 0xBEEBEEBEC
+; CHECK-NEXT:    movq (%rax), %rcx
+; CHECK-NEXT:    movq 16(%rax), %rdx
+; CHECK-NEXT:    addq 8(%rax), %rcx
+; CHECK-NEXT:    addq 24(%rax), %rdx
+; CHECK-NEXT:    addq %rcx, %rdx
+; CHECK-NEXT:    movq %rdx, (%rax)
+; CHECK-NEXT:    retq
 entry:
   %0 = load i64, i64* inttoptr (i64 add (i64 51250129900, i64 0) to i64*)
   %1 = load i64, i64* inttoptr (i64 add (i64 51250129900, i64 8) to i64*)
@@ -53,6 +92,16 @@ entry:
 
 
 define void @constant_expressions2() {
+; CHECK-LABEL: constant_expressions2:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    movabsq $51250129900, %rax ## imm = 0xBEEBEEBEC
+; CHECK-NEXT:    movq (%rax), %rcx
+; CHECK-NEXT:    movq 16(%rax), %rdx
+; CHECK-NEXT:    addq 8(%rax), %rcx
+; CHECK-NEXT:    addq 24(%rax), %rdx
+; CHECK-NEXT:    addq %rcx, %rdx
+; CHECK-NEXT:    movq %rdx, (%rax)
+; CHECK-NEXT:    retq
 entry:
   %0 = load i64, i64* inttoptr (i64 51250129900 to i64*)
   %1 = load i64, i64* inttoptr (i64 51250129908 to i64*)

diff --git a/llvm/test/CodeGen/X86/lea-recursion.ll b/llvm/test/CodeGen/X86/lea-recursion.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -mtriple=x86_64-- | grep lea | count 13
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 
 ; This testcase was written to demonstrate an instruction-selection problem,
 ; however it also happens to expose a limitation in the DAGCombiner's
@@ -12,6 +13,37 @@
 @g1 = weak global [1000 x i32] zeroinitializer, align 32		; <[1000 x i32]*> [#uses=7]
 
 define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl {{.*}}(%rip), %eax
+; CHECK-NEXT:    movl {{.*}}(%rip), %ecx
+; CHECK-NEXT:    leal (%rax,%rcx), %edx
+; CHECK-NEXT:    leal 1(%rax,%rcx), %eax
+; CHECK-NEXT:    movl %eax, g0+{{.*}}(%rip)
+; CHECK-NEXT:    movl g1+{{.*}}(%rip), %eax
+; CHECK-NEXT:    leal 1(%rax,%rdx), %ecx
+; CHECK-NEXT:    leal 2(%rax,%rdx), %eax
+; CHECK-NEXT:    movl %eax, g0+{{.*}}(%rip)
+; CHECK-NEXT:    movl g1+{{.*}}(%rip), %eax
+; CHECK-NEXT:    leal 1(%rax,%rcx), %edx
+; CHECK-NEXT:    leal 2(%rax,%rcx), %eax
+; CHECK-NEXT:    movl %eax, g0+{{.*}}(%rip)
+; CHECK-NEXT:    movl g1+{{.*}}(%rip), %eax
+; CHECK-NEXT:    leal 1(%rax,%rdx), %ecx
+; CHECK-NEXT:    leal 2(%rax,%rdx), %eax
+; CHECK-NEXT:    movl %eax, g0+{{.*}}(%rip)
+; CHECK-NEXT:    movl g1+{{.*}}(%rip), %eax
+; CHECK-NEXT:    leal 1(%rax,%rcx), %edx
+; CHECK-NEXT:    leal 2(%rax,%rcx), %eax
+; CHECK-NEXT:    movl %eax, g0+{{.*}}(%rip)
+; CHECK-NEXT:    movl g1+{{.*}}(%rip), %eax
+; CHECK-NEXT:    leal 1(%rax,%rdx), %ecx
+; CHECK-NEXT:    leal 2(%rax,%rdx), %eax
+; CHECK-NEXT:    movl %eax, g0+{{.*}}(%rip)
+; CHECK-NEXT:    movl g1+{{.*}}(%rip), %eax
+; CHECK-NEXT:    leal 2(%rax,%rcx), %eax
+; CHECK-NEXT:    movl %eax, g0+{{.*}}(%rip)
+; CHECK-NEXT:    retq
 entry:
 	%tmp4 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g0, i32 0, i32 0)		; <i32> [#uses=1]
 	%tmp8 = load i32, i32* getelementptr ([1000 x i32], [1000 x i32]* @g1, i32 0, i32 0)		; <i32> [#uses=1]

diff --git a/llvm/test/CodeGen/X86/limited-prec.ll b/llvm/test/CodeGen/X86/limited-prec.ll
diff --git a/llvm/test/CodeGen/X86/loop-strength-reduce5.ll b/llvm/test/CodeGen/X86/loop-strength-reduce5.ll
@@ -1,9 +1,29 @@
-; RUN: llc < %s -mtriple=i686-- | grep inc | count 1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 
 @X = weak global i16 0		; <i16*> [#uses=1]
 @Y = weak global i16 0		; <i16*> [#uses=1]
 
 define void @foo(i32 %N) nounwind {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    testl %eax, %eax
+; CHECK-NEXT:    jle .LBB0_3
+; CHECK-NEXT:  # %bb.1: # %bb.preheader
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB0_2: # %bb
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    movw %dx, X
+; CHECK-NEXT:    movw %cx, Y
+; CHECK-NEXT:    incl %edx
+; CHECK-NEXT:    addl $4, %ecx
+; CHECK-NEXT:    cmpl %edx, %eax
+; CHECK-NEXT:    jne .LBB0_2
+; CHECK-NEXT:  .LBB0_3: # %return
+; CHECK-NEXT:    retl
 entry:
 	%tmp1019 = icmp sgt i32 %N, 0		; <i1> [#uses=1]
 	br i1 %tmp1019, label %bb, label %return

diff --git a/llvm/test/CodeGen/X86/loop-strength-reduce6.ll b/llvm/test/CodeGen/X86/loop-strength-reduce6.ll
@@ -1,6 +1,11 @@
-; RUN: llc < %s -mtriple=x86_64-- | not grep inc
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 
 define fastcc i32 @decodeMP3(i32 %isize, i32* %done) nounwind {
+; CHECK-LABEL: decodeMP3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    retq
 entry:
 	br label %cond_true189
 

diff --git a/llvm/test/CodeGen/X86/loop-strength-reduce7.ll b/llvm/test/CodeGen/X86/loop-strength-reduce7.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s | not grep imul
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s | FileCheck %s
 
 target triple = "i386-apple-darwin9.6"
 	%struct.III_psy_xmin = type { [22 x double], [13 x [3 x double]] }
@@ -7,6 +8,30 @@ target triple = "i386-apple-darwin9.6"
 	%struct.lame_global_flags = type { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i8*, i8*, i32, i32, float, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, float, i32, i32, i32, float, float, float, float, i32, i32, i32, i32, i32, i32, i32, i32 }
 
 define fastcc void @outer_loop(%struct.lame_global_flags* nocapture %gfp, double* nocapture %xr, i32 %targ_bits, double* nocapture %best_noise, %struct.III_psy_xmin* nocapture %l3_xmin, i32* nocapture %l3_enc, %struct.III_scalefac_t* nocapture %scalefac, %struct.gr_info* nocapture %cod_info, i32 %ch) nounwind {
+; CHECK-LABEL: outer_loop:
+; CHECK:       ## %bb.0: ## %entry
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    movl $88, %eax
+; CHECK-NEXT:    movl $168, %ecx
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  LBB0_2: ## %bb28.i37
+; CHECK-NEXT:    ## =>This Loop Header: Depth=1
+; CHECK-NEXT:    ## Child Loop BB0_3 Depth 2
+; CHECK-NEXT:    xorl %edx, %edx
+; CHECK-NEXT:    movl %eax, %esi
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  LBB0_3: ## %bb29.i38
+; CHECK-NEXT:    ## Parent Loop BB0_2 Depth=1
+; CHECK-NEXT:    ## => This Inner Loop Header: Depth=2
+; CHECK-NEXT:    incl %edx
+; CHECK-NEXT:    addl $12, %esi
+; CHECK-NEXT:    cmpl $11, %edx
+; CHECK-NEXT:    jbe LBB0_3
+; CHECK-NEXT:  ## %bb.1: ## %bb28.i37.loopexit
+; CHECK-NEXT:    ## in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT:    addl $4, %eax
+; CHECK-NEXT:    addl $168, %ecx
+; CHECK-NEXT:    jmp LBB0_2
 entry:
 	br label %bb4
 

diff --git a/llvm/test/CodeGen/X86/lsr-negative-stride.ll b/llvm/test/CodeGen/X86/lsr-negative-stride.ll
@@ -1,8 +1,5 @@
-; RUN: llc < %s -mtriple=i686-- > %t
-; RUN: not grep neg %t
-; RUN: not grep sub.*esp %t
-; RUN: not grep esi %t
-; RUN: not grep push %t
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 
 ; This corresponds to:
 ;int t(int a, int b) {
@@ -17,6 +14,41 @@
 
 
 define i32 @t(i32 %a, i32 %b) nounwind {
+; CHECK-LABEL: t:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %edx
+; CHECK-NEXT:    cmpl %ecx, %edx
+; CHECK-NEXT:    jne .LBB0_2
+; CHECK-NEXT:  # %bb.1:
+; CHECK-NEXT:    movl %edx, %eax
+; CHECK-NEXT:    retl
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB0_2: # %bb.outer
+; CHECK-NEXT:    # =>This Loop Header: Depth=1
+; CHECK-NEXT:    # Child Loop BB0_3 Depth 2
+; CHECK-NEXT:    movl %edx, %eax
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB0_3: # %bb
+; CHECK-NEXT:    # Parent Loop BB0_2 Depth=1
+; CHECK-NEXT:    # => This Inner Loop Header: Depth=2
+; CHECK-NEXT:    subl %ecx, %eax
+; CHECK-NEXT:    jle .LBB0_5
+; CHECK-NEXT:  # %bb.4: # %cond_true
+; CHECK-NEXT:    # in Loop: Header=BB0_3 Depth=2
+; CHECK-NEXT:    cmpl %eax, %ecx
+; CHECK-NEXT:    movl %eax, %edx
+; CHECK-NEXT:    jne .LBB0_3
+; CHECK-NEXT:    jmp .LBB0_6
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB0_5: # %cond_false
+; CHECK-NEXT:    # in Loop: Header=BB0_2 Depth=1
+; CHECK-NEXT:    subl %edx, %ecx
+; CHECK-NEXT:    cmpl %edx, %ecx
+; CHECK-NEXT:    movl %edx, %eax
+; CHECK-NEXT:    jne .LBB0_2
+; CHECK-NEXT:  .LBB0_6: # %bb17
+; CHECK-NEXT:    retl
 entry:
 	%tmp1434 = icmp eq i32 %a, %b		; <i1> [#uses=1]
 	br i1 %tmp1434, label %bb17, label %bb.outer

diff --git a/llvm/test/CodeGen/X86/lsr-sort.ll b/llvm/test/CodeGen/X86/lsr-sort.ll
@@ -1,10 +1,23 @@
-; RUN: llc < %s -mtriple=x86_64-- > %t
-; RUN: grep inc %t | count 1
-; RUN: not grep incw %t
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 
 @X = common global i16 0		; <i16*> [#uses=1]
 
 define i32 @foo(i32 %N) nounwind {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    jle .LBB0_2
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB0_1: # %bb
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    movw %ax, {{.*}}(%rip)
+; CHECK-NEXT:    incl %eax
+; CHECK-NEXT:    cmpl %eax, %edi
+; CHECK-NEXT:    jne .LBB0_1
+; CHECK-NEXT:  .LBB0_2: # %return
+; CHECK-NEXT:    retq
 entry:
 	%0 = icmp sgt i32 %N, 0		; <i1> [#uses=1]
 	br i1 %0, label %bb, label %return

diff --git a/llvm/test/CodeGen/X86/maskmovdqu.ll b/llvm/test/CodeGen/X86/maskmovdqu.ll
@@ -1,10 +1,38 @@
-; RUN: llc < %s -mtriple=i686--    -mattr=+sse2,-avx | grep -i edi
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2,-avx | grep -i rdi
-; RUN: llc < %s -mtriple=i686--    -mattr=+avx | grep -i edi
-; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | grep -i rdi
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686--    -mattr=+sse2,-avx | FileCheck %s --check-prefixes=ALL,i686_SSE2
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2,-avx | FileCheck %s --check-prefixes=ALL,x86_64_SSE2
+; RUN: llc < %s -mtriple=i686--    -mattr=+avx | FileCheck %s --check-prefixes=ALL,i686_AVX
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx | FileCheck %s --check-prefixes=ALL,x86_64_AVX
 ; rdar://6573467
 
 define void @test(<16 x i8> %a, <16 x i8> %b, i32 %dummy, i8* %c) nounwind {
+; i686_SSE2-LABEL: test:
+; i686_SSE2:       # %bb.0: # %entry
+; i686_SSE2-NEXT:    pushl %edi
+; i686_SSE2-NEXT:    movl {{[0-9]+}}(%esp), %edi
+; i686_SSE2-NEXT:    maskmovdqu %xmm1, %xmm0
+; i686_SSE2-NEXT:    popl %edi
+; i686_SSE2-NEXT:    retl
+;
+; x86_64_SSE2-LABEL: test:
+; x86_64_SSE2:       # %bb.0: # %entry
+; x86_64_SSE2-NEXT:    movq %rsi, %rdi
+; x86_64_SSE2-NEXT:    maskmovdqu %xmm1, %xmm0
+; x86_64_SSE2-NEXT:    retq
+;
+; i686_AVX-LABEL: test:
+; i686_AVX:       # %bb.0: # %entry
+; i686_AVX-NEXT:    pushl %edi
+; i686_AVX-NEXT:    movl {{[0-9]+}}(%esp), %edi
+; i686_AVX-NEXT:    vmaskmovdqu %xmm1, %xmm0
+; i686_AVX-NEXT:    popl %edi
+; i686_AVX-NEXT:    retl
+;
+; x86_64_AVX-LABEL: test:
+; x86_64_AVX:       # %bb.0: # %entry
+; x86_64_AVX-NEXT:    movq %rsi, %rdi
+; x86_64_AVX-NEXT:    vmaskmovdqu %xmm1, %xmm0
+; x86_64_AVX-NEXT:    retq
 entry:
 	tail call void @llvm.x86.sse2.maskmov.dqu( <16 x i8> %a, <16 x i8> %b, i8* %c )
 	ret void

diff --git a/llvm/test/CodeGen/X86/movfs.ll b/llvm/test/CodeGen/X86/movfs.ll
@@ -1,6 +1,12 @@
-; RUN: llc < %s -mtriple=i686-- | grep fs
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 
 define i32 @foo() nounwind readonly {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl %fs:196, %eax
+; CHECK-NEXT:    movl (%eax), %eax
+; CHECK-NEXT:    retl
 entry:
 	%tmp = load i32*, i32* addrspace(257)* getelementptr (i32*, i32* addrspace(257)* inttoptr (i32 72 to i32* addrspace(257)*), i32 31)		; <i32*> [#uses=1]
 	%tmp1 = load i32, i32* %tmp		; <i32> [#uses=1]

diff --git a/llvm/test/CodeGen/X86/mul-remat.ll b/llvm/test/CodeGen/X86/mul-remat.ll
@@ -1,7 +1,13 @@
-; RUN: llc < %s -mtriple=i686-- | grep mov | count 1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 ; PR1874
-	
+
 define i32 @test(i32 %a, i32 %b) {
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    imull {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    retl
 entry:
 	%tmp3 = mul i32 %b, %a
 	ret i32 %tmp3

diff --git a/llvm/test/CodeGen/X86/mul-shift-reassoc.ll b/llvm/test/CodeGen/X86/mul-shift-reassoc.ll
@@ -1,9 +1,16 @@
-; RUN: llc < %s -mtriple=i686-- | grep lea
-; RUN: llc < %s -mtriple=i686-- | not grep add
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 
 define i32 @test(i32 %X, i32 %Y) {
 	; Push the shl through the mul to allow an LEA to be formed, instead
         ; of using a shift and add separately.
+; CHECK-LABEL: test:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    imull %eax, %ecx
+; CHECK-NEXT:    leal (%eax,%ecx,2), %eax
+; CHECK-NEXT:    retl
         %tmp.2 = shl i32 %X, 1          ; <i32> [#uses=1]
         %tmp.3 = mul i32 %tmp.2, %Y             ; <i32> [#uses=1]
         %tmp.5 = add i32 %tmp.3, %Y             ; <i32> [#uses=1]

diff --git a/llvm/test/CodeGen/X86/neg-shl-add.ll b/llvm/test/CodeGen/X86/neg-shl-add.ll
@@ -1,15 +1,31 @@
-; RUN: llc -mtriple=x86_64-- < %s | not grep negq
-
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=x86_64-- < %s | FileCheck %s
 ; These sequences don't need neg instructions; they can be done with
 ; a single shift and sub each.
 
 define i64 @foo(i64 %x, i64 %y, i64 %n) nounwind {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rdx, %rcx
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    # kill: def $cl killed $cl killed $rcx
+; CHECK-NEXT:    shlq %cl, %rsi
+; CHECK-NEXT:    subq %rsi, %rax
+; CHECK-NEXT:    retq
   %a = sub i64 0, %y
   %b = shl i64 %a, %n
   %c = add i64 %b, %x
   ret i64 %c
 }
 define i64 @boo(i64 %x, i64 %y, i64 %n) nounwind {
+; CHECK-LABEL: boo:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rdx, %rcx
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    # kill: def $cl killed $cl killed $rcx
+; CHECK-NEXT:    shlq %cl, %rsi
+; CHECK-NEXT:    subq %rsi, %rax
+; CHECK-NEXT:    retq
   %a = sub i64 0, %y
   %b = shl i64 %a, %n
   %c = add i64 %x, %b

diff --git a/llvm/test/CodeGen/X86/neg_fp.ll b/llvm/test/CodeGen/X86/neg_fp.ll
@@ -1,10 +1,22 @@
-; RUN: llc < %s -mtriple=i686-- -mattr=+sse4.1 -o %t
-; RUN: grep xorps %t | count 1
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- -mattr=+sse4.1 | FileCheck %s
 
 ; Test that when we don't -enable-unsafe-fp-math, we don't do the optimization
 ; -0 - (A - B) to (B - A) because A==B, -0 != 0
 
 define float @negfp(float %a, float %b) {
+; CHECK-LABEL: negfp:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushl %eax
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-NEXT:    subss {{[0-9]+}}(%esp), %xmm0
+; CHECK-NEXT:    xorps {{\.LCPI.*}}, %xmm0
+; CHECK-NEXT:    movss %xmm0, (%esp)
+; CHECK-NEXT:    flds (%esp)
+; CHECK-NEXT:    popl %eax
+; CHECK-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-NEXT:    retl
 entry:
 	%sub = fsub float %a, %b		; <float> [#uses=1]
 	%neg = fsub float -0.000000e+00, %sub		; <float> [#uses=1]

diff --git a/llvm/test/CodeGen/X86/negate-add-zero.ll b/llvm/test/CodeGen/X86/negate-add-zero.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -enable-unsafe-fp-math | not grep xor
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -enable-unsafe-fp-math | FileCheck %s
 ; PR3374
 
 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
@@ -824,6 +825,52 @@ declare void @_ZN11MatrixTools9transposeI11FixedMatrixIdLi6ELi6ELi0ELi0EEEENT_13
 declare void @_ZN21HNodeTranslateRotate311toCartesianEv(%struct.HNodeTranslateRotate3*)
 
 define linkonce void @_ZN21HNodeTranslateRotate36setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE(%struct.HNodeTranslateRotate3* %this, %"struct.CDSVector<double,0,CDS::DefaultAlloc>"* %velv) {
+; CHECK-LABEL: _ZN21HNodeTranslateRotate36setVelERK9CDSVectorIdLi1EN3CDS12DefaultAllocEE:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    fldl 0
+; CHECK-NEXT:    fldl 3184(%ecx)
+; CHECK-NEXT:    fld %st(1)
+; CHECK-NEXT:    fmull 3176(%ecx)
+; CHECK-NEXT:    fldz
+; CHECK-NEXT:    fld %st(1)
+; CHECK-NEXT:    fadd %st(1), %st
+; CHECK-NEXT:    fld %st(3)
+; CHECK-NEXT:    fmul %st(5), %st
+; CHECK-NEXT:    fadd %st(2), %st
+; CHECK-NEXT:    fxch %st(5)
+; CHECK-NEXT:    fmul %st, %st(0)
+; CHECK-NEXT:    fadd %st, %st(5)
+; CHECK-NEXT:    fsubr %st, %st(5)
+; CHECK-NEXT:    fxch %st(4)
+; CHECK-NEXT:    fmull -8
+; CHECK-NEXT:    fxch %st(5)
+; CHECK-NEXT:    fstl 8
+; CHECK-NEXT:    fxch %st(2)
+; CHECK-NEXT:    fsubp %st, %st(5)
+; CHECK-NEXT:    fxch %st(4)
+; CHECK-NEXT:    fsubp %st, %st(2)
+; CHECK-NEXT:    fxch %st(1)
+; CHECK-NEXT:    fadd %st(2), %st
+; CHECK-NEXT:    faddp %st, %st(2)
+; CHECK-NEXT:    fxch %st(1)
+; CHECK-NEXT:    fstl 16
+; CHECK-NEXT:    fxch %st(2)
+; CHECK-NEXT:    fadd %st, %st(0)
+; CHECK-NEXT:    fxch %st(1)
+; CHECK-NEXT:    fadd %st, %st(0)
+; CHECK-NEXT:    fxch %st(2)
+; CHECK-NEXT:    fadd %st, %st(0)
+; CHECK-NEXT:    fxch %st(1)
+; CHECK-NEXT:    fstpl 2056(%ecx)
+; CHECK-NEXT:    fxch %st(1)
+; CHECK-NEXT:    fstpl 2064(%ecx)
+; CHECK-NEXT:    fstpl 2072(%ecx)
+; CHECK-NEXT:    movl %eax, 0
+; CHECK-NEXT:    movl $4, 4
+; CHECK-NEXT:    movl $3, 8
+; CHECK-NEXT:    ud2
 	%1 = getelementptr double, double* null, i32 -1		; <double*> [#uses=1]
 	%2 = load double, double* %1, align 8		; <double> [#uses=1]
 	%3 = load double, double* null, align 8		; <double> [#uses=2]

diff --git a/llvm/test/CodeGen/X86/negative-stride-fptosi-user.ll b/llvm/test/CodeGen/X86/negative-stride-fptosi-user.ll
@@ -1,11 +1,36 @@
-; RUN: llc < %s -mtriple=x86_64-- | grep cvtsi2sd
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s
 
 ; LSR previously eliminated the sitofp by introducing an induction
 ; variable which stepped by a bogus ((double)UINT32_C(-1)). It's theoretically
 ; possible to eliminate the sitofp using a proper -1.0 step though; this
 ; test should be changed if that is done.
 
 define void @foo(i32 %N) nounwind {
+; CHECK-LABEL: foo:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rbp
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    pushq %rax
+; CHECK-NEXT:    testl %edi, %edi
+; CHECK-NEXT:    jns .LBB0_3
+; CHECK-NEXT:  # %bb.1: # %bb.preheader
+; CHECK-NEXT:    movl %edi, %ebx
+; CHECK-NEXT:    xorl %ebp, %ebp
+; CHECK-NEXT:    .p2align 4, 0x90
+; CHECK-NEXT:  .LBB0_2: # %bb
+; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
+; CHECK-NEXT:    xorps %xmm0, %xmm0
+; CHECK-NEXT:    cvtsi2sd %ebp, %xmm0
+; CHECK-NEXT:    callq bar
+; CHECK-NEXT:    decl %ebp
+; CHECK-NEXT:    cmpl %ebp, %ebx
+; CHECK-NEXT:    jne .LBB0_2
+; CHECK-NEXT:  .LBB0_3: # %return
+; CHECK-NEXT:    addq $8, %rsp
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    popq %rbp
+; CHECK-NEXT:    retq
 entry:
   %0 = icmp slt i32 %N, 0                         ; <i1> [#uses=1]
   br i1 %0, label %bb, label %return

diff --git a/llvm/test/CodeGen/X86/nobt.ll b/llvm/test/CodeGen/X86/nobt.ll
@@ -1,9 +1,19 @@
-; RUN: llc < %s -mtriple=i686-- | not grep btl
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 
 ; This tests some cases where BT must not be generated.  See also bt.ll.
 ; Fixes 20040709-[12].c in gcc testsuite.
 
 define void @test2(i32 %x, i32 %n) nounwind {
+; CHECK-LABEL: test2:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    testb %al, %al
+; CHECK-NEXT:    jne .LBB0_2
+; CHECK-NEXT:  # %bb.1: # %bb
+; CHECK-NEXT:    calll foo
+; CHECK-NEXT:  .LBB0_2: # %UnifiedReturnBlock
+; CHECK-NEXT:    retl
 entry:
         %tmp1 = and i32 %x, 1
         %tmp2 = urem i32 %tmp1, 15
@@ -20,6 +30,15 @@ UnifiedReturnBlock:		; preds = %entry
 }
 
 define void @test3(i32 %x, i32 %n) nounwind {
+; CHECK-LABEL: test3:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    testb %al, %al
+; CHECK-NEXT:    jne .LBB1_2
+; CHECK-NEXT:  # %bb.1: # %bb
+; CHECK-NEXT:    calll foo
+; CHECK-NEXT:  .LBB1_2: # %UnifiedReturnBlock
+; CHECK-NEXT:    retl
 entry:
         %tmp1 = and i32 %x, 1
         %tmp2 = urem i32 %tmp1, 15
@@ -36,6 +55,15 @@ UnifiedReturnBlock:		; preds = %entry
 }
 
 define void @test4(i32 %x, i32 %n) nounwind {
+; CHECK-LABEL: test4:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movb $1, %al
+; CHECK-NEXT:    testb %al, %al
+; CHECK-NEXT:    jne .LBB2_2
+; CHECK-NEXT:  # %bb.1: # %bb
+; CHECK-NEXT:    calll foo
+; CHECK-NEXT:  .LBB2_2: # %UnifiedReturnBlock
+; CHECK-NEXT:    retl
 entry:
         %tmp1 = and i32 %x, 1
         %tmp2 = urem i32 %tmp1, 15
@@ -52,6 +80,15 @@ UnifiedReturnBlock:		; preds = %entry
 }
 
 define void @test5(i32 %x, i32 %n) nounwind {
+; CHECK-LABEL: test5:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movb $1, %al
+; CHECK-NEXT:    testb %al, %al
+; CHECK-NEXT:    jne .LBB3_2
+; CHECK-NEXT:  # %bb.1: # %bb
+; CHECK-NEXT:    calll foo
+; CHECK-NEXT:  .LBB3_2: # %UnifiedReturnBlock
+; CHECK-NEXT:    retl
 entry:
         %tmp1 = and i32 %x, 1
         %tmp2 = urem i32 %tmp1, 15