120 changes: 60 additions & 60 deletions llvm/test/CodeGen/RISCV/rvv/vmfle-rv64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,12 +31,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f16(
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f16(
Expand Down Expand Up @@ -83,12 +83,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f16(
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f16(
Expand Down Expand Up @@ -135,12 +135,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f16(
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f16(
Expand Down Expand Up @@ -187,12 +187,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f16(
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu
; CHECK-NEXT: vmfle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmfle.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f16(
Expand Down Expand Up @@ -239,12 +239,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfle.mask.nxv16f16(
define <vscale x 16 x i1> @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu
; CHECK-NEXT: vmfle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmfle.vv v25, v8, v12
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfle.nxv16f16(
Expand Down Expand Up @@ -291,12 +291,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f32(
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f32(
Expand Down Expand Up @@ -343,12 +343,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f32(
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f32(
Expand Down Expand Up @@ -395,12 +395,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f32(
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu
; CHECK-NEXT: vmfle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmfle.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f32(
Expand Down Expand Up @@ -447,12 +447,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfle.mask.nxv8f32(
define <vscale x 8 x i1> @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu
; CHECK-NEXT: vmfle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmfle.vv v25, v8, v12
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfle.nxv8f32(
Expand Down Expand Up @@ -499,12 +499,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfle.mask.nxv1f64(
define <vscale x 1 x i1> @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmfle.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfle.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfle.nxv1f64(
Expand Down Expand Up @@ -551,12 +551,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfle.mask.nxv2f64(
define <vscale x 2 x i1> @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmfle.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmfle.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfle.nxv2f64(
Expand Down Expand Up @@ -603,12 +603,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfle.mask.nxv4f64(
define <vscale x 4 x i1> @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmfle.vv v0, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmfle.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmfle.vv v25, v8, v12
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfle.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfle.nxv4f64(
Expand Down Expand Up @@ -658,7 +658,7 @@ define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f16_f16(<vscale x 1 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -707,7 +707,7 @@ define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f16_f16(<vscale x 2 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -756,7 +756,7 @@ define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f16_f16(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -805,7 +805,7 @@ define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f16_f16(<vscale x 8 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -854,7 +854,7 @@ define <vscale x 16 x i1> @intrinsic_vmfle_mask_vf_nxv16f16_f16(<vscale x 16 x i
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -903,7 +903,7 @@ define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f32_f32(<vscale x 1 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -952,7 +952,7 @@ define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f32_f32(<vscale x 2 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1001,7 +1001,7 @@ define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f32_f32(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1050,7 +1050,7 @@ define <vscale x 8 x i1> @intrinsic_vmfle_mask_vf_nxv8f32_f32(<vscale x 8 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1099,7 +1099,7 @@ define <vscale x 1 x i1> @intrinsic_vmfle_mask_vf_nxv1f64_f64(<vscale x 1 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1148,7 +1148,7 @@ define <vscale x 2 x i1> @intrinsic_vmfle_mask_vf_nxv2f64_f64(<vscale x 2 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1197,7 +1197,7 @@ define <vscale x 4 x i1> @intrinsic_vmfle_mask_vf_nxv4f64_f64(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfle.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down
120 changes: 60 additions & 60 deletions llvm/test/CodeGen/RISCV/rvv/vmflt-rv32.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,12 +31,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16(
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
Expand Down Expand Up @@ -83,12 +83,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16(
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
Expand Down Expand Up @@ -135,12 +135,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16(
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
Expand Down Expand Up @@ -187,12 +187,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16(
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu
; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
Expand Down Expand Up @@ -239,12 +239,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16(
define <vscale x 16 x i1> @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu
; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v12
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
Expand Down Expand Up @@ -291,12 +291,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
Expand Down Expand Up @@ -343,12 +343,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32(
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
Expand Down Expand Up @@ -395,12 +395,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32(
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu
; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
Expand Down Expand Up @@ -447,12 +447,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32(
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu
; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v12
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
Expand Down Expand Up @@ -499,12 +499,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64(
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
Expand Down Expand Up @@ -551,12 +551,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64(
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
Expand Down Expand Up @@ -603,12 +603,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64(
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v12
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
Expand Down Expand Up @@ -658,7 +658,7 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -707,7 +707,7 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -756,7 +756,7 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -805,7 +805,7 @@ define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -854,7 +854,7 @@ define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -903,7 +903,7 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -952,7 +952,7 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1001,7 +1001,7 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1050,7 +1050,7 @@ define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1106,7 +1106,7 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f64_f64(<vscale x 1 x i1>
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m1,tu,mu
; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1163,7 +1163,7 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f64_f64(<vscale x 2 x i1>
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m2,tu,mu
; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1220,7 +1220,7 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f64_f64(<vscale x 4 x i1>
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m4,tu,mu
; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down
120 changes: 60 additions & 60 deletions llvm/test/CodeGen/RISCV/rvv/vmflt-rv64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,12 +31,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f16(
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f16(
Expand Down Expand Up @@ -83,12 +83,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f16(
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f16(
Expand Down Expand Up @@ -135,12 +135,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f16(
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f16(
Expand Down Expand Up @@ -187,12 +187,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f16(
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu
; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f16(
Expand Down Expand Up @@ -239,12 +239,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmflt.mask.nxv16f16(
define <vscale x 16 x i1> @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu
; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v12
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmflt.nxv16f16(
Expand Down Expand Up @@ -291,12 +291,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f32(
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f32(
Expand Down Expand Up @@ -343,12 +343,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f32(
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f32(
Expand Down Expand Up @@ -395,12 +395,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f32(
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu
; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f32(
Expand Down Expand Up @@ -447,12 +447,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmflt.mask.nxv8f32(
define <vscale x 8 x i1> @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu
; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v12
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmflt.nxv8f32(
Expand Down Expand Up @@ -499,12 +499,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmflt.mask.nxv1f64(
define <vscale x 1 x i1> @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmflt.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmflt.nxv1f64(
Expand Down Expand Up @@ -551,12 +551,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmflt.mask.nxv2f64(
define <vscale x 2 x i1> @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmflt.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmflt.nxv2f64(
Expand Down Expand Up @@ -603,12 +603,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmflt.mask.nxv4f64(
define <vscale x 4 x i1> @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmflt.vv v0, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmflt.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmflt.vv v25, v8, v12
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmflt.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmflt.nxv4f64(
Expand Down Expand Up @@ -658,7 +658,7 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f16_f16(<vscale x 1 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -707,7 +707,7 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f16_f16(<vscale x 2 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -756,7 +756,7 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f16_f16(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -805,7 +805,7 @@ define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f16_f16(<vscale x 8 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -854,7 +854,7 @@ define <vscale x 16 x i1> @intrinsic_vmflt_mask_vf_nxv16f16_f16(<vscale x 16 x i
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -903,7 +903,7 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f32_f32(<vscale x 1 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -952,7 +952,7 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f32_f32(<vscale x 2 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1001,7 +1001,7 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f32_f32(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1050,7 +1050,7 @@ define <vscale x 8 x i1> @intrinsic_vmflt_mask_vf_nxv8f32_f32(<vscale x 8 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1099,7 +1099,7 @@ define <vscale x 1 x i1> @intrinsic_vmflt_mask_vf_nxv1f64_f64(<vscale x 1 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1148,7 +1148,7 @@ define <vscale x 2 x i1> @intrinsic_vmflt_mask_vf_nxv2f64_f64(<vscale x 2 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1197,7 +1197,7 @@ define <vscale x 4 x i1> @intrinsic_vmflt_mask_vf_nxv4f64_f64(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmflt.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down
120 changes: 60 additions & 60 deletions llvm/test/CodeGen/RISCV/rvv/vmfne-rv32.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,12 +31,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16(
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
Expand Down Expand Up @@ -83,12 +83,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16(
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
Expand Down Expand Up @@ -135,12 +135,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16(
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
Expand Down Expand Up @@ -187,12 +187,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16(
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu
; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
Expand Down Expand Up @@ -239,12 +239,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16(
define <vscale x 16 x i1> @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu
; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v12
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
Expand Down Expand Up @@ -291,12 +291,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32(
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
Expand Down Expand Up @@ -343,12 +343,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32(
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
Expand Down Expand Up @@ -395,12 +395,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32(
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu
; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
Expand Down Expand Up @@ -447,12 +447,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32(
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu
; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v12
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
Expand Down Expand Up @@ -499,12 +499,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64(
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
Expand Down Expand Up @@ -551,12 +551,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64(
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
Expand Down Expand Up @@ -603,12 +603,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64(
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i32 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v12
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
Expand Down Expand Up @@ -658,7 +658,7 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -707,7 +707,7 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -756,7 +756,7 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -805,7 +805,7 @@ define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -854,7 +854,7 @@ define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -903,7 +903,7 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -952,7 +952,7 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1001,7 +1001,7 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1050,7 +1050,7 @@ define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1106,7 +1106,7 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f64_f64(<vscale x 1 x i1>
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m1,tu,mu
; CHECK-NEXT: vsetvli zero, a2, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1163,7 +1163,7 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f64_f64(<vscale x 2 x i1>
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m2,tu,mu
; CHECK-NEXT: vsetvli zero, a2, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1220,7 +1220,7 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f64_f64(<vscale x 4 x i1>
; CHECK-NEXT: sw a1, 12(sp)
; CHECK-NEXT: fld ft0, 8(sp)
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a2, e64,m4,tu,mu
; CHECK-NEXT: vsetvli zero, a2, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down
120 changes: 60 additions & 60 deletions llvm/test/CodeGen/RISCV/rvv/vmfne-rv64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,12 +31,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f16(
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16(<vscale x 1 x i1> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf4,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,tu,mu
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f16(
Expand Down Expand Up @@ -83,12 +83,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f16(
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16(<vscale x 2 x i1> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,mf2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,tu,mu
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f16(
Expand Down Expand Up @@ -135,12 +135,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f16(
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16(<vscale x 4 x i1> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m1,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e16,m1,tu,mu
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f16(
Expand Down Expand Up @@ -187,12 +187,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f16(
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16(<vscale x 8 x i1> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e16,m2,tu,mu
; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f16(
Expand Down Expand Up @@ -239,12 +239,12 @@ declare <vscale x 16 x i1> @llvm.riscv.vmfne.mask.nxv16f16(
define <vscale x 16 x i1> @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16(<vscale x 16 x i1> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x half> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e16,m4,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e16,m4,tu,mu
; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v12
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 16 x i1> @llvm.riscv.vmfne.nxv16f16(
Expand Down Expand Up @@ -291,12 +291,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f32(
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32(<vscale x 1 x i1> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,mf2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,tu,mu
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f32(
Expand Down Expand Up @@ -343,12 +343,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f32(
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32(<vscale x 2 x i1> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m1,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e32,m1,tu,mu
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f32(
Expand Down Expand Up @@ -395,12 +395,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f32(
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32(<vscale x 4 x i1> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e32,m2,tu,mu
; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f32(
Expand Down Expand Up @@ -447,12 +447,12 @@ declare <vscale x 8 x i1> @llvm.riscv.vmfne.mask.nxv8f32(
define <vscale x 8 x i1> @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32(<vscale x 8 x i1> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x float> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e32,m4,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e32,m4,tu,mu
; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v12
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 8 x i1> @llvm.riscv.vmfne.nxv8f32(
Expand Down Expand Up @@ -499,12 +499,12 @@ declare <vscale x 1 x i1> @llvm.riscv.vmfne.mask.nxv1f64(
define <vscale x 1 x i1> @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64(<vscale x 1 x i1> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m1,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v9
; CHECK-NEXT: vsetvli zero, zero, e64,m1,tu,mu
; CHECK-NEXT: vmfne.vv v25, v9, v10, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v9
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v9, v10, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 1 x i1> @llvm.riscv.vmfne.nxv1f64(
Expand Down Expand Up @@ -551,12 +551,12 @@ declare <vscale x 2 x i1> @llvm.riscv.vmfne.mask.nxv2f64(
define <vscale x 2 x i1> @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64(<vscale x 2 x i1> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m2,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v10
; CHECK-NEXT: vsetvli zero, zero, e64,m2,tu,mu
; CHECK-NEXT: vmfne.vv v25, v10, v12, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v10
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v10, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 2 x i1> @llvm.riscv.vmfne.nxv2f64(
Expand Down Expand Up @@ -603,12 +603,12 @@ declare <vscale x 4 x i1> @llvm.riscv.vmfne.mask.nxv4f64(
define <vscale x 4 x i1> @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64(<vscale x 4 x i1> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x double> %3, i64 %4) nounwind {
; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: vsetvli zero, a0, e64,m4,ta,mu
; CHECK-NEXT: vmfne.vv v0, v8, v12
; CHECK-NEXT: vsetvli zero, zero, e64,m4,tu,mu
; CHECK-NEXT: vmfne.vv v25, v12, v16, v0.t
; CHECK-NEXT: vmfne.vv v25, v8, v12
; CHECK-NEXT: vmv1r.v v26, v0
; CHECK-NEXT: vmv1r.v v0, v25
; CHECK-NEXT: vmfne.vv v26, v12, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v26
; CHECK-NEXT: ret
entry:
%mask = call <vscale x 4 x i1> @llvm.riscv.vmfne.nxv4f64(
Expand Down Expand Up @@ -658,7 +658,7 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f16_f16(<vscale x 1 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,mf4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -707,7 +707,7 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f16_f16(<vscale x 2 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -756,7 +756,7 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f16_f16(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m1,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -805,7 +805,7 @@ define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f16_f16(<vscale x 8 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -854,7 +854,7 @@ define <vscale x 16 x i1> @intrinsic_vmfne_mask_vf_nxv16f16_f16(<vscale x 16 x i
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.h.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e16,m4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e16,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -903,7 +903,7 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f32_f32(<vscale x 1 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,mf2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -952,7 +952,7 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f32_f32(<vscale x 2 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m1,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1001,7 +1001,7 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f32_f32(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1050,7 +1050,7 @@ define <vscale x 8 x i1> @intrinsic_vmfne_mask_vf_nxv8f32_f32(<vscale x 8 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.w.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e32,m4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e32,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1099,7 +1099,7 @@ define <vscale x 1 x i1> @intrinsic_vmfne_mask_vf_nxv1f64_f64(<vscale x 1 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m1,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e64,m1,ta,mu
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1148,7 +1148,7 @@ define <vscale x 2 x i1> @intrinsic_vmfne_mask_vf_nxv2f64_f64(<vscale x 2 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m2,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e64,m2,ta,mu
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down Expand Up @@ -1197,7 +1197,7 @@ define <vscale x 4 x i1> @intrinsic_vmfne_mask_vf_nxv4f64_f64(<vscale x 4 x i1>
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vmv1r.v v25, v0
; CHECK-NEXT: fmv.d.x ft0, a0
; CHECK-NEXT: vsetvli zero, a1, e64,m4,tu,mu
; CHECK-NEXT: vsetvli zero, a1, e64,m4,ta,mu
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vmfne.vf v25, v8, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v25
Expand Down
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