70 changes: 35 additions & 35 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ declare <1 x i8> @llvm.masked.gather.v1i8.v1p0i8(<1 x i8*>, i32, <1 x i1>, <1 x
define <1 x i8> @mgather_v1i8(<1 x i8*> %ptrs, <1 x i1> %m, <1 x i8> %passthru) {
; RV32-LABEL: mgather_v1i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 1, e8,mf4,tu,mu
; RV32-NEXT: vsetivli a0, 1, e8,mf8,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
Expand All @@ -29,7 +29,7 @@ declare <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*>, i32, <2 x i1>, <2 x
define <2 x i8> @mgather_v2i8(<2 x i8*> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {
; RV32-LABEL: mgather_v2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e8,mf4,tu,mu
; RV32-NEXT: vsetivli a0, 2, e8,mf8,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
Expand All @@ -47,17 +47,17 @@ define <2 x i8> @mgather_v2i8(<2 x i8*> %ptrs, <2 x i1> %m, <2 x i8> %passthru)
define <2 x i16> @mgather_v2i8_sextload_v2i16(<2 x i8*> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {
; RV32-LABEL: mgather_v2i8_sextload_v2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e8,mf4,tu,mu
; RV32-NEXT: vsetivli a0, 2, e8,mf8,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; RV32-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; RV32-NEXT: vsext.vf2 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_v2i8_sextload_v2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli a0, 2, e8,mf8,tu,mu
; RV64-NEXT: vloxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; RV64-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; RV64-NEXT: vsext.vf2 v8, v9
; RV64-NEXT: ret
%v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)
Expand All @@ -68,17 +68,17 @@ define <2 x i16> @mgather_v2i8_sextload_v2i16(<2 x i8*> %ptrs, <2 x i1> %m, <2 x
define <2 x i16> @mgather_v2i8_zextload_v2i16(<2 x i8*> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {
; RV32-LABEL: mgather_v2i8_zextload_v2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e8,mf4,tu,mu
; RV32-NEXT: vsetivli a0, 2, e8,mf8,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; RV32-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; RV32-NEXT: vzext.vf2 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_v2i8_zextload_v2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli a0, 2, e8,mf8,tu,mu
; RV64-NEXT: vloxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; RV64-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; RV64-NEXT: vzext.vf2 v8, v9
; RV64-NEXT: ret
%v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)
Expand All @@ -89,17 +89,17 @@ define <2 x i16> @mgather_v2i8_zextload_v2i16(<2 x i8*> %ptrs, <2 x i1> %m, <2 x
define <2 x i32> @mgather_v2i8_sextload_v2i32(<2 x i8*> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {
; RV32-LABEL: mgather_v2i8_sextload_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e8,mf4,tu,mu
; RV32-NEXT: vsetivli a0, 2, e8,mf8,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; RV32-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; RV32-NEXT: vsext.vf4 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_v2i8_sextload_v2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli a0, 2, e8,mf8,tu,mu
; RV64-NEXT: vloxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; RV64-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; RV64-NEXT: vsext.vf4 v8, v9
; RV64-NEXT: ret
%v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)
Expand All @@ -110,17 +110,17 @@ define <2 x i32> @mgather_v2i8_sextload_v2i32(<2 x i8*> %ptrs, <2 x i1> %m, <2 x
define <2 x i32> @mgather_v2i8_zextload_v2i32(<2 x i8*> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {
; RV32-LABEL: mgather_v2i8_zextload_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e8,mf4,tu,mu
; RV32-NEXT: vsetivli a0, 2, e8,mf8,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; RV32-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; RV32-NEXT: vzext.vf4 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_v2i8_zextload_v2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli a0, 2, e8,mf8,tu,mu
; RV64-NEXT: vloxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; RV64-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; RV64-NEXT: vzext.vf4 v8, v9
; RV64-NEXT: ret
%v = call <2 x i8> @llvm.masked.gather.v2i8.v2p0i8(<2 x i8*> %ptrs, i32 1, <2 x i1> %m, <2 x i8> %passthru)
Expand All @@ -131,7 +131,7 @@ define <2 x i32> @mgather_v2i8_zextload_v2i32(<2 x i8*> %ptrs, <2 x i1> %m, <2 x
define <2 x i64> @mgather_v2i8_sextload_v2i64(<2 x i8*> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {
; RV32-LABEL: mgather_v2i8_sextload_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e8,mf4,tu,mu
; RV32-NEXT: vsetivli a0, 2, e8,mf8,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli a0, 2, e64,m1,ta,mu
; RV32-NEXT: vsext.vf8 v8, v9
Expand All @@ -152,7 +152,7 @@ define <2 x i64> @mgather_v2i8_sextload_v2i64(<2 x i8*> %ptrs, <2 x i1> %m, <2 x
define <2 x i64> @mgather_v2i8_zextload_v2i64(<2 x i8*> %ptrs, <2 x i1> %m, <2 x i8> %passthru) {
; RV32-LABEL: mgather_v2i8_zextload_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e8,mf4,tu,mu
; RV32-NEXT: vsetivli a0, 2, e8,mf8,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli a0, 2, e64,m1,ta,mu
; RV32-NEXT: vzext.vf8 v8, v9
Expand Down Expand Up @@ -272,7 +272,7 @@ declare <1 x i16> @llvm.masked.gather.v1i16.v1p0i16(<1 x i16*>, i32, <1 x i1>, <
define <1 x i16> @mgather_v1i16(<1 x i16*> %ptrs, <1 x i1> %m, <1 x i16> %passthru) {
; RV32-LABEL: mgather_v1i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 1, e16,mf2,tu,mu
; RV32-NEXT: vsetivli a0, 1, e16,mf4,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
Expand All @@ -292,7 +292,7 @@ declare <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*>, i32, <2 x i1>, <
define <2 x i16> @mgather_v2i16(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {
; RV32-LABEL: mgather_v2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e16,mf2,tu,mu
; RV32-NEXT: vsetivli a0, 2, e16,mf4,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
Expand All @@ -310,17 +310,17 @@ define <2 x i16> @mgather_v2i16(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16> %passth
define <2 x i32> @mgather_v2i16_sextload_v2i32(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {
; RV32-LABEL: mgather_v2i16_sextload_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e16,mf2,tu,mu
; RV32-NEXT: vsetivli a0, 2, e16,mf4,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; RV32-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; RV32-NEXT: vsext.vf2 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_v2i16_sextload_v2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli a0, 2, e16,mf4,tu,mu
; RV64-NEXT: vloxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; RV64-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; RV64-NEXT: vsext.vf2 v8, v9
; RV64-NEXT: ret
%v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru)
Expand All @@ -331,17 +331,17 @@ define <2 x i32> @mgather_v2i16_sextload_v2i32(<2 x i16*> %ptrs, <2 x i1> %m, <2
define <2 x i32> @mgather_v2i16_zextload_v2i32(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {
; RV32-LABEL: mgather_v2i16_zextload_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e16,mf2,tu,mu
; RV32-NEXT: vsetivli a0, 2, e16,mf4,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; RV32-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; RV32-NEXT: vzext.vf2 v8, v9
; RV32-NEXT: ret
;
; RV64-LABEL: mgather_v2i16_zextload_v2i32:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli a0, 2, e16,mf4,tu,mu
; RV64-NEXT: vloxei64.v v9, (zero), v8, v0.t
; RV64-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; RV64-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; RV64-NEXT: vzext.vf2 v8, v9
; RV64-NEXT: ret
%v = call <2 x i16> @llvm.masked.gather.v2i16.v2p0i16(<2 x i16*> %ptrs, i32 2, <2 x i1> %m, <2 x i16> %passthru)
Expand All @@ -352,7 +352,7 @@ define <2 x i32> @mgather_v2i16_zextload_v2i32(<2 x i16*> %ptrs, <2 x i1> %m, <2
define <2 x i64> @mgather_v2i16_sextload_v2i64(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {
; RV32-LABEL: mgather_v2i16_sextload_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e16,mf2,tu,mu
; RV32-NEXT: vsetivli a0, 2, e16,mf4,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli a0, 2, e64,m1,ta,mu
; RV32-NEXT: vsext.vf4 v8, v9
Expand All @@ -373,7 +373,7 @@ define <2 x i64> @mgather_v2i16_sextload_v2i64(<2 x i16*> %ptrs, <2 x i1> %m, <2
define <2 x i64> @mgather_v2i16_zextload_v2i64(<2 x i16*> %ptrs, <2 x i1> %m, <2 x i16> %passthru) {
; RV32-LABEL: mgather_v2i16_zextload_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e16,mf2,tu,mu
; RV32-NEXT: vsetivli a0, 2, e16,mf4,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli a0, 2, e64,m1,ta,mu
; RV32-NEXT: vzext.vf4 v8, v9
Expand Down Expand Up @@ -572,7 +572,7 @@ declare <1 x i32> @llvm.masked.gather.v1i32.v1p0i32(<1 x i32*>, i32, <1 x i1>, <
define <1 x i32> @mgather_v1i32(<1 x i32*> %ptrs, <1 x i1> %m, <1 x i32> %passthru) {
; RV32-LABEL: mgather_v1i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 1, e32,m1,tu,mu
; RV32-NEXT: vsetivli a0, 1, e32,mf2,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
Expand All @@ -592,7 +592,7 @@ declare <2 x i32> @llvm.masked.gather.v2i32.v2p0i32(<2 x i32*>, i32, <2 x i1>, <
define <2 x i32> @mgather_v2i32(<2 x i32*> %ptrs, <2 x i1> %m, <2 x i32> %passthru) {
; RV32-LABEL: mgather_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e32,m1,tu,mu
; RV32-NEXT: vsetivli a0, 2, e32,mf2,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
Expand All @@ -610,7 +610,7 @@ define <2 x i32> @mgather_v2i32(<2 x i32*> %ptrs, <2 x i1> %m, <2 x i32> %passth
define <2 x i64> @mgather_v2i32_sextload_v2i64(<2 x i32*> %ptrs, <2 x i1> %m, <2 x i32> %passthru) {
; RV32-LABEL: mgather_v2i32_sextload_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e32,m1,tu,mu
; RV32-NEXT: vsetivli a0, 2, e32,mf2,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli a0, 2, e64,m1,ta,mu
; RV32-NEXT: vsext.vf2 v8, v9
Expand All @@ -631,7 +631,7 @@ define <2 x i64> @mgather_v2i32_sextload_v2i64(<2 x i32*> %ptrs, <2 x i1> %m, <2
define <2 x i64> @mgather_v2i32_zextload_v2i64(<2 x i32*> %ptrs, <2 x i1> %m, <2 x i32> %passthru) {
; RV32-LABEL: mgather_v2i32_zextload_v2i64:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e32,m1,tu,mu
; RV32-NEXT: vsetivli a0, 2, e32,mf2,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vsetivli a0, 2, e64,m1,ta,mu
; RV32-NEXT: vzext.vf2 v8, v9
Expand Down Expand Up @@ -1271,7 +1271,7 @@ declare <1 x half> @llvm.masked.gather.v1f16.v1p0f16(<1 x half*>, i32, <1 x i1>,
define <1 x half> @mgather_v1f16(<1 x half*> %ptrs, <1 x i1> %m, <1 x half> %passthru) {
; RV32-LABEL: mgather_v1f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 1, e16,mf2,tu,mu
; RV32-NEXT: vsetivli a0, 1, e16,mf4,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
Expand All @@ -1291,7 +1291,7 @@ declare <2 x half> @llvm.masked.gather.v2f16.v2p0f16(<2 x half*>, i32, <2 x i1>,
define <2 x half> @mgather_v2f16(<2 x half*> %ptrs, <2 x i1> %m, <2 x half> %passthru) {
; RV32-LABEL: mgather_v2f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e16,mf2,tu,mu
; RV32-NEXT: vsetivli a0, 2, e16,mf4,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
Expand Down Expand Up @@ -1487,7 +1487,7 @@ declare <1 x float> @llvm.masked.gather.v1f32.v1p0f32(<1 x float*>, i32, <1 x i1
define <1 x float> @mgather_v1f32(<1 x float*> %ptrs, <1 x i1> %m, <1 x float> %passthru) {
; RV32-LABEL: mgather_v1f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 1, e32,m1,tu,mu
; RV32-NEXT: vsetivli a0, 1, e32,mf2,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
Expand All @@ -1507,7 +1507,7 @@ declare <2 x float> @llvm.masked.gather.v2f32.v2p0f32(<2 x float*>, i32, <2 x i1
define <2 x float> @mgather_v2f32(<2 x float*> %ptrs, <2 x i1> %m, <2 x float> %passthru) {
; RV32-LABEL: mgather_v2f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e32,m1,tu,mu
; RV32-NEXT: vsetivli a0, 2, e32,mf2,tu,mu
; RV32-NEXT: vloxei32.v v9, (zero), v8, v0.t
; RV32-NEXT: vmv1r.v v8, v9
; RV32-NEXT: ret
Expand Down Expand Up @@ -2185,7 +2185,7 @@ define <32 x i8> @mgather_baseidx_v32i8(i8* %base, <32 x i8> %idxs, <32 x i1> %m
; RV64-NEXT: vslidedown.vi v28, v8, 16
; RV64-NEXT: vsetivli a1, 16, e64,m8,ta,mu
; RV64-NEXT: vsext.vf8 v16, v28
; RV64-NEXT: vsetivli a1, 2, e8,m1,ta,mu
; RV64-NEXT: vsetivli a1, 2, e8,mf4,ta,mu
; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetivli a1, 16, e8,m1,tu,mu
; RV64-NEXT: vloxei64.v v26, (a0), v16, v0.t
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-fp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
define void @masked_load_v1f16(<1 x half>* %a, <1 x half>* %m_ptr, <1 x half>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 1, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 1, e16,mf4,ta,mu
; CHECK-NEXT: vle16.v v25, (a1)
; CHECK-NEXT: fmv.h.x ft0, zero
; CHECK-NEXT: vmfeq.vf v0, v25, ft0
Expand All @@ -23,7 +23,7 @@ declare <1 x half> @llvm.masked.load.v1f16(<1 x half>*, i32, <1 x i1>, <1 x half
define void @masked_load_v1f32(<1 x float>* %a, <1 x float>* %m_ptr, <1 x float>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 1, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 1, e32,mf2,ta,mu
; CHECK-NEXT: vle32.v v25, (a1)
; CHECK-NEXT: fmv.w.x ft0, zero
; CHECK-NEXT: vmfeq.vf v0, v25, ft0
Expand Down Expand Up @@ -69,7 +69,7 @@ declare <1 x double> @llvm.masked.load.v1f64(<1 x double>*, i32, <1 x i1>, <1 x
define void @masked_load_v2f16(<2 x half>* %a, <2 x half>* %m_ptr, <2 x half>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 2, e16,mf4,ta,mu
; CHECK-NEXT: vle16.v v25, (a1)
; CHECK-NEXT: fmv.h.x ft0, zero
; CHECK-NEXT: vmfeq.vf v0, v25, ft0
Expand All @@ -87,7 +87,7 @@ declare <2 x half> @llvm.masked.load.v2f16(<2 x half>*, i32, <2 x i1>, <2 x half
define void @masked_load_v2f32(<2 x float>* %a, <2 x float>* %m_ptr, <2 x float>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 2, e32,mf2,ta,mu
; CHECK-NEXT: vle32.v v25, (a1)
; CHECK-NEXT: fmv.w.x ft0, zero
; CHECK-NEXT: vmfeq.vf v0, v25, ft0
Expand Down Expand Up @@ -133,7 +133,7 @@ declare <2 x double> @llvm.masked.load.v2f64(<2 x double>*, i32, <2 x i1>, <2 x
define void @masked_load_v4f16(<4 x half>* %a, <4 x half>* %m_ptr, <4 x half>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 4, e16,mf2,ta,mu
; CHECK-NEXT: vle16.v v25, (a1)
; CHECK-NEXT: fmv.h.x ft0, zero
; CHECK-NEXT: vmfeq.vf v0, v25, ft0
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
define void @masked_load_v1i8(<1 x i8>* %a, <1 x i8>* %m_ptr, <1 x i8>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 1, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 1, e8,mf8,ta,mu
; CHECK-NEXT: vle8.v v25, (a1)
; CHECK-NEXT: vmseq.vi v0, v25, 0
; CHECK-NEXT: vle8.v v25, (a0), v0.t
Expand All @@ -22,7 +22,7 @@ declare <1 x i8> @llvm.masked.load.v1i8(<1 x i8>*, i32, <1 x i1>, <1 x i8>)
define void @masked_load_v1i16(<1 x i16>* %a, <1 x i16>* %m_ptr, <1 x i16>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 1, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 1, e16,mf4,ta,mu
; CHECK-NEXT: vle16.v v25, (a1)
; CHECK-NEXT: vmseq.vi v0, v25, 0
; CHECK-NEXT: vle16.v v25, (a0), v0.t
Expand All @@ -39,7 +39,7 @@ declare <1 x i16> @llvm.masked.load.v1i16(<1 x i16>*, i32, <1 x i1>, <1 x i16>)
define void @masked_load_v1i32(<1 x i32>* %a, <1 x i32>* %m_ptr, <1 x i32>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 1, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 1, e32,mf2,ta,mu
; CHECK-NEXT: vle32.v v25, (a1)
; CHECK-NEXT: vmseq.vi v0, v25, 0
; CHECK-NEXT: vle32.v v25, (a0), v0.t
Expand Down Expand Up @@ -73,7 +73,7 @@ declare <1 x i64> @llvm.masked.load.v1i64(<1 x i64>*, i32, <1 x i1>, <1 x i64>)
define void @masked_load_v2i8(<2 x i8>* %a, <2 x i8>* %m_ptr, <2 x i8>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 2, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 2, e8,mf8,ta,mu
; CHECK-NEXT: vle8.v v25, (a1)
; CHECK-NEXT: vmseq.vi v0, v25, 0
; CHECK-NEXT: vle8.v v25, (a0), v0.t
Expand All @@ -90,7 +90,7 @@ declare <2 x i8> @llvm.masked.load.v2i8(<2 x i8>*, i32, <2 x i1>, <2 x i8>)
define void @masked_load_v2i16(<2 x i16>* %a, <2 x i16>* %m_ptr, <2 x i16>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 2, e16,mf4,ta,mu
; CHECK-NEXT: vle16.v v25, (a1)
; CHECK-NEXT: vmseq.vi v0, v25, 0
; CHECK-NEXT: vle16.v v25, (a0), v0.t
Expand All @@ -107,7 +107,7 @@ declare <2 x i16> @llvm.masked.load.v2i16(<2 x i16>*, i32, <2 x i1>, <2 x i16>)
define void @masked_load_v2i32(<2 x i32>* %a, <2 x i32>* %m_ptr, <2 x i32>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 2, e32,mf2,ta,mu
; CHECK-NEXT: vle32.v v25, (a1)
; CHECK-NEXT: vmseq.vi v0, v25, 0
; CHECK-NEXT: vle32.v v25, (a0), v0.t
Expand Down Expand Up @@ -141,7 +141,7 @@ declare <2 x i64> @llvm.masked.load.v2i64(<2 x i64>*, i32, <2 x i1>, <2 x i64>)
define void @masked_load_v4i8(<4 x i8>* %a, <4 x i8>* %m_ptr, <4 x i8>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 4, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 4, e8,mf4,ta,mu
; CHECK-NEXT: vle8.v v25, (a1)
; CHECK-NEXT: vmseq.vi v0, v25, 0
; CHECK-NEXT: vle8.v v25, (a0), v0.t
Expand All @@ -158,7 +158,7 @@ declare <4 x i8> @llvm.masked.load.v4i8(<4 x i8>*, i32, <4 x i1>, <4 x i8>)
define void @masked_load_v4i16(<4 x i16>* %a, <4 x i16>* %m_ptr, <4 x i16>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 4, e16,mf2,ta,mu
; CHECK-NEXT: vle16.v v25, (a1)
; CHECK-NEXT: vmseq.vi v0, v25, 0
; CHECK-NEXT: vle16.v v25, (a0), v0.t
Expand Down Expand Up @@ -209,7 +209,7 @@ declare <4 x i64> @llvm.masked.load.v4i64(<4 x i64>*, i32, <4 x i1>, <4 x i64>)
define void @masked_load_v8i8(<8 x i8>* %a, <8 x i8>* %m_ptr, <8 x i8>* %res_ptr) nounwind {
; CHECK-LABEL: masked_load_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 8, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 8, e8,mf2,ta,mu
; CHECK-NEXT: vle8.v v25, (a1)
; CHECK-NEXT: vmseq.vi v0, v25, 0
; CHECK-NEXT: vle8.v v25, (a0), v0.t
Expand Down
45 changes: 19 additions & 26 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-scatter.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ declare void @llvm.masked.scatter.v1i8.v1p0i8(<1 x i8>, <1 x i8*>, i32, <1 x i1>
define void @mscatter_v1i8(<1 x i8> %val, <1 x i8*> %ptrs, <1 x i1> %m) {
; RV32-LABEL: mscatter_v1i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 1, e8,mf4,ta,mu
; RV32-NEXT: vsetivli a0, 1, e8,mf8,ta,mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
Expand All @@ -27,7 +27,7 @@ declare void @llvm.masked.scatter.v2i8.v2p0i8(<2 x i8>, <2 x i8*>, i32, <2 x i1>
define void @mscatter_v2i8(<2 x i8> %val, <2 x i8*> %ptrs, <2 x i1> %m) {
; RV32-LABEL: mscatter_v2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e8,mf4,ta,mu
; RV32-NEXT: vsetivli a0, 2, e8,mf8,ta,mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
Expand All @@ -43,17 +43,15 @@ define void @mscatter_v2i8(<2 x i8> %val, <2 x i8*> %ptrs, <2 x i1> %m) {
define void @mscatter_v2i16_truncstore_v2i8(<2 x i16> %val, <2 x i8*> %ptrs, <2 x i1> %m) {
; RV32-LABEL: mscatter_v2i16_truncstore_v2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e8,mf2,ta,mu
; RV32-NEXT: vsetivli a0, 2, e8,mf8,ta,mu
; RV32-NEXT: vnsrl.wi v25, v8, 0
; RV32-NEXT: vsetivli a0, 2, e8,mf4,ta,mu
; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_v2i16_truncstore_v2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli a0, 2, e8,mf2,ta,mu
; RV64-NEXT: vnsrl.wi v25, v8, 0
; RV64-NEXT: vsetivli a0, 2, e8,mf8,ta,mu
; RV64-NEXT: vnsrl.wi v25, v8, 0
; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i16> %val to <2 x i8>
Expand All @@ -64,20 +62,19 @@ define void @mscatter_v2i16_truncstore_v2i8(<2 x i16> %val, <2 x i8*> %ptrs, <2
define void @mscatter_v2i32_truncstore_v2i8(<2 x i32> %val, <2 x i8*> %ptrs, <2 x i1> %m) {
; RV32-LABEL: mscatter_v2i32_truncstore_v2i8:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e16,mf2,ta,mu
; RV32-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; RV32-NEXT: vnsrl.wi v25, v8, 0
; RV32-NEXT: vsetivli a0, 2, e8,mf4,ta,mu
; RV32-NEXT: vsetivli a0, 2, e8,mf8,ta,mu
; RV32-NEXT: vnsrl.wi v26, v25, 0
; RV32-NEXT: vsoxei32.v v26, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_v2i32_truncstore_v2i8:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli a0, 2, e16,mf2,ta,mu
; RV64-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; RV64-NEXT: vnsrl.wi v25, v8, 0
; RV64-NEXT: vsetivli a0, 2, e8,mf4,ta,mu
; RV64-NEXT: vnsrl.wi v26, v25, 0
; RV64-NEXT: vsetivli a0, 2, e8,mf8,ta,mu
; RV64-NEXT: vnsrl.wi v26, v25, 0
; RV64-NEXT: vsoxei64.v v26, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i32> %val to <2 x i8>
Expand All @@ -94,7 +91,6 @@ define void @mscatter_v2i64_truncstore_v2i8(<2 x i64> %val, <2 x i8*> %ptrs, <2
; RV32-NEXT: vnsrl.wi v26, v25, 0
; RV32-NEXT: vsetivli a0, 2, e8,mf8,ta,mu
; RV32-NEXT: vnsrl.wi v25, v26, 0
; RV32-NEXT: vsetivli a0, 2, e8,mf4,ta,mu
; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
; RV32-NEXT: ret
;
Expand Down Expand Up @@ -205,7 +201,7 @@ declare void @llvm.masked.scatter.v1i16.v1p0i16(<1 x i16>, <1 x i16*>, i32, <1 x
define void @mscatter_v1i16(<1 x i16> %val, <1 x i16*> %ptrs, <1 x i1> %m) {
; RV32-LABEL: mscatter_v1i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 1, e16,mf2,ta,mu
; RV32-NEXT: vsetivli a0, 1, e16,mf4,ta,mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
Expand All @@ -223,7 +219,7 @@ declare void @llvm.masked.scatter.v2i16.v2p0i16(<2 x i16>, <2 x i16*>, i32, <2 x
define void @mscatter_v2i16(<2 x i16> %val, <2 x i16*> %ptrs, <2 x i1> %m) {
; RV32-LABEL: mscatter_v2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e16,mf2,ta,mu
; RV32-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
Expand All @@ -239,16 +235,15 @@ define void @mscatter_v2i16(<2 x i16> %val, <2 x i16*> %ptrs, <2 x i1> %m) {
define void @mscatter_v2i32_truncstore_v2i16(<2 x i32> %val, <2 x i16*> %ptrs, <2 x i1> %m) {
; RV32-LABEL: mscatter_v2i32_truncstore_v2i16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e16,mf2,ta,mu
; RV32-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; RV32-NEXT: vnsrl.wi v25, v8, 0
; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
; RV32-NEXT: ret
;
; RV64-LABEL: mscatter_v2i32_truncstore_v2i16:
; RV64: # %bb.0:
; RV64-NEXT: vsetivli a0, 2, e16,mf2,ta,mu
; RV64-NEXT: vnsrl.wi v25, v8, 0
; RV64-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; RV64-NEXT: vnsrl.wi v25, v8, 0
; RV64-NEXT: vsoxei64.v v25, (zero), v9, v0.t
; RV64-NEXT: ret
%tval = trunc <2 x i32> %val to <2 x i16>
Expand All @@ -263,7 +258,6 @@ define void @mscatter_v2i64_truncstore_v2i16(<2 x i64> %val, <2 x i16*> %ptrs, <
; RV32-NEXT: vnsrl.wi v25, v8, 0
; RV32-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; RV32-NEXT: vnsrl.wi v26, v25, 0
; RV32-NEXT: vsetivli a0, 2, e16,mf2,ta,mu
; RV32-NEXT: vsoxei32.v v26, (zero), v9, v0.t
; RV32-NEXT: ret
;
Expand Down Expand Up @@ -445,7 +439,7 @@ declare void @llvm.masked.scatter.v1i32.v1p0i32(<1 x i32>, <1 x i32*>, i32, <1 x
define void @mscatter_v1i32(<1 x i32> %val, <1 x i32*> %ptrs, <1 x i1> %m) {
; RV32-LABEL: mscatter_v1i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 1, e32,m1,ta,mu
; RV32-NEXT: vsetivli a0, 1, e32,mf2,ta,mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
Expand All @@ -463,7 +457,7 @@ declare void @llvm.masked.scatter.v2i32.v2p0i32(<2 x i32>, <2 x i32*>, i32, <2 x
define void @mscatter_v2i32(<2 x i32> %val, <2 x i32*> %ptrs, <2 x i1> %m) {
; RV32-LABEL: mscatter_v2i32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; RV32-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
Expand All @@ -481,7 +475,6 @@ define void @mscatter_v2i64_truncstore_v2i32(<2 x i64> %val, <2 x i32*> %ptrs, <
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; RV32-NEXT: vnsrl.wi v25, v8, 0
; RV32-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; RV32-NEXT: vsoxei32.v v25, (zero), v9, v0.t
; RV32-NEXT: ret
;
Expand Down Expand Up @@ -1042,7 +1035,7 @@ declare void @llvm.masked.scatter.v1f16.v1p0f16(<1 x half>, <1 x half*>, i32, <1
define void @mscatter_v1f16(<1 x half> %val, <1 x half*> %ptrs, <1 x i1> %m) {
; RV32-LABEL: mscatter_v1f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 1, e16,mf2,ta,mu
; RV32-NEXT: vsetivli a0, 1, e16,mf4,ta,mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
Expand All @@ -1060,7 +1053,7 @@ declare void @llvm.masked.scatter.v2f16.v2p0f16(<2 x half>, <2 x half*>, i32, <2
define void @mscatter_v2f16(<2 x half> %val, <2 x half*> %ptrs, <2 x i1> %m) {
; RV32-LABEL: mscatter_v2f16:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e16,mf2,ta,mu
; RV32-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
Expand Down Expand Up @@ -1238,7 +1231,7 @@ declare void @llvm.masked.scatter.v1f32.v1p0f32(<1 x float>, <1 x float*>, i32,
define void @mscatter_v1f32(<1 x float> %val, <1 x float*> %ptrs, <1 x i1> %m) {
; RV32-LABEL: mscatter_v1f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 1, e32,m1,ta,mu
; RV32-NEXT: vsetivli a0, 1, e32,mf2,ta,mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
Expand All @@ -1256,7 +1249,7 @@ declare void @llvm.masked.scatter.v2f32.v2p0f32(<2 x float>, <2 x float*>, i32,
define void @mscatter_v2f32(<2 x float> %val, <2 x float*> %ptrs, <2 x i1> %m) {
; RV32-LABEL: mscatter_v2f32:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; RV32-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; RV32-NEXT: vsoxei32.v v8, (zero), v9, v0.t
; RV32-NEXT: ret
;
Expand Down Expand Up @@ -1856,7 +1849,7 @@ define void @mscatter_baseidx_v32i8(<32 x i8> %val, i8* %base, <32 x i8> %idxs,
; RV64-NEXT: vslidedown.vi v28, v10, 16
; RV64-NEXT: vsetivli a1, 16, e64,m8,ta,mu
; RV64-NEXT: vsext.vf8 v8, v28
; RV64-NEXT: vsetivli a1, 2, e8,m1,ta,mu
; RV64-NEXT: vsetivli a1, 2, e8,mf4,ta,mu
; RV64-NEXT: vslidedown.vi v0, v0, 2
; RV64-NEXT: vsetivli a1, 16, e8,m1,ta,mu
; RV64-NEXT: vsoxei64.v v26, (a0), v8, v0.t
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-fp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
define void @masked_store_v1f16(<1 x half>* %val_ptr, <1 x half>* %a, <1 x half>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 1, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 1, e16,mf4,ta,mu
; CHECK-NEXT: vle16.v v25, (a2)
; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero
Expand All @@ -23,7 +23,7 @@ declare void @llvm.masked.store.v1f16.p0v1f16(<1 x half>, <1 x half>*, i32, <1 x
define void @masked_store_v1f32(<1 x float>* %val_ptr, <1 x float>* %a, <1 x float>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 1, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 1, e32,mf2,ta,mu
; CHECK-NEXT: vle32.v v25, (a2)
; CHECK-NEXT: vle32.v v26, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero
Expand Down Expand Up @@ -69,7 +69,7 @@ declare void @llvm.masked.store.v1f64.p0v1f64(<1 x double>, <1 x double>*, i32,
define void @masked_store_v2f16(<2 x half>* %val_ptr, <2 x half>* %a, <2 x half>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 2, e16,mf4,ta,mu
; CHECK-NEXT: vle16.v v25, (a2)
; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero
Expand All @@ -87,7 +87,7 @@ declare void @llvm.masked.store.v2f16.p0v2f16(<2 x half>, <2 x half>*, i32, <2 x
define void @masked_store_v2f32(<2 x float>* %val_ptr, <2 x float>* %a, <2 x float>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 2, e32,mf2,ta,mu
; CHECK-NEXT: vle32.v v25, (a2)
; CHECK-NEXT: vle32.v v26, (a0)
; CHECK-NEXT: fmv.w.x ft0, zero
Expand Down Expand Up @@ -133,7 +133,7 @@ declare void @llvm.masked.store.v2f64.p0v2f64(<2 x double>, <2 x double>*, i32,
define void @masked_store_v4f16(<4 x half>* %val_ptr, <4 x half>* %a, <4 x half>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 4, e16,mf2,ta,mu
; CHECK-NEXT: vle16.v v25, (a2)
; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: fmv.h.x ft0, zero
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,7 +5,7 @@
define void @masked_store_v1i8(<1 x i8>* %val_ptr, <1 x i8>* %a, <1 x i8>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v1i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 1, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 1, e8,mf8,ta,mu
; CHECK-NEXT: vle8.v v25, (a2)
; CHECK-NEXT: vle8.v v26, (a0)
; CHECK-NEXT: vmseq.vi v0, v25, 0
Expand All @@ -22,7 +22,7 @@ declare void @llvm.masked.store.v1i8.p0v1i8(<1 x i8>, <1 x i8>*, i32, <1 x i1>)
define void @masked_store_v1i16(<1 x i16>* %val_ptr, <1 x i16>* %a, <1 x i16>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 1, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 1, e16,mf4,ta,mu
; CHECK-NEXT: vle16.v v25, (a2)
; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: vmseq.vi v0, v25, 0
Expand All @@ -39,7 +39,7 @@ declare void @llvm.masked.store.v1i16.p0v1i16(<1 x i16>, <1 x i16>*, i32, <1 x i
define void @masked_store_v1i32(<1 x i32>* %val_ptr, <1 x i32>* %a, <1 x i32>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 1, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 1, e32,mf2,ta,mu
; CHECK-NEXT: vle32.v v25, (a2)
; CHECK-NEXT: vle32.v v26, (a0)
; CHECK-NEXT: vmseq.vi v0, v25, 0
Expand Down Expand Up @@ -73,7 +73,7 @@ declare void @llvm.masked.store.v1i64.p0v1i64(<1 x i64>, <1 x i64>*, i32, <1 x i
define void @masked_store_v2i8(<2 x i8>* %val_ptr, <2 x i8>* %a, <2 x i8>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 2, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 2, e8,mf8,ta,mu
; CHECK-NEXT: vle8.v v25, (a2)
; CHECK-NEXT: vle8.v v26, (a0)
; CHECK-NEXT: vmseq.vi v0, v25, 0
Expand All @@ -90,7 +90,7 @@ declare void @llvm.masked.store.v2i8.p0v2i8(<2 x i8>, <2 x i8>*, i32, <2 x i1>)
define void @masked_store_v2i16(<2 x i16>* %val_ptr, <2 x i16>* %a, <2 x i16>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 2, e16,mf4,ta,mu
; CHECK-NEXT: vle16.v v25, (a2)
; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: vmseq.vi v0, v25, 0
Expand All @@ -107,7 +107,7 @@ declare void @llvm.masked.store.v2i16.p0v2i16(<2 x i16>, <2 x i16>*, i32, <2 x i
define void @masked_store_v2i32(<2 x i32>* %val_ptr, <2 x i32>* %a, <2 x i32>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 2, e32,mf2,ta,mu
; CHECK-NEXT: vle32.v v25, (a2)
; CHECK-NEXT: vle32.v v26, (a0)
; CHECK-NEXT: vmseq.vi v0, v25, 0
Expand Down Expand Up @@ -141,7 +141,7 @@ declare void @llvm.masked.store.v2i64.p0v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i
define void @masked_store_v4i8(<4 x i8>* %val_ptr, <4 x i8>* %a, <4 x i8>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 4, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 4, e8,mf4,ta,mu
; CHECK-NEXT: vle8.v v25, (a2)
; CHECK-NEXT: vle8.v v26, (a0)
; CHECK-NEXT: vmseq.vi v0, v25, 0
Expand All @@ -158,7 +158,7 @@ declare void @llvm.masked.store.v4i8.p0v4i8(<4 x i8>, <4 x i8>*, i32, <4 x i1>)
define void @masked_store_v4i16(<4 x i16>* %val_ptr, <4 x i16>* %a, <4 x i16>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 4, e16,mf2,ta,mu
; CHECK-NEXT: vle16.v v25, (a2)
; CHECK-NEXT: vle16.v v26, (a0)
; CHECK-NEXT: vmseq.vi v0, v25, 0
Expand Down Expand Up @@ -209,7 +209,7 @@ declare void @llvm.masked.store.v4i64.p0v4i64(<4 x i64>, <4 x i64>*, i32, <4 x i
define void @masked_store_v8i8(<8 x i8>* %val_ptr, <8 x i8>* %a, <8 x i8>* %m_ptr) nounwind {
; CHECK-LABEL: masked_store_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a3, 8, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a3, 8, e8,mf2,ta,mu
; CHECK-NEXT: vle8.v v25, (a2)
; CHECK-NEXT: vle8.v v26, (a0)
; CHECK-NEXT: vmseq.vi v0, v25, 0
Expand Down
94 changes: 56 additions & 38 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ declare half @llvm.vector.reduce.fadd.v1f16(half, <1 x half>)
define half @vreduce_fadd_v1f16(<1 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 1, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 1, e16,mf4,ta,mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vfmv.f.s ft0, v25
; CHECK-NEXT: fadd.h fa0, fa0, ft0
Expand All @@ -20,12 +20,13 @@ define half @vreduce_fadd_v1f16(<1 x half>* %x, half %s) {
define half @vreduce_ord_fadd_v1f16(<1 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v1f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 1, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 1, e16,mf4,ta,mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vsetivli a0, 1, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 1, e16,mf4,ta,mu
; CHECK-NEXT: vfredosum.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret
%v = load <1 x half>, <1 x half>* %x
Expand All @@ -38,12 +39,13 @@ declare half @llvm.vector.reduce.fadd.v2f16(half, <2 x half>)
define half @vreduce_fadd_v2f16(<2 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 2, e16,mf4,ta,mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; CHECK-NEXT: vfredsum.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.f.s ft0, v25
; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret
Expand All @@ -55,12 +57,13 @@ define half @vreduce_fadd_v2f16(<2 x half>* %x, half %s) {
define half @vreduce_ord_fadd_v2f16(<2 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 2, e16,mf4,ta,mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; CHECK-NEXT: vfredosum.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret
%v = load <2 x half>, <2 x half>* %x
Expand All @@ -73,12 +76,13 @@ declare half @llvm.vector.reduce.fadd.v4f16(half, <4 x half>)
define half @vreduce_fadd_v4f16(<4 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_fadd_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 4, e16,mf2,ta,mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: vfredsum.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.f.s ft0, v25
; CHECK-NEXT: fadd.h fa0, fa0, ft0
; CHECK-NEXT: ret
Expand All @@ -90,12 +94,13 @@ define half @vreduce_fadd_v4f16(<4 x half>* %x, half %s) {
define half @vreduce_ord_fadd_v4f16(<4 x half>* %x, half %s) {
; CHECK-LABEL: vreduce_ord_fadd_v4f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 4, e16,mf2,ta,mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: vfredosum.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
Expand Down Expand Up @@ -308,7 +313,7 @@ declare float @llvm.vector.reduce.fadd.v1f32(float, <1 x float>)
define float @vreduce_fadd_v1f32(<1 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_fadd_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 1, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 1, e32,mf2,ta,mu
; CHECK-NEXT: vle32.v v25, (a0)
; CHECK-NEXT: vfmv.f.s ft0, v25
; CHECK-NEXT: fadd.s fa0, fa0, ft0
Expand All @@ -321,12 +326,13 @@ define float @vreduce_fadd_v1f32(<1 x float>* %x, float %s) {
define float @vreduce_ord_fadd_v1f32(<1 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_v1f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 1, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 1, e32,mf2,ta,mu
; CHECK-NEXT: vle32.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vsetivli a0, 1, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 1, e32,mf2,ta,mu
; CHECK-NEXT: vfredosum.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e32,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret
%v = load <1 x float>, <1 x float>* %x
Expand All @@ -339,12 +345,13 @@ declare float @llvm.vector.reduce.fadd.v2f32(float, <2 x float>)
define float @vreduce_fadd_v2f32(<2 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_fadd_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 2, e32,mf2,ta,mu
; CHECK-NEXT: vle32.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vmv.v.i v26, 0
; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; CHECK-NEXT: vfredsum.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e32,m1,ta,mu
; CHECK-NEXT: vfmv.f.s ft0, v25
; CHECK-NEXT: fadd.s fa0, fa0, ft0
; CHECK-NEXT: ret
Expand All @@ -356,12 +363,13 @@ define float @vreduce_fadd_v2f32(<2 x float>* %x, float %s) {
define float @vreduce_ord_fadd_v2f32(<2 x float>* %x, float %s) {
; CHECK-LABEL: vreduce_ord_fadd_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a1, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 2, e32,mf2,ta,mu
; CHECK-NEXT: vle32.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v26, fa0
; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; CHECK-NEXT: vfredosum.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e32,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret
%v = load <2 x float>, <2 x float>* %x
Expand Down Expand Up @@ -799,12 +807,13 @@ define half @vreduce_fmin_v2f16(<2 x half>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI42_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI42_0)(a1)
; CHECK-NEXT: vsetivli a1, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 2, e16,mf4,ta,mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v26, ft0
; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; CHECK-NEXT: vfredmin.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret
%v = load <2 x half>, <2 x half>* %x
Expand All @@ -819,12 +828,13 @@ define half @vreduce_fmin_v4f16(<4 x half>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI43_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI43_0)(a1)
; CHECK-NEXT: vsetivli a1, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 4, e16,mf2,ta,mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v26, ft0
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: vfredmin.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
Expand All @@ -837,12 +847,13 @@ define half @vreduce_fmin_v4f16_nonans(<4 x half>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI44_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI44_0)(a1)
; CHECK-NEXT: vsetivli a1, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 4, e16,mf2,ta,mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v26, ft0
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: vfredmin.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
Expand All @@ -855,12 +866,13 @@ define half @vreduce_fmin_v4f16_nonans_noinfs(<4 x half>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI45_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI45_0)(a1)
; CHECK-NEXT: vsetivli a1, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 4, e16,mf2,ta,mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v26, ft0
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: vfredmin.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
Expand Down Expand Up @@ -900,12 +912,13 @@ define float @vreduce_fmin_v2f32(<2 x float>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI47_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI47_0)(a1)
; CHECK-NEXT: vsetivli a1, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 2, e32,mf2,ta,mu
; CHECK-NEXT: vle32.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v26, ft0
; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; CHECK-NEXT: vfredmin.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e32,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret
%v = load <2 x float>, <2 x float>* %x
Expand Down Expand Up @@ -1110,12 +1123,13 @@ define half @vreduce_fmax_v2f16(<2 x half>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI57_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI57_0)(a1)
; CHECK-NEXT: vsetivli a1, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 2, e16,mf4,ta,mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v26, ft0
; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; CHECK-NEXT: vfredmax.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret
%v = load <2 x half>, <2 x half>* %x
Expand All @@ -1130,12 +1144,13 @@ define half @vreduce_fmax_v4f16(<4 x half>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI58_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI58_0)(a1)
; CHECK-NEXT: vsetivli a1, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 4, e16,mf2,ta,mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v26, ft0
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: vfredmax.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
Expand All @@ -1148,12 +1163,13 @@ define half @vreduce_fmax_v4f16_nonans(<4 x half>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI59_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI59_0)(a1)
; CHECK-NEXT: vsetivli a1, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 4, e16,mf2,ta,mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v26, ft0
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: vfredmax.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
Expand All @@ -1166,12 +1182,13 @@ define half @vreduce_fmax_v4f16_nonans_noinfs(<4 x half>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI60_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI60_0)(a1)
; CHECK-NEXT: vsetivli a1, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 4, e16,mf2,ta,mu
; CHECK-NEXT: vle16.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v26, ft0
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: vfredmax.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret
%v = load <4 x half>, <4 x half>* %x
Expand Down Expand Up @@ -1211,12 +1228,13 @@ define float @vreduce_fmax_v2f32(<2 x float>* %x) {
; CHECK: # %bb.0:
; CHECK-NEXT: lui a1, %hi(.LCPI62_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI62_0)(a1)
; CHECK-NEXT: vsetivli a1, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 2, e32,mf2,ta,mu
; CHECK-NEXT: vle32.v v25, (a0)
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vfmv.v.f v26, ft0
; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; CHECK-NEXT: vfredmax.vs v25, v25, v26
; CHECK-NEXT: vsetvli zero, zero, e32,m1,ta,mu
; CHECK-NEXT: vfmv.f.s fa0, v25
; CHECK-NEXT: ret
%v = load <2 x float>, <2 x float>* %x
Expand Down
303 changes: 177 additions & 126 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
View file

Large diffs are not rendered by default.

40 changes: 20 additions & 20 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-fp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
define <2 x half> @select_v2f16(i1 zeroext %c, <2 x half> %a, <2 x half> %b) {
; CHECK-LABEL: select_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vsetvli zero, zero, e16,mf4,ta,mu
; CHECK-NEXT: vfmv.f.s ft1, v9
; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: vslidedown.vi v25, v9, 1
Expand All @@ -19,7 +19,7 @@ define <2 x half> @select_v2f16(i1 zeroext %c, <2 x half> %a, <2 x half> %b) {
; CHECK-NEXT: fmv.h ft0, ft1
; CHECK-NEXT: fmv.h ft2, ft3
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; CHECK-NEXT: vfmv.v.f v8, ft2
; CHECK-NEXT: vfmv.s.f v8, ft0
; CHECK-NEXT: ret
Expand All @@ -31,7 +31,7 @@ define <2 x half> @selectcc_v2f16(half %a, half %b, <2 x half> %c, <2 x half> %d
; CHECK-LABEL: selectcc_v2f16:
; CHECK: # %bb.0:
; CHECK-NEXT: feq.h a0, fa0, fa1
; CHECK-NEXT: vsetivli a1, 1, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 1, e16,mf4,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v9, 1
; CHECK-NEXT: vfmv.f.s ft1, v25
; CHECK-NEXT: vslidedown.vi v25, v8, 1
Expand All @@ -40,15 +40,15 @@ define <2 x half> @selectcc_v2f16(half %a, half %b, <2 x half> %c, <2 x half> %d
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h ft0, ft1
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: vsetivli a1, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 2, e16,mf4,ta,mu
; CHECK-NEXT: vfmv.v.f v25, ft0
; CHECK-NEXT: vfmv.f.s ft1, v9
; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: bnez a0, .LBB1_4
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: fmv.h ft0, ft1
; CHECK-NEXT: .LBB1_4:
; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; CHECK-NEXT: vfmv.s.f v25, ft0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
Expand All @@ -62,15 +62,15 @@ define <4 x half> @select_v4f16(i1 zeroext %c, <4 x half> %a, <4 x half> %b) {
; CHECK: # %bb.0:
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfmv.f.s ft1, v9
; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: bnez a0, .LBB2_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h ft0, ft1
; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: fsh ft0, 8(sp)
; CHECK-NEXT: vsetivli a1, 1, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 1, e16,mf2,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v9, 3
; CHECK-NEXT: vfmv.f.s ft0, v25
; CHECK-NEXT: vslidedown.vi v25, v8, 3
Expand All @@ -80,7 +80,7 @@ define <4 x half> @select_v4f16(i1 zeroext %c, <4 x half> %a, <4 x half> %b) {
; CHECK-NEXT: fmv.h ft1, ft0
; CHECK-NEXT: .LBB2_4:
; CHECK-NEXT: fsh ft1, 14(sp)
; CHECK-NEXT: vsetivli a1, 1, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 1, e16,mf2,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v9, 2
; CHECK-NEXT: vfmv.f.s ft0, v25
; CHECK-NEXT: vslidedown.vi v25, v8, 2
Expand All @@ -90,7 +90,7 @@ define <4 x half> @select_v4f16(i1 zeroext %c, <4 x half> %a, <4 x half> %b) {
; CHECK-NEXT: fmv.h ft1, ft0
; CHECK-NEXT: .LBB2_6:
; CHECK-NEXT: fsh ft1, 12(sp)
; CHECK-NEXT: vsetivli a1, 1, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 1, e16,mf2,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v9, 1
; CHECK-NEXT: vfmv.f.s ft0, v25
; CHECK-NEXT: vslidedown.vi v25, v8, 1
Expand All @@ -100,7 +100,7 @@ define <4 x half> @select_v4f16(i1 zeroext %c, <4 x half> %a, <4 x half> %b) {
; CHECK-NEXT: fmv.h ft1, ft0
; CHECK-NEXT: .LBB2_8:
; CHECK-NEXT: fsh ft1, 10(sp)
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi sp, sp, 16
Expand All @@ -115,15 +115,15 @@ define <4 x half> @selectcc_v4f16(half %a, half %b, <4 x half> %c, <4 x half> %d
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: feq.h a0, fa0, fa1
; CHECK-NEXT: vsetvli zero, zero, e16,m1,ta,mu
; CHECK-NEXT: vsetvli zero, zero, e16,mf2,ta,mu
; CHECK-NEXT: vfmv.f.s ft1, v9
; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: bnez a0, .LBB3_2
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.h ft0, ft1
; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: fsh ft0, 8(sp)
; CHECK-NEXT: vsetivli a1, 1, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 1, e16,mf2,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v9, 3
; CHECK-NEXT: vfmv.f.s ft0, v25
; CHECK-NEXT: vslidedown.vi v25, v8, 3
Expand All @@ -133,7 +133,7 @@ define <4 x half> @selectcc_v4f16(half %a, half %b, <4 x half> %c, <4 x half> %d
; CHECK-NEXT: fmv.h ft1, ft0
; CHECK-NEXT: .LBB3_4:
; CHECK-NEXT: fsh ft1, 14(sp)
; CHECK-NEXT: vsetivli a1, 1, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 1, e16,mf2,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v9, 2
; CHECK-NEXT: vfmv.f.s ft0, v25
; CHECK-NEXT: vslidedown.vi v25, v8, 2
Expand All @@ -143,7 +143,7 @@ define <4 x half> @selectcc_v4f16(half %a, half %b, <4 x half> %c, <4 x half> %d
; CHECK-NEXT: fmv.h ft1, ft0
; CHECK-NEXT: .LBB3_6:
; CHECK-NEXT: fsh ft1, 12(sp)
; CHECK-NEXT: vsetivli a1, 1, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 1, e16,mf2,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v9, 1
; CHECK-NEXT: vfmv.f.s ft0, v25
; CHECK-NEXT: vslidedown.vi v25, v8, 1
Expand All @@ -153,7 +153,7 @@ define <4 x half> @selectcc_v4f16(half %a, half %b, <4 x half> %c, <4 x half> %d
; CHECK-NEXT: fmv.h ft1, ft0
; CHECK-NEXT: .LBB3_8:
; CHECK-NEXT: fsh ft1, 10(sp)
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: addi a0, sp, 8
; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -1069,7 +1069,7 @@ define <16 x half> @selectcc_v16f16(half %a, half %b, <16 x half> %c, <16 x half
define <2 x float> @select_v2f32(i1 zeroext %c, <2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: select_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli zero, zero, e32,m1,ta,mu
; CHECK-NEXT: vsetvli zero, zero, e32,mf2,ta,mu
; CHECK-NEXT: vfmv.f.s ft1, v9
; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: vslidedown.vi v25, v9, 1
Expand All @@ -1081,7 +1081,7 @@ define <2 x float> @select_v2f32(i1 zeroext %c, <2 x float> %a, <2 x float> %b)
; CHECK-NEXT: fmv.s ft0, ft1
; CHECK-NEXT: fmv.s ft2, ft3
; CHECK-NEXT: .LBB8_2:
; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; CHECK-NEXT: vfmv.v.f v8, ft2
; CHECK-NEXT: vfmv.s.f v8, ft0
; CHECK-NEXT: ret
Expand All @@ -1093,7 +1093,7 @@ define <2 x float> @selectcc_v2f32(float %a, float %b, <2 x float> %c, <2 x floa
; CHECK-LABEL: selectcc_v2f32:
; CHECK: # %bb.0:
; CHECK-NEXT: feq.s a0, fa0, fa1
; CHECK-NEXT: vsetivli a1, 1, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 1, e32,mf2,ta,mu
; CHECK-NEXT: vslidedown.vi v25, v9, 1
; CHECK-NEXT: vfmv.f.s ft1, v25
; CHECK-NEXT: vslidedown.vi v25, v8, 1
Expand All @@ -1102,15 +1102,15 @@ define <2 x float> @selectcc_v2f32(float %a, float %b, <2 x float> %c, <2 x floa
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: fmv.s ft0, ft1
; CHECK-NEXT: .LBB9_2:
; CHECK-NEXT: vsetivli a1, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 2, e32,mf2,ta,mu
; CHECK-NEXT: vfmv.v.f v25, ft0
; CHECK-NEXT: vfmv.f.s ft1, v9
; CHECK-NEXT: vfmv.f.s ft0, v8
; CHECK-NEXT: bnez a0, .LBB9_4
; CHECK-NEXT: # %bb.3:
; CHECK-NEXT: fmv.s ft0, ft1
; CHECK-NEXT: .LBB9_4:
; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; CHECK-NEXT: vfmv.s.f v25, ft0
; CHECK-NEXT: vmv1r.v v8, v25
; CHECK-NEXT: ret
Expand Down
40 changes: 20 additions & 20 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-int.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,7 +12,7 @@ define <1 x i1> @select_v1i1(i1 zeroext %c, <1 x i1> %a, <1 x i1> %b) {
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: vsetivli a0, 1, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 1, e8,mf8,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: vmsne.vi v26, v25, 0
; CHECK-NEXT: vmandnot.mm v25, v26, v8
Expand All @@ -33,7 +33,7 @@ define <1 x i1> @selectcc_v1i1(i1 signext %a, i1 signext %b, <1 x i1> %c, <1 x i
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: vsetivli a1, 1, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 1, e8,mf8,ta,mu
; CHECK-NEXT: vmv.v.x v25, a0
; CHECK-NEXT: vmsne.vi v26, v25, 0
; CHECK-NEXT: vmandnot.mm v25, v26, v8
Expand All @@ -53,7 +53,7 @@ define <2 x i1> @select_v2i1(i1 zeroext %c, <2 x i1> %a, <2 x i1> %b) {
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: .LBB2_2:
; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e8,mf8,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: vmsne.vi v26, v25, 0
; CHECK-NEXT: vmandnot.mm v25, v26, v8
Expand All @@ -74,7 +74,7 @@ define <2 x i1> @selectcc_v2i1(i1 signext %a, i1 signext %b, <2 x i1> %c, <2 x i
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: .LBB3_2:
; CHECK-NEXT: vsetivli a1, 2, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 2, e8,mf8,ta,mu
; CHECK-NEXT: vmv.v.x v25, a0
; CHECK-NEXT: vmsne.vi v26, v25, 0
; CHECK-NEXT: vmandnot.mm v25, v26, v8
Expand All @@ -94,7 +94,7 @@ define <4 x i1> @select_v4i1(i1 zeroext %c, <4 x i1> %a, <4 x i1> %b) {
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: .LBB4_2:
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e8,mf4,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: vmsne.vi v26, v25, 0
; CHECK-NEXT: vmandnot.mm v25, v26, v8
Expand All @@ -115,7 +115,7 @@ define <4 x i1> @selectcc_v4i1(i1 signext %a, i1 signext %b, <4 x i1> %c, <4 x i
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: .LBB5_2:
; CHECK-NEXT: vsetivli a1, 4, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 4, e8,mf4,ta,mu
; CHECK-NEXT: vmv.v.x v25, a0
; CHECK-NEXT: vmsne.vi v26, v25, 0
; CHECK-NEXT: vmandnot.mm v25, v26, v8
Expand All @@ -135,7 +135,7 @@ define <8 x i1> @select_v8i1(i1 zeroext %c, <8 x i1> %a, <8 x i1> %b) {
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: .LBB6_2:
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 8, e8,mf2,ta,mu
; CHECK-NEXT: vmv.v.x v25, a1
; CHECK-NEXT: vmsne.vi v26, v25, 0
; CHECK-NEXT: vmandnot.mm v25, v26, v8
Expand All @@ -156,7 +156,7 @@ define <8 x i1> @selectcc_v8i1(i1 signext %a, i1 signext %b, <8 x i1> %c, <8 x i
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: .LBB7_2:
; CHECK-NEXT: vsetivli a1, 8, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a1, 8, e8,mf2,ta,mu
; CHECK-NEXT: vmv.v.x v25, a0
; CHECK-NEXT: vmsne.vi v26, v25, 0
; CHECK-NEXT: vmandnot.mm v25, v26, v8
Expand Down Expand Up @@ -217,7 +217,7 @@ define <2 x i8> @select_v2i8(i1 zeroext %c, <2 x i8> %a, <2 x i8> %b) {
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: .LBB10_2:
; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e8,mf8,ta,mu
; CHECK-NEXT: vand.vx v25, v8, a1
; CHECK-NEXT: vmv.v.x v26, a1
; CHECK-NEXT: vxor.vi v26, v26, -1
Expand All @@ -236,7 +236,7 @@ define <2 x i8> @selectcc_v2i8(i8 signext %a, i8 signext %b, <2 x i8> %c, <2 x i
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: .LBB11_2:
; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e8,mf8,ta,mu
; CHECK-NEXT: vand.vx v25, v8, a2
; CHECK-NEXT: vmv.v.x v26, a2
; CHECK-NEXT: vxor.vi v26, v26, -1
Expand All @@ -256,7 +256,7 @@ define <4 x i8> @select_v4i8(i1 zeroext %c, <4 x i8> %a, <4 x i8> %b) {
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: .LBB12_2:
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e8,mf4,ta,mu
; CHECK-NEXT: vand.vx v25, v8, a1
; CHECK-NEXT: vmv.v.x v26, a1
; CHECK-NEXT: vxor.vi v26, v26, -1
Expand All @@ -275,7 +275,7 @@ define <4 x i8> @selectcc_v4i8(i8 signext %a, i8 signext %b, <4 x i8> %c, <4 x i
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: .LBB13_2:
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e8,mf4,ta,mu
; CHECK-NEXT: vand.vx v25, v8, a2
; CHECK-NEXT: vmv.v.x v26, a2
; CHECK-NEXT: vxor.vi v26, v26, -1
Expand All @@ -295,7 +295,7 @@ define <8 x i8> @select_v8i8(i1 zeroext %c, <8 x i8> %a, <8 x i8> %b) {
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: .LBB14_2:
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 8, e8,mf2,ta,mu
; CHECK-NEXT: vand.vx v25, v8, a1
; CHECK-NEXT: vmv.v.x v26, a1
; CHECK-NEXT: vxor.vi v26, v26, -1
Expand All @@ -314,7 +314,7 @@ define <8 x i8> @selectcc_v8i8(i8 signext %a, i8 signext %b, <8 x i8> %c, <8 x i
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: .LBB15_2:
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 8, e8,mf2,ta,mu
; CHECK-NEXT: vand.vx v25, v8, a2
; CHECK-NEXT: vmv.v.x v26, a2
; CHECK-NEXT: vxor.vi v26, v26, -1
Expand Down Expand Up @@ -373,7 +373,7 @@ define <2 x i16> @select_v2i16(i1 zeroext %c, <2 x i16> %a, <2 x i16> %b) {
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: .LBB18_2:
; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; CHECK-NEXT: vand.vx v25, v8, a1
; CHECK-NEXT: vmv.v.x v26, a1
; CHECK-NEXT: vxor.vi v26, v26, -1
Expand All @@ -392,7 +392,7 @@ define <2 x i16> @selectcc_v2i16(i16 signext %a, i16 signext %b, <2 x i16> %c, <
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: .LBB19_2:
; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; CHECK-NEXT: vand.vx v25, v8, a2
; CHECK-NEXT: vmv.v.x v26, a2
; CHECK-NEXT: vxor.vi v26, v26, -1
Expand All @@ -412,7 +412,7 @@ define <4 x i16> @select_v4i16(i1 zeroext %c, <4 x i16> %a, <4 x i16> %b) {
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: .LBB20_2:
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: vand.vx v25, v8, a1
; CHECK-NEXT: vmv.v.x v26, a1
; CHECK-NEXT: vxor.vi v26, v26, -1
Expand All @@ -431,7 +431,7 @@ define <4 x i16> @selectcc_v4i16(i16 signext %a, i16 signext %b, <4 x i16> %c, <
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: .LBB21_2:
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: vand.vx v25, v8, a2
; CHECK-NEXT: vmv.v.x v26, a2
; CHECK-NEXT: vxor.vi v26, v26, -1
Expand Down Expand Up @@ -529,7 +529,7 @@ define <2 x i32> @select_v2i32(i1 zeroext %c, <2 x i32> %a, <2 x i32> %b) {
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a1, zero
; CHECK-NEXT: .LBB26_2:
; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; CHECK-NEXT: vand.vx v25, v8, a1
; CHECK-NEXT: vmv.v.x v26, a1
; CHECK-NEXT: vxor.vi v26, v26, -1
Expand All @@ -548,7 +548,7 @@ define <2 x i32> @selectcc_v2i32(i32 signext %a, i32 signext %b, <2 x i32> %c, <
; CHECK-NEXT: # %bb.1:
; CHECK-NEXT: mv a2, zero
; CHECK-NEXT: .LBB27_2:
; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; CHECK-NEXT: vand.vx v25, v8, a2
; CHECK-NEXT: vmv.v.x v26, a2
; CHECK-NEXT: vxor.vi v26, v26, -1
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv32.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ declare <2 x i8> @llvm.experimental.stepvector.v2i8()
define <2 x i8> @stepvector_v2i8() {
; CHECK-LABEL: stepvector_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e8,mf8,ta,mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.experimental.stepvector.v2i8()
Expand All @@ -19,7 +19,7 @@ declare <4 x i8> @llvm.experimental.stepvector.v4i8()
define <4 x i8> @stepvector_v4i8() {
; CHECK-LABEL: stepvector_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e8,mf4,ta,mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.experimental.stepvector.v4i8()
Expand All @@ -31,7 +31,7 @@ declare <8 x i8> @llvm.experimental.stepvector.v8i8()
define <8 x i8> @stepvector_v8i8() {
; CHECK-LABEL: stepvector_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 8, e8,mf2,ta,mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.experimental.stepvector.v8i8()
Expand All @@ -55,7 +55,7 @@ declare <2 x i16> @llvm.experimental.stepvector.v2i16()
define <2 x i16> @stepvector_v2i16() {
; CHECK-LABEL: stepvector_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.experimental.stepvector.v2i16()
Expand All @@ -67,7 +67,7 @@ declare <4 x i16> @llvm.experimental.stepvector.v4i16()
define <4 x i16> @stepvector_v4i16() {
; CHECK-LABEL: stepvector_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.experimental.stepvector.v4i16()
Expand Down Expand Up @@ -112,7 +112,7 @@ declare <2 x i32> @llvm.experimental.stepvector.v2i32()
define <2 x i32> @stepvector_v2i32() {
; CHECK-LABEL: stepvector_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.experimental.stepvector.v2i32()
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-stepvector-rv64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ declare <2 x i8> @llvm.experimental.stepvector.v2i8()
define <2 x i8> @stepvector_v2i8() {
; CHECK-LABEL: stepvector_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 2, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e8,mf8,ta,mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.experimental.stepvector.v2i8()
Expand All @@ -19,7 +19,7 @@ declare <4 x i8> @llvm.experimental.stepvector.v4i8()
define <4 x i8> @stepvector_v4i8() {
; CHECK-LABEL: stepvector_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 4, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e8,mf4,ta,mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.experimental.stepvector.v4i8()
Expand All @@ -31,7 +31,7 @@ declare <8 x i8> @llvm.experimental.stepvector.v8i8()
define <8 x i8> @stepvector_v8i8() {
; CHECK-LABEL: stepvector_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 8, e8,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 8, e8,mf2,ta,mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.experimental.stepvector.v8i8()
Expand All @@ -55,7 +55,7 @@ declare <2 x i16> @llvm.experimental.stepvector.v2i16()
define <2 x i16> @stepvector_v2i16() {
; CHECK-LABEL: stepvector_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.experimental.stepvector.v2i16()
Expand All @@ -67,7 +67,7 @@ declare <4 x i16> @llvm.experimental.stepvector.v4i16()
define <4 x i16> @stepvector_v4i16() {
; CHECK-LABEL: stepvector_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.experimental.stepvector.v4i16()
Expand Down Expand Up @@ -112,7 +112,7 @@ declare <2 x i32> @llvm.experimental.stepvector.v2i32()
define <2 x i32> @stepvector_v2i32() {
; CHECK-LABEL: stepvector_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; CHECK-NEXT: vid.v v8
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.experimental.stepvector.v2i32()
Expand Down
72 changes: 36 additions & 36 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vadd-vp.ll
View file

Large diffs are not rendered by default.

72 changes: 36 additions & 36 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vand-vp.ll
View file

Large diffs are not rendered by default.

48 changes: 24 additions & 24 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdiv-vp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ declare <2 x i8> @llvm.vp.sdiv.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
define <2 x i8> @vdiv_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vv_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.sdiv.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
Expand All @@ -19,7 +19,7 @@ define <2 x i8> @vdiv_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroex
define <2 x i8> @vdiv_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vv_v2i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <2 x i1> undef, i1 true, i32 0
Expand All @@ -31,7 +31,7 @@ define <2 x i8> @vdiv_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %e
define <2 x i8> @vdiv_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vx_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vdiv.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i8> undef, i8 %b, i32 0
Expand All @@ -43,7 +43,7 @@ define <2 x i8> @vdiv_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl
define <2 x i8> @vdiv_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vx_v2i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i8> undef, i8 %b, i32 0
Expand All @@ -59,7 +59,7 @@ declare <4 x i8> @llvm.vp.sdiv.v4i8(<4 x i8>, <4 x i8>, <4 x i1>, i32)
define <4 x i8> @vdiv_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vv_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.sdiv.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
Expand All @@ -69,7 +69,7 @@ define <4 x i8> @vdiv_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroex
define <4 x i8> @vdiv_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vv_v4i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <4 x i1> undef, i1 true, i32 0
Expand All @@ -81,7 +81,7 @@ define <4 x i8> @vdiv_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %e
define <4 x i8> @vdiv_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vx_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vdiv.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> undef, i8 %b, i32 0
Expand All @@ -93,7 +93,7 @@ define <4 x i8> @vdiv_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl
define <4 x i8> @vdiv_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vx_v4i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> undef, i8 %b, i32 0
Expand All @@ -109,7 +109,7 @@ declare <8 x i8> @llvm.vp.sdiv.v8i8(<8 x i8>, <8 x i8>, <8 x i1>, i32)
define <8 x i8> @vdiv_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vv_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.sdiv.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
Expand All @@ -119,7 +119,7 @@ define <8 x i8> @vdiv_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroex
define <8 x i8> @vdiv_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vv_v8i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <8 x i1> undef, i1 true, i32 0
Expand All @@ -131,7 +131,7 @@ define <8 x i8> @vdiv_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %e
define <8 x i8> @vdiv_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vx_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vdiv.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i8> undef, i8 %b, i32 0
Expand All @@ -143,7 +143,7 @@ define <8 x i8> @vdiv_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl
define <8 x i8> @vdiv_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vx_v8i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i8> undef, i8 %b, i32 0
Expand Down Expand Up @@ -209,7 +209,7 @@ declare <2 x i16> @llvm.vp.sdiv.v2i16(<2 x i16>, <2 x i16>, <2 x i1>, i32)
define <2 x i16> @vdiv_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vv_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.sdiv.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
Expand All @@ -219,7 +219,7 @@ define <2 x i16> @vdiv_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 ze
define <2 x i16> @vdiv_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vv_v2i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <2 x i1> undef, i1 true, i32 0
Expand All @@ -231,7 +231,7 @@ define <2 x i16> @vdiv_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroex
define <2 x i16> @vdiv_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vx_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vdiv.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i16> undef, i16 %b, i32 0
Expand All @@ -243,7 +243,7 @@ define <2 x i16> @vdiv_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext
define <2 x i16> @vdiv_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vx_v2i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i16> undef, i16 %b, i32 0
Expand All @@ -259,7 +259,7 @@ declare <4 x i16> @llvm.vp.sdiv.v4i16(<4 x i16>, <4 x i16>, <4 x i1>, i32)
define <4 x i16> @vdiv_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vv_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.sdiv.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
Expand All @@ -269,7 +269,7 @@ define <4 x i16> @vdiv_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 ze
define <4 x i16> @vdiv_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vv_v4i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <4 x i1> undef, i1 true, i32 0
Expand All @@ -281,7 +281,7 @@ define <4 x i16> @vdiv_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroex
define <4 x i16> @vdiv_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vx_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vdiv.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i16> undef, i16 %b, i32 0
Expand All @@ -293,7 +293,7 @@ define <4 x i16> @vdiv_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext
define <4 x i16> @vdiv_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vx_v4i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i16> undef, i16 %b, i32 0
Expand Down Expand Up @@ -409,7 +409,7 @@ declare <2 x i32> @llvm.vp.sdiv.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
define <2 x i32> @vdiv_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vv_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vdiv.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.sdiv.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
Expand All @@ -419,7 +419,7 @@ define <2 x i32> @vdiv_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 ze
define <2 x i32> @vdiv_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vv_v2i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vdiv.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <2 x i1> undef, i1 true, i32 0
Expand All @@ -431,7 +431,7 @@ define <2 x i32> @vdiv_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroex
define <2 x i32> @vdiv_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vx_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vdiv.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i32> undef, i32 %b, i32 0
Expand All @@ -443,7 +443,7 @@ define <2 x i32> @vdiv_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext
define <2 x i32> @vdiv_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vdiv_vx_v2i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vdiv.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i32> undef, i32 %b, i32 0
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vdivu-vp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ declare <2 x i8> @llvm.vp.udiv.v2i8(<2 x i8>, <2 x i8>, <2 x i1>, i32)
define <2 x i8> @vdivu_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vv_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <2 x i8> @llvm.vp.udiv.v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 %evl)
Expand All @@ -19,7 +19,7 @@ define <2 x i8> @vdivu_vv_v2i8(<2 x i8> %va, <2 x i8> %b, <2 x i1> %m, i32 zeroe
define <2 x i8> @vdivu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vv_v2i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,ta,mu
; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <2 x i1> undef, i1 true, i32 0
Expand All @@ -31,7 +31,7 @@ define <2 x i8> @vdivu_vv_v2i8_unmasked(<2 x i8> %va, <2 x i8> %b, i32 zeroext %
define <2 x i8> @vdivu_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vx_v2i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vdivu.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i8> undef, i8 %b, i32 0
Expand All @@ -43,7 +43,7 @@ define <2 x i8> @vdivu_vx_v2i8(<2 x i8> %va, i8 %b, <2 x i1> %m, i32 zeroext %ev
define <2 x i8> @vdivu_vx_v2i8_unmasked(<2 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vx_v2i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e8,mf8,ta,mu
; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i8> undef, i8 %b, i32 0
Expand All @@ -59,7 +59,7 @@ declare <4 x i8> @llvm.vp.udiv.v4i8(<4 x i8>, <4 x i8>, <4 x i1>, i32)
define <4 x i8> @vdivu_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vv_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <4 x i8> @llvm.vp.udiv.v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 %evl)
Expand All @@ -69,7 +69,7 @@ define <4 x i8> @vdivu_vv_v4i8(<4 x i8> %va, <4 x i8> %b, <4 x i1> %m, i32 zeroe
define <4 x i8> @vdivu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vv_v4i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,ta,mu
; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <4 x i1> undef, i1 true, i32 0
Expand All @@ -81,7 +81,7 @@ define <4 x i8> @vdivu_vv_v4i8_unmasked(<4 x i8> %va, <4 x i8> %b, i32 zeroext %
define <4 x i8> @vdivu_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vx_v4i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vdivu.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> undef, i8 %b, i32 0
Expand All @@ -93,7 +93,7 @@ define <4 x i8> @vdivu_vx_v4i8(<4 x i8> %va, i8 %b, <4 x i1> %m, i32 zeroext %ev
define <4 x i8> @vdivu_vx_v4i8_unmasked(<4 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vx_v4i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e8,mf4,ta,mu
; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i8> undef, i8 %b, i32 0
Expand All @@ -109,7 +109,7 @@ declare <8 x i8> @llvm.vp.udiv.v8i8(<8 x i8>, <8 x i8>, <8 x i1>, i32)
define <8 x i8> @vdivu_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vv_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <8 x i8> @llvm.vp.udiv.v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 %evl)
Expand All @@ -119,7 +119,7 @@ define <8 x i8> @vdivu_vv_v8i8(<8 x i8> %va, <8 x i8> %b, <8 x i1> %m, i32 zeroe
define <8 x i8> @vdivu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vv_v8i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,ta,mu
; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <8 x i1> undef, i1 true, i32 0
Expand All @@ -131,7 +131,7 @@ define <8 x i8> @vdivu_vv_v8i8_unmasked(<8 x i8> %va, <8 x i8> %b, i32 zeroext %
define <8 x i8> @vdivu_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vx_v8i8:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vdivu.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i8> undef, i8 %b, i32 0
Expand All @@ -143,7 +143,7 @@ define <8 x i8> @vdivu_vx_v8i8(<8 x i8> %va, i8 %b, <8 x i1> %m, i32 zeroext %ev
define <8 x i8> @vdivu_vx_v8i8_unmasked(<8 x i8> %va, i8 %b, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vx_v8i8_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e8,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e8,mf2,ta,mu
; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x i8> undef, i8 %b, i32 0
Expand Down Expand Up @@ -209,7 +209,7 @@ declare <2 x i16> @llvm.vp.udiv.v2i16(<2 x i16>, <2 x i16>, <2 x i1>, i32)
define <2 x i16> @vdivu_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vv_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <2 x i16> @llvm.vp.udiv.v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 %evl)
Expand All @@ -219,7 +219,7 @@ define <2 x i16> @vdivu_vv_v2i16(<2 x i16> %va, <2 x i16> %b, <2 x i1> %m, i32 z
define <2 x i16> @vdivu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vv_v2i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,ta,mu
; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <2 x i1> undef, i1 true, i32 0
Expand All @@ -231,7 +231,7 @@ define <2 x i16> @vdivu_vv_v2i16_unmasked(<2 x i16> %va, <2 x i16> %b, i32 zeroe
define <2 x i16> @vdivu_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vx_v2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vdivu.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i16> undef, i16 %b, i32 0
Expand All @@ -243,7 +243,7 @@ define <2 x i16> @vdivu_vx_v2i16(<2 x i16> %va, i16 %b, <2 x i1> %m, i32 zeroext
define <2 x i16> @vdivu_vx_v2i16_unmasked(<2 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vx_v2i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e16,mf4,ta,mu
; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i16> undef, i16 %b, i32 0
Expand All @@ -259,7 +259,7 @@ declare <4 x i16> @llvm.vp.udiv.v4i16(<4 x i16>, <4 x i16>, <4 x i1>, i32)
define <4 x i16> @vdivu_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vv_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <4 x i16> @llvm.vp.udiv.v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 %evl)
Expand All @@ -269,7 +269,7 @@ define <4 x i16> @vdivu_vv_v4i16(<4 x i16> %va, <4 x i16> %b, <4 x i1> %m, i32 z
define <4 x i16> @vdivu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vv_v4i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e16,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,ta,mu
; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <4 x i1> undef, i1 true, i32 0
Expand All @@ -281,7 +281,7 @@ define <4 x i16> @vdivu_vv_v4i16_unmasked(<4 x i16> %va, <4 x i16> %b, i32 zeroe
define <4 x i16> @vdivu_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vx_v4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vdivu.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i16> undef, i16 %b, i32 0
Expand All @@ -293,7 +293,7 @@ define <4 x i16> @vdivu_vx_v4i16(<4 x i16> %va, i16 %b, <4 x i1> %m, i32 zeroext
define <4 x i16> @vdivu_vx_v4i16_unmasked(<4 x i16> %va, i16 %b, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vx_v4i16_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e16,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e16,mf2,ta,mu
; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x i16> undef, i16 %b, i32 0
Expand Down Expand Up @@ -409,7 +409,7 @@ declare <2 x i32> @llvm.vp.udiv.v2i32(<2 x i32>, <2 x i32>, <2 x i1>, i32)
define <2 x i32> @vdivu_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vv_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vdivu.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret
%v = call <2 x i32> @llvm.vp.udiv.v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 %evl)
Expand All @@ -419,7 +419,7 @@ define <2 x i32> @vdivu_vv_v2i32(<2 x i32> %va, <2 x i32> %b, <2 x i1> %m, i32 z
define <2 x i32> @vdivu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vv_v2i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, a0, e32,m1,ta,mu
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,ta,mu
; CHECK-NEXT: vdivu.vv v8, v8, v9
; CHECK-NEXT: ret
%head = insertelement <2 x i1> undef, i1 true, i32 0
Expand All @@ -431,7 +431,7 @@ define <2 x i32> @vdivu_vv_v2i32_unmasked(<2 x i32> %va, <2 x i32> %b, i32 zeroe
define <2 x i32> @vdivu_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vx_v2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vdivu.vx v8, v8, a0, v0.t
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i32> undef, i32 %b, i32 0
Expand All @@ -443,7 +443,7 @@ define <2 x i32> @vdivu_vx_v2i32(<2 x i32> %va, i32 %b, <2 x i1> %m, i32 zeroext
define <2 x i32> @vdivu_vx_v2i32_unmasked(<2 x i32> %va, i32 %b, i32 zeroext %evl) {
; CHECK-LABEL: vdivu_vx_v2i32_unmasked:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a1, a1, e32,m1,ta,mu
; CHECK-NEXT: vsetvli a1, a1, e32,mf2,ta,mu
; CHECK-NEXT: vdivu.vx v8, v8, a0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x i32> undef, i32 %b, i32 0
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmax.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)
define <2 x half> @vfmax_v2f16_vv(<2 x half> %a, <2 x half> %b) {
; CHECK-LABEL: vfmax_v2f16_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; CHECK-NEXT: vfmax.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x half> @llvm.maxnum.v2f16(<2 x half> %a, <2 x half> %b)
Expand All @@ -19,7 +19,7 @@ define <2 x half> @vfmax_v2f16_vv(<2 x half> %a, <2 x half> %b) {
define <2 x half> @vfmax_v2f16_vf(<2 x half> %a, half %b) {
; CHECK-LABEL: vfmax_v2f16_vf:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; CHECK-NEXT: vfmax.vf v8, v8, fa0
; CHECK-NEXT: ret
%head = insertelement <2 x half> undef, half %b, i32 0
Expand All @@ -33,7 +33,7 @@ declare <4 x half> @llvm.maxnum.v4f16(<4 x half>, <4 x half>)
define <4 x half> @vfmax_v4f16_vv(<4 x half> %a, <4 x half> %b) {
; CHECK-LABEL: vfmax_v4f16_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: vfmax.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x half> @llvm.maxnum.v4f16(<4 x half> %a, <4 x half> %b)
Expand All @@ -43,7 +43,7 @@ define <4 x half> @vfmax_v4f16_vv(<4 x half> %a, <4 x half> %b) {
define <4 x half> @vfmax_v4f16_vf(<4 x half> %a, half %b) {
; CHECK-LABEL: vfmax_v4f16_vf:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: vfmax.vf v8, v8, fa0
; CHECK-NEXT: ret
%head = insertelement <4 x half> undef, half %b, i32 0
Expand Down Expand Up @@ -105,7 +105,7 @@ declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>)
define <2 x float> @vfmax_v2f32_vv(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: vfmax_v2f32_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; CHECK-NEXT: vfmax.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b)
Expand All @@ -115,7 +115,7 @@ define <2 x float> @vfmax_v2f32_vv(<2 x float> %a, <2 x float> %b) {
define <2 x float> @vfmax_v2f32_vf(<2 x float> %a, float %b) {
; CHECK-LABEL: vfmax_v2f32_vf:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; CHECK-NEXT: vfmax.vf v8, v8, fa0
; CHECK-NEXT: ret
%head = insertelement <2 x float> undef, float %b, i32 0
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vfmin.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ declare <2 x half> @llvm.minnum.v2f16(<2 x half>, <2 x half>)
define <2 x half> @vfmin_v2f16_vv(<2 x half> %a, <2 x half> %b) {
; CHECK-LABEL: vfmin_v2f16_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; CHECK-NEXT: vfmin.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x half> @llvm.minnum.v2f16(<2 x half> %a, <2 x half> %b)
Expand All @@ -19,7 +19,7 @@ define <2 x half> @vfmin_v2f16_vv(<2 x half> %a, <2 x half> %b) {
define <2 x half> @vfmin_v2f16_vf(<2 x half> %a, half %b) {
; CHECK-LABEL: vfmin_v2f16_vf:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 2, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e16,mf4,ta,mu
; CHECK-NEXT: vfmin.vf v8, v8, fa0
; CHECK-NEXT: ret
%head = insertelement <2 x half> undef, half %b, i32 0
Expand All @@ -33,7 +33,7 @@ declare <4 x half> @llvm.minnum.v4f16(<4 x half>, <4 x half>)
define <4 x half> @vfmin_v4f16_vv(<4 x half> %a, <4 x half> %b) {
; CHECK-LABEL: vfmin_v4f16_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: vfmin.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <4 x half> @llvm.minnum.v4f16(<4 x half> %a, <4 x half> %b)
Expand All @@ -43,7 +43,7 @@ define <4 x half> @vfmin_v4f16_vv(<4 x half> %a, <4 x half> %b) {
define <4 x half> @vfmin_v4f16_vf(<4 x half> %a, half %b) {
; CHECK-LABEL: vfmin_v4f16_vf:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 4, e16,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 4, e16,mf2,ta,mu
; CHECK-NEXT: vfmin.vf v8, v8, fa0
; CHECK-NEXT: ret
%head = insertelement <4 x half> undef, half %b, i32 0
Expand Down Expand Up @@ -105,7 +105,7 @@ declare <2 x float> @llvm.minnum.v2f32(<2 x float>, <2 x float>)
define <2 x float> @vfmin_v2f32_vv(<2 x float> %a, <2 x float> %b) {
; CHECK-LABEL: vfmin_v2f32_vv:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; CHECK-NEXT: vfmin.vv v8, v8, v9
; CHECK-NEXT: ret
%v = call <2 x float> @llvm.minnum.v2f32(<2 x float> %a, <2 x float> %b)
Expand All @@ -115,7 +115,7 @@ define <2 x float> @vfmin_v2f32_vv(<2 x float> %a, <2 x float> %b) {
define <2 x float> @vfmin_v2f32_vf(<2 x float> %a, float %b) {
; CHECK-LABEL: vfmin_v2f32_vf:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli a0, 2, e32,m1,ta,mu
; CHECK-NEXT: vsetivli a0, 2, e32,mf2,ta,mu
; CHECK-NEXT: vfmin.vf v8, v8, fa0
; CHECK-NEXT: ret
%head = insertelement <2 x float> undef, float %b, i32 0
Expand Down
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