100 changes: 94 additions & 6 deletions llvm/test/DebugInfo/X86/debug-names-types.ll
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Original file line number Diff line number Diff line change
@@ -1,15 +1,10 @@
; UNSUPPORTED: system-windows
; This checks that .debug_names can be generated with monolithic -fdebug-type-sections, and does not generate when split-dwarf is enabled.
; This checks that .debug_names can be generated with monolithic, and split-dwarf, when -fdebug-type-sections is enabled.
; Generated with: clang++ main.cpp -g2 -gdwarf-5 -gpubnames -fdebug-types-section

; RUN: llc -mtriple=x86_64 -generate-type-units -dwarf-version=5 -filetype=obj %s -o %t
; RUN: llvm-dwarfdump -debug-info -debug-names %t | FileCheck %s

; RUN: llc -mtriple=x86_64 -generate-type-units -dwarf-version=5 -filetype=obj -split-dwarf-file=%t.mainTypes.dwo --split-dwarf-output=%t.mainTypes.dwo %s -o %t
; RUN: llvm-readelf --sections %t | FileCheck %s --check-prefixes=CHECK-SPLIT

; CHECK-SPLIT-NOT: .debug_names

; CHECK: .debug_info contents:
; CHECK: DW_TAG_type_unit
; CHECK-NEXT: DW_AT_language (DW_LANG_C_plus_plus_14)
Expand Down Expand Up @@ -117,6 +112,99 @@
; CHECK-NEXT: ]
; CHECK-NEXT: }

; RUN: llc -mtriple=x86_64 -generate-type-units -dwarf-version=5 -filetype=obj -split-dwarf-file=%t.mainTypes.dwo --split-dwarf-output=%t.mainTypes.dwo %s -o %t
; RUN: llvm-dwarfdump -debug-names %t | FileCheck %s --check-prefixes=CHECK-SPLIT

; CHECK-SPLIT: .debug_names contents
; CHECK-SPLIT: Foreign TU count: 1
; CHECK-SPLIT-NEXT: Bucket count: 4
; CHECK-SPLIT-NEXT: Name count: 4
; CHECK-SPLIT-NEXT: Abbreviations table size: 0x28
; CHECK-SPLIT-NEXT: Augmentation: 'LLVM0700'
; CHECK-SPLIT-NEXT: }
; CHECK-SPLIT-NEXT: Compilation Unit offsets [
; CHECK-SPLIT-NEXT: CU[0]: 0x00000000
; CHECK-SPLIT-NEXT: ]
; CHECK-SPLIT-NEXT: Foreign Type Unit signatures [
; CHECK-SPLIT-NEXT: ForeignTU[0]: 0x675d23e4f33235f2
; CHECK-SPLIT-NEXT: ]
; CHECK-SPLIT-NEXT: Abbreviations [
; CHECK-SPLIT-NEXT: Abbreviation [[ABBREV:0x[0-9a-f]*]] {
; CHECK-SPLIT-NEXT: Tag: DW_TAG_structure_type
; CHECK-SPLIT-NEXT: DW_IDX_die_offset: DW_FORM_ref4
; CHECK-SPLIT-NEXT: }
; CHECK-SPLIT-NEXT: Abbreviation [[ABBREV1:0x[0-9a-f]*]] {
; CHECK-SPLIT-NEXT: Tag: DW_TAG_structure_type
; CHECK-SPLIT-NEXT: DW_IDX_type_unit: DW_FORM_data1
; CHECK-SPLIT-NEXT: DW_IDX_die_offset: DW_FORM_ref4
; CHECK-SPLIT-NEXT: }
; CHECK-SPLIT-NEXT: Abbreviation [[ABBREV2:0x[0-9a-f]*]] {
; CHECK-SPLIT-NEXT: Tag: DW_TAG_base_type
; CHECK-SPLIT-NEXT: DW_IDX_die_offset: DW_FORM_ref4
; CHECK-SPLIT-NEXT: }
; CHECK-SPLIT-NEXT: Abbreviation [[ABBREV3:0x[0-9a-f]*]] {
; CHECK-SPLIT-NEXT: Tag: DW_TAG_subprogram
; CHECK-SPLIT-NEXT: DW_IDX_die_offset: DW_FORM_ref4
; CHECK-SPLIT-NEXT: }
; CHECK-SPLIT-NEXT: Abbreviation [[ABBREV4:0x[0-9a-f]*]] {
; CHECK-SPLIT-NEXT: Tag: DW_TAG_base_type
; CHECK-SPLIT-NEXT: DW_IDX_type_unit: DW_FORM_data1
; CHECK-SPLIT-NEXT: DW_IDX_die_offset: DW_FORM_ref4
; CHECK-SPLIT-NEXT: }
; CHECK-SPLIT-NEXT: ]
; CHECK-SPLIT-NEXT: Bucket 0 [
; CHECK-SPLIT-NEXT: Name 1 {
; CHECK-SPLIT-NEXT: Hash: 0xB888030
; CHECK-SPLIT-NEXT: String: {{.+}} "int"
; CHECK-SPLIT-NEXT: Entry @ {{.+}} {
; CHECK-SPLIT-NEXT: Abbrev: [[ABBREV2]]
; CHECK-SPLIT-NEXT: Tag: DW_TAG_base_type
; CHECK-SPLIT-NEXT: DW_IDX_die_offset: 0x00000035
; CHECK-SPLIT-NEXT: }
; CHECK-SPLIT-NEXT: }
; CHECK-SPLIT-NEXT: ]
; CHECK-SPLIT-NEXT: Bucket 1 [
; CHECK-SPLIT-NEXT: Name 2 {
; CHECK-SPLIT-NEXT: Hash: 0xB887389
; CHECK-SPLIT-NEXT: String: {{.+}} "Foo"
; CHECK-SPLIT-NEXT: Entry @ {{.+}} {
; CHECK-SPLIT-NEXT: Abbrev: [[ABBREV1]]
; CHECK-SPLIT-NEXT: Tag: DW_TAG_structure_type
; CHECK-SPLIT-NEXT: DW_IDX_type_unit: 0x00
; CHECK-SPLIT-NEXT: DW_IDX_die_offset: 0x0000001f
; CHECK-SPLIT-NEXT: }
; CHECK-SPLIT-NEXT: Entry @ 0xae {
; CHECK-SPLIT-NEXT: Abbrev: [[ABBREV]]
; CHECK-SPLIT-NEXT: Tag: DW_TAG_structure_type
; CHECK-SPLIT-NEXT: DW_IDX_die_offset: 0x00000039
; CHECK-SPLIT-NEXT: }
; CHECK-SPLIT-NEXT: }
; CHECK-SPLIT-NEXT: ]
; CHECK-SPLIT-NEXT: Bucket 2 [
; CHECK-SPLIT-NEXT: Name 3 {
; CHECK-SPLIT-NEXT: Hash: 0x7C9A7F6A
; CHECK-SPLIT-NEXT: String: {{.+}} "main"
; CHECK-SPLIT-NEXT: Entry @ {{.+}} {
; CHECK-SPLIT-NEXT: Abbrev: [[ABBREV3]]
; CHECK-SPLIT-NEXT: Tag: DW_TAG_subprogram
; CHECK-SPLIT-NEXT: DW_IDX_die_offset: 0x0000001a
; CHECK-SPLIT-NEXT: }
; CHECK-SPLIT-NEXT: }
; CHECK-SPLIT-NEXT: ]
; CHECK-SPLIT-NEXT: Bucket 3 [
; CHECK-SPLIT-NEXT: Name 4 {
; CHECK-SPLIT-NEXT: Hash: 0x7C952063
; CHECK-SPLIT-NEXT: String: {{.+}} "char"
; CHECK-SPLIT-NEXT: Entry @ {{.+}} {
; CHECK-SPLIT-NEXT: Abbrev: [[ABBREV4]]
; CHECK-SPLIT-NEXT: Tag: DW_TAG_base_type
; CHECK-SPLIT-NEXT: DW_IDX_type_unit: 0x00
; CHECK-SPLIT-NEXT: DW_IDX_die_offset: 0x00000034
; CHECK-SPLIT-NEXT: }
; CHECK-SPLIT-NEXT: }
; CHECK-SPLIT-NEXT: ]
; CHECK-SPLIT-NEXT: }


; ModuleID = 'main.cpp'
source_filename = "main.cpp"
Expand Down
71 changes: 71 additions & 0 deletions llvm/test/Transforms/LoopVectorize/preserve-or-disjoint.ll
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Original file line number Diff line number Diff line change
@@ -0,0 +1,71 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
; RUN: opt -p loop-vectorize -force-vector-width=4 -force-vector-interleave=1 -S %s | FileCheck %s

; TODO: Preserve disjoint flag on OR instruction.
define void @generate_disjoint_flags(i64 %n, ptr noalias %x) {
; CHECK-LABEL: define void @generate_disjoint_flags(
; CHECK-SAME: i64 [[N:%.*]], ptr noalias [[X:%.*]]) {
; CHECK-NEXT: entry:
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[X]], i64 [[TMP0]]
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i32 0
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4
; CHECK-NEXT: [[TMP3:%.*]] = or <4 x i32> [[WIDE_LOAD]], <i32 1, i32 1, i32 1, i32 1>
; CHECK-NEXT: [[TMP4:%.*]] = or <4 x i32> [[WIDE_LOAD]], <i32 3, i32 3, i32 3, i32 3>
; CHECK-NEXT: [[TMP5:%.*]] = add nuw nsw <4 x i32> [[TMP3]], [[TMP4]]
; CHECK-NEXT: store <4 x i32> [[TMP5]], ptr [[TMP2]], align 4
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: middle.block:
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]]
; CHECK: scalar.ph:
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ]
; CHECK-NEXT: br label [[LOOP:%.*]]
; CHECK: loop:
; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
; CHECK-NEXT: [[GEP_X:%.*]] = getelementptr inbounds i32, ptr [[X]], i64 [[IV]]
; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[GEP_X]], align 4
; CHECK-NEXT: [[OR_1:%.*]] = or disjoint i32 [[LV]], 1
; CHECK-NEXT: [[OR_2:%.*]] = or i32 [[LV]], 3
; CHECK-NEXT: [[ADD:%.*]] = add nuw nsw i32 [[OR_1]], [[OR_2]]
; CHECK-NEXT: store i32 [[ADD]], ptr [[GEP_X]], align 4
; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
; CHECK-NEXT: [[EXITCOND:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
; CHECK-NEXT: br i1 [[EXITCOND]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: exit:
; CHECK-NEXT: ret void
;
entry:
br label %loop

loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%gep.x = getelementptr inbounds i32, ptr %x, i64 %iv
%lv = load i32, ptr %gep.x, align 4
%or.1 = or disjoint i32 %lv, 1
%or.2 = or i32 %lv, 3
%add = add nsw nuw i32 %or.1, %or.2
store i32 %add, ptr %gep.x, align 4
%iv.next = add i64 %iv, 1
%exitcond = icmp eq i64 %iv.next, %n
br i1 %exitcond, label %exit, label %loop

exit:
ret void
}
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
;.
49 changes: 49 additions & 0 deletions llvm/test/Transforms/LoopVectorize/vplan-printing.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -757,6 +757,55 @@ end:
ret void
}

; FIXME: Preserve disjoint flag on OR recipe.
define void @print_disjoint_flags(i64 %n, ptr noalias %x) {
; CHECK-LABEL: Checking a loop in 'print_disjoint_flags'
; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count
; CHECK-NEXT: Live-in ir<%n> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT: vector.ph:
; CHECK-NEXT: Successor(s): vector loop
; CHECK-EMPTY:
; CHECK-NEXT: <x1> vector loop: {
; CHECK-NEXT: vector.body:
; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
; CHECK-NEXT: CLONE ir<%gep.x> = getelementptr inbounds ir<%x>, vp<[[STEPS]]>
; CHECK-NEXT: WIDEN ir<%lv> = load ir<%gep.x>
; CHECK-NEXT: WIDEN ir<%or.1> = or ir<%lv>, ir<1>
; CHECK-NEXT: WIDEN ir<%or.2> = or ir<%lv>, ir<3>
; CHECK-NEXT: WIDEN ir<%add> = add nuw nsw ir<%or.1>, ir<%or.2>
; CHECK-NEXT: WIDEN store ir<%gep.x>, ir<%add>
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = VF * UF + nuw vp<[[CAN_IV]]>
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]>
; CHECK-NEXT: No successors
; CHECK-NEXT: }
; CHECK-NEXT: Successor(s): middle.block
; CHECK-EMPTY:
; CHECK-NEXT: middle.block:
; CHECK-NEXT: No successors
; CHECK-NEXT: }
;
entry:
br label %loop

loop:
%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
%gep.x = getelementptr inbounds i32, ptr %x, i64 %iv
%lv = load i32, ptr %gep.x, align 4
%or.1 = or disjoint i32 %lv, 1
%or.2 = or i32 %lv, 3
%add = add nsw nuw i32 %or.1, %or.2
store i32 %add, ptr %gep.x, align 4
%iv.next = add i64 %iv, 1
%exitcond = icmp eq i64 %iv.next, %n
br i1 %exitcond, label %exit, label %loop

exit:
ret void
}

!llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4}

Expand Down
4 changes: 2 additions & 2 deletions llvm/test/tools/llvm-mca/RISCV/SiFive7/div-fdiv.s
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Original file line number Diff line number Diff line change
Expand Up @@ -32,8 +32,8 @@ fdiv.s f1, f2, f3
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

Expand Down
4 changes: 2 additions & 2 deletions llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass-c.s
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Original file line number Diff line number Diff line change
Expand Up @@ -70,8 +70,8 @@ c.jr a0
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

Expand Down
4 changes: 2 additions & 2 deletions llvm/test/tools/llvm-mca/RISCV/SiFive7/gpr-bypass.s
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Original file line number Diff line number Diff line change
Expand Up @@ -218,8 +218,8 @@ jr a0
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

Expand Down
422 changes: 211 additions & 211 deletions llvm/test/tools/llvm-mca/RISCV/SiFive7/reductions.s
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Large diffs are not rendered by default.

106 changes: 53 additions & 53 deletions llvm/test/tools/llvm-mca/RISCV/SiFive7/strided-load-x0.s
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Original file line number Diff line number Diff line change
Expand Up @@ -37,13 +37,13 @@ vle64.v v1, (a1)

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 26
# CHECK-NEXT: Total Cycles: 3523
# CHECK-NEXT: Total Cycles: 3546
# CHECK-NEXT: Total uOps: 26

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.01
# CHECK-NEXT: IPC: 0.01
# CHECK-NEXT: Block RThroughput: 3517.0
# CHECK-NEXT: Block RThroughput: 3541.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -55,71 +55,71 @@ vle64.v v1, (a1)

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: 1 515 512.00 * vlse8.v v1, (a1), a2
# CHECK-NEXT: 1 259 256.00 * vlse16.v v1, (a1), a2
# CHECK-NEXT: 1 19 16.00 * vlse32.v v1, (a1), a2
# CHECK-NEXT: 1 67 64.00 * vlse64.v v1, (a1), a2
# CHECK-NEXT: 1 515 512.00 * vlse8.v v1, (a1), zero
# CHECK-NEXT: 1 259 256.00 * vlse16.v v1, (a1), zero
# CHECK-NEXT: 1 19 16.00 * vlse32.v v1, (a1), zero
# CHECK-NEXT: 1 67 64.00 * vlse64.v v1, (a1), zero
# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a1)
# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a1)
# CHECK-NEXT: 1 4 2.00 * vle32.v v1, (a1)
# CHECK-NEXT: 1 4 4.00 * vle64.v v1, (a1)
# CHECK-NEXT: 1 515 513.00 * vlse8.v v1, (a1), a2
# CHECK-NEXT: 1 259 257.00 * vlse16.v v1, (a1), a2
# CHECK-NEXT: 1 19 17.00 * vlse32.v v1, (a1), a2
# CHECK-NEXT: 1 67 65.00 * vlse64.v v1, (a1), a2
# CHECK-NEXT: 1 515 513.00 * vlse8.v v1, (a1), zero
# CHECK-NEXT: 1 259 257.00 * vlse16.v v1, (a1), zero
# CHECK-NEXT: 1 19 17.00 * vlse32.v v1, (a1), zero
# CHECK-NEXT: 1 67 65.00 * vlse64.v v1, (a1), zero
# CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a1)
# CHECK-NEXT: 1 4 2.00 * vle16.v v1, (a1)
# CHECK-NEXT: 1 4 3.00 * vle32.v v1, (a1)
# CHECK-NEXT: 1 4 5.00 * vle64.v v1, (a1)
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: 1 515 512.00 * vlse8.v v1, (a1), a2
# CHECK-NEXT: 1 259 256.00 * vlse16.v v1, (a1), a2
# CHECK-NEXT: 1 131 128.00 * vlse32.v v1, (a1), a2
# CHECK-NEXT: 1 11 8.00 * vlse64.v v1, (a1), a2
# CHECK-NEXT: 1 515 512.00 * vlse8.v v1, (a1), zero
# CHECK-NEXT: 1 259 256.00 * vlse16.v v1, (a1), zero
# CHECK-NEXT: 1 131 128.00 * vlse32.v v1, (a1), zero
# CHECK-NEXT: 1 11 8.00 * vlse64.v v1, (a1), zero
# CHECK-NEXT: 1 4 1.00 * vle8.v v1, (a1)
# CHECK-NEXT: 1 4 1.00 * vle16.v v1, (a1)
# CHECK-NEXT: 1 4 1.00 * vle32.v v1, (a1)
# CHECK-NEXT: 1 4 2.00 * vle64.v v1, (a1)
# CHECK-NEXT: 1 515 513.00 * vlse8.v v1, (a1), a2
# CHECK-NEXT: 1 259 257.00 * vlse16.v v1, (a1), a2
# CHECK-NEXT: 1 131 129.00 * vlse32.v v1, (a1), a2
# CHECK-NEXT: 1 11 9.00 * vlse64.v v1, (a1), a2
# CHECK-NEXT: 1 515 513.00 * vlse8.v v1, (a1), zero
# CHECK-NEXT: 1 259 257.00 * vlse16.v v1, (a1), zero
# CHECK-NEXT: 1 131 129.00 * vlse32.v v1, (a1), zero
# CHECK-NEXT: 1 11 9.00 * vlse64.v v1, (a1), zero
# CHECK-NEXT: 1 4 2.00 * vle8.v v1, (a1)
# CHECK-NEXT: 1 4 2.00 * vle16.v v1, (a1)
# CHECK-NEXT: 1 4 2.00 * vle32.v v1, (a1)
# CHECK-NEXT: 1 4 3.00 * vle64.v v1, (a1)

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 2.00 - 3517.00 - 3517.00 -
# CHECK-NEXT: - - 2.00 - - 24.00 3541.00 -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, m1, tu, mu
# CHECK-NEXT: - - - - 512.00 - 512.00 - vlse8.v v1, (a1), a2
# CHECK-NEXT: - - - - 256.00 - 256.00 - vlse16.v v1, (a1), a2
# CHECK-NEXT: - - - - 16.00 - 16.00 - vlse32.v v1, (a1), a2
# CHECK-NEXT: - - - - 64.00 - 64.00 - vlse64.v v1, (a1), a2
# CHECK-NEXT: - - - - 512.00 - 512.00 - vlse8.v v1, (a1), zero
# CHECK-NEXT: - - - - 256.00 - 256.00 - vlse16.v v1, (a1), zero
# CHECK-NEXT: - - - - 16.00 - 16.00 - vlse32.v v1, (a1), zero
# CHECK-NEXT: - - - - 64.00 - 64.00 - vlse64.v v1, (a1), zero
# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a1)
# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a1)
# CHECK-NEXT: - - - - 2.00 - 2.00 - vle32.v v1, (a1)
# CHECK-NEXT: - - - - 4.00 - 4.00 - vle64.v v1, (a1)
# CHECK-NEXT: - - - - - 1.00 513.00 - vlse8.v v1, (a1), a2
# CHECK-NEXT: - - - - - 1.00 257.00 - vlse16.v v1, (a1), a2
# CHECK-NEXT: - - - - - 1.00 17.00 - vlse32.v v1, (a1), a2
# CHECK-NEXT: - - - - - 1.00 65.00 - vlse64.v v1, (a1), a2
# CHECK-NEXT: - - - - - 1.00 513.00 - vlse8.v v1, (a1), zero
# CHECK-NEXT: - - - - - 1.00 257.00 - vlse16.v v1, (a1), zero
# CHECK-NEXT: - - - - - 1.00 17.00 - vlse32.v v1, (a1), zero
# CHECK-NEXT: - - - - - 1.00 65.00 - vlse64.v v1, (a1), zero
# CHECK-NEXT: - - - - - 1.00 2.00 - vle8.v v1, (a1)
# CHECK-NEXT: - - - - - 1.00 2.00 - vle16.v v1, (a1)
# CHECK-NEXT: - - - - - 1.00 3.00 - vle32.v v1, (a1)
# CHECK-NEXT: - - - - - 1.00 5.00 - vle64.v v1, (a1)
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e64, m1, tu, mu
# CHECK-NEXT: - - - - 512.00 - 512.00 - vlse8.v v1, (a1), a2
# CHECK-NEXT: - - - - 256.00 - 256.00 - vlse16.v v1, (a1), a2
# CHECK-NEXT: - - - - 128.00 - 128.00 - vlse32.v v1, (a1), a2
# CHECK-NEXT: - - - - 8.00 - 8.00 - vlse64.v v1, (a1), a2
# CHECK-NEXT: - - - - 512.00 - 512.00 - vlse8.v v1, (a1), zero
# CHECK-NEXT: - - - - 256.00 - 256.00 - vlse16.v v1, (a1), zero
# CHECK-NEXT: - - - - 128.00 - 128.00 - vlse32.v v1, (a1), zero
# CHECK-NEXT: - - - - 8.00 - 8.00 - vlse64.v v1, (a1), zero
# CHECK-NEXT: - - - - 1.00 - 1.00 - vle8.v v1, (a1)
# CHECK-NEXT: - - - - 1.00 - 1.00 - vle16.v v1, (a1)
# CHECK-NEXT: - - - - 1.00 - 1.00 - vle32.v v1, (a1)
# CHECK-NEXT: - - - - 2.00 - 2.00 - vle64.v v1, (a1)
# CHECK-NEXT: - - - - - 1.00 513.00 - vlse8.v v1, (a1), a2
# CHECK-NEXT: - - - - - 1.00 257.00 - vlse16.v v1, (a1), a2
# CHECK-NEXT: - - - - - 1.00 129.00 - vlse32.v v1, (a1), a2
# CHECK-NEXT: - - - - - 1.00 9.00 - vlse64.v v1, (a1), a2
# CHECK-NEXT: - - - - - 1.00 513.00 - vlse8.v v1, (a1), zero
# CHECK-NEXT: - - - - - 1.00 257.00 - vlse16.v v1, (a1), zero
# CHECK-NEXT: - - - - - 1.00 129.00 - vlse32.v v1, (a1), zero
# CHECK-NEXT: - - - - - 1.00 9.00 - vlse64.v v1, (a1), zero
# CHECK-NEXT: - - - - - 1.00 2.00 - vle8.v v1, (a1)
# CHECK-NEXT: - - - - - 1.00 2.00 - vle16.v v1, (a1)
# CHECK-NEXT: - - - - - 1.00 2.00 - vle32.v v1, (a1)
# CHECK-NEXT: - - - - - 1.00 3.00 - vle64.v v1, (a1)
1,498 changes: 749 additions & 749 deletions llvm/test/tools/llvm-mca/RISCV/SiFive7/vector-integer-arithmetic.s
View file

Large diffs are not rendered by default.

16 changes: 8 additions & 8 deletions llvm/test/tools/llvm-mca/RISCV/different-lmul-instruments.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ vadd.vv v12, v12, v12
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.33
# CHECK-NEXT: IPC: 0.33
# CHECK-NEXT: Block RThroughput: 18.0
# CHECK-NEXT: Block RThroughput: 20.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -28,30 +28,30 @@ vadd.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 2.00 - 18.00 18.00 - -
# CHECK-NEXT: - - 2.00 - 20.00 2.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12

# CHECK: Timeline view:
# CHECK-NEXT: 01
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/tools/llvm-mca/RISCV/different-sew-instruments.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,13 +11,13 @@ vdiv.vv v8, v8, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 4
# CHECK-NEXT: Total Cycles: 358
# CHECK-NEXT: Total Cycles: 359
# CHECK-NEXT: Total uOps: 4

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.01
# CHECK-NEXT: IPC: 0.01
# CHECK-NEXT: Block RThroughput: 354.0
# CHECK-NEXT: Block RThroughput: 356.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -29,30 +29,30 @@ vdiv.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 240 241.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 114 115.00 vdiv.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 2.00 - 354.00 354.00 - -
# CHECK-NEXT: - - 2.00 - 356.00 2.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 0123
Expand Down
40 changes: 20 additions & 20 deletions llvm/test/tools/llvm-mca/RISCV/disable-im.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,13 +13,13 @@ vadd.vv v12, v12, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 6
# CHECK-NEXT: Total Cycles: 40
# CHECK-NEXT: Total Cycles: 42
# CHECK-NEXT: Total uOps: 6

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.15
# CHECK-NEXT: IPC: 0.15
# CHECK-NEXT: Block RThroughput: 48.0
# CHECK-NEXT: uOps Per Cycle: 0.14
# CHECK-NEXT: IPC: 0.14
# CHECK-NEXT: Block RThroughput: 51.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -31,45 +31,45 @@ vadd.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m2, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 3.00 - 48.00 48.00 - -
# CHECK-NEXT: - - 3.00 - 51.00 3.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m2, tu, mu
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12

# CHECK: Timeline view:
# CHECK-NEXT: 0123456789 0123456789
# CHECK-NEXT: Index 0123456789 0123456789
# CHECK-NEXT: Index 0123456789 0123456789 01

# CHECK: [0,0] DeeE . . . . . . . . vsetvli zero, a0, e8, m2, tu, mu
# CHECK-NEXT: [0,1] . DeeeE . . . . . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,2] . DeeE . . . . . . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,3] . . . . DeeeE . . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,4] . . . . DeeE . . . . vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: [0,5] . . . . . . . DeeeE vadd.vv v12, v12, v12
# CHECK: [0,0] DeeE . . . . . . . .. vsetvli zero, a0, e8, m2, tu, mu
# CHECK-NEXT: [0,1] . DeeeE . . . . . . .. vadd.vv v12, v12, v12
# CHECK-NEXT: [0,2] . DeeE . . . . . . .. vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,3] . . . . DeeeE. . . .. vadd.vv v12, v12, v12
# CHECK-NEXT: [0,4] . . . . .DeeE. . . .. vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: [0,5] . . . . . . . . DeeeE vadd.vv v12, v12, v12

# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/tools/llvm-mca/RISCV/fractional-lmul-data.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,13 +11,13 @@ vdiv.vv v12, v12, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 4
# CHECK-NEXT: Total Cycles: 90
# CHECK-NEXT: Total Cycles: 91
# CHECK-NEXT: Total uOps: 4

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.04
# CHECK-NEXT: IPC: 0.04
# CHECK-NEXT: Block RThroughput: 86.0
# CHECK-NEXT: Block RThroughput: 88.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -29,27 +29,27 @@ vdiv.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e32, mf2, tu, mu
# CHECK-NEXT: 1 56 56.00 vdiv.vv v12, v12, v12
# CHECK-NEXT: 1 56 57.00 vdiv.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, zero, e8, mf8, tu, mu
# CHECK-NEXT: 1 30 30.00 vdiv.vv v12, v12, v12
# CHECK-NEXT: 1 30 31.00 vdiv.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 2.00 - 86.00 86.00 - -
# CHECK-NEXT: - - 2.00 - 88.00 2.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e32, mf2, tu, mu
# CHECK-NEXT: - - - - 56.00 56.00 - - vdiv.vv v12, v12, v12
# CHECK-NEXT: - - - - 57.00 1.00 - - vdiv.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, zero, e8, mf8, tu, mu
# CHECK-NEXT: - - - - 30.00 30.00 - - vdiv.vv v12, v12, v12
# CHECK-NEXT: - - - - 31.00 1.00 - - vdiv.vv v12, v12, v12
12 changes: 6 additions & 6 deletions llvm/test/tools/llvm-mca/RISCV/lmul-instrument-at-start.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ vadd.vv v12, v12, v12
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.25
# CHECK-NEXT: IPC: 0.25
# CHECK-NEXT: Block RThroughput: 2.0
# CHECK-NEXT: Block RThroughput: 3.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -25,26 +25,26 @@ vadd.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 2.00 2.00 - -
# CHECK-NEXT: - - 1.00 - 3.00 1.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 01234567
Expand Down
26 changes: 13 additions & 13 deletions llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-middle.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,13 +8,13 @@ vadd.vv v12, v12, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 3
# CHECK-NEXT: Total Cycles: 21
# CHECK-NEXT: Total Cycles: 22
# CHECK-NEXT: Total uOps: 3

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.14
# CHECK-NEXT: IPC: 0.14
# CHECK-NEXT: Block RThroughput: 17.0
# CHECK-NEXT: Block RThroughput: 19.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -25,37 +25,37 @@ vadd.vv v12, v12, v12
# CHECK-NEXT: [6]: HasSideEffects (U)

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, mf8, tu, mu
# CHECK-NEXT: 1 4 1.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 17.00 17.00 - -
# CHECK-NEXT: - - 1.00 - 19.00 2.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, mf8, tu, mu
# CHECK-NEXT: - - - - 1.00 1.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 2.00 1.00 - - vadd.vv v12, v12, v12

# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK-NEXT: Index 0123456789 01

# CHECK: [0,0] DeeeE. . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,1] .DeeE. . . . vsetvli zero, a0, e8, mf8, tu, mu
# CHECK-NEXT: [0,2] . . . .DeeeE vadd.vv v12, v12, v12
# CHECK: [0,0] DeeeE. . . .. vadd.vv v12, v12, v12
# CHECK-NEXT: [0,1] .DeeE. . . .. vsetvli zero, a0, e8, mf8, tu, mu
# CHECK-NEXT: [0,2] . . . . DeeeE vadd.vv v12, v12, v12

# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/tools/llvm-mca/RISCV/lmul-instrument-in-region.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ vadd.vv v12, v12, v12
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.25
# CHECK-NEXT: IPC: 0.25
# CHECK-NEXT: Block RThroughput: 2.0
# CHECK-NEXT: Block RThroughput: 3.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -29,26 +29,26 @@ vadd.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 2.00 2.00 - -
# CHECK-NEXT: - - 1.00 - 3.00 1.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 01234567
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/tools/llvm-mca/RISCV/lmul-instrument-straddles-region.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ vadd.vv v12, v12, v12
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.25
# CHECK-NEXT: IPC: 0.25
# CHECK-NEXT: Block RThroughput: 2.0
# CHECK-NEXT: Block RThroughput: 3.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -30,26 +30,26 @@ vadd.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 2.00 2.00 - -
# CHECK-NEXT: - - 1.00 - 3.00 1.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 01234567
Expand Down
52 changes: 26 additions & 26 deletions llvm/test/tools/llvm-mca/RISCV/multiple-same-lmul-instruments.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,13 +15,13 @@ vsub.vv v12, v12, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 8
# CHECK-NEXT: Total Cycles: 28
# CHECK-NEXT: Total Cycles: 29
# CHECK-NEXT: Total uOps: 8

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.29
# CHECK-NEXT: IPC: 0.29
# CHECK-NEXT: Block RThroughput: 22.0
# CHECK-NEXT: uOps Per Cycle: 0.28
# CHECK-NEXT: IPC: 0.28
# CHECK-NEXT: Block RThroughput: 27.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -33,51 +33,51 @@ vsub.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 2.00 vsub.vv v12, v12, v12
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 3.00 vsub.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m4, tu, mu
# CHECK-NEXT: 1 4 8.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 8.00 vsub.vv v12, v12, v12
# CHECK-NEXT: 1 4 9.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 9.00 vsub.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 3.00 - 22.00 22.00 - -
# CHECK-NEXT: - - 3.00 - 27.00 5.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 2.00 2.00 - - vsub.vv v12, v12, v12
# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 3.00 1.00 - - vsub.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m4, tu, mu
# CHECK-NEXT: - - - - 8.00 8.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 8.00 8.00 - - vsub.vv v12, v12, v12
# CHECK-NEXT: - - - - 9.00 1.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 9.00 1.00 - - vsub.vv v12, v12, v12

# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 01234567
# CHECK-NEXT: Index 0123456789 012345678

# CHECK: [0,0] DeeE . . . . . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE . . . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,2] . DeeE . . . . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,3] . . DeeeE . . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,4] . . .DeeeE . . . vsub.vv v12, v12, v12
# CHECK-NEXT: [0,5] . . . DeeE . . . vsetvli zero, a0, e8, m4, tu, mu
# CHECK-NEXT: [0,6] . . . DeeeE. . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,7] . . . . . DeeeE vsub.vv v12, v12, v12
# CHECK: [0,0] DeeE . . . . . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,1] . DeeeE . . . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,2] . DeeE . . . . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,3] . . DeeeE . . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,4] . . .DeeeE . . . vsub.vv v12, v12, v12
# CHECK-NEXT: [0,5] . . . DeeE . . . vsetvli zero, a0, e8, m4, tu, mu
# CHECK-NEXT: [0,6] . . . DeeeE. . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,7] . . . . . DeeeE vsub.vv v12, v12, v12

# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
Expand Down
30 changes: 15 additions & 15 deletions llvm/test/tools/llvm-mca/RISCV/multiple-same-sew-instruments.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,13 +16,13 @@ vdivu.vv v8, v8, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 8
# CHECK-NEXT: Total Cycles: 570
# CHECK-NEXT: Total Cycles: 574
# CHECK-NEXT: Total uOps: 8

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.01
# CHECK-NEXT: IPC: 0.01
# CHECK-NEXT: Block RThroughput: 566.0
# CHECK-NEXT: Block RThroughput: 571.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -34,38 +34,38 @@ vdivu.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 114 115.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 114 114.00 vdivu.vv v8, v8, v12
# CHECK-NEXT: 1 114 115.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 114 115.00 vdivu.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e32, m1, tu, mu
# CHECK-NEXT: 1 112 112.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 112 112.00 vdivu.vv v8, v8, v12
# CHECK-NEXT: 1 112 113.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 112 113.00 vdivu.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 3.00 - 566.00 566.00 - -
# CHECK-NEXT: - - 3.00 - 571.00 5.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 114.00 114.00 - - vdivu.vv v8, v8, v12
# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 115.00 1.00 - - vdivu.vv v8, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e32, m1, tu, mu
# CHECK-NEXT: - - - - 112.00 112.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 112.00 112.00 - - vdivu.vv v8, v8, v12
# CHECK-NEXT: - - - - 113.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 113.00 1.00 - - vdivu.vv v8, v8, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 0123
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/tools/llvm-mca/RISCV/needs-sew-but-only-lmul.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,13 +10,13 @@ vdiv.vv v8, v8, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 3
# CHECK-NEXT: Total Cycles: 484
# CHECK-NEXT: Total Cycles: 485
# CHECK-NEXT: Total uOps: 3

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.01
# CHECK-NEXT: IPC: 0.01
# CHECK-NEXT: Block RThroughput: 480.0
# CHECK-NEXT: Block RThroughput: 482.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -28,28 +28,28 @@ vdiv.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 240 241.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 240 241.00 vdiv.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 480.00 480.00 - -
# CHECK-NEXT: - - 1.00 - 482.00 2.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 0123
Expand Down
26 changes: 13 additions & 13 deletions llvm/test/tools/llvm-mca/RISCV/no-vsetvli-to-start.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,13 +7,13 @@ vadd.vv v12, v12, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 3
# CHECK-NEXT: Total Cycles: 21
# CHECK-NEXT: Total Cycles: 22
# CHECK-NEXT: Total uOps: 3

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.14
# CHECK-NEXT: IPC: 0.14
# CHECK-NEXT: Block RThroughput: 18.0
# CHECK-NEXT: Block RThroughput: 20.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -24,37 +24,37 @@ vadd.vv v12, v12, v12
# CHECK-NEXT: [6]: HasSideEffects (U)

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 18.00 18.00 - -
# CHECK-NEXT: - - 1.00 - 20.00 2.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12

# CHECK: Timeline view:
# CHECK-NEXT: 0123456789
# CHECK-NEXT: Index 0123456789 0
# CHECK-NEXT: Index 0123456789 01

# CHECK: [0,0] DeeeE. . . . vadd.vv v12, v12, v12
# CHECK-NEXT: [0,1] .DeeE. . . . vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,2] . . . .DeeeE vadd.vv v12, v12, v12
# CHECK: [0,0] DeeeE. . . .. vadd.vv v12, v12, v12
# CHECK-NEXT: [0,1] .DeeE. . . .. vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: [0,2] . . . . DeeeE vadd.vv v12, v12, v12

# CHECK: Average Wait times (based on the timeline view):
# CHECK-NEXT: [0]: Executions
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/tools/llvm-mca/RISCV/sew-instrument-at-start.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ vdiv.vv v8, v8, v12
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.01
# CHECK-NEXT: IPC: 0.01
# CHECK-NEXT: Block RThroughput: 240.0
# CHECK-NEXT: Block RThroughput: 241.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -26,26 +26,26 @@ vdiv.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 240 241.00 vdiv.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 240.00 240.00 - -
# CHECK-NEXT: - - 1.00 - 241.00 1.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 0123
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-middle.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,13 +13,13 @@ vdiv.vv v8, v8, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 3
# CHECK-NEXT: Total Cycles: 2833
# CHECK-NEXT: Total Cycles: 2834
# CHECK-NEXT: Total uOps: 3

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.00
# CHECK-NEXT: IPC: 0.00
# CHECK-NEXT: Block RThroughput: 2832.0
# CHECK-NEXT: Block RThroughput: 2834.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -30,29 +30,29 @@ vdiv.vv v8, v8, v12
# CHECK-NEXT: [6]: HasSideEffects (U)

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 1920 1920.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 1920 1921.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 1 912 912.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 912 913.00 vdiv.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 2832.00 2832.00 - -
# CHECK-NEXT: - - 1.00 - 2834.00 2.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - - - 1920.00 1920.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 1921.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: - - - - 912.00 912.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 913.00 1.00 - - vdiv.vv v8, v8, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 0
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/tools/llvm-mca/RISCV/sew-instrument-in-region.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ vdiv.vv v8, v8, v12
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.02
# CHECK-NEXT: IPC: 0.02
# CHECK-NEXT: Block RThroughput: 114.0
# CHECK-NEXT: Block RThroughput: 115.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -30,26 +30,26 @@ vdiv.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 114 115.00 vdiv.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 114.00 114.00 - -
# CHECK-NEXT: - - 1.00 - 115.00 1.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 0123
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/tools/llvm-mca/RISCV/sew-instrument-straddles-region.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,7 +19,7 @@ vdiv.vv v8, v8, v12
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.02
# CHECK-NEXT: IPC: 0.02
# CHECK-NEXT: Block RThroughput: 114.0
# CHECK-NEXT: Block RThroughput: 115.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -31,26 +31,26 @@ vdiv.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: 1 114 114.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 114 115.00 vdiv.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 1.00 - 114.00 114.00 - -
# CHECK-NEXT: - - 1.00 - 115.00 1.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e64, m1, tu, mu
# CHECK-NEXT: - - - - 114.00 114.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 115.00 1.00 - - vdiv.vv v8, v8, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 0123
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814 changes: 407 additions & 407 deletions llvm/test/tools/llvm-mca/RISCV/vle-vse.s
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Large diffs are not rendered by default.

16 changes: 8 additions & 8 deletions llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-instrument.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ vadd.vv v12, v12, v12
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.33
# CHECK-NEXT: IPC: 0.33
# CHECK-NEXT: Block RThroughput: 18.0
# CHECK-NEXT: Block RThroughput: 20.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -26,30 +26,30 @@ vadd.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e8, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 2.00 - 18.00 18.00 - -
# CHECK-NEXT: - - 2.00 - 20.00 2.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e8, m8, tu, mu
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12

# CHECK: Timeline view:
# CHECK-NEXT: 01
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/tools/llvm-mca/RISCV/vsetivli-lmul-sew-instrument.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,13 +8,13 @@ vdiv.vv v8, v8, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 4
# CHECK-NEXT: Total Cycles: 1140
# CHECK-NEXT: Total Cycles: 1141
# CHECK-NEXT: Total uOps: 4

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.00
# CHECK-NEXT: IPC: 0.00
# CHECK-NEXT: Block RThroughput: 1136.0
# CHECK-NEXT: Block RThroughput: 1138.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -26,30 +26,30 @@ vdiv.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e8, m1, tu, mu
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 240 241.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetivli zero, 8, e32, m8, tu, mu
# CHECK-NEXT: 1 896 896.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 896 897.00 vdiv.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 2.00 - 1136.00 1136.00 - -
# CHECK-NEXT: - - 2.00 - 1138.00 2.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e8, m1, tu, mu
# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetivli zero, 8, e32, m8, tu, mu
# CHECK-NEXT: - - - - 896.00 896.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 897.00 1.00 - - vdiv.vv v8, v8, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 0123
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-instrument.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,7 +14,7 @@ vadd.vv v12, v12, v12
# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.33
# CHECK-NEXT: IPC: 0.33
# CHECK-NEXT: Block RThroughput: 18.0
# CHECK-NEXT: Block RThroughput: 20.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -26,30 +26,30 @@ vadd.vv v12, v12, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 4 2.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 3.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: 1 4 16.00 vadd.vv v12, v12, v12
# CHECK-NEXT: 1 4 17.00 vadd.vv v12, v12, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 2.00 - 18.00 18.00 - -
# CHECK-NEXT: - - 2.00 - 20.00 2.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 2.00 2.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 3.00 1.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m8, tu, mu
# CHECK-NEXT: - - - - 16.00 16.00 - - vadd.vv v12, v12, v12
# CHECK-NEXT: - - - - 17.00 1.00 - - vadd.vv v12, v12, v12

# CHECK: Timeline view:
# CHECK-NEXT: 01
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/tools/llvm-mca/RISCV/vsetvli-lmul-sew-instrument.s
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,13 +8,13 @@ vdiv.vv v8, v8, v12

# CHECK: Iterations: 1
# CHECK-NEXT: Instructions: 4
# CHECK-NEXT: Total Cycles: 1140
# CHECK-NEXT: Total Cycles: 1141
# CHECK-NEXT: Total uOps: 4

# CHECK: Dispatch Width: 2
# CHECK-NEXT: uOps Per Cycle: 0.00
# CHECK-NEXT: IPC: 0.00
# CHECK-NEXT: Block RThroughput: 1136.0
# CHECK-NEXT: Block RThroughput: 1138.0

# CHECK: Instruction Info:
# CHECK-NEXT: [1]: #uOps
Expand All @@ -26,30 +26,30 @@ vdiv.vv v8, v8, v12

# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: 1 240 240.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 240 241.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 3 1.00 U vsetvli zero, a0, e32, m8, tu, mu
# CHECK-NEXT: 1 896 896.00 vdiv.vv v8, v8, v12
# CHECK-NEXT: 1 896 897.00 vdiv.vv v8, v8, v12

# CHECK: Resources:
# CHECK-NEXT: [0] - SiFive7FDiv
# CHECK-NEXT: [1] - SiFive7IDiv
# CHECK-NEXT: [2] - SiFive7PipeA
# CHECK-NEXT: [3] - SiFive7PipeB
# CHECK-NEXT: [4] - SiFive7PipeV
# CHECK-NEXT: [5] - SiFive7VA
# CHECK-NEXT: [4] - SiFive7VA
# CHECK-NEXT: [5] - SiFive7VCQ
# CHECK-NEXT: [6] - SiFive7VL
# CHECK-NEXT: [7] - SiFive7VS

# CHECK: Resource pressure per iteration:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7]
# CHECK-NEXT: - - 2.00 - 1136.00 1136.00 - -
# CHECK-NEXT: - - 2.00 - 1138.00 2.00 - -

# CHECK: Resource pressure by instruction:
# CHECK-NEXT: [0] [1] [2] [3] [4] [5] [6] [7] Instructions:
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e8, m1, tu, mu
# CHECK-NEXT: - - - - 240.00 240.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 241.00 1.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - 1.00 - - - - - vsetvli zero, a0, e32, m8, tu, mu
# CHECK-NEXT: - - - - 896.00 896.00 - - vdiv.vv v8, v8, v12
# CHECK-NEXT: - - - - 897.00 1.00 - - vdiv.vv v8, v8, v12

# CHECK: Timeline view:
# CHECK-NEXT: Index 0123
Expand Down
1 change: 1 addition & 0 deletions llvm/utils/gn/secondary/llvm/test/BUILD.gn
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Original file line number Diff line number Diff line change
Expand Up @@ -65,6 +65,7 @@ write_lit_config("lit_site_cfg") {
"LLVM_HAVE_OPT_VIEWER_MODULES=0",
"LLVM_HOST_TRIPLE=$llvm_current_triple",
"LLVM_INCLUDE_DXIL_TESTS=0",
"LLVM_INCLUDE_SPIRV_TOOLS_TESTS=0",
"LLVM_LIBS_DIR=" + rebase_path("$root_out_dir/lib", dir),
"LLVM_LINK_LLVM_DYLIB=0",
"LLVM_LIT_TOOLS_DIR=", # Intentionally empty, matches cmake build.
Expand Down
1 change: 1 addition & 0 deletions mlir/lib/Dialect/Mesh/IR/CMakeLists.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -13,4 +13,5 @@ add_mlir_dialect_library(MLIRMeshDialect
MLIRArithDialect
MLIRIR
MLIRSupport
MLIRViewLikeInterface
)
2 changes: 1 addition & 1 deletion polly/lib/External/isl/interface/extract_interface.cc
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Original file line number Diff line number Diff line change
Expand Up @@ -47,8 +47,8 @@
#endif
#include <llvm/Support/raw_ostream.h>
#include <llvm/Support/CommandLine.h>
#include <llvm/Support/Host.h>
#include <llvm/Support/ManagedStatic.h>
#include <llvm/TargetParser/Host.h>
#include <clang/AST/ASTContext.h>
#include <clang/AST/ASTConsumer.h>
#include <clang/Basic/Builtins.h>
Expand Down
1 change: 1 addition & 0 deletions utils/bazel/llvm-project-overlay/mlir/BUILD.bazel
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Original file line number Diff line number Diff line change
Expand Up @@ -3237,6 +3237,7 @@ cc_library(
":InferTypeOpInterface",
":MeshIncGen",
":Support",
":ViewLikeInterface",
"//llvm:Support",
],
)
Expand Down