40 changes: 20 additions & 20 deletions llvm/test/CodeGen/ARM/neon_vabd.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -144,25 +144,25 @@ define <2 x i64> @sabd_2d(<2 x i64> %a, <2 x i64> %b) {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, lr}
; CHECK-NEXT: push {r4, r5, r6, lr}
; CHECK-NEXT: vmov r0, r12, d0
; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: mov r6, #0
; CHECK-NEXT: vmov r2, r3, d2
; CHECK-NEXT: vmov r1, lr, d1
; CHECK-NEXT: vmov r4, r5, d3
; CHECK-NEXT: vmov r2, r3, d3
; CHECK-NEXT: vmov r12, lr, d0
; CHECK-NEXT: vmov r4, r5, d2
; CHECK-NEXT: vsub.i64 q8, q0, q1
; CHECK-NEXT: subs r0, r2, r0
; CHECK-NEXT: sbcs r0, r3, r12
; CHECK-NEXT: sbcs r0, r3, r1
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: movwlt r0, #1
; CHECK-NEXT: subs r1, r4, r1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mvnne r0, #0
; CHECK-NEXT: subs r1, r4, r12
; CHECK-NEXT: sbcs r1, r5, lr
; CHECK-NEXT: vdup.32 d19, r0
; CHECK-NEXT: movwlt r6, #1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: mvnne r6, #0
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vdup.32 d19, r6
; CHECK-NEXT: mvnne r0, #0
; CHECK-NEXT: vdup.32 d18, r0
; CHECK-NEXT: vdup.32 d18, r6
; CHECK-NEXT: veor q8, q8, q9
; CHECK-NEXT: vsub.i64 q0, q9, q8
; CHECK-NEXT: pop {r4, r5, r6, pc}
Expand Down Expand Up @@ -475,25 +475,25 @@ define <2 x i64> @smaxmin_v2i64(<2 x i64> %0, <2 x i64> %1) {
; CHECK: @ %bb.0:
; CHECK-NEXT: .save {r4, r5, r6, lr}
; CHECK-NEXT: push {r4, r5, r6, lr}
; CHECK-NEXT: vmov r0, r12, d0
; CHECK-NEXT: vmov r0, r1, d1
; CHECK-NEXT: mov r6, #0
; CHECK-NEXT: vmov r2, r3, d2
; CHECK-NEXT: vmov r1, lr, d1
; CHECK-NEXT: vmov r4, r5, d3
; CHECK-NEXT: vmov r2, r3, d3
; CHECK-NEXT: vmov r12, lr, d0
; CHECK-NEXT: vmov r4, r5, d2
; CHECK-NEXT: vsub.i64 q8, q0, q1
; CHECK-NEXT: subs r0, r2, r0
; CHECK-NEXT: sbcs r0, r3, r12
; CHECK-NEXT: sbcs r0, r3, r1
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: movwlt r0, #1
; CHECK-NEXT: subs r1, r4, r1
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: mvnne r0, #0
; CHECK-NEXT: subs r1, r4, r12
; CHECK-NEXT: sbcs r1, r5, lr
; CHECK-NEXT: vdup.32 d19, r0
; CHECK-NEXT: movwlt r6, #1
; CHECK-NEXT: cmp r6, #0
; CHECK-NEXT: mvnne r6, #0
; CHECK-NEXT: cmp r0, #0
; CHECK-NEXT: vdup.32 d19, r6
; CHECK-NEXT: mvnne r0, #0
; CHECK-NEXT: vdup.32 d18, r0
; CHECK-NEXT: vdup.32 d18, r6
; CHECK-NEXT: veor q8, q8, q9
; CHECK-NEXT: vsub.i64 q0, q9, q8
; CHECK-NEXT: pop {r4, r5, r6, pc}
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/ARM/overflow-intrinsic-optimizations.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -164,9 +164,9 @@ cont2:

define void @extern_loop(i32 %n) local_unnamed_addr #0 {
; Do not replace the compare around the clobbering call.
; CHECK: add {{r[0-9]+}}, {{r[0-9]+}}, #1
; CHECK-NEXT: bl external_fn
; CHECK: cmp
; CHECK: bl external_fn
; CHECK-NEXT: adds
; CHECK-NEXT: bvs
entry:
%0 = tail call { i32, i1 } @llvm.ssub.with.overflow.i32(i32 %n, i32 1)
%1 = extractvalue { i32, i1 } %0, 1
Expand Down
44 changes: 21 additions & 23 deletions llvm/test/CodeGen/ARM/sadd_sat.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -72,22 +72,21 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-T16-NEXT: adcs r3, r4
; CHECK-T16-NEXT: eors r4, r3
; CHECK-T16-NEXT: bics r4, r1
; CHECK-T16-NEXT: asrs r1, r3, #31
; CHECK-T16-NEXT: asrs r0, r3, #31
; CHECK-T16-NEXT: movs r1, #1
; CHECK-T16-NEXT: lsls r1, r1, #31
; CHECK-T16-NEXT: eors r1, r0
; CHECK-T16-NEXT: cmp r4, #0
; CHECK-T16-NEXT: mov r0, r1
; CHECK-T16-NEXT: bmi .LBB1_2
; CHECK-T16-NEXT: bpl .LBB1_3
; CHECK-T16-NEXT: @ %bb.1:
; CHECK-T16-NEXT: mov r0, r2
; CHECK-T16-NEXT: bpl .LBB1_4
; CHECK-T16-NEXT: .LBB1_2:
; CHECK-T16-NEXT: cmp r4, #0
; CHECK-T16-NEXT: bmi .LBB1_4
; CHECK-T16-NEXT: @ %bb.3:
; CHECK-T16-NEXT: mov r1, r3
; CHECK-T16-NEXT: pop {r4, pc}
; CHECK-T16-NEXT: .LBB1_3:
; CHECK-T16-NEXT: mov r0, r2
; CHECK-T16-NEXT: bmi .LBB1_2
; CHECK-T16-NEXT: .LBB1_4:
; CHECK-T16-NEXT: movs r2, #1
; CHECK-T16-NEXT: lsls r2, r2, #31
; CHECK-T16-NEXT: eors r1, r2
; CHECK-T16-NEXT: mov r1, r3
; CHECK-T16-NEXT: pop {r4, pc}
;
; CHECK-T2-LABEL: func2:
Expand Down Expand Up @@ -128,23 +127,22 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-T15TE-NEXT: adcs r3, r4
; CHECK-T15TE-NEXT: eors r4, r3
; CHECK-T15TE-NEXT: bics r4, r1
; CHECK-T15TE-NEXT: asrs r1, r3, #31
; CHECK-T15TE-NEXT: asrs r0, r3, #31
; CHECK-T15TE-NEXT: movs r1, #1
; CHECK-T15TE-NEXT: lsls r1, r1, #31
; CHECK-T15TE-NEXT: eors r1, r0
; CHECK-T15TE-NEXT: cmp r4, #0
; CHECK-T15TE-NEXT: mov r12, r1
; CHECK-T15TE-NEXT: mov r0, r12
; CHECK-T15TE-NEXT: bmi .LBB1_2
; CHECK-T15TE-NEXT: bpl .LBB1_3
; CHECK-T15TE-NEXT: @ %bb.1:
; CHECK-T15TE-NEXT: movs r0, r2
; CHECK-T15TE-NEXT: bpl .LBB1_4
; CHECK-T15TE-NEXT: .LBB1_2:
; CHECK-T15TE-NEXT: cmp r4, #0
; CHECK-T15TE-NEXT: bmi .LBB1_4
; CHECK-T15TE-NEXT: @ %bb.3:
; CHECK-T15TE-NEXT: movs r1, r3
; CHECK-T15TE-NEXT: pop {r4, pc}
; CHECK-T15TE-NEXT: .LBB1_3:
; CHECK-T15TE-NEXT: mov r12, r2
; CHECK-T15TE-NEXT: mov r0, r12
; CHECK-T15TE-NEXT: bmi .LBB1_2
; CHECK-T15TE-NEXT: .LBB1_4:
; CHECK-T15TE-NEXT: movs r2, #1
; CHECK-T15TE-NEXT: lsls r2, r2, #31
; CHECK-T15TE-NEXT: eors r1, r2
; CHECK-T15TE-NEXT: movs r1, r3
; CHECK-T15TE-NEXT: pop {r4, pc}
%tmp = call i64 @llvm.sadd.sat.i64(i64 %x, i64 %y)
ret i64 %tmp
Expand Down
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/ARM/sadd_sat_plus.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -63,22 +63,22 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; CHECK-T1-NEXT: adcs r3, r1
; CHECK-T1-NEXT: eors r1, r3
; CHECK-T1-NEXT: bics r1, r2
; CHECK-T1-NEXT: asrs r2, r3, #31
; CHECK-T1-NEXT: asrs r0, r3, #31
; CHECK-T1-NEXT: movs r2, #1
; CHECK-T1-NEXT: lsls r2, r2, #31
; CHECK-T1-NEXT: eors r2, r0
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: mov r0, r2
; CHECK-T1-NEXT: bmi .LBB1_2
; CHECK-T1-NEXT: bpl .LBB1_3
; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: mov r0, r4
; CHECK-T1-NEXT: bpl .LBB1_4
; CHECK-T1-NEXT: .LBB1_2:
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: bmi .LBB1_4
; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r1, r3
; CHECK-T1-NEXT: mov r1, r2
; CHECK-T1-NEXT: pop {r4, pc}
; CHECK-T1-NEXT: .LBB1_3:
; CHECK-T1-NEXT: mov r0, r4
; CHECK-T1-NEXT: bmi .LBB1_2
; CHECK-T1-NEXT: .LBB1_4:
; CHECK-T1-NEXT: movs r1, #1
; CHECK-T1-NEXT: lsls r1, r1, #31
; CHECK-T1-NEXT: eors r2, r1
; CHECK-T1-NEXT: mov r2, r3
; CHECK-T1-NEXT: mov r1, r2
; CHECK-T1-NEXT: pop {r4, pc}
;
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/ARM/select.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -320,11 +320,11 @@ define float @f10(i32 %a, i32 %b) nounwind uwtable readnone ssp {
;
; CHECK-VFP-LABEL: f10:
; CHECK-VFP: @ %bb.0:
; CHECK-VFP-NEXT: vmov.f32 s2, #1.000000e+00
; CHECK-VFP-NEXT: vldr s0, .LCPI9_0
; CHECK-VFP-NEXT: vmov.f32 s0, #1.000000e+00
; CHECK-VFP-NEXT: vldr s2, .LCPI9_0
; CHECK-VFP-NEXT: cmp r0, r1
; CHECK-VFP-NEXT: vmoveq.f32 s0, s2
; CHECK-VFP-NEXT: vmov r0, s0
; CHECK-VFP-NEXT: vmoveq.f32 s2, s0
; CHECK-VFP-NEXT: vmov r0, s2
; CHECK-VFP-NEXT: bx lr
; CHECK-VFP-NEXT: .p2align 2
; CHECK-VFP-NEXT: @ %bb.1:
Expand All @@ -333,12 +333,12 @@ define float @f10(i32 %a, i32 %b) nounwind uwtable readnone ssp {
;
; CHECK-NEON-LABEL: f10:
; CHECK-NEON: @ %bb.0:
; CHECK-NEON-NEXT: vldr s0, LCPI9_0
; CHECK-NEON-NEXT: vmov.f32 s2, #1.000000e+00
; CHECK-NEON-NEXT: vldr s2, LCPI9_0
; CHECK-NEON-NEXT: vmov.f32 s0, #1.000000e+00
; CHECK-NEON-NEXT: cmp r0, r1
; CHECK-NEON-NEXT: it eq
; CHECK-NEON-NEXT: vmoveq.f32 s0, s2
; CHECK-NEON-NEXT: vmov r0, s0
; CHECK-NEON-NEXT: vmoveq.f32 s2, s0
; CHECK-NEON-NEXT: vmov r0, s2
; CHECK-NEON-NEXT: bx lr
; CHECK-NEON-NEXT: .p2align 2
; CHECK-NEON-NEXT: @ %bb.1:
Expand All @@ -364,11 +364,11 @@ define float @f11(i32 %a, i32 %b) nounwind uwtable readnone ssp {
;
; CHECK-VFP-LABEL: f11:
; CHECK-VFP: @ %bb.0:
; CHECK-VFP-NEXT: vmov.f32 s2, #-1.000000e+00
; CHECK-VFP-NEXT: vldr s0, .LCPI10_0
; CHECK-VFP-NEXT: vmov.f32 s0, #-1.000000e+00
; CHECK-VFP-NEXT: vldr s2, .LCPI10_0
; CHECK-VFP-NEXT: cmp r0, r1
; CHECK-VFP-NEXT: vmoveq.f32 s0, s2
; CHECK-VFP-NEXT: vmov r0, s0
; CHECK-VFP-NEXT: vmoveq.f32 s2, s0
; CHECK-VFP-NEXT: vmov r0, s2
; CHECK-VFP-NEXT: bx lr
; CHECK-VFP-NEXT: .p2align 2
; CHECK-VFP-NEXT: @ %bb.1:
Expand All @@ -377,12 +377,12 @@ define float @f11(i32 %a, i32 %b) nounwind uwtable readnone ssp {
;
; CHECK-NEON-LABEL: f11:
; CHECK-NEON: @ %bb.0:
; CHECK-NEON-NEXT: vldr s0, LCPI10_0
; CHECK-NEON-NEXT: vmov.f32 s2, #-1.000000e+00
; CHECK-NEON-NEXT: vldr s2, LCPI10_0
; CHECK-NEON-NEXT: vmov.f32 s0, #-1.000000e+00
; CHECK-NEON-NEXT: cmp r0, r1
; CHECK-NEON-NEXT: it eq
; CHECK-NEON-NEXT: vmoveq.f32 s0, s2
; CHECK-NEON-NEXT: vmov r0, s0
; CHECK-NEON-NEXT: vmoveq.f32 s2, s0
; CHECK-NEON-NEXT: vmov r0, s2
; CHECK-NEON-NEXT: bx lr
; CHECK-NEON-NEXT: .p2align 2
; CHECK-NEON-NEXT: @ %bb.1:
Expand All @@ -406,11 +406,11 @@ define float @f12(i32 %a, i32 %b) nounwind uwtable readnone ssp {
;
; CHECK-VFP-LABEL: f12:
; CHECK-VFP: @ %bb.0:
; CHECK-VFP-NEXT: vmov.f32 s2, #1.000000e+00
; CHECK-VFP-NEXT: vldr s0, .LCPI11_0
; CHECK-VFP-NEXT: vmov.f32 s0, #1.000000e+00
; CHECK-VFP-NEXT: vldr s2, .LCPI11_0
; CHECK-VFP-NEXT: cmp r0, r1
; CHECK-VFP-NEXT: vmoveq.f32 s0, s2
; CHECK-VFP-NEXT: vmov r0, s0
; CHECK-VFP-NEXT: vmoveq.f32 s2, s0
; CHECK-VFP-NEXT: vmov r0, s2
; CHECK-VFP-NEXT: bx lr
; CHECK-VFP-NEXT: .p2align 2
; CHECK-VFP-NEXT: @ %bb.1:
Expand All @@ -419,12 +419,12 @@ define float @f12(i32 %a, i32 %b) nounwind uwtable readnone ssp {
;
; CHECK-NEON-LABEL: f12:
; CHECK-NEON: @ %bb.0:
; CHECK-NEON-NEXT: vldr s0, LCPI11_0
; CHECK-NEON-NEXT: vmov.f32 s2, #1.000000e+00
; CHECK-NEON-NEXT: vldr s2, LCPI11_0
; CHECK-NEON-NEXT: vmov.f32 s0, #1.000000e+00
; CHECK-NEON-NEXT: cmp r0, r1
; CHECK-NEON-NEXT: it eq
; CHECK-NEON-NEXT: vmoveq.f32 s0, s2
; CHECK-NEON-NEXT: vmov r0, s0
; CHECK-NEON-NEXT: vmoveq.f32 s2, s0
; CHECK-NEON-NEXT: vmov r0, s2
; CHECK-NEON-NEXT: bx lr
; CHECK-NEON-NEXT: .p2align 2
; CHECK-NEON-NEXT: @ %bb.1:
Expand Down
12 changes: 7 additions & 5 deletions llvm/test/CodeGen/ARM/select_const.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -645,12 +645,13 @@ define i64 @opaque_constant1(i1 %cond, i64 %x) {
; THUMB2-NEXT: push {r7, lr}
; THUMB2-NEXT: ands r12, r0, #1
; THUMB2-NEXT: mov.w lr, #1
; THUMB2-NEXT: itt ne
; THUMB2-NEXT: movne.w lr, #65536
; THUMB2-NEXT: it ne
; THUMB2-NEXT: movne.w r12, #1
; THUMB2-NEXT: it ne
; THUMB2-NEXT: movne.w lr, #65536
; THUMB2-NEXT: subs.w r0, lr, #1
; THUMB2-NEXT: sbc r1, r12, #0
; THUMB2-NEXT: eor r3, r3, #1
; THUMB2-NEXT: sbc r1, r12, #0
; THUMB2-NEXT: eor r2, r2, #65537
; THUMB2-NEXT: orrs r2, r3
; THUMB2-NEXT: itt ne
Expand Down Expand Up @@ -688,11 +689,12 @@ define i64 @opaque_constant1(i1 %cond, i64 %x) {
; THUMB-NEXT: ldr r6, .LCPI24_0
; THUMB-NEXT: eors r2, r6
; THUMB-NEXT: orrs r2, r3
; THUMB-NEXT: cmp r2, #0
; THUMB-NEXT: beq .LBB24_5
; THUMB-NEXT: @ %bb.4:
; THUMB-NEXT: movs r1, r4
; THUMB-NEXT: mov r12, r4
; THUMB-NEXT: mov r1, r12
; THUMB-NEXT: .LBB24_5:
; THUMB-NEXT: cmp r2, #0
; THUMB-NEXT: beq .LBB24_7
; THUMB-NEXT: @ %bb.6:
; THUMB-NEXT: movs r0, r5
Expand Down
14 changes: 7 additions & 7 deletions llvm/test/CodeGen/ARM/shift-i64.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -52,14 +52,14 @@ define i64 @test_lshr(i64 %val, i64 %amt) {
define i64 @test_ashr(i64 %val, i64 %amt) {
; CHECK-LABEL: test_ashr:
; CHECK: @ %bb.0:
; CHECK-NEXT: asr r3, r1, r2
; CHECK-NEXT: subs r12, r2, #32
; CHECK-NEXT: rsb r3, r2, #32
; CHECK-NEXT: lsr r0, r0, r2
; CHECK-NEXT: rsb r2, r2, #32
; CHECK-NEXT: asrpl r3, r1, #31
; CHECK-NEXT: orr r0, r0, r1, lsl r2
; CHECK-NEXT: asrpl r0, r1, r12
; CHECK-NEXT: mov r1, r3
; CHECK-NEXT: orr r0, r0, r1, lsl r3
; CHECK-NEXT: subs r3, r2, #32
; CHECK-NEXT: asr r2, r1, r2
; CHECK-NEXT: asrpl r2, r1, #31
; CHECK-NEXT: asrpl r0, r1, r3
; CHECK-NEXT: mov r1, r2
; CHECK-NEXT: mov pc, lr
;
; EXPAND-LABEL: test_ashr:
Expand Down
21 changes: 10 additions & 11 deletions llvm/test/CodeGen/ARM/ssub_sat.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -71,22 +71,21 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-T1-NEXT: sbcs r2, r3
; CHECK-T1-NEXT: eors r4, r2
; CHECK-T1-NEXT: ands r4, r1
; CHECK-T1-NEXT: asrs r1, r2, #31
; CHECK-T1-NEXT: asrs r0, r2, #31
; CHECK-T1-NEXT: movs r1, #1
; CHECK-T1-NEXT: lsls r1, r1, #31
; CHECK-T1-NEXT: eors r1, r0
; CHECK-T1-NEXT: cmp r4, #0
; CHECK-T1-NEXT: mov r0, r1
; CHECK-T1-NEXT: bmi .LBB1_2
; CHECK-T1-NEXT: bpl .LBB1_3
; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: mov r0, r5
; CHECK-T1-NEXT: bpl .LBB1_4
; CHECK-T1-NEXT: .LBB1_2:
; CHECK-T1-NEXT: cmp r4, #0
; CHECK-T1-NEXT: bmi .LBB1_4
; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r1, r2
; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
; CHECK-T1-NEXT: .LBB1_3:
; CHECK-T1-NEXT: mov r0, r5
; CHECK-T1-NEXT: bmi .LBB1_2
; CHECK-T1-NEXT: .LBB1_4:
; CHECK-T1-NEXT: movs r2, #1
; CHECK-T1-NEXT: lsls r2, r2, #31
; CHECK-T1-NEXT: eors r1, r2
; CHECK-T1-NEXT: mov r1, r2
; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
;
; CHECK-T2-LABEL: func2:
Expand Down
22 changes: 11 additions & 11 deletions llvm/test/CodeGen/ARM/ssub_sat_plus.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -65,22 +65,22 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; CHECK-T1-NEXT: sbcs r3, r2
; CHECK-T1-NEXT: eors r1, r3
; CHECK-T1-NEXT: ands r1, r5
; CHECK-T1-NEXT: asrs r2, r3, #31
; CHECK-T1-NEXT: asrs r0, r3, #31
; CHECK-T1-NEXT: movs r2, #1
; CHECK-T1-NEXT: lsls r2, r2, #31
; CHECK-T1-NEXT: eors r2, r0
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: mov r0, r2
; CHECK-T1-NEXT: bmi .LBB1_2
; CHECK-T1-NEXT: bpl .LBB1_3
; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: mov r0, r4
; CHECK-T1-NEXT: bpl .LBB1_4
; CHECK-T1-NEXT: .LBB1_2:
; CHECK-T1-NEXT: cmp r1, #0
; CHECK-T1-NEXT: bmi .LBB1_4
; CHECK-T1-NEXT: @ %bb.3:
; CHECK-T1-NEXT: mov r1, r3
; CHECK-T1-NEXT: mov r1, r2
; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
; CHECK-T1-NEXT: .LBB1_3:
; CHECK-T1-NEXT: mov r0, r4
; CHECK-T1-NEXT: bmi .LBB1_2
; CHECK-T1-NEXT: .LBB1_4:
; CHECK-T1-NEXT: movs r1, #1
; CHECK-T1-NEXT: lsls r1, r1, #31
; CHECK-T1-NEXT: eors r2, r1
; CHECK-T1-NEXT: mov r2, r3
; CHECK-T1-NEXT: mov r1, r2
; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
;
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/ARM/sub-cmp-peephole.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -136,8 +136,8 @@ define float @float_sel(i32 %a, i32 %b, float %x, float %y) {
;
; CHECK-V8-LABEL: float_sel:
; CHECK-V8: @ %bb.0: @ %entry
; CHECK-V8-NEXT: vmov s0, r3
; CHECK-V8-NEXT: subs r0, r0, r1
; CHECK-V8-NEXT: vmov s0, r3
; CHECK-V8-NEXT: vmov s2, r2
; CHECK-V8-NEXT: vseleq.f32 s0, s2, s0
; CHECK-V8-NEXT: vmov r0, s0
Expand Down
8 changes: 3 additions & 5 deletions llvm/test/CodeGen/ARM/uadd_sat.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -45,21 +45,19 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-T1-NEXT: movs r5, #0
; CHECK-T1-NEXT: adds r4, r0, r2
; CHECK-T1-NEXT: adcs r1, r3
; CHECK-T1-NEXT: mov r3, r5
; CHECK-T1-NEXT: adcs r3, r5
; CHECK-T1-NEXT: mov r0, r5
; CHECK-T1-NEXT: adcs r0, r5
; CHECK-T1-NEXT: mvns r2, r5
; CHECK-T1-NEXT: cmp r3, #0
; CHECK-T1-NEXT: cmp r0, #0
; CHECK-T1-NEXT: mov r0, r2
; CHECK-T1-NEXT: beq .LBB1_3
; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: cmp r3, #0
; CHECK-T1-NEXT: beq .LBB1_4
; CHECK-T1-NEXT: .LBB1_2:
; CHECK-T1-NEXT: mov r1, r2
; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
; CHECK-T1-NEXT: .LBB1_3:
; CHECK-T1-NEXT: mov r0, r4
; CHECK-T1-NEXT: cmp r3, #0
; CHECK-T1-NEXT: bne .LBB1_2
; CHECK-T1-NEXT: .LBB1_4:
; CHECK-T1-NEXT: mov r2, r1
Expand Down
24 changes: 11 additions & 13 deletions llvm/test/CodeGen/ARM/uadd_sat_plus.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -44,31 +44,29 @@ define i32 @func32(i32 %x, i32 %y, i32 %z) nounwind {
define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; CHECK-T1-LABEL: func64:
; CHECK-T1: @ %bb.0:
; CHECK-T1-NEXT: .save {r4, r5, r7, lr}
; CHECK-T1-NEXT: push {r4, r5, r7, lr}
; CHECK-T1-NEXT: movs r5, #0
; CHECK-T1-NEXT: ldr r2, [sp, #20]
; CHECK-T1-NEXT: ldr r3, [sp, #16]
; CHECK-T1-NEXT: .save {r4, lr}
; CHECK-T1-NEXT: push {r4, lr}
; CHECK-T1-NEXT: movs r4, #0
; CHECK-T1-NEXT: ldr r2, [sp, #12]
; CHECK-T1-NEXT: ldr r3, [sp, #8]
; CHECK-T1-NEXT: adds r3, r0, r3
; CHECK-T1-NEXT: adcs r2, r1
; CHECK-T1-NEXT: mov r4, r5
; CHECK-T1-NEXT: adcs r4, r5
; CHECK-T1-NEXT: mvns r1, r5
; CHECK-T1-NEXT: cmp r4, #0
; CHECK-T1-NEXT: mov r0, r4
; CHECK-T1-NEXT: adcs r0, r4
; CHECK-T1-NEXT: mvns r1, r4
; CHECK-T1-NEXT: cmp r0, #0
; CHECK-T1-NEXT: mov r0, r1
; CHECK-T1-NEXT: beq .LBB1_3
; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: cmp r4, #0
; CHECK-T1-NEXT: beq .LBB1_4
; CHECK-T1-NEXT: .LBB1_2:
; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
; CHECK-T1-NEXT: pop {r4, pc}
; CHECK-T1-NEXT: .LBB1_3:
; CHECK-T1-NEXT: mov r0, r3
; CHECK-T1-NEXT: cmp r4, #0
; CHECK-T1-NEXT: bne .LBB1_2
; CHECK-T1-NEXT: .LBB1_4:
; CHECK-T1-NEXT: mov r1, r2
; CHECK-T1-NEXT: pop {r4, r5, r7, pc}
; CHECK-T1-NEXT: pop {r4, pc}
;
; CHECK-T2-LABEL: func64:
; CHECK-T2: @ %bb.0:
Expand Down
322 changes: 162 additions & 160 deletions llvm/test/CodeGen/ARM/umulo-128-legalisation-lowering.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,207 +7,209 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
; ARMV6: @ %bb.0: @ %start
; ARMV6-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; ARMV6-NEXT: sub sp, sp, #28
; ARMV6-NEXT: ldr lr, [sp, #72]
; ARMV6-NEXT: mov r6, r0
; ARMV6-NEXT: str r0, [sp, #8] @ 4-byte Spill
; ARMV6-NEXT: ldr r4, [sp, #84]
; ARMV6-NEXT: umull r1, r0, r2, lr
; ARMV6-NEXT: umull r5, r10, r4, r2
; ARMV6-NEXT: str r1, [r6]
; ARMV6-NEXT: ldr r4, [sp, #72]
; ARMV6-NEXT: mov r7, r0
; ARMV6-NEXT: str r0, [sp, #4] @ 4-byte Spill
; ARMV6-NEXT: ldr r12, [sp, #64]
; ARMV6-NEXT: umull r1, r0, r2, r4
; ARMV6-NEXT: ldr r5, [sp, #68]
; ARMV6-NEXT: str r1, [r7]
; ARMV6-NEXT: ldr r1, [sp, #76]
; ARMV6-NEXT: umull r7, r6, r1, r12
; ARMV6-NEXT: str r6, [sp, #8] @ 4-byte Spill
; ARMV6-NEXT: umull r6, r9, r5, r4
; ARMV6-NEXT: add r7, r6, r7
; ARMV6-NEXT: umull r4, r6, r12, r4
; ARMV6-NEXT: str r4, [sp, #16] @ 4-byte Spill
; ARMV6-NEXT: mov r4, #0
; ARMV6-NEXT: adds r8, r6, r7
; ARMV6-NEXT: ldr r6, [sp, #80]
; ARMV6-NEXT: umull r1, r7, r3, r6
; ARMV6-NEXT: str r7, [sp, #12] @ 4-byte Spill
; ARMV6-NEXT: add r1, r5, r1
; ARMV6-NEXT: umull r7, r5, r6, r2
; ARMV6-NEXT: mov r6, lr
; ARMV6-NEXT: str r7, [sp, #16] @ 4-byte Spill
; ARMV6-NEXT: mov r7, #0
; ARMV6-NEXT: adds r1, r5, r1
; ARMV6-NEXT: str r1, [sp, #4] @ 4-byte Spill
; ARMV6-NEXT: adc r1, r7, #0
; ARMV6-NEXT: str r1, [sp, #24] @ 4-byte Spill
; ARMV6-NEXT: ldr r1, [sp, #64]
; ARMV6-NEXT: ldr r7, [sp, #76]
; ARMV6-NEXT: ldr r5, [sp, #64]
; ARMV6-NEXT: umull r12, r9, r7, r1
; ARMV6-NEXT: ldr r1, [sp, #68]
; ARMV6-NEXT: umull r11, r8, r1, lr
; ARMV6-NEXT: adc r7, r4, #0
; ARMV6-NEXT: ldr r4, [sp, #84]
; ARMV6-NEXT: str r7, [sp, #24] @ 4-byte Spill
; ARMV6-NEXT: umull r12, lr, r3, r6
; ARMV6-NEXT: umull r11, r7, r4, r2
; ARMV6-NEXT: add r12, r11, r12
; ARMV6-NEXT: umull r11, lr, r5, lr
; ARMV6-NEXT: mov r5, r6
; ARMV6-NEXT: mov r6, #0
; ARMV6-NEXT: adds r12, lr, r12
; ARMV6-NEXT: umull r2, lr, r2, r7
; ARMV6-NEXT: adc r6, r6, #0
; ARMV6-NEXT: umull r11, r10, r6, r2
; ARMV6-NEXT: adds r12, r10, r12
; ARMV6-NEXT: mov r10, #0
; ARMV6-NEXT: adc r6, r10, #0
; ARMV6-NEXT: str r6, [sp, #20] @ 4-byte Spill
; ARMV6-NEXT: ldr r6, [sp, #16] @ 4-byte Reload
; ARMV6-NEXT: adds r11, r11, r6
; ARMV6-NEXT: ldr r6, [sp, #4] @ 4-byte Reload
; ARMV6-NEXT: adc r6, r12, r6
; ARMV6-NEXT: mov r12, #0
; ARMV6-NEXT: umlal r0, r12, r3, r5
; ARMV6-NEXT: ldr r5, [sp, #8] @ 4-byte Reload
; ARMV6-NEXT: adds r6, r6, r11
; ARMV6-NEXT: str r6, [sp, #12] @ 4-byte Spill
; ARMV6-NEXT: adc r6, r8, r12
; ARMV6-NEXT: str r6, [sp, #16] @ 4-byte Spill
; ARMV6-NEXT: ldr r6, [sp, #64]
; ARMV6-NEXT: ldr r6, [sp, #72]
; ARMV6-NEXT: mov r12, #0
; ARMV6-NEXT: umull r2, r8, r2, r1
; ARMV6-NEXT: umlal r0, r12, r3, r6
; ARMV6-NEXT: adds r0, r2, r0
; ARMV6-NEXT: str r0, [r5, #4]
; ARMV6-NEXT: adcs r0, r12, lr
; ARMV6-NEXT: mov r2, #0
; ARMV6-NEXT: adc r2, r2, #0
; ARMV6-NEXT: orrs lr, r6, r1
; ARMV6-NEXT: ldr r6, [sp, #80]
; ARMV6-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
; ARMV6-NEXT: adcs r8, r12, r8
; ARMV6-NEXT: adc r12, r10, #0
; ARMV6-NEXT: cmp lr, #0
; ARMV6-NEXT: str r0, [r2, #4]
; ARMV6-NEXT: movne lr, #1
; ARMV6-NEXT: umlal r0, r2, r3, r7
; ARMV6-NEXT: orrs r12, r6, r4
; ARMV6-NEXT: movne r12, #1
; ARMV6-NEXT: ldr r11, [sp, #8] @ 4-byte Reload
; ARMV6-NEXT: cmp r7, #0
; ARMV6-NEXT: movne r7, #1
; ARMV6-NEXT: ldr r0, [sp, #64]
; ARMV6-NEXT: cmp r11, #0
; ARMV6-NEXT: umlal r8, r12, r3, r1
; ARMV6-NEXT: movne r11, #1
; ARMV6-NEXT: cmp r9, #0
; ARMV6-NEXT: ldr r6, [sp, #12] @ 4-byte Reload
; ARMV6-NEXT: movne r9, #1
; ARMV6-NEXT: cmp r8, #0
; ARMV6-NEXT: movne r8, #1
; ARMV6-NEXT: cmp r6, #0
; ARMV6-NEXT: movne r6, #1
; ARMV6-NEXT: cmp r10, #0
; ARMV6-NEXT: orrs r10, r0, r5
; ARMV6-NEXT: ldr r0, [sp, #80]
; ARMV6-NEXT: movne r10, #1
; ARMV6-NEXT: cmp r1, #0
; ARMV6-NEXT: movne r1, #1
; ARMV6-NEXT: cmp r7, #0
; ARMV6-NEXT: movne r7, #1
; ARMV6-NEXT: ldr r6, [sp, #12] @ 4-byte Reload
; ARMV6-NEXT: orrs r0, r0, r4
; ARMV6-NEXT: movne r0, #1
; ARMV6-NEXT: cmp r4, #0
; ARMV6-NEXT: movne r4, #1
; ARMV6-NEXT: cmp r3, #0
; ARMV6-NEXT: movne r3, #1
; ARMV6-NEXT: adds r0, r0, r11
; ARMV6-NEXT: str r0, [r5, #8]
; ARMV6-NEXT: and r1, r1, r7
; ARMV6-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
; ARMV6-NEXT: orr r1, r1, r8
; ARMV6-NEXT: cmp r5, #0
; ARMV6-NEXT: movne r5, #1
; ARMV6-NEXT: cmp r1, #0
; ARMV6-NEXT: movne r1, #1
; ARMV6-NEXT: adds r6, r8, r6
; ARMV6-NEXT: str r6, [r2, #8]
; ARMV6-NEXT: and r1, r5, r1
; ARMV6-NEXT: ldr r6, [sp, #16] @ 4-byte Reload
; ARMV6-NEXT: orr r1, r1, r9
; ARMV6-NEXT: adcs r0, r2, r0
; ARMV6-NEXT: str r0, [r5, #12]
; ARMV6-NEXT: and r0, r4, r3
; ARMV6-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
; ARMV6-NEXT: orr r0, r0, r10
; ARMV6-NEXT: orr r0, r0, r6
; ARMV6-NEXT: orr r0, r0, r2
; ARMV6-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
; ARMV6-NEXT: orr r1, r1, r2
; ARMV6-NEXT: and r2, lr, r12
; ARMV6-NEXT: orr r1, r2, r1
; ARMV6-NEXT: orr r0, r1, r0
; ARMV6-NEXT: orr r1, r1, r11
; ARMV6-NEXT: and r0, r10, r0
; ARMV6-NEXT: adcs r6, r12, r6
; ARMV6-NEXT: str r6, [r2, #12]
; ARMV6-NEXT: ldr r6, [sp, #24] @ 4-byte Reload
; ARMV6-NEXT: orr r1, r1, r6
; ARMV6-NEXT: orr r0, r0, r1
; ARMV6-NEXT: and r1, r4, r3
; ARMV6-NEXT: orr r1, r1, r7
; ARMV6-NEXT: ldr r3, [sp, #20] @ 4-byte Reload
; ARMV6-NEXT: orr r1, r1, lr
; ARMV6-NEXT: orr r1, r1, r3
; ARMV6-NEXT: orr r0, r0, r1
; ARMV6-NEXT: mov r1, #0
; ARMV6-NEXT: adc r1, r1, #0
; ARMV6-NEXT: orr r0, r0, r1
; ARMV6-NEXT: and r0, r0, #1
; ARMV6-NEXT: strb r0, [r5, #16]
; ARMV6-NEXT: strb r0, [r2, #16]
; ARMV6-NEXT: add sp, sp, #28
; ARMV6-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
;
; ARMV7-LABEL: muloti_test:
; ARMV7: @ %bb.0: @ %start
; ARMV7-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
; ARMV7-NEXT: sub sp, sp, #36
; ARMV7-NEXT: ldr r5, [sp, #84]
; ARMV7-NEXT: mov r8, r0
; ARMV7-NEXT: ldr r1, [sp, #72]
; ARMV7-NEXT: ldr r10, [sp, #80]
; ARMV7-NEXT: ldr r9, [sp, #76]
; ARMV7-NEXT: umull r4, lr, r5, r1
; ARMV7-NEXT: umull r0, r7, r2, r10
; ARMV7-NEXT: str r4, [sp, #24] @ 4-byte Spill
; ARMV7-NEXT: ldr r4, [sp, #88]
; ARMV7-NEXT: umull r1, r6, r1, r10
; ARMV7-NEXT: sub sp, sp, #44
; ARMV7-NEXT: ldr r8, [sp, #88]
; ARMV7-NEXT: mov r9, r0
; ARMV7-NEXT: ldr r7, [sp, #96]
; ARMV7-NEXT: ldr lr, [sp, #100]
; ARMV7-NEXT: umull r0, r5, r2, r8
; ARMV7-NEXT: ldr r4, [sp, #80]
; ARMV7-NEXT: str r0, [sp, #32] @ 4-byte Spill
; ARMV7-NEXT: umull r11, r0, r2, r5
; ARMV7-NEXT: str r6, [sp, #20] @ 4-byte Spill
; ARMV7-NEXT: str r1, [sp, #28] @ 4-byte Spill
; ARMV7-NEXT: umull r6, r12, r3, r4
; ARMV7-NEXT: umull r1, r0, r3, r7
; ARMV7-NEXT: str r0, [sp, #4] @ 4-byte Spill
; ARMV7-NEXT: umull r0, r11, lr, r2
; ARMV7-NEXT: str r1, [sp, #20] @ 4-byte Spill
; ARMV7-NEXT: ldr r1, [sp, #92]
; ARMV7-NEXT: str r0, [sp, #8] @ 4-byte Spill
; ARMV7-NEXT: mov r0, #0
; ARMV7-NEXT: umlal r7, r0, r3, r10
; ARMV7-NEXT: str r0, [sp] @ 4-byte Spill
; ARMV7-NEXT: umull r0, r10, r7, r2
; ARMV7-NEXT: mov r7, r1
; ARMV7-NEXT: umull r6, r12, r1, r4
; ARMV7-NEXT: str r0, [sp, #40] @ 4-byte Spill
; ARMV7-NEXT: ldr r0, [sp, #84]
; ARMV7-NEXT: str r6, [sp, #24] @ 4-byte Spill
; ARMV7-NEXT: umull r6, r1, r0, r8
; ARMV7-NEXT: str r6, [sp, #16] @ 4-byte Spill
; ARMV7-NEXT: umull r6, r1, r1, r2
; ARMV7-NEXT: umull r2, r4, r4, r2
; ARMV7-NEXT: str r6, [sp, #4] @ 4-byte Spill
; ARMV7-NEXT: umull r6, r2, r2, r7
; ARMV7-NEXT: mov r7, r4
; ARMV7-NEXT: str r6, [sp, #8] @ 4-byte Spill
; ARMV7-NEXT: str r2, [sp, #12] @ 4-byte Spill
; ARMV7-NEXT: adds r2, r11, r7
; ARMV7-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
; ARMV7-NEXT: mov r11, #0
; ARMV7-NEXT: str r4, [sp] @ 4-byte Spill
; ARMV7-NEXT: umull r6, r4, r9, r10
; ARMV7-NEXT: adcs r9, r0, r7
; ARMV7-NEXT: ldr r0, [sp, #32] @ 4-byte Reload
; ARMV7-NEXT: adc r10, r11, #0
; ARMV7-NEXT: stm r8, {r0, r2}
; ARMV7-NEXT: ldr r0, [sp, #24] @ 4-byte Reload
; ARMV7-NEXT: umlal r9, r10, r3, r5
; ARMV7-NEXT: umull r2, r6, r4, r8
; ARMV7-NEXT: str r2, [sp, #36] @ 4-byte Spill
; ARMV7-NEXT: ldr r2, [sp, #32] @ 4-byte Reload
; ARMV7-NEXT: str r6, [sp, #28] @ 4-byte Spill
; ARMV7-NEXT: mov r6, #0
; ARMV7-NEXT: str r2, [r9]
; ARMV7-NEXT: umlal r5, r6, r3, r8
; ARMV7-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
; ARMV7-NEXT: add r0, r6, r0
; ARMV7-NEXT: adds r0, r2, r0
; ARMV7-NEXT: ldr r6, [sp, #4] @ 4-byte Reload
; ARMV7-NEXT: adc r2, r11, #0
; ARMV7-NEXT: ldr r4, [sp] @ 4-byte Reload
; ARMV7-NEXT: add r4, r4, r2
; ARMV7-NEXT: adds r2, r10, r4
; ARMV7-NEXT: str r2, [sp, #20] @ 4-byte Spill
; ARMV7-NEXT: mov r2, #0
; ARMV7-NEXT: adc r2, r2, #0
; ARMV7-NEXT: cmp r12, #0
; ARMV7-NEXT: str r2, [sp, #32] @ 4-byte Spill
; ARMV7-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
; ARMV7-NEXT: ldr r7, [sp, #28] @ 4-byte Reload
; ARMV7-NEXT: add r2, r6, r2
; ARMV7-NEXT: ldr r6, [sp] @ 4-byte Reload
; ARMV7-NEXT: adds r2, r6, r2
; ARMV7-NEXT: ldr r6, [sp, #12] @ 4-byte Reload
; ARMV7-NEXT: adc r11, r11, #0
; ARMV7-NEXT: adds r7, r7, r6
; ARMV7-NEXT: ldr r6, [sp, #92]
; ARMV7-NEXT: adc r0, r0, r2
; ARMV7-NEXT: str r0, [sp, #28] @ 4-byte Spill
; ARMV7-NEXT: ldr r0, [sp, #92]
; ARMV7-NEXT: cmp r3, #0
; ARMV7-NEXT: movwne r3, #1
; ARMV7-NEXT: ldr r2, [sp, #76]
; ARMV7-NEXT: cmp r0, #0
; ARMV7-NEXT: movwne r0, #1
; ARMV7-NEXT: movwne r12, #1
; ARMV7-NEXT: cmp r1, #0
; ARMV7-NEXT: ldr r2, [sp, #96]
; ARMV7-NEXT: movwne r1, #1
; ARMV7-NEXT: cmp r12, #0
; ARMV7-NEXT: and r0, r0, r3
; ARMV7-NEXT: movwne r12, #1
; ARMV7-NEXT: cmp r5, #0
; ARMV7-NEXT: orr r0, r0, r1
; ARMV7-NEXT: movwne r5, #1
; ARMV7-NEXT: orrs r10, r7, r0
; ARMV7-NEXT: movwne r10, #1
; ARMV7-NEXT: orrs r7, r2, lr
; ARMV7-NEXT: ldr r2, [sp, #92]
; ARMV7-NEXT: movwne r7, #1
; ARMV7-NEXT: cmp r0, #0
; ARMV7-NEXT: movwne r0, #1
; ARMV7-NEXT: cmp r2, #0
; ARMV7-NEXT: mov r1, r2
; ARMV7-NEXT: mov r3, r2
; ARMV7-NEXT: movwne r1, #1
; ARMV7-NEXT: mov r4, r2
; ARMV7-NEXT: mov r8, r2
; ARMV7-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; ARMV7-NEXT: movwne r4, #1
; ARMV7-NEXT: and r0, r0, r4
; ARMV7-NEXT: mov r4, #0
; ARMV7-NEXT: adds r5, r2, r5
; ARMV7-NEXT: str r5, [r9, #4]
; ARMV7-NEXT: orr r0, r0, r1
; ARMV7-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
; ARMV7-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
; ARMV7-NEXT: and r5, r10, r7
; ARMV7-NEXT: orr r0, r0, r12
; ARMV7-NEXT: mov r12, #0
; ARMV7-NEXT: add r1, r2, r1
; ARMV7-NEXT: ldr r2, [sp, #12] @ 4-byte Reload
; ARMV7-NEXT: adcs r2, r6, r2
; ARMV7-NEXT: ldr r6, [sp, #28] @ 4-byte Reload
; ARMV7-NEXT: adc r7, r4, #0
; ARMV7-NEXT: adds r1, r6, r1
; ARMV7-NEXT: umlal r2, r7, r3, r8
; ARMV7-NEXT: adc r4, r4, #0
; ARMV7-NEXT: orr r0, r0, r4
; ARMV7-NEXT: orr r0, r5, r0
; ARMV7-NEXT: ldr r4, [sp, #40] @ 4-byte Reload
; ARMV7-NEXT: ldr r5, [sp, #36] @ 4-byte Reload
; ARMV7-NEXT: adds r5, r5, r4
; ARMV7-NEXT: ldr r4, [sp, #20] @ 4-byte Reload
; ARMV7-NEXT: adc r1, r1, r4
; ARMV7-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
; ARMV7-NEXT: cmp r4, #0
; ARMV7-NEXT: ldr r2, [sp, #72]
; ARMV7-NEXT: movwne r4, #1
; ARMV7-NEXT: cmp r3, #0
; ARMV7-NEXT: movwne r3, #1
; ARMV7-NEXT: cmp lr, #0
; ARMV7-NEXT: and r1, r1, r5
; ARMV7-NEXT: movwne lr, #1
; ARMV7-NEXT: orrs r2, r2, r3
; ARMV7-NEXT: ldr r3, [sp, #88]
; ARMV7-NEXT: movwne r2, #1
; ARMV7-NEXT: cmp r11, #0
; ARMV7-NEXT: movwne r11, #1
; ARMV7-NEXT: adds r2, r2, r5
; ARMV7-NEXT: and r3, lr, r3
; ARMV7-NEXT: str r2, [r9, #8]
; ARMV7-NEXT: adcs r1, r7, r1
; ARMV7-NEXT: str r1, [r9, #12]
; ARMV7-NEXT: orr r1, r3, r11
; ARMV7-NEXT: ldr r2, [sp, #32] @ 4-byte Reload
; ARMV7-NEXT: orr r1, r1, r4
; ARMV7-NEXT: orr r0, r0, r12
; ARMV7-NEXT: orrs r3, r3, r6
; ARMV7-NEXT: orr r1, r1, lr
; ARMV7-NEXT: movwne r3, #1
; ARMV7-NEXT: adds r7, r9, r7
; ARMV7-NEXT: str r7, [r8, #8]
; ARMV7-NEXT: and r2, r2, r3
; ARMV7-NEXT: ldr r7, [sp, #28] @ 4-byte Reload
; ARMV7-NEXT: orr r0, r0, r11
; ARMV7-NEXT: adcs r7, r10, r7
; ARMV7-NEXT: str r7, [r8, #12]
; ARMV7-NEXT: ldr r7, [sp, #32] @ 4-byte Reload
; ARMV7-NEXT: orr r1, r1, r7
; ARMV7-NEXT: orr r1, r2, r1
; ARMV7-NEXT: orr r0, r1, r0
; ARMV7-NEXT: mov r1, #0
; ARMV7-NEXT: adc r1, r1, #0
; ARMV7-NEXT: orr r1, r1, r2
; ARMV7-NEXT: orr r0, r0, r1
; ARMV7-NEXT: adc r1, r12, #0
; ARMV7-NEXT: orr r0, r0, r1
; ARMV7-NEXT: and r0, r0, #1
; ARMV7-NEXT: strb r0, [r8, #16]
; ARMV7-NEXT: add sp, sp, #36
; ARMV7-NEXT: strb r0, [r9, #16]
; ARMV7-NEXT: add sp, sp, #44
; ARMV7-NEXT: pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}
start:
%0 = tail call { i128, i1 } @llvm.umul.with.overflow.i128(i128 %l, i128 %r) #2
Expand Down
53 changes: 26 additions & 27 deletions llvm/test/CodeGen/ARM/umulo-64-legalisation-lowering.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,50 +5,49 @@
define { i64, i8 } @mulodi_test(i64 %l, i64 %r) unnamed_addr #0 {
; ARMV6-LABEL: mulodi_test:
; ARMV6: @ %bb.0: @ %start
; ARMV6-NEXT: push {r4, r5, r6, lr}
; ARMV6-NEXT: umull r12, lr, r3, r0
; ARMV6-NEXT: mov r6, #0
; ARMV6-NEXT: umull r4, r5, r1, r2
; ARMV6-NEXT: umull r0, r2, r0, r2
; ARMV6-NEXT: add r4, r4, r12
; ARMV6-NEXT: adds r12, r2, r4
; ARMV6-NEXT: adc r2, r6, #0
; ARMV6-NEXT: push {r4, r5, r11, lr}
; ARMV6-NEXT: umull r12, lr, r1, r2
; ARMV6-NEXT: umull r4, r5, r3, r0
; ARMV6-NEXT: cmp lr, #0
; ARMV6-NEXT: movne lr, #1
; ARMV6-NEXT: cmp r3, #0
; ARMV6-NEXT: movne r3, #1
; ARMV6-NEXT: cmp r1, #0
; ARMV6-NEXT: umull r0, r2, r0, r2
; ARMV6-NEXT: movne r1, #1
; ARMV6-NEXT: cmp r5, #0
; ARMV6-NEXT: and r1, r1, r3
; ARMV6-NEXT: movne r5, #1
; ARMV6-NEXT: cmp lr, #0
; ARMV6-NEXT: orr r1, r1, r5
; ARMV6-NEXT: movne lr, #1
; ARMV6-NEXT: cmp r5, #0
; ARMV6-NEXT: orr r1, r1, lr
; ARMV6-NEXT: orr r2, r1, r2
; ARMV6-NEXT: mov r1, r12
; ARMV6-NEXT: pop {r4, r5, r6, pc}
; ARMV6-NEXT: movne r5, #1
; ARMV6-NEXT: orr r3, r1, r5
; ARMV6-NEXT: add r1, r12, r4
; ARMV6-NEXT: adds r1, r2, r1
; ARMV6-NEXT: mov r5, #0
; ARMV6-NEXT: adc r2, r5, #0
; ARMV6-NEXT: orr r2, r3, r2
; ARMV6-NEXT: pop {r4, r5, r11, pc}
;
; ARMV7-LABEL: mulodi_test:
; ARMV7: @ %bb.0: @ %start
; ARMV7-NEXT: push {r4, r5, r11, lr}
; ARMV7-NEXT: umull r12, lr, r1, r2
; ARMV7-NEXT: umull r12, lr, r3, r0
; ARMV7-NEXT: cmp r3, #0
; ARMV7-NEXT: umull r4, r5, r3, r0
; ARMV7-NEXT: movwne r3, #1
; ARMV7-NEXT: cmp r1, #0
; ARMV7-NEXT: umull r0, r4, r0, r2
; ARMV7-NEXT: umull r2, r5, r1, r2
; ARMV7-NEXT: movwne r1, #1
; ARMV7-NEXT: umull r0, r2, r0, r2
; ARMV7-NEXT: cmp lr, #0
; ARMV7-NEXT: and r1, r1, r3
; ARMV7-NEXT: movwne lr, #1
; ARMV7-NEXT: cmp r5, #0
; ARMV7-NEXT: orr r1, r1, lr
; ARMV7-NEXT: movwne r5, #1
; ARMV7-NEXT: orr r3, r1, r5
; ARMV7-NEXT: add r1, r12, r4
; ARMV7-NEXT: mov r5, #0
; ARMV7-NEXT: adds r1, r2, r1
; ARMV7-NEXT: adc r2, r5, #0
; ARMV7-NEXT: cmp lr, #0
; ARMV7-NEXT: orr r1, r1, r5
; ARMV7-NEXT: movwne lr, #1
; ARMV7-NEXT: orr r3, r1, lr
; ARMV7-NEXT: add r1, r2, r12
; ARMV7-NEXT: mov r2, #0
; ARMV7-NEXT: adds r1, r4, r1
; ARMV7-NEXT: adc r2, r2, #0
; ARMV7-NEXT: orr r2, r3, r2
; ARMV7-NEXT: pop {r4, r5, r11, pc}
start:
Expand Down
7 changes: 3 additions & 4 deletions llvm/test/CodeGen/ARM/usub_sat.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -49,16 +49,15 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-T1-NEXT: adcs r0, r1
; CHECK-T1-NEXT: movs r3, #1
; CHECK-T1-NEXT: eors r3, r0
; CHECK-T1-NEXT: cmp r3, #0
; CHECK-T1-NEXT: mov r0, r1
; CHECK-T1-NEXT: beq .LBB1_3
; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: cmp r3, #0
; CHECK-T1-NEXT: beq .LBB1_4
; CHECK-T1-NEXT: .LBB1_2:
; CHECK-T1-NEXT: pop {r4, pc}
; CHECK-T1-NEXT: .LBB1_3:
; CHECK-T1-NEXT: mov r0, r2
; CHECK-T1-NEXT: cmp r3, #0
; CHECK-T1-NEXT: bne .LBB1_2
; CHECK-T1-NEXT: .LBB1_4:
; CHECK-T1-NEXT: mov r1, r4
Expand All @@ -70,7 +69,7 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-T2-NEXT: mov.w r12, #0
; CHECK-T2-NEXT: sbcs r1, r3
; CHECK-T2-NEXT: adc r2, r12, #0
; CHECK-T2-NEXT: eors r2, r2, #1
; CHECK-T2-NEXT: teq.w r2, #1
; CHECK-T2-NEXT: itt ne
; CHECK-T2-NEXT: movne r0, #0
; CHECK-T2-NEXT: movne r1, #0
Expand All @@ -82,7 +81,7 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
; CHECK-ARM-NEXT: mov r12, #0
; CHECK-ARM-NEXT: sbcs r1, r1, r3
; CHECK-ARM-NEXT: adc r2, r12, #0
; CHECK-ARM-NEXT: eors r2, r2, #1
; CHECK-ARM-NEXT: teq r2, #1
; CHECK-ARM-NEXT: movwne r0, #0
; CHECK-ARM-NEXT: movwne r1, #0
; CHECK-ARM-NEXT: bx lr
Expand Down
7 changes: 3 additions & 4 deletions llvm/test/CodeGen/ARM/usub_sat_plus.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -55,16 +55,15 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; CHECK-T1-NEXT: adcs r0, r1
; CHECK-T1-NEXT: movs r4, #1
; CHECK-T1-NEXT: eors r4, r0
; CHECK-T1-NEXT: cmp r4, #0
; CHECK-T1-NEXT: mov r0, r1
; CHECK-T1-NEXT: beq .LBB1_3
; CHECK-T1-NEXT: @ %bb.1:
; CHECK-T1-NEXT: cmp r4, #0
; CHECK-T1-NEXT: beq .LBB1_4
; CHECK-T1-NEXT: .LBB1_2:
; CHECK-T1-NEXT: pop {r4, pc}
; CHECK-T1-NEXT: .LBB1_3:
; CHECK-T1-NEXT: mov r0, r3
; CHECK-T1-NEXT: cmp r4, #0
; CHECK-T1-NEXT: bne .LBB1_2
; CHECK-T1-NEXT: .LBB1_4:
; CHECK-T1-NEXT: mov r1, r2
Expand All @@ -77,7 +76,7 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; CHECK-T2-NEXT: subs r0, r0, r2
; CHECK-T2-NEXT: sbcs r1, r3
; CHECK-T2-NEXT: adc r2, r12, #0
; CHECK-T2-NEXT: eors r2, r2, #1
; CHECK-T2-NEXT: teq.w r2, #1
; CHECK-T2-NEXT: itt ne
; CHECK-T2-NEXT: movne r0, #0
; CHECK-T2-NEXT: movne r1, #0
Expand All @@ -91,7 +90,7 @@ define i64 @func64(i64 %x, i64 %y, i64 %z) nounwind {
; CHECK-ARM-NEXT: subs r0, r0, r2
; CHECK-ARM-NEXT: sbcs r1, r1, r3
; CHECK-ARM-NEXT: adc r2, r12, #0
; CHECK-ARM-NEXT: eors r2, r2, #1
; CHECK-ARM-NEXT: teq r2, #1
; CHECK-ARM-NEXT: movwne r0, #0
; CHECK-ARM-NEXT: movwne r1, #0
; CHECK-ARM-NEXT: bx lr
Expand Down
358 changes: 177 additions & 181 deletions llvm/test/CodeGen/ARM/vselect_imax.ll
View file

Large diffs are not rendered by default.

85 changes: 29 additions & 56 deletions llvm/test/CodeGen/ARM/wide-compares.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -129,19 +129,16 @@ declare void @g()
define i64 @test_slt_select(i64 %c, i64 %d, i64 %a, i64 %b) {
; CHECK-ARM-LABEL: test_slt_select:
; CHECK-ARM: @ %bb.0: @ %entry
; CHECK-ARM-NEXT: push {r4, r5, r6, r7, r11, lr}
; CHECK-ARM-NEXT: ldr r12, [sp, #32]
; CHECK-ARM-NEXT: mov r6, #0
; CHECK-ARM-NEXT: ldr lr, [sp, #24]
; CHECK-ARM-NEXT: ldr r7, [sp, #36]
; CHECK-ARM-NEXT: ldr r5, [sp, #28]
; CHECK-ARM-NEXT: push {r4, r5, r6, lr}
; CHECK-ARM-NEXT: ldr r12, [sp, #24]
; CHECK-ARM-NEXT: ldr lr, [sp, #16]
; CHECK-ARM-NEXT: ldr r6, [sp, #28]
; CHECK-ARM-NEXT: ldr r5, [sp, #20]
; CHECK-ARM-NEXT: subs r4, lr, r12
; CHECK-ARM-NEXT: sbcs r7, r5, r7
; CHECK-ARM-NEXT: movwlo r6, #1
; CHECK-ARM-NEXT: cmp r6, #0
; CHECK-ARM-NEXT: moveq r0, r2
; CHECK-ARM-NEXT: moveq r1, r3
; CHECK-ARM-NEXT: pop {r4, r5, r6, r7, r11, pc}
; CHECK-ARM-NEXT: sbcs r6, r5, r6
; CHECK-ARM-NEXT: movhs r0, r2
; CHECK-ARM-NEXT: movhs r1, r3
; CHECK-ARM-NEXT: pop {r4, r5, r6, pc}
;
; CHECK-THUMB1-NOMOV-LABEL: test_slt_select:
; CHECK-THUMB1-NOMOV: @ %bb.0: @ %entry
Expand All @@ -157,22 +154,13 @@ define i64 @test_slt_select(i64 %c, i64 %d, i64 %a, i64 %b) {
; CHECK-THUMB1-NOMOV-NEXT: sbcs r5, r4
; CHECK-THUMB1-NOMOV-NEXT: blo .LBB2_2
; CHECK-THUMB1-NOMOV-NEXT: @ %bb.1: @ %entry
; CHECK-THUMB1-NOMOV-NEXT: movs r4, #0
; CHECK-THUMB1-NOMOV-NEXT: cmp r4, #0
; CHECK-THUMB1-NOMOV-NEXT: beq .LBB2_3
; CHECK-THUMB1-NOMOV-NEXT: b .LBB2_4
; CHECK-THUMB1-NOMOV-NEXT: .LBB2_2:
; CHECK-THUMB1-NOMOV-NEXT: movs r4, #1
; CHECK-THUMB1-NOMOV-NEXT: cmp r4, #0
; CHECK-THUMB1-NOMOV-NEXT: bne .LBB2_4
; CHECK-THUMB1-NOMOV-NEXT: .LBB2_3: @ %entry
; CHECK-THUMB1-NOMOV-NEXT: movs r0, r2
; CHECK-THUMB1-NOMOV-NEXT: .LBB2_4: @ %entry
; CHECK-THUMB1-NOMOV-NEXT: cmp r4, #0
; CHECK-THUMB1-NOMOV-NEXT: bne .LBB2_6
; CHECK-THUMB1-NOMOV-NEXT: @ %bb.5: @ %entry
; CHECK-THUMB1-NOMOV-NEXT: mov r12, r2
; CHECK-THUMB1-NOMOV-NEXT: mov r0, r12
; CHECK-THUMB1-NOMOV-NEXT: .LBB2_2: @ %entry
; CHECK-THUMB1-NOMOV-NEXT: blo .LBB2_4
; CHECK-THUMB1-NOMOV-NEXT: @ %bb.3: @ %entry
; CHECK-THUMB1-NOMOV-NEXT: movs r1, r3
; CHECK-THUMB1-NOMOV-NEXT: .LBB2_6: @ %entry
; CHECK-THUMB1-NOMOV-NEXT: .LBB2_4: @ %entry
; CHECK-THUMB1-NOMOV-NEXT: add sp, #4
; CHECK-THUMB1-NOMOV-NEXT: pop {r4, r5, r6, r7}
; CHECK-THUMB1-NOMOV-NEXT: pop {r2}
Expand All @@ -188,46 +176,31 @@ define i64 @test_slt_select(i64 %c, i64 %d, i64 %a, i64 %b) {
; CHECK-THUMB1-NEXT: ldr r7, [sp, #24]
; CHECK-THUMB1-NEXT: subs r6, r7, r6
; CHECK-THUMB1-NEXT: sbcs r5, r4
; CHECK-THUMB1-NEXT: blo .LBB2_2
; CHECK-THUMB1-NEXT: bhs .LBB2_3
; CHECK-THUMB1-NEXT: @ %bb.1: @ %entry
; CHECK-THUMB1-NEXT: movs r4, #0
; CHECK-THUMB1-NEXT: cmp r4, #0
; CHECK-THUMB1-NEXT: beq .LBB2_3
; CHECK-THUMB1-NEXT: b .LBB2_4
; CHECK-THUMB1-NEXT: .LBB2_2:
; CHECK-THUMB1-NEXT: movs r4, #1
; CHECK-THUMB1-NEXT: cmp r4, #0
; CHECK-THUMB1-NEXT: bne .LBB2_4
; CHECK-THUMB1-NEXT: bhs .LBB2_4
; CHECK-THUMB1-NEXT: .LBB2_2: @ %entry
; CHECK-THUMB1-NEXT: add sp, #4
; CHECK-THUMB1-NEXT: pop {r4, r5, r6, r7, pc}
; CHECK-THUMB1-NEXT: .LBB2_3: @ %entry
; CHECK-THUMB1-NEXT: mov r0, r2
; CHECK-THUMB1-NEXT: blo .LBB2_2
; CHECK-THUMB1-NEXT: .LBB2_4: @ %entry
; CHECK-THUMB1-NEXT: cmp r4, #0
; CHECK-THUMB1-NEXT: beq .LBB2_6
; CHECK-THUMB1-NEXT: @ %bb.5: @ %entry
; CHECK-THUMB1-NEXT: add sp, #4
; CHECK-THUMB1-NEXT: pop {r4, r5, r6, r7, pc}
; CHECK-THUMB1-NEXT: .LBB2_6: @ %entry
; CHECK-THUMB1-NEXT: mov r1, r3
; CHECK-THUMB1-NEXT: add sp, #4
; CHECK-THUMB1-NEXT: pop {r4, r5, r6, r7, pc}
;
; CHECK-THUMB2-LABEL: test_slt_select:
; CHECK-THUMB2: @ %bb.0: @ %entry
; CHECK-THUMB2-NEXT: push {r4, r5, r6, r7, lr}
; CHECK-THUMB2-NEXT: sub sp, #4
; CHECK-THUMB2-NEXT: ldrd r12, r7, [sp, #32]
; CHECK-THUMB2-NEXT: movs r6, #0
; CHECK-THUMB2-NEXT: ldrd lr, r5, [sp, #24]
; CHECK-THUMB2-NEXT: push {r4, r5, r6, lr}
; CHECK-THUMB2-NEXT: ldrd r12, r6, [sp, #24]
; CHECK-THUMB2-NEXT: ldrd lr, r5, [sp, #16]
; CHECK-THUMB2-NEXT: subs.w r4, lr, r12
; CHECK-THUMB2-NEXT: sbcs.w r7, r5, r7
; CHECK-THUMB2-NEXT: it lo
; CHECK-THUMB2-NEXT: movlo r6, #1
; CHECK-THUMB2-NEXT: cmp r6, #0
; CHECK-THUMB2-NEXT: itt eq
; CHECK-THUMB2-NEXT: moveq r0, r2
; CHECK-THUMB2-NEXT: moveq r1, r3
; CHECK-THUMB2-NEXT: add sp, #4
; CHECK-THUMB2-NEXT: pop {r4, r5, r6, r7, pc}
; CHECK-THUMB2-NEXT: sbcs.w r6, r5, r6
; CHECK-THUMB2-NEXT: itt hs
; CHECK-THUMB2-NEXT: movhs r0, r2
; CHECK-THUMB2-NEXT: movhs r1, r3
; CHECK-THUMB2-NEXT: pop {r4, r5, r6, pc}
entry:
%cmp = icmp ult i64 %a, %b
%r1 = select i1 %cmp, i64 %c, i64 %d
Expand Down
3 changes: 1 addition & 2 deletions llvm/test/CodeGen/Thumb/arm_q15_to_q31.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -501,9 +501,8 @@ define void @arm_q15_to_q31_altorder(ptr nocapture noundef readonly %pSrc, ptr n
; CHECK-NEXT: lsls r2, r2, #16
; CHECK-NEXT: str r2, [r1, #48]
; CHECK-NEXT: adds r1, #64
; CHECK-NEXT: subs r3, r3, #4
; CHECK-NEXT: adds r0, #32
; CHECK-NEXT: cmp r3, #0
; CHECK-NEXT: subs r3, r3, #4
; CHECK-NEXT: bne .LBB1_5
; CHECK-NEXT: .LBB1_6: @ %while.end
; CHECK-NEXT: movs r2, #3
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/Thumb/select.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -94,8 +94,8 @@ entry:
; CHECK-LABEL: f8:
; CHECK: cmp r0, r1
; CHECK: blt
; CHECK: movs
; CHECK: cmp r0, r1
; CHECK: mov
; CHECK: mov
; CHECK: blt
; CHECK: movs
; CHECK: movs
Expand Down
426 changes: 198 additions & 228 deletions llvm/test/CodeGen/Thumb/smul_fix_sat.ll
View file

Large diffs are not rendered by default.

250 changes: 175 additions & 75 deletions llvm/test/CodeGen/Thumb/stack-guard-xo.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -33,9 +33,9 @@ define dso_local i32 @main() #0 {
; V6M-LABEL: main:
; V6M: @ %bb.0: @ %entry
; V6M-NEXT: push {r7, lr}
; V6M-NEXT: sub sp, #
; V6M-NEXT: sub sp, #24
; V6M-NEXT: movs r0, #0
; V6M-NEXT: str r0, [sp, #
; V6M-NEXT: str r0, [sp, #4]
; V6M-NEXT: mrs r12, apsr
; V6M-NEXT: movs r0, :upper8_15:__stack_chk_guard
; V6M-NEXT: lsls r0, r0, #8
Expand All @@ -46,10 +46,10 @@ define dso_local i32 @main() #0 {
; V6M-NEXT: adds r0, :lower0_7:__stack_chk_guard
; V6M-NEXT: msr apsr, r12
; V6M-NEXT: ldr r0, [r0]
; V6M-NEXT: str r0, [sp, #
; V6M-NEXT: add r0, sp, #
; V6M-NEXT: str r0, [sp, #20]
; V6M-NEXT: add r0, sp, #8
; V6M-NEXT: ldrb r0, [r0]
; V6M-NEXT: ldr r1, [sp, #
; V6M-NEXT: ldr r1, [sp, #20]
; V6M-NEXT: mrs r12, apsr
; V6M-NEXT: movs r2, :upper8_15:__stack_chk_guard
; V6M-NEXT: lsls r2, r2, #8
Expand All @@ -63,7 +63,7 @@ define dso_local i32 @main() #0 {
; V6M-NEXT: cmp r2, r1
; V6M-NEXT: bne .LBB0_2
; V6M-NEXT: @ %bb.1: @ %entry
; V6M-NEXT: add sp, #
; V6M-NEXT: add sp, #24
; V6M-NEXT: pop {r7, pc}
; V6M-NEXT: .LBB0_2: @ %entry
; V6M-NEXT: bl __stack_chk_fail
Expand Down Expand Up @@ -105,77 +105,177 @@ entry:
@bb = hidden local_unnamed_addr global i64 0, align 8

define dso_local i64 @cc() local_unnamed_addr #1 {
; CHECK-LABEL: cc:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push {r4, r5, r7, lr}
; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: movs r0, #1
; CHECK-NEXT: lsls r3, r0, #31
; CHECK-NEXT: ldr r0, .LCPI1_0
; CHECK-NEXT: ldr r2, [r0]
; CHECK-NEXT: asrs r4, r2, #31
; CHECK-NEXT: eors r3, r4
; CHECK-NEXT: ldr r0, .LCPI1_1
; CHECK-NEXT: ldm r0!, {r1, r5}
; CHECK-NEXT: subs r0, r2, r1
; CHECK-NEXT: sbcs r3, r5
; CHECK-NEXT: subs r0, r2, r1
; CHECK-NEXT: ldr r1, .LCPI1_2
; CHECK-NEXT: ldr r1, [r1]
; CHECK-NEXT: str r1, [sp, #4]
; CHECK-NEXT: mov r1, r4
; CHECK-NEXT: sbcs r1, r5
; CHECK-NEXT: ands r3, r4
; CHECK-NEXT: ands r2, r0
; CHECK-NEXT: mov r4, r2
; CHECK-NEXT: orrs r4, r3
; CHECK-NEXT: cmp r4, #0
; CHECK-NEXT: beq .LBB1_2
; CHECK-NEXT: @ %bb.1: @ %entry
; CHECK-NEXT: mov r1, r3
; CHECK-NEXT: .LBB1_2: @ %entry
; CHECK-NEXT: beq .LBB1_4
; CHECK-NEXT: @ %bb.3: @ %entry
; CHECK-NEXT: mov r0, r2
; CHECK-NEXT: .LBB1_4: @ %entry
; CHECK-NEXT: ldr r2, [sp, #4]
; CHECK-NEXT: ldr r3, .LCPI1_2
; CHECK-NEXT: ldr r3, [r3]
; CHECK-NEXT: cmp r3, r2
; CHECK-NEXT: bne .LBB1_6
; CHECK-NEXT: @ %bb.5: @ %entry
; CHECK-NEXT: add sp, #8
; CHECK-NEXT: pop {r4, r5, r7, pc}
; CHECK-NEXT: .LBB1_6: @ %entry
; CHECK-NEXT: bl __stack_chk_fail
; CHECK-NEXT: .p2align 2
; CHECK-NEXT: @ %bb.7:
; CHECK-NEXT: .LCPI1_0:
; CHECK-NEXT: .long aa
; CHECK-NEXT: .LCPI1_1:
; CHECK-NEXT: .long bb
; CHECK-NEXT: .LCPI1_2:
; CHECK-NEXT: .long __stack_chk_guard
;
; V6M-LABEL: cc:
; V6M: @ %bb.0: @ %entry
; V6M-NEXT: push {r4, r5, r7, lr}
; V6M-NEXT: sub sp, #8
; V6M-NEXT: movs r0, #1
; V6M-NEXT: lsls r3, r0, #31
; V6M-NEXT: movs r0, :upper8_15:aa
; V6M-NEXT: lsls r0, r0, #8
; V6M-NEXT: adds r0, :upper0_7:aa
; V6M-NEXT: lsls r0, r0, #8
; V6M-NEXT: adds r0, :lower8_15:aa
; V6M-NEXT: lsls r0, r0, #8
; V6M-NEXT: adds r0, :lower0_7:aa
; V6M-NEXT: ldr r2, [r0]
; V6M-NEXT: asrs r4, r2, #31
; V6M-NEXT: eors r3, r4
; V6M-NEXT: movs r0, :upper8_15:bb
; V6M-NEXT: lsls r0, r0, #8
; V6M-NEXT: adds r0, :upper0_7:bb
; V6M-NEXT: lsls r0, r0, #8
; V6M-NEXT: adds r0, :lower8_15:bb
; V6M-NEXT: lsls r0, r0, #8
; V6M-NEXT: adds r0, :lower0_7:bb
; V6M-NEXT: ldm r0!, {r1, r5}
; V6M-NEXT: subs r0, r2, r1
; V6M-NEXT: sbcs r3, r5
; V6M-NEXT: subs r0, r2, r1
; V6M-NEXT: mrs r12, apsr
; V6M-NEXT: movs r1, :upper8_15:__stack_chk_guard
; V6M-NEXT: lsls r1, r1, #8
; V6M-NEXT: adds r1, :upper0_7:__stack_chk_guard
; V6M-NEXT: lsls r1, r1, #8
; V6M-NEXT: adds r1, :lower8_15:__stack_chk_guard
; V6M-NEXT: lsls r1, r1, #8
; V6M-NEXT: adds r1, :lower0_7:__stack_chk_guard
; V6M-NEXT: msr apsr, r12
; V6M-NEXT: ldr r1, [r1]
; V6M-NEXT: str r1, [sp, #4]
; V6M-NEXT: mov r1, r4
; V6M-NEXT: sbcs r1, r5
; V6M-NEXT: ands r3, r4
; V6M-NEXT: ands r2, r0
; V6M-NEXT: mov r4, r2
; V6M-NEXT: orrs r4, r3
; V6M-NEXT: beq .LBB1_2
; V6M-NEXT: @ %bb.1: @ %entry
; V6M-NEXT: mov r1, r3
; V6M-NEXT: .LBB1_2: @ %entry
; V6M-NEXT: cmp r4, #0
; V6M-NEXT: beq .LBB1_4
; V6M-NEXT: @ %bb.3: @ %entry
; V6M-NEXT: mov r0, r2
; V6M-NEXT: .LBB1_4: @ %entry
; V6M-NEXT: ldr r2, [sp, #4]
; V6M-NEXT: mrs r12, apsr
; V6M-NEXT: movs r3, :upper8_15:__stack_chk_guard
; V6M-NEXT: lsls r3, r3, #8
; V6M-NEXT: adds r3, :upper0_7:__stack_chk_guard
; V6M-NEXT: lsls r3, r3, #8
; V6M-NEXT: adds r3, :lower8_15:__stack_chk_guard
; V6M-NEXT: lsls r3, r3, #8
; V6M-NEXT: adds r3, :lower0_7:__stack_chk_guard
; V6M-NEXT: msr apsr, r12
; V6M-NEXT: ldr r3, [r3]
; V6M-NEXT: cmp r3, r2
; V6M-NEXT: bne .LBB1_6
; V6M-NEXT: @ %bb.5: @ %entry
; V6M-NEXT: add sp, #8
; V6M-NEXT: pop {r4, r5, r7, pc}
; V6M-NEXT: .LBB1_6: @ %entry
; V6M-NEXT: bl __stack_chk_fail
; V6M-NEXT: push {r4, r5, r7, lr}
; V6M-NEXT: sub sp, #8
; V6M-NEXT: movs r0, #1
; V6M-NEXT: lsls r3, r0, #31
; V6M-NEXT: movs r0, :upper8_15:aa
; V6M-NEXT: lsls r0, r0, #8
; V6M-NEXT: adds r0, :upper0_7:aa
; V6M-NEXT: lsls r0, r0, #8
; V6M-NEXT: adds r0, :lower8_15:aa
; V6M-NEXT: lsls r0, r0, #8
; V6M-NEXT: adds r0, :lower0_7:aa
; V6M-NEXT: ldr r2, [r0]
; V6M-NEXT: asrs r4, r2, #31
; V6M-NEXT: eors r3, r4
; V6M-NEXT: movs r0, :upper8_15:bb
; V6M-NEXT: lsls r0, r0, #8
; V6M-NEXT: adds r0, :upper0_7:bb
; V6M-NEXT: lsls r0, r0, #8
; V6M-NEXT: adds r0, :lower8_15:bb
; V6M-NEXT: lsls r0, r0, #8
; V6M-NEXT: adds r0, :lower0_7:bb
; V6M-NEXT: ldm r0!, {r1, r5}
; V6M-NEXT: subs r0, r2, r1
; V6M-NEXT: sbcs r3, r5
; V6M-NEXT: subs r0, r2, r1
; V6M-NEXT: mrs r12, apsr
; V6M-NEXT: movs r1, :upper8_15:__stack_chk_guard
; V6M-NEXT: lsls r1, r1, #8
; V6M-NEXT: adds r1, :upper0_7:__stack_chk_guard
; V6M-NEXT: lsls r1, r1, #8
; V6M-NEXT: adds r1, :lower8_15:__stack_chk_guard
; V6M-NEXT: lsls r1, r1, #8
; V6M-NEXT: adds r1, :lower0_7:__stack_chk_guard
; V6M-NEXT: msr apsr, r12
; V6M-NEXT: ldr r1, [r1]
; V6M-NEXT: str r1, [sp, #4]
; V6M-NEXT: mov r1, r4
; V6M-NEXT: sbcs r1, r5
; V6M-NEXT: ands r3, r4
; V6M-NEXT: ands r2, r0
; V6M-NEXT: mov r4, r2
; V6M-NEXT: orrs r4, r3
; V6M-NEXT: cmp r4, #0
; V6M-NEXT: beq .LBB1_2
; V6M-NEXT: @ %bb.1: @ %entry
; V6M-NEXT: mov r1, r3
; V6M-NEXT: .LBB1_2: @ %entry
; V6M-NEXT: beq .LBB1_4
; V6M-NEXT: @ %bb.3: @ %entry
; V6M-NEXT: mov r0, r2
; V6M-NEXT: .LBB1_4: @ %entry
; V6M-NEXT: ldr r2, [sp, #4]
; V6M-NEXT: mrs r12, apsr
; V6M-NEXT: movs r3, :upper8_15:__stack_chk_guard
; V6M-NEXT: lsls r3, r3, #8
; V6M-NEXT: adds r3, :upper0_7:__stack_chk_guard
; V6M-NEXT: lsls r3, r3, #8
; V6M-NEXT: adds r3, :lower8_15:__stack_chk_guard
; V6M-NEXT: lsls r3, r3, #8
; V6M-NEXT: adds r3, :lower0_7:__stack_chk_guard
; V6M-NEXT: msr apsr, r12
; V6M-NEXT: ldr r3, [r3]
; V6M-NEXT: cmp r3, r2
; V6M-NEXT: bne .LBB1_6
; V6M-NEXT: @ %bb.5: @ %entry
; V6M-NEXT: add sp, #8
; V6M-NEXT: pop {r4, r5, r7, pc}
; V6M-NEXT: .LBB1_6: @ %entry
; V6M-NEXT: bl __stack_chk_fail
;
; V8MBASE-LABEL: cc:
; V8MBASE: @ %bb.0: @ %entry
; V8MBASE-NEXT: push {r4, r5, r7, lr}
; V8MBASE-NEXT: sub sp, #8
; V8MBASE-NEXT: movs r0, #1
; V8MBASE-NEXT: lsls r3, r0, #31
; V8MBASE-NEXT: movw r0, :lower16:aa
; V8MBASE-NEXT: movt r0, :upper16:aa
; V8MBASE-NEXT: ldr r2, [r0]
; V8MBASE-NEXT: asrs r4, r2, #31
; V8MBASE-NEXT: eors r3, r4
; V8MBASE-NEXT: movw r0, :lower16:bb
; V8MBASE-NEXT: movt r0, :upper16:bb
; V8MBASE-NEXT: ldm r0!, {r1, r5}
; V8MBASE-NEXT: subs r0, r2, r1
; V8MBASE-NEXT: sbcs r3, r5
; V8MBASE-NEXT: subs r0, r2, r1
; V8MBASE-NEXT: movw r1, :lower16:__stack_chk_guard
; V8MBASE-NEXT: movt r1, :upper16:__stack_chk_guard
; V8MBASE-NEXT: ldr r1, [r1]
; V8MBASE-NEXT: str r1, [sp, #4]
; V8MBASE-NEXT: mov r1, r4
; V8MBASE-NEXT: sbcs r1, r5
; V8MBASE-NEXT: ands r3, r4
; V8MBASE-NEXT: ands r2, r0
; V8MBASE-NEXT: mov r4, r2
; V8MBASE-NEXT: orrs r4, r3
; V8MBASE-NEXT: cmp r4, #0
; V8MBASE-NEXT: beq .LBB1_2
; V8MBASE-NEXT: @ %bb.1: @ %entry
; V8MBASE-NEXT: mov r1, r3
; V8MBASE-NEXT: .LBB1_2: @ %entry
; V8MBASE-NEXT: beq .LBB1_4
; V8MBASE-NEXT: @ %bb.3: @ %entry
; V8MBASE-NEXT: mov r0, r2
; V8MBASE-NEXT: .LBB1_4: @ %entry
; V8MBASE-NEXT: ldr r2, [sp, #4]
; V8MBASE-NEXT: movw r3, :lower16:__stack_chk_guard
; V8MBASE-NEXT: movt r3, :upper16:__stack_chk_guard
; V8MBASE-NEXT: ldr r3, [r3]
; V8MBASE-NEXT: cmp r3, r2
; V8MBASE-NEXT: bne .LBB1_6
; V8MBASE-NEXT: @ %bb.5: @ %entry
; V8MBASE-NEXT: add sp, #8
; V8MBASE-NEXT: pop {r4, r5, r7, pc}
; V8MBASE-NEXT: .LBB1_6: @ %entry
; V8MBASE-NEXT: bl __stack_chk_fail

entry:
%0 = load i32, ptr @aa, align 4
Expand Down
161 changes: 82 additions & 79 deletions llvm/test/CodeGen/Thumb/umul_fix_sat.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,95 +38,94 @@ define i64 @func2(i64 %x, i64 %y) nounwind {
; ARM-NEXT: sub sp, #28
; ARM-NEXT: str r3, [sp, #24] @ 4-byte Spill
; ARM-NEXT: mov r5, r1
; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill
; ARM-NEXT: str r1, [sp, #4] @ 4-byte Spill
; ARM-NEXT: movs r4, #0
; ARM-NEXT: mov r6, r0
; ARM-NEXT: str r0, [sp, #12] @ 4-byte Spill
; ARM-NEXT: str r0, [sp, #8] @ 4-byte Spill
; ARM-NEXT: mov r1, r4
; ARM-NEXT: mov r7, r2
; ARM-NEXT: str r2, [sp, #16] @ 4-byte Spill
; ARM-NEXT: str r2, [sp, #12] @ 4-byte Spill
; ARM-NEXT: mov r3, r4
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: str r0, [sp] @ 4-byte Spill
; ARM-NEXT: str r1, [sp, #20] @ 4-byte Spill
; ARM-NEXT: str r0, [sp, #20] @ 4-byte Spill
; ARM-NEXT: str r1, [sp, #16] @ 4-byte Spill
; ARM-NEXT: mov r0, r5
; ARM-NEXT: mov r1, r4
; ARM-NEXT: mov r2, r7
; ARM-NEXT: mov r3, r4
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: mov r5, r1
; ARM-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; ARM-NEXT: ldr r1, [sp, #16] @ 4-byte Reload
; ARM-NEXT: adds r0, r0, r1
; ARM-NEXT: str r0, [sp, #20] @ 4-byte Spill
; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill
; ARM-NEXT: adcs r5, r4
; ARM-NEXT: mov r0, r6
; ARM-NEXT: mov r1, r4
; ARM-NEXT: ldr r7, [sp, #24] @ 4-byte Reload
; ARM-NEXT: mov r2, r7
; ARM-NEXT: mov r3, r4
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
; ARM-NEXT: ldr r2, [sp, #16] @ 4-byte Reload
; ARM-NEXT: adds r0, r0, r2
; ARM-NEXT: str r0, [sp, #20] @ 4-byte Spill
; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill
; ARM-NEXT: adcs r1, r4
; ARM-NEXT: adds r0, r5, r1
; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
; ARM-NEXT: str r0, [sp] @ 4-byte Spill
; ARM-NEXT: mov r6, r4
; ARM-NEXT: adcs r6, r4
; ARM-NEXT: ldr r5, [sp, #8] @ 4-byte Reload
; ARM-NEXT: ldr r5, [sp, #4] @ 4-byte Reload
; ARM-NEXT: mov r0, r5
; ARM-NEXT: mov r1, r4
; ARM-NEXT: mov r2, r7
; ARM-NEXT: mov r3, r4
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: mov r7, r1
; ARM-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; ARM-NEXT: ldr r1, [sp] @ 4-byte Reload
; ARM-NEXT: adds r0, r0, r1
; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
; ARM-NEXT: str r0, [sp] @ 4-byte Spill
; ARM-NEXT: adcs r7, r6
; ARM-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
; ARM-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; ARM-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
; ARM-NEXT: mov r2, r4
; ARM-NEXT: mov r3, r4
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: mov r6, r0
; ARM-NEXT: str r1, [sp, #24] @ 4-byte Spill
; ARM-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; ARM-NEXT: ldr r0, [sp, #8] @ 4-byte Reload
; ARM-NEXT: mov r1, r5
; ARM-NEXT: mov r2, r4
; ARM-NEXT: mov r3, r4
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: adds r0, r0, r6
; ARM-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
; ARM-NEXT: adcs r1, r2
; ARM-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
; ARM-NEXT: adds r2, r2, r0
; ARM-NEXT: ldr r2, [sp] @ 4-byte Reload
; ARM-NEXT: adds r0, r2, r0
; ARM-NEXT: adcs r1, r7
; ARM-NEXT: lsrs r3, r2, #2
; ARM-NEXT: orrs r3, r1
; ARM-NEXT: lsrs r5, r0, #2
; ARM-NEXT: orrs r5, r1
; ARM-NEXT: lsls r0, r0, #30
; ARM-NEXT: ldr r3, [sp, #16] @ 4-byte Reload
; ARM-NEXT: lsrs r1, r3, #2
; ARM-NEXT: adds r2, r0, r1
; ARM-NEXT: lsls r0, r3, #30
; ARM-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; ARM-NEXT: lsrs r1, r1, #2
; ARM-NEXT: adds r3, r0, r1
; ARM-NEXT: mvns r1, r4
; ARM-NEXT: cmp r3, #0
; ARM-NEXT: cmp r5, #0
; ARM-NEXT: mov r0, r1
; ARM-NEXT: beq .LBB1_3
; ARM-NEXT: @ %bb.1:
; ARM-NEXT: cmp r3, #0
; ARM-NEXT: beq .LBB1_4
; ARM-NEXT: .LBB1_2:
; ARM-NEXT: add sp, #28
; ARM-NEXT: pop {r4, r5, r6, r7, pc}
; ARM-NEXT: .LBB1_3:
; ARM-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
; ARM-NEXT: lsls r0, r0, #30
; ARM-NEXT: ldr r4, [sp] @ 4-byte Reload
; ARM-NEXT: lsrs r4, r4, #2
; ARM-NEXT: adds r0, r0, r4
; ARM-NEXT: cmp r3, #0
; ARM-NEXT: mov r0, r3
; ARM-NEXT: bne .LBB1_2
; ARM-NEXT: .LBB1_4:
; ARM-NEXT: lsls r1, r2, #30
; ARM-NEXT: ldr r2, [sp, #20] @ 4-byte Reload
; ARM-NEXT: lsrs r2, r2, #2
; ARM-NEXT: adds r1, r1, r2
; ARM-NEXT: mov r1, r2
; ARM-NEXT: add sp, #28
; ARM-NEXT: pop {r4, r5, r6, r7, pc}
%tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 2)
Expand Down Expand Up @@ -225,17 +224,16 @@ define i64 @func5(i64 %x, i64 %y) {
; ARM-NEXT: mov r3, r5
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: adds r3, r1, r6
; ARM-NEXT: mov r6, r5
; ARM-NEXT: adcs r6, r5
; ARM-NEXT: orrs r6, r4
; ARM-NEXT: mov r2, r5
; ARM-NEXT: adcs r2, r5
; ARM-NEXT: orrs r2, r4
; ARM-NEXT: mvns r1, r5
; ARM-NEXT: cmp r6, #0
; ARM-NEXT: cmp r2, #0
; ARM-NEXT: mov r2, r1
; ARM-NEXT: bne .LBB4_2
; ARM-NEXT: @ %bb.1:
; ARM-NEXT: mov r2, r0
; ARM-NEXT: .LBB4_2:
; ARM-NEXT: cmp r6, #0
; ARM-NEXT: bne .LBB4_4
; ARM-NEXT: @ %bb.3:
; ARM-NEXT: mov r1, r3
Expand Down Expand Up @@ -399,25 +397,27 @@ define i64 @func7(i64 %x, i64 %y) nounwind {
; ARM-NEXT: mov r2, r4
; ARM-NEXT: mov r3, r4
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: mov r2, r1
; ARM-NEXT: adds r0, r0, r5
; ARM-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
; ARM-NEXT: adcs r1, r2
; ARM-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; ARM-NEXT: adds r3, r2, r0
; ARM-NEXT: adcs r1, r6
; ARM-NEXT: mvns r2, r4
; ARM-NEXT: cmp r1, #0
; ARM-NEXT: mov r0, r2
; ARM-NEXT: bne .LBB7_2
; ARM-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
; ARM-NEXT: adcs r2, r1
; ARM-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
; ARM-NEXT: adds r3, r1, r0
; ARM-NEXT: adcs r2, r6
; ARM-NEXT: mvns r1, r4
; ARM-NEXT: cmp r2, #0
; ARM-NEXT: mov r0, r1
; ARM-NEXT: beq .LBB7_3
; ARM-NEXT: @ %bb.1:
; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; ARM-NEXT: beq .LBB7_4
; ARM-NEXT: .LBB7_2:
; ARM-NEXT: cmp r1, #0
; ARM-NEXT: bne .LBB7_4
; ARM-NEXT: @ %bb.3:
; ARM-NEXT: mov r2, r3
; ARM-NEXT: add sp, #28
; ARM-NEXT: pop {r4, r5, r6, r7, pc}
; ARM-NEXT: .LBB7_3:
; ARM-NEXT: ldr r0, [sp, #4] @ 4-byte Reload
; ARM-NEXT: bne .LBB7_2
; ARM-NEXT: .LBB7_4:
; ARM-NEXT: mov r1, r2
; ARM-NEXT: mov r1, r3
; ARM-NEXT: add sp, #28
; ARM-NEXT: pop {r4, r5, r6, r7, pc}
%tmp = call i64 @llvm.umul.fix.sat.i64(i64 %x, i64 %y, i32 32)
Expand All @@ -433,23 +433,23 @@ define i64 @func8(i64 %x, i64 %y) nounwind {
; ARM-NEXT: sub sp, #28
; ARM-NEXT: str r3, [sp, #24] @ 4-byte Spill
; ARM-NEXT: mov r7, r2
; ARM-NEXT: str r2, [sp, #20] @ 4-byte Spill
; ARM-NEXT: str r2, [sp, #16] @ 4-byte Spill
; ARM-NEXT: mov r5, r1
; ARM-NEXT: str r1, [sp, #12] @ 4-byte Spill
; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill
; ARM-NEXT: movs r4, #0
; ARM-NEXT: mov r6, r0
; ARM-NEXT: str r0, [sp, #16] @ 4-byte Spill
; ARM-NEXT: str r0, [sp, #12] @ 4-byte Spill
; ARM-NEXT: mov r1, r4
; ARM-NEXT: mov r3, r4
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: str r1, [sp, #8] @ 4-byte Spill
; ARM-NEXT: str r1, [sp, #20] @ 4-byte Spill
; ARM-NEXT: mov r0, r5
; ARM-NEXT: mov r1, r4
; ARM-NEXT: mov r2, r7
; ARM-NEXT: mov r3, r4
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: mov r7, r1
; ARM-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
; ARM-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; ARM-NEXT: adds r5, r0, r1
; ARM-NEXT: adcs r7, r4
; ARM-NEXT: mov r0, r6
Expand All @@ -459,57 +459,60 @@ define i64 @func8(i64 %x, i64 %y) nounwind {
; ARM-NEXT: mov r3, r4
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: adds r0, r0, r5
; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
; ARM-NEXT: str r0, [sp, #20] @ 4-byte Spill
; ARM-NEXT: adcs r1, r4
; ARM-NEXT: adds r0, r7, r1
; ARM-NEXT: str r0, [sp, #8] @ 4-byte Spill
; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
; ARM-NEXT: mov r5, r4
; ARM-NEXT: adcs r5, r4
; ARM-NEXT: ldr r7, [sp, #12] @ 4-byte Reload
; ARM-NEXT: ldr r7, [sp, #8] @ 4-byte Reload
; ARM-NEXT: mov r0, r7
; ARM-NEXT: mov r1, r4
; ARM-NEXT: mov r2, r6
; ARM-NEXT: mov r3, r4
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: mov r6, r1
; ARM-NEXT: ldr r1, [sp, #8] @ 4-byte Reload
; ARM-NEXT: ldr r1, [sp, #4] @ 4-byte Reload
; ARM-NEXT: adds r0, r0, r1
; ARM-NEXT: str r0, [sp, #8] @ 4-byte Spill
; ARM-NEXT: str r0, [sp, #4] @ 4-byte Spill
; ARM-NEXT: adcs r6, r5
; ARM-NEXT: ldr r0, [sp, #20] @ 4-byte Reload
; ARM-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
; ARM-NEXT: ldr r1, [sp, #24] @ 4-byte Reload
; ARM-NEXT: mov r2, r4
; ARM-NEXT: mov r3, r4
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: mov r5, r0
; ARM-NEXT: str r1, [sp, #24] @ 4-byte Spill
; ARM-NEXT: ldr r0, [sp, #16] @ 4-byte Reload
; ARM-NEXT: ldr r0, [sp, #12] @ 4-byte Reload
; ARM-NEXT: mov r1, r7
; ARM-NEXT: mov r2, r4
; ARM-NEXT: mov r3, r4
; ARM-NEXT: bl __aeabi_lmul
; ARM-NEXT: adds r0, r0, r5
; ARM-NEXT: ldr r2, [sp, #24] @ 4-byte Reload
; ARM-NEXT: adcs r1, r2
; ARM-NEXT: ldr r2, [sp, #8] @ 4-byte Reload
; ARM-NEXT: adds r5, r2, r0
; ARM-NEXT: ldr r2, [sp, #4] @ 4-byte Reload
; ARM-NEXT: adds r0, r2, r0
; ARM-NEXT: adcs r1, r6
; ARM-NEXT: lsrs r3, r5, #31
; ARM-NEXT: mvns r2, r4
; ARM-NEXT: cmp r3, #0
; ARM-NEXT: mov r0, r2
; ARM-NEXT: bne .LBB8_2
; ARM-NEXT: lsls r1, r1, #1
; ARM-NEXT: lsrs r5, r0, #31
; ARM-NEXT: adds r2, r1, r5
; ARM-NEXT: lsls r0, r0, #1
; ARM-NEXT: ldr r1, [sp, #20] @ 4-byte Reload
; ARM-NEXT: lsrs r1, r1, #31
; ARM-NEXT: adds r3, r0, r1
; ARM-NEXT: mvns r1, r4
; ARM-NEXT: cmp r5, #0
; ARM-NEXT: mov r0, r1
; ARM-NEXT: beq .LBB8_3
; ARM-NEXT: @ %bb.1:
; ARM-NEXT: lsls r0, r5, #1
; ARM-NEXT: ldr r4, [sp, #4] @ 4-byte Reload
; ARM-NEXT: lsrs r4, r4, #31
; ARM-NEXT: adds r0, r0, r4
; ARM-NEXT: beq .LBB8_4
; ARM-NEXT: .LBB8_2:
; ARM-NEXT: cmp r3, #0
; ARM-NEXT: bne .LBB8_4
; ARM-NEXT: @ %bb.3:
; ARM-NEXT: lsls r1, r1, #1
; ARM-NEXT: adds r2, r1, r3
; ARM-NEXT: add sp, #28
; ARM-NEXT: pop {r4, r5, r6, r7, pc}
; ARM-NEXT: .LBB8_3:
; ARM-NEXT: mov r0, r3
; ARM-NEXT: bne .LBB8_2
; ARM-NEXT: .LBB8_4:
; ARM-NEXT: mov r1, r2
; ARM-NEXT: add sp, #28
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Thumb2/LowOverheadLoops/arm_cmplx_dot_prod_f32.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,13 +15,13 @@ define void @arm_cmplx_dot_prod_f32(ptr %pSrcA, ptr %pSrcB, i32 %numSamples, ptr
; CHECK-NEXT: lsrs r4, r2, #2
; CHECK-NEXT: mov.w lr, #2
; CHECK-NEXT: cmp r4, #2
; CHECK-NEXT: vldrw.u32 q2, [r1], #32
; CHECK-NEXT: vldrw.u32 q1, [r0], #32
; CHECK-NEXT: it lt
; CHECK-NEXT: lsrlt.w lr, r2, #2
; CHECK-NEXT: rsb r4, lr, r2, lsr #2
; CHECK-NEXT: vldrw.u32 q2, [r1], #32
; CHECK-NEXT: add.w lr, r4, #1
; CHECK-NEXT: vldrw.u32 q1, [r0], #32
; CHECK-NEXT: vmov.i32 q0, #0x0
; CHECK-NEXT: add.w lr, r4, #1
; CHECK-NEXT: .LBB0_2: @ %while.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vcmla.f32 q0, q1, q2, #0
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/Thumb2/LowOverheadLoops/exitcount.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,26 +7,26 @@ define void @foo(ptr nocapture readonly %st, ptr %x) {
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .save {r4, lr}
; CHECK-NEXT: push {r4, lr}
; CHECK-NEXT: ldrd r12, r2, [r0]
; CHECK-NEXT: ldrd r4, r3, [r0, #8]
; CHECK-NEXT: rsb r12, r12, r2, lsl #1
; CHECK-NEXT: ldrd r12, r3, [r0]
; CHECK-NEXT: ldrd r4, r2, [r0, #8]
; CHECK-NEXT: rsb r12, r12, r3, lsl #1
; CHECK-NEXT: dlstp.16 lr, r12
; CHECK-NEXT: .LBB0_1: @ %do.body
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u16 q0, [r3], #16
; CHECK-NEXT: vldrh.u16 q0, [r2], #16
; CHECK-NEXT: vstrh.16 q0, [r4], #16
; CHECK-NEXT: letp lr, .LBB0_1
; CHECK-NEXT: @ %bb.2: @ %do.end
; CHECK-NEXT: ldr r2, [r0]
; CHECK-NEXT: ldr r3, [r0]
; CHECK-NEXT: ldr r0, [r0, #8]
; CHECK-NEXT: add.w r0, r0, r12, lsl #1
; CHECK-NEXT: mov.w r3, #6144
; CHECK-NEXT: dlstp.16 lr, r2
; CHECK-NEXT: mov.w r2, #6144
; CHECK-NEXT: dlstp.16 lr, r3
; CHECK-NEXT: .LBB0_3: @ %do.body6
; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: vldrh.u16 q0, [r1], #16
; CHECK-NEXT: vcvt.f16.s16 q0, q0
; CHECK-NEXT: vmul.f16 q0, q0, r3
; CHECK-NEXT: vmul.f16 q0, q0, r2
; CHECK-NEXT: vstrh.16 q0, [r0], #16
; CHECK-NEXT: letp lr, .LBB0_3
; CHECK-NEXT: @ %bb.4: @ %do.end13
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/Thumb2/LowOverheadLoops/fast-fp-loops.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,12 +9,12 @@ define arm_aapcs_vfpcc void @fast_float_mul(ptr nocapture %a, ptr nocapture read
; CHECK-NEXT: beq.w .LBB0_11
; CHECK-NEXT: @ %bb.1: @ %vector.memcheck
; CHECK-NEXT: add.w r4, r2, r3, lsl #2
; CHECK-NEXT: add.w lr, r0, r3, lsl #2
; CHECK-NEXT: cmp r4, r0
; CHECK-NEXT: cset r4, hi
; CHECK-NEXT: cmp lr, r2
; CHECK-NEXT: csel r12, zr, r4, ls
; CHECK-NEXT: cmp lr, r1
; CHECK-NEXT: add.w r4, r0, r3, lsl #2
; CHECK-NEXT: cset r12, hi
; CHECK-NEXT: cmp r4, r2
; CHECK-NEXT: csel r12, zr, r12, ls
; CHECK-NEXT: cmp r4, r1
; CHECK-NEXT: add.w r4, r1, r3, lsl #2
; CHECK-NEXT: cset lr, hi
; CHECK-NEXT: cmp r4, r0
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/Thumb2/float-ops.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -289,15 +289,15 @@ define float @select_f(float %a, float %b, i1 %c) {
define double @select_d(double %a, double %b, i1 %c) {
; CHECK-LABEL: select_d:
; NOREGS: ldr{{(.w)?}} [[REG:r[0-9]+]], [sp]
; NOREGS: ands [[REG]], [[REG]], #1
; ONLYREGS: ands r0, r0, #1
; NOREGS: lsls.w [[REG]], [[REG]], #31
; ONLYREGS: lsls r0, r0, #31
; NOREGS-DAG: moveq r0, r2
; NOREGS-DAG: moveq r1, r3
; ONLYREGS-DAG: csel r0, r0, r2
; ONLYREGS-DAG: csel r1, r1, r3
; SP: ands r0, r0, #1
; ONLYREGS-DAG: csel r0, r2, r1
; ONLYREGS-DAG: csel r1, r12, r3
; SP-DAG: vmov [[ALO:r[0-9]+]], [[AHI:r[0-9]+]], d0
; SP-DAG: vmov [[BLO:r[0-9]+]], [[BHI:r[0-9]+]], d1
; SP: lsls r0, r0, #31
; SP: itt ne
; SP-DAG: movne [[BLO]], [[ALO]]
; SP-DAG: movne [[BHI]], [[AHI]]
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/Thumb2/mve-blockplacement.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -489,10 +489,10 @@ define i32 @d(i64 %e, i32 %f, i64 %g, i32 %h) {
; CHECK-NEXT: @ Parent Loop BB1_10 Depth=2
; CHECK-NEXT: @ => This Inner Loop Header: Depth=3
; CHECK-NEXT: vqadd.u32 q2, q5, r1
; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: adds r1, #4
; CHECK-NEXT: vcmp.u32 hi, q7, q2
; CHECK-NEXT: vshl.i32 q2, q1, #2
; CHECK-NEXT: add.w r1, r1, #4
; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: vadd.i32 q2, q2, r8
; CHECK-NEXT: vadd.i32 q1, q1, r9
; CHECK-NEXT: vpst
Expand All @@ -508,10 +508,10 @@ define i32 @d(i64 %e, i32 %f, i64 %g, i32 %h) {
; CHECK-NEXT: @ Parent Loop BB1_10 Depth=2
; CHECK-NEXT: @ => This Inner Loop Header: Depth=3
; CHECK-NEXT: vqadd.u32 q2, q5, r1
; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: adds r1, #4
; CHECK-NEXT: vcmp.u32 hi, q6, q2
; CHECK-NEXT: vshl.i32 q2, q1, #2
; CHECK-NEXT: add.w r1, r1, #4
; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: vadd.i32 q2, q2, r8
; CHECK-NEXT: vadd.i32 q1, q1, r9
; CHECK-NEXT: vpst
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/Thumb2/mve-doublereduct.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -411,12 +411,12 @@ define i32 @nested_smin_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
; CHECK: @ %bb.0:
; CHECK-NEXT: mvn r3, #-2147483648
; CHECK-NEXT: mvn r2, #-2147483648
; CHECK-NEXT: vminv.s32 r3, q0
; CHECK-NEXT: vminv.s32 r2, q1
; CHECK-NEXT: cmp r3, r0
; CHECK-NEXT: csel r0, r3, r0, lt
; CHECK-NEXT: cmp r2, r1
; CHECK-NEXT: csel r1, r2, r1, lt
; CHECK-NEXT: vminv.s32 r3, q1
; CHECK-NEXT: vminv.s32 r2, q0
; CHECK-NEXT: cmp r3, r1
; CHECK-NEXT: csel r1, r3, r1, lt
; CHECK-NEXT: cmp r2, r0
; CHECK-NEXT: csel r0, r2, r0, lt
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: csel r0, r0, r1, lt
; CHECK-NEXT: bx lr
Expand All @@ -433,12 +433,12 @@ define i32 @nested_smax_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
; CHECK: @ %bb.0:
; CHECK-NEXT: mov.w r3, #-2147483648
; CHECK-NEXT: mov.w r2, #-2147483648
; CHECK-NEXT: vmaxv.s32 r3, q0
; CHECK-NEXT: vmaxv.s32 r2, q1
; CHECK-NEXT: cmp r3, r0
; CHECK-NEXT: csel r0, r3, r0, gt
; CHECK-NEXT: cmp r2, r1
; CHECK-NEXT: csel r1, r2, r1, gt
; CHECK-NEXT: vmaxv.s32 r3, q1
; CHECK-NEXT: vmaxv.s32 r2, q0
; CHECK-NEXT: cmp r3, r1
; CHECK-NEXT: csel r1, r3, r1, gt
; CHECK-NEXT: cmp r2, r0
; CHECK-NEXT: csel r0, r2, r0, gt
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: csel r0, r0, r1, gt
; CHECK-NEXT: bx lr
Expand All @@ -455,12 +455,12 @@ define i32 @nested_umin_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
; CHECK: @ %bb.0:
; CHECK-NEXT: mov.w r3, #-1
; CHECK-NEXT: mov.w r2, #-1
; CHECK-NEXT: vminv.u32 r3, q0
; CHECK-NEXT: vminv.u32 r2, q1
; CHECK-NEXT: cmp r3, r0
; CHECK-NEXT: csel r0, r3, r0, lo
; CHECK-NEXT: cmp r2, r1
; CHECK-NEXT: csel r1, r2, r1, lo
; CHECK-NEXT: vminv.u32 r3, q1
; CHECK-NEXT: vminv.u32 r2, q0
; CHECK-NEXT: cmp r3, r1
; CHECK-NEXT: csel r1, r3, r1, lo
; CHECK-NEXT: cmp r2, r0
; CHECK-NEXT: csel r0, r2, r0, lo
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: csel r0, r0, r1, lo
; CHECK-NEXT: bx lr
Expand All @@ -477,12 +477,12 @@ define i32 @nested_umax_i32(<4 x i32> %a, <4 x i32> %b, i32 %c, i32 %d) {
; CHECK: @ %bb.0:
; CHECK-NEXT: movs r3, #0
; CHECK-NEXT: movs r2, #0
; CHECK-NEXT: vmaxv.u32 r3, q0
; CHECK-NEXT: vmaxv.u32 r2, q1
; CHECK-NEXT: cmp r3, r0
; CHECK-NEXT: csel r0, r3, r0, hi
; CHECK-NEXT: cmp r2, r1
; CHECK-NEXT: csel r1, r2, r1, hi
; CHECK-NEXT: vmaxv.u32 r3, q1
; CHECK-NEXT: vmaxv.u32 r2, q0
; CHECK-NEXT: cmp r3, r1
; CHECK-NEXT: csel r1, r3, r1, hi
; CHECK-NEXT: cmp r2, r0
; CHECK-NEXT: csel r0, r2, r0, hi
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: csel r0, r0, r1, hi
; CHECK-NEXT: bx lr
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Thumb2/mve-float16regloops.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1365,8 +1365,8 @@ define void @arm_biquad_cascade_df2T_f16(ptr nocapture readonly %S, ptr nocaptur
; CHECK-NEXT: @ in Loop: Header=BB17_3 Depth=1
; CHECK-NEXT: vstr.16 s5, [r6, #2]
; CHECK-NEXT: add.w r12, r12, #10
; CHECK-NEXT: adds r6, #4
; CHECK-NEXT: subs.w r9, r9, #1
; CHECK-NEXT: add.w r6, r6, #4
; CHECK-NEXT: mov r1, r2
; CHECK-NEXT: beq .LBB17_8
; CHECK-NEXT: .LBB17_3: @ %do.body
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/Thumb2/mve-float32regloops.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1375,8 +1375,8 @@ define arm_aapcs_vfpcc void @arm_biquad_cascade_stereo_df2T_f32(ptr nocapture re
; CHECK-NEXT: le lr, .LBB17_3
; CHECK-NEXT: @ %bb.4: @ %bb75
; CHECK-NEXT: @ in Loop: Header=BB17_2 Depth=1
; CHECK-NEXT: adds r3, #20
; CHECK-NEXT: subs.w r12, r12, #1
; CHECK-NEXT: add.w r3, r3, #20
; CHECK-NEXT: vstrb.8 q3, [r0], #16
; CHECK-NEXT: mov r1, r2
; CHECK-NEXT: bne .LBB17_2
Expand Down Expand Up @@ -1514,8 +1514,8 @@ define arm_aapcs_vfpcc void @fms(ptr nocapture readonly %pSrc1, ptr nocapture re
; CHECK-NEXT: le lr, .LBB18_3
; CHECK-NEXT: @ %bb.4: @ %while.end
; CHECK-NEXT: @ in Loop: Header=BB18_2 Depth=1
; CHECK-NEXT: adds r2, #4
; CHECK-NEXT: subs.w r12, r12, #1
; CHECK-NEXT: add.w r2, r2, #4
; CHECK-NEXT: bne .LBB18_2
; CHECK-NEXT: .LBB18_5: @ %do.end
; CHECK-NEXT: pop {r4, r5, r7, pc}
Expand Down Expand Up @@ -1918,8 +1918,8 @@ define void @arm_biquad_cascade_df2T_f32(ptr nocapture readonly %S, ptr nocaptur
; CHECK-NEXT: @ in Loop: Header=BB20_3 Depth=1
; CHECK-NEXT: vstr s6, [r6, #4]
; CHECK-NEXT: add.w r12, r12, #20
; CHECK-NEXT: adds r6, #8
; CHECK-NEXT: subs r0, #1
; CHECK-NEXT: add.w r6, r6, #8
; CHECK-NEXT: mov r1, r2
; CHECK-NEXT: beq .LBB20_8
; CHECK-NEXT: .LBB20_3: @ %do.body
Expand Down
116 changes: 58 additions & 58 deletions llvm/test/CodeGen/Thumb2/mve-fmas.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -893,33 +893,33 @@ define arm_aapcs_vfpcc <4 x float> @vfma32_v1_pred(<4 x float> %src1, <4 x float
;
; CHECK-MVE-LABEL: vfma32_v1_pred:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s2
; CHECK-MVE-NEXT: vmov.f32 s12, s3
; CHECK-MVE-NEXT: vmla.f32 s14, s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s2
; CHECK-MVE-NEXT: vmov.f32 s14, s3
; CHECK-MVE-NEXT: vmla.f32 s12, s6, s10
; CHECK-MVE-NEXT: vmov.f32 s10, s1
; CHECK-MVE-NEXT: vmla.f32 s12, s7, s11
; CHECK-MVE-NEXT: vmla.f32 s14, s7, s11
; CHECK-MVE-NEXT: vmla.f32 s10, s5, s9
; CHECK-MVE-NEXT: vmov.f32 s9, s0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: vmla.f32 s9, s4, s8
; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s12
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s14
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s12
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s14
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s9
; CHECK-MVE-NEXT: bx lr
entry:
Expand All @@ -946,33 +946,33 @@ define arm_aapcs_vfpcc <4 x float> @vfma32_v2_pred(<4 x float> %src1, <4 x float
;
; CHECK-MVE-LABEL: vfma32_v2_pred:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s2
; CHECK-MVE-NEXT: vmov.f32 s12, s3
; CHECK-MVE-NEXT: vmla.f32 s14, s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s2
; CHECK-MVE-NEXT: vmov.f32 s14, s3
; CHECK-MVE-NEXT: vmla.f32 s12, s6, s10
; CHECK-MVE-NEXT: vmov.f32 s10, s1
; CHECK-MVE-NEXT: vmla.f32 s12, s7, s11
; CHECK-MVE-NEXT: vmla.f32 s14, s7, s11
; CHECK-MVE-NEXT: vmla.f32 s10, s5, s9
; CHECK-MVE-NEXT: vmov.f32 s9, s0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: vmla.f32 s9, s4, s8
; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s12
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s14
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s12
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s14
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s9
; CHECK-MVE-NEXT: bx lr
entry:
Expand All @@ -999,33 +999,33 @@ define arm_aapcs_vfpcc <4 x float> @vfms32_pred(<4 x float> %src1, <4 x float> %
;
; CHECK-MVE-LABEL: vfms32_pred:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s14, s2
; CHECK-MVE-NEXT: vmov.f32 s12, s3
; CHECK-MVE-NEXT: vmls.f32 s14, s6, s10
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: vmov.f32 s12, s2
; CHECK-MVE-NEXT: vmov.f32 s14, s3
; CHECK-MVE-NEXT: vmls.f32 s12, s6, s10
; CHECK-MVE-NEXT: vmov.f32 s10, s1
; CHECK-MVE-NEXT: vmls.f32 s12, s7, s11
; CHECK-MVE-NEXT: vmls.f32 s14, s7, s11
; CHECK-MVE-NEXT: vmls.f32 s10, s5, s9
; CHECK-MVE-NEXT: vmov.f32 s9, s0
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: vmls.f32 s9, s4, s8
; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s12
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s14
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s12
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s10
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s14
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s9
; CHECK-MVE-NEXT: bx lr
entry:
Expand Down Expand Up @@ -1055,33 +1055,33 @@ define arm_aapcs_vfpcc <4 x float> @vfmar32_pred(<4 x float> %src1, <4 x float>
;
; CHECK-MVE-LABEL: vfmar32_pred:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: vmov.f32 s10, s3
; CHECK-MVE-NEXT: vmov.f32 s12, s2
; CHECK-MVE-NEXT: vmov.f32 s14, s1
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: vmov.f32 s10, s2
; CHECK-MVE-NEXT: vmov.f32 s12, s1
; CHECK-MVE-NEXT: vmov.f32 s14, s3
; CHECK-MVE-NEXT: vmov.f32 s9, s0
; CHECK-MVE-NEXT: vmla.f32 s10, s7, s8
; CHECK-MVE-NEXT: vmla.f32 s12, s6, s8
; CHECK-MVE-NEXT: vmla.f32 s14, s5, s8
; CHECK-MVE-NEXT: vmla.f32 s10, s6, s8
; CHECK-MVE-NEXT: vmla.f32 s12, s5, s8
; CHECK-MVE-NEXT: vmla.f32 s14, s7, s8
; CHECK-MVE-NEXT: vmla.f32 s9, s4, s8
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s10
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s12
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s14
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s10
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s14
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s9
; CHECK-MVE-NEXT: bx lr
entry:
Expand Down Expand Up @@ -1112,32 +1112,32 @@ define arm_aapcs_vfpcc <4 x float> @vfmas32_pred(<4 x float> %src1, <4 x float>
;
; CHECK-MVE-LABEL: vfmas32_pred:
; CHECK-MVE: @ %bb.0: @ %entry
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s4, #0
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: vmov.f32 s10, s8
; CHECK-MVE-NEXT: vmov.f32 s12, s8
; CHECK-MVE-NEXT: vmov.f32 s14, s8
; CHECK-MVE-NEXT: vmla.f32 s8, s0, s4
; CHECK-MVE-NEXT: vmla.f32 s10, s3, s7
; CHECK-MVE-NEXT: vmla.f32 s12, s2, s6
; CHECK-MVE-NEXT: vmla.f32 s14, s1, s5
; CHECK-MVE-NEXT: vmla.f32 s10, s2, s6
; CHECK-MVE-NEXT: vmla.f32 s12, s1, s5
; CHECK-MVE-NEXT: vmla.f32 s14, s3, s7
; CHECK-MVE-NEXT: cset r0, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s7, #0
; CHECK-MVE-NEXT: vcmp.f32 s5, #0
; CHECK-MVE-NEXT: cset r1, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: vcmp.f32 s6, #0
; CHECK-MVE-NEXT: cset r2, mi
; CHECK-MVE-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-MVE-NEXT: cset r3, mi
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s10
; CHECK-MVE-NEXT: cmp r3, #0
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s12
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s14
; CHECK-MVE-NEXT: vseleq.f32 s2, s2, s10
; CHECK-MVE-NEXT: cmp r2, #0
; CHECK-MVE-NEXT: vseleq.f32 s1, s1, s12
; CHECK-MVE-NEXT: cmp r1, #0
; CHECK-MVE-NEXT: vseleq.f32 s3, s3, s14
; CHECK-MVE-NEXT: cmp r0, #0
; CHECK-MVE-NEXT: vseleq.f32 s0, s0, s8
; CHECK-MVE-NEXT: bx lr
entry:
Expand Down
704 changes: 323 additions & 381 deletions llvm/test/CodeGen/Thumb2/mve-fpclamptosat_vec.ll
View file

Large diffs are not rendered by default.

3,789 changes: 1,748 additions & 2,041 deletions llvm/test/CodeGen/Thumb2/mve-fptosi-sat-vector.ll
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Large diffs are not rendered by default.

2,953 changes: 1,350 additions & 1,603 deletions llvm/test/CodeGen/Thumb2/mve-fptoui-sat-vector.ll
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Large diffs are not rendered by default.

16 changes: 8 additions & 8 deletions llvm/test/CodeGen/Thumb2/mve-gather-scatter-ptr-address.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -623,9 +623,9 @@ define arm_aapcs_vfpcc void @three_pointer_iv_v4i32(ptr nocapture readonly %x, p
; CHECK-NEXT: vldrw.u32 q3, [r0, q0]
; CHECK-NEXT: vldrw.u32 q4, [r0, q1, uxtw #2]
; CHECK-NEXT: vldrw.u32 q5, [r0, q2]
; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: adds r0, #48
; CHECK-NEXT: vmul.i32 q3, q4, q3
; CHECK-NEXT: add.w r0, r0, #48
; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: vmul.i32 q5, q4, q5
; CHECK-NEXT: vmul.i32 q4, q4, r3
; CHECK-NEXT: vstrw.32 q4, [r1, q1, uxtw #2]
Expand Down Expand Up @@ -705,9 +705,9 @@ define arm_aapcs_vfpcc void @three_pointer_iv_v4i8(ptr nocapture readonly %x, pt
; CHECK-NEXT: vldrb.u32 q3, [r0, q0]
; CHECK-NEXT: vldrb.u32 q4, [r0, q1]
; CHECK-NEXT: vldrb.u32 q5, [r0, q2]
; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: adds r0, #12
; CHECK-NEXT: vmul.i32 q3, q4, q3
; CHECK-NEXT: add.w r0, r0, #12
; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: vmul.i32 q5, q4, q5
; CHECK-NEXT: vmul.i32 q4, q4, r3
; CHECK-NEXT: vstrb.32 q4, [r1, q1]
Expand Down Expand Up @@ -793,9 +793,9 @@ define arm_aapcs_vfpcc void @three_pointer_iv_v8i16(ptr nocapture readonly %x, p
; CHECK-NEXT: vldrh.u16 q3, [r0, q0]
; CHECK-NEXT: vldrh.u16 q4, [r0, q1, uxtw #1]
; CHECK-NEXT: vldrh.u16 q5, [r0, q2]
; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: adds r0, #48
; CHECK-NEXT: vmul.i16 q3, q4, q3
; CHECK-NEXT: add.w r0, r0, #48
; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: vmul.i16 q5, q4, q5
; CHECK-NEXT: vmul.i16 q4, q4, r3
; CHECK-NEXT: vstrh.16 q4, [r1, q1, uxtw #1]
Expand Down Expand Up @@ -887,9 +887,9 @@ define arm_aapcs_vfpcc void @three_pointer_iv_v16i8(ptr nocapture readonly %x, p
; CHECK-NEXT: vldrb.u8 q3, [r0, q0]
; CHECK-NEXT: vldrb.u8 q4, [r0, q1]
; CHECK-NEXT: vldrb.u8 q5, [r0, q2]
; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: adds r0, #48
; CHECK-NEXT: vmul.i8 q3, q4, q3
; CHECK-NEXT: add.w r0, r0, #48
; CHECK-NEXT: subs r2, #4
; CHECK-NEXT: vmul.i8 q5, q4, q5
; CHECK-NEXT: vmul.i8 q4, q4, r3
; CHECK-NEXT: vstrb.8 q4, [r1, q1]
Expand Down
93 changes: 47 additions & 46 deletions llvm/test/CodeGen/Thumb2/mve-laneinterleaving.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -307,82 +307,83 @@ define arm_aapcs_vfpcc <4 x i32> @ext_ops_trunc_i32(<4 x i32> %a, <4 x i32> %b)
; CHECK-NEXT: vmov.f32 s10, s7
; CHECK-NEXT: vmov r10, s8
; CHECK-NEXT: vmov.f32 s8, s6
; CHECK-NEXT: vmov r7, s2
; CHECK-NEXT: vmov.f32 s2, s1
; CHECK-NEXT: vmov.f32 s6, s5
; CHECK-NEXT: vmov r2, s8
; CHECK-NEXT: asr.w r0, r10, #31
; CHECK-NEXT: asrs r5, r7, #31
; CHECK-NEXT: adds.w r4, r10, r2
; CHECK-NEXT: eor.w r6, r10, r2
; CHECK-NEXT: adds.w r6, r10, r2
; CHECK-NEXT: eor.w r7, r10, r2
; CHECK-NEXT: adc r3, r0, #0
; CHECK-NEXT: asrl r4, r3, r2
; CHECK-NEXT: subs r0, r4, r2
; CHECK-NEXT: asrl r6, r3, r2
; CHECK-NEXT: subs r0, r6, r2
; CHECK-NEXT: vmov r6, s2
; CHECK-NEXT: sbc lr, r3, #0
; CHECK-NEXT: vmov r3, s10
; CHECK-NEXT: vmov.f32 s2, s1
; CHECK-NEXT: umull r0, r8, r0, r2
; CHECK-NEXT: adds r4, r7, r3
; CHECK-NEXT: eor.w r1, r7, r3
; CHECK-NEXT: asrs r5, r6, #31
; CHECK-NEXT: adds r4, r6, r3
; CHECK-NEXT: adc r5, r5, #0
; CHECK-NEXT: eor.w r1, r6, r3
; CHECK-NEXT: asrl r4, r5, r3
; CHECK-NEXT: subs r4, r4, r3
; CHECK-NEXT: sbc r5, r5, #0
; CHECK-NEXT: orrs.w r6, r6, r10, asr #31
; CHECK-NEXT: orrs.w r7, r7, r10, asr #31
; CHECK-NEXT: umull r4, r12, r4, r3
; CHECK-NEXT: csetm r9, eq
; CHECK-NEXT: orrs.w r1, r1, r7, asr #31
; CHECK-NEXT: mov.w r6, #0
; CHECK-NEXT: orrs.w r1, r1, r6, asr #31
; CHECK-NEXT: mov.w r7, #0
; CHECK-NEXT: csetm r1, eq
; CHECK-NEXT: bfi r6, r9, #0, #8
; CHECK-NEXT: bfi r7, r9, #0, #8
; CHECK-NEXT: mla r5, r5, r3, r12
; CHECK-NEXT: bfi r6, r1, #8, #8
; CHECK-NEXT: rsbs r1, r7, #0
; CHECK-NEXT: bfi r7, r1, #8, #8
; CHECK-NEXT: rsbs r1, r6, #0
; CHECK-NEXT: vmsr p0, r7
; CHECK-NEXT: mla r7, lr, r2, r8
; CHECK-NEXT: lsll r4, r5, r1
; CHECK-NEXT: rsb.w r1, r10, #0
; CHECK-NEXT: lsll r4, r5, r3
; CHECK-NEXT: lsll r0, r7, r1
; CHECK-NEXT: vmov lr, s2
; CHECK-NEXT: vmov r3, s2
; CHECK-NEXT: vmov r1, s6
; CHECK-NEXT: lsll r0, r7, r2
; CHECK-NEXT: lsll r4, r5, r3
; CHECK-NEXT: vmsr p0, r6
; CHECK-NEXT: vmov q3[2], q3[0], r0, r4
; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: vpsel q2, q3, q2
; CHECK-NEXT: adds.w r2, lr, r1
; CHECK-NEXT: asr.w r0, lr, #31
; CHECK-NEXT: adc r3, r0, #0
; CHECK-NEXT: asrl r2, r3, r1
; CHECK-NEXT: adds r2, r3, r1
; CHECK-NEXT: asr.w r0, r3, #31
; CHECK-NEXT: adc r5, r0, #0
; CHECK-NEXT: asrl r2, r5, r1
; CHECK-NEXT: subs r0, r2, r1
; CHECK-NEXT: vmov r2, s0
; CHECK-NEXT: sbc r7, r3, #0
; CHECK-NEXT: vmov r3, s4
; CHECK-NEXT: umull r0, r6, r0, r1
; CHECK-NEXT: asrs r5, r2, #31
; CHECK-NEXT: adds r4, r2, r3
; CHECK-NEXT: adc r5, r5, #0
; CHECK-NEXT: asrl r4, r5, r3
; CHECK-NEXT: subs r4, r4, r3
; CHECK-NEXT: sbc r8, r5, #0
; CHECK-NEXT: mla r5, r7, r1, r6
; CHECK-NEXT: eor.w r6, lr, r1
; CHECK-NEXT: orrs.w r6, r6, lr, asr #31
; CHECK-NEXT: eor.w r7, r2, r3
; CHECK-NEXT: umull r4, lr, r0, r1
; CHECK-NEXT: vmov r0, s4
; CHECK-NEXT: asrs r5, r2, #31
; CHECK-NEXT: adds r6, r2, r0
; CHECK-NEXT: adc r7, r5, #0
; CHECK-NEXT: mla r5, r8, r1, lr
; CHECK-NEXT: asrl r6, r7, r0
; CHECK-NEXT: subs.w r8, r6, r0
; CHECK-NEXT: eor.w r6, r2, r0
; CHECK-NEXT: sbc lr, r7, #0
; CHECK-NEXT: eor.w r7, r3, r1
; CHECK-NEXT: orrs.w r6, r6, r2, asr #31
; CHECK-NEXT: orr.w r7, r7, r3, asr #31
; CHECK-NEXT: csetm r6, eq
; CHECK-NEXT: cmp r7, #0
; CHECK-NEXT: bfi r12, r6, #0, #8
; CHECK-NEXT: csetm r6, eq
; CHECK-NEXT: orrs.w r7, r7, r2, asr #31
; CHECK-NEXT: csetm r7, eq
; CHECK-NEXT: rsb.w lr, lr, #0
; CHECK-NEXT: bfi r12, r7, #0, #8
; CHECK-NEXT: lsll r0, r5, lr
; CHECK-NEXT: bfi r12, r6, #8, #8
; CHECK-NEXT: umull r4, r6, r4, r3
; CHECK-NEXT: lsll r0, r5, r1
; CHECK-NEXT: rsbs r1, r2, #0
; CHECK-NEXT: umull r6, r7, r8, r0
; CHECK-NEXT: rsb.w r8, r3, #0
; CHECK-NEXT: lsll r4, r5, r8
; CHECK-NEXT: vmsr p0, r12
; CHECK-NEXT: mla r7, r8, r3, r6
; CHECK-NEXT: lsll r4, r7, r1
; CHECK-NEXT: lsll r4, r7, r3
; CHECK-NEXT: vmov q0[2], q0[0], r4, r0
; CHECK-NEXT: mla r3, lr, r0, r7
; CHECK-NEXT: lsll r4, r5, r1
; CHECK-NEXT: rsbs r1, r2, #0
; CHECK-NEXT: lsll r6, r3, r1
; CHECK-NEXT: lsll r6, r3, r0
; CHECK-NEXT: vmov q0[2], q0[0], r6, r4
; CHECK-NEXT: vpsel q0, q0, q1
; CHECK-NEXT: vmov.f32 s1, s2
; CHECK-NEXT: vmov.f32 s2, s8
Expand Down
64 changes: 24 additions & 40 deletions llvm/test/CodeGen/Thumb2/mve-minmaxi.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,8 @@ declare i8 @llvm.smax.i8(i8 %a, i8 %b) readnone
define arm_aapcs_vfpcc i8 @smaxi8(i8 %a, i8 %b) {
; CHECK-LABEL: smaxi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: sxtb r0, r0
; CHECK-NEXT: sxtb r1, r1
; CHECK-NEXT: sxtb r0, r0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: csel r0, r0, r1, gt
; CHECK-NEXT: bx lr
Expand All @@ -20,8 +20,8 @@ declare i16 @llvm.smax.i16(i16 %a, i16 %b) readnone
define arm_aapcs_vfpcc i16 @smaxi16(i16 %a, i16 %b) {
; CHECK-LABEL: smaxi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: sxth r1, r1
; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: csel r0, r0, r1, gt
; CHECK-NEXT: bx lr
Expand All @@ -48,10 +48,8 @@ define arm_aapcs_vfpcc i64 @smaxi64(i64 %a, i64 %b) {
; CHECK: @ %bb.0:
; CHECK-NEXT: subs.w r12, r2, r0
; CHECK-NEXT: sbcs.w r12, r3, r1
; CHECK-NEXT: cset r12, lt
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: csel r1, r1, r3, ne
; CHECK-NEXT: csel r0, r0, r2, lt
; CHECK-NEXT: csel r1, r1, r3, lt
; CHECK-NEXT: bx lr
%c = call i64 @llvm.smax.i64(i64 %a, i64 %b)
ret i64 %c
Expand Down Expand Up @@ -205,10 +203,8 @@ define arm_aapcs_vfpcc <1 x i64> @smax1i64(<1 x i64> %a, <1 x i64> %b) {
; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: subs.w r12, r2, r0
; CHECK-NEXT: sbcs.w r12, r3, r1
; CHECK-NEXT: cset r12, lt
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: csel r1, r1, r3, ne
; CHECK-NEXT: csel r0, r0, r2, lt
; CHECK-NEXT: csel r1, r1, r3, lt
; CHECK-NEXT: add sp, #8
; CHECK-NEXT: bx lr
%c = call <1 x i64> @llvm.smax.v1i64(<1 x i64> %a, <1 x i64> %b)
Expand Down Expand Up @@ -290,8 +286,8 @@ declare i8 @llvm.umax.i8(i8 %a, i8 %b) readnone
define arm_aapcs_vfpcc i8 @umaxi8(i8 %a, i8 %b) {
; CHECK-LABEL: umaxi8:
; CHECK: @ %bb.0:
; CHECK-NEXT: uxtb r0, r0
; CHECK-NEXT: uxtb r1, r1
; CHECK-NEXT: uxtb r0, r0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: csel r0, r0, r1, hi
; CHECK-NEXT: bx lr
Expand All @@ -304,8 +300,8 @@ declare i16 @llvm.umax.i16(i16 %a, i16 %b) readnone
define arm_aapcs_vfpcc i16 @umaxi16(i16 %a, i16 %b) {
; CHECK-LABEL: umaxi16:
; CHECK: @ %bb.0:
; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: uxth r1, r1
; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: csel r0, r0, r1, hi
; CHECK-NEXT: bx lr
Expand All @@ -332,10 +328,8 @@ define arm_aapcs_vfpcc i64 @umaxi64(i64 %a, i64 %b) {
; CHECK: @ %bb.0:
; CHECK-NEXT: subs.w r12, r2, r0
; CHECK-NEXT: sbcs.w r12, r3, r1
; CHECK-NEXT: cset r12, lo
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: csel r1, r1, r3, ne
; CHECK-NEXT: csel r0, r0, r2, lo
; CHECK-NEXT: csel r1, r1, r3, lo
; CHECK-NEXT: bx lr
%c = call i64 @llvm.umax.i64(i64 %a, i64 %b)
ret i64 %c
Expand Down Expand Up @@ -482,10 +476,8 @@ define arm_aapcs_vfpcc <1 x i64> @umax1i64(<1 x i64> %a, <1 x i64> %b) {
; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: subs.w r12, r2, r0
; CHECK-NEXT: sbcs.w r12, r3, r1
; CHECK-NEXT: cset r12, lo
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: csel r1, r1, r3, ne
; CHECK-NEXT: csel r0, r0, r2, lo
; CHECK-NEXT: csel r1, r1, r3, lo
; CHECK-NEXT: add sp, #8
; CHECK-NEXT: bx lr
%c = call <1 x i64> @llvm.umax.v1i64(<1 x i64> %a, <1 x i64> %b)
Expand Down Expand Up @@ -567,8 +559,8 @@ declare i8 @llvm.smin.i8(i8 %a, i8 %b) readnone
define arm_aapcs_vfpcc i8 @smini8(i8 %a, i8 %b) {
; CHECK-LABEL: smini8:
; CHECK: @ %bb.0:
; CHECK-NEXT: sxtb r0, r0
; CHECK-NEXT: sxtb r1, r1
; CHECK-NEXT: sxtb r0, r0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: csel r0, r0, r1, lt
; CHECK-NEXT: bx lr
Expand All @@ -581,8 +573,8 @@ declare i16 @llvm.smin.i16(i16 %a, i16 %b) readnone
define arm_aapcs_vfpcc i16 @smini16(i16 %a, i16 %b) {
; CHECK-LABEL: smini16:
; CHECK: @ %bb.0:
; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: sxth r1, r1
; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: csel r0, r0, r1, lt
; CHECK-NEXT: bx lr
Expand All @@ -609,10 +601,8 @@ define arm_aapcs_vfpcc i64 @smini64(i64 %a, i64 %b) {
; CHECK: @ %bb.0:
; CHECK-NEXT: subs.w r12, r0, r2
; CHECK-NEXT: sbcs.w r12, r1, r3
; CHECK-NEXT: cset r12, lt
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: csel r1, r1, r3, ne
; CHECK-NEXT: csel r0, r0, r2, lt
; CHECK-NEXT: csel r1, r1, r3, lt
; CHECK-NEXT: bx lr
%c = call i64 @llvm.smin.i64(i64 %a, i64 %b)
ret i64 %c
Expand Down Expand Up @@ -766,10 +756,8 @@ define arm_aapcs_vfpcc <1 x i64> @smin1i64(<1 x i64> %a, <1 x i64> %b) {
; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: subs.w r12, r0, r2
; CHECK-NEXT: sbcs.w r12, r1, r3
; CHECK-NEXT: cset r12, lt
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: csel r1, r1, r3, ne
; CHECK-NEXT: csel r0, r0, r2, lt
; CHECK-NEXT: csel r1, r1, r3, lt
; CHECK-NEXT: add sp, #8
; CHECK-NEXT: bx lr
%c = call <1 x i64> @llvm.smin.v1i64(<1 x i64> %a, <1 x i64> %b)
Expand Down Expand Up @@ -851,8 +839,8 @@ declare i8 @llvm.umin.i8(i8 %a, i8 %b) readnone
define arm_aapcs_vfpcc i8 @umini8(i8 %a, i8 %b) {
; CHECK-LABEL: umini8:
; CHECK: @ %bb.0:
; CHECK-NEXT: uxtb r0, r0
; CHECK-NEXT: uxtb r1, r1
; CHECK-NEXT: uxtb r0, r0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: csel r0, r0, r1, lo
; CHECK-NEXT: bx lr
Expand All @@ -865,8 +853,8 @@ declare i16 @llvm.umin.i16(i16 %a, i16 %b) readnone
define arm_aapcs_vfpcc i16 @umini16(i16 %a, i16 %b) {
; CHECK-LABEL: umini16:
; CHECK: @ %bb.0:
; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: uxth r1, r1
; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: cmp r0, r1
; CHECK-NEXT: csel r0, r0, r1, lo
; CHECK-NEXT: bx lr
Expand All @@ -893,10 +881,8 @@ define arm_aapcs_vfpcc i64 @umini64(i64 %a, i64 %b) {
; CHECK: @ %bb.0:
; CHECK-NEXT: subs.w r12, r0, r2
; CHECK-NEXT: sbcs.w r12, r1, r3
; CHECK-NEXT: cset r12, lo
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: csel r1, r1, r3, ne
; CHECK-NEXT: csel r0, r0, r2, lo
; CHECK-NEXT: csel r1, r1, r3, lo
; CHECK-NEXT: bx lr
%c = call i64 @llvm.umin.i64(i64 %a, i64 %b)
ret i64 %c
Expand Down Expand Up @@ -1043,10 +1029,8 @@ define arm_aapcs_vfpcc <1 x i64> @umin1i64(<1 x i64> %a, <1 x i64> %b) {
; CHECK-NEXT: sub sp, #8
; CHECK-NEXT: subs.w r12, r0, r2
; CHECK-NEXT: sbcs.w r12, r1, r3
; CHECK-NEXT: cset r12, lo
; CHECK-NEXT: cmp.w r12, #0
; CHECK-NEXT: csel r0, r0, r2, ne
; CHECK-NEXT: csel r1, r1, r3, ne
; CHECK-NEXT: csel r0, r0, r2, lo
; CHECK-NEXT: csel r1, r1, r3, lo
; CHECK-NEXT: add sp, #8
; CHECK-NEXT: bx lr
%c = call <1 x i64> @llvm.umin.v1i64(<1 x i64> %a, <1 x i64> %b)
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/Thumb2/mve-pipelineloops.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,8 +13,8 @@ define void @arm_cmplx_dot_prod_q15(ptr noundef %pSrcA, ptr noundef %pSrcB, i32
; CHECK-NEXT: movs r6, #2
; CHECK-NEXT: lsrs r7, r2, #3
; CHECK-NEXT: rsb r6, r6, r2, lsr #3
; CHECK-NEXT: movs r5, #0
; CHECK-NEXT: cmp r7, #2
; CHECK-NEXT: mov.w r5, #0
; CHECK-NEXT: csel r7, r6, r5, hs
; CHECK-NEXT: add.w lr, r7, #1
; CHECK-NEXT: mov r4, r5
Expand Down
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