80 changes: 40 additions & 40 deletions llvm/test/CodeGen/RISCV/float-convert.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -51,7 +51,7 @@ define i32 @fcvt_w_s_sat(float %a) nounwind {
; RV32IF-NEXT: feq.s a0, ft0, ft0
; RV32IF-NEXT: bnez a0, .LBB1_2
; RV32IF-NEXT: # %bb.1: # %start
; RV32IF-NEXT: mv a0, zero
; RV32IF-NEXT: li a0, 0
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB1_2:
; RV32IF-NEXT: fcvt.w.s a0, ft0, rtz
Expand All @@ -63,7 +63,7 @@ define i32 @fcvt_w_s_sat(float %a) nounwind {
; RV64IF-NEXT: feq.s a0, ft0, ft0
; RV64IF-NEXT: bnez a0, .LBB1_2
; RV64IF-NEXT: # %bb.1: # %start
; RV64IF-NEXT: mv a0, zero
; RV64IF-NEXT: li a0, 0
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB1_2:
; RV64IF-NEXT: fcvt.w.s a0, ft0, rtz
Expand All @@ -84,7 +84,7 @@ define i32 @fcvt_w_s_sat(float %a) nounwind {
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixsfsi@plt
; RV32I-NEXT: mv s1, zero
; RV32I-NEXT: li s1, 0
; RV32I-NEXT: lui s4, 524288
; RV32I-NEXT: lui s3, 524288
; RV32I-NEXT: bltz s2, .LBB1_2
Expand Down Expand Up @@ -131,7 +131,7 @@ define i32 @fcvt_w_s_sat(float %a) nounwind {
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixsfdi@plt
; RV64I-NEXT: mv s1, zero
; RV64I-NEXT: li s1, 0
; RV64I-NEXT: lui s4, 524288
; RV64I-NEXT: lui s3, 524288
; RV64I-NEXT: bltz s2, .LBB1_2
Expand Down Expand Up @@ -209,7 +209,7 @@ define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) {
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fcvt.wu.s a1, ft0, rtz
; RV32IF-NEXT: addi a0, zero, 1
; RV32IF-NEXT: li a0, 1
; RV32IF-NEXT: beqz a1, .LBB3_2
; RV32IF-NEXT: # %bb.1:
; RV32IF-NEXT: mv a0, a1
Expand All @@ -220,7 +220,7 @@ define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) {
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fcvt.wu.s a1, ft0, rtz
; RV64IF-NEXT: addi a0, zero, 1
; RV64IF-NEXT: li a0, 1
; RV64IF-NEXT: beqz a1, .LBB3_2
; RV64IF-NEXT: # %bb.1:
; RV64IF-NEXT: mv a0, a1
Expand All @@ -235,7 +235,7 @@ define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) {
; RV32I-NEXT: .cfi_offset ra, -4
; RV32I-NEXT: call __fixunssfsi@plt
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: li a0, 1
; RV32I-NEXT: beqz a1, .LBB3_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, a1
Expand All @@ -252,7 +252,7 @@ define i32 @fcvt_wu_s_multiple_use(float %x, i32* %y) {
; RV64I-NEXT: .cfi_offset ra, -8
; RV64I-NEXT: call __fixunssfsi@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: beqz a1, .LBB3_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: mv a0, a1
Expand All @@ -273,7 +273,7 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind {
; RV32IF-NEXT: feq.s a0, ft0, ft0
; RV32IF-NEXT: bnez a0, .LBB4_2
; RV32IF-NEXT: # %bb.1: # %start
; RV32IF-NEXT: mv a0, zero
; RV32IF-NEXT: li a0, 0
; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB4_2:
; RV32IF-NEXT: fcvt.wu.s a0, ft0, rtz
Expand All @@ -285,7 +285,7 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind {
; RV64IF-NEXT: feq.s a0, ft0, ft0
; RV64IF-NEXT: bnez a0, .LBB4_2
; RV64IF-NEXT: # %bb.1: # %start
; RV64IF-NEXT: mv a0, zero
; RV64IF-NEXT: li a0, 0
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB4_2:
; RV64IF-NEXT: fcvt.wu.s a0, ft0, rtz
Expand All @@ -299,12 +299,12 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind {
; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixunssfsi@plt
; RV32I-NEXT: mv s2, zero
; RV32I-NEXT: li s2, 0
; RV32I-NEXT: bltz s1, .LBB4_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s2, a0
Expand All @@ -314,7 +314,7 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind {
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: addi a0, zero, -1
; RV32I-NEXT: li a0, -1
; RV32I-NEXT: bgtz a1, .LBB4_4
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv a0, s2
Expand All @@ -334,12 +334,12 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind {
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __gesf2@plt
; RV64I-NEXT: mv s2, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixunssfdi@plt
; RV64I-NEXT: mv s1, zero
; RV64I-NEXT: li s1, 0
; RV64I-NEXT: bltz s2, .LBB4_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s1, a0
Expand All @@ -350,7 +350,7 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind {
; RV64I-NEXT: call __gtsf2@plt
; RV64I-NEXT: blez a0, .LBB4_4
; RV64I-NEXT: # %bb.3:
; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: li a0, -1
; RV64I-NEXT: srli s1, a0, 32
; RV64I-NEXT: .LBB4_4: # %start
; RV64I-NEXT: mv a0, s1
Expand Down Expand Up @@ -647,14 +647,14 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV32IF-NEXT: mv a2, a0
; RV32IF-NEXT: bnez s0, .LBB12_2
; RV32IF-NEXT: # %bb.1: # %start
; RV32IF-NEXT: mv a2, zero
; RV32IF-NEXT: li a2, 0
; RV32IF-NEXT: .LBB12_2: # %start
; RV32IF-NEXT: lui a0, %hi(.LCPI12_1)
; RV32IF-NEXT: flw ft0, %lo(.LCPI12_1)(a0)
; RV32IF-NEXT: flw ft1, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flt.s a3, ft0, ft1
; RV32IF-NEXT: fmv.s ft0, ft1
; RV32IF-NEXT: addi a0, zero, -1
; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a3, .LBB12_9
; RV32IF-NEXT: # %bb.3: # %start
; RV32IF-NEXT: feq.s a2, ft0, ft0
Expand All @@ -667,7 +667,7 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV32IF-NEXT: .LBB12_6: # %start
; RV32IF-NEXT: bnez a2, .LBB12_8
; RV32IF-NEXT: .LBB12_7: # %start
; RV32IF-NEXT: mv a1, zero
; RV32IF-NEXT: li a1, 0
; RV32IF-NEXT: .LBB12_8: # %start
; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -678,7 +678,7 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV32IF-NEXT: feq.s a2, ft0, ft0
; RV32IF-NEXT: bnez a2, .LBB12_4
; RV32IF-NEXT: .LBB12_10: # %start
; RV32IF-NEXT: mv a0, zero
; RV32IF-NEXT: li a0, 0
; RV32IF-NEXT: lui a4, 524288
; RV32IF-NEXT: bnez s0, .LBB12_5
; RV32IF-NEXT: .LBB12_11: # %start
Expand All @@ -695,7 +695,7 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV64IF-NEXT: feq.s a0, ft0, ft0
; RV64IF-NEXT: bnez a0, .LBB12_2
; RV64IF-NEXT: # %bb.1: # %start
; RV64IF-NEXT: mv a0, zero
; RV64IF-NEXT: li a0, 0
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB12_2:
; RV64IF-NEXT: fcvt.l.s a0, ft0, rtz
Expand All @@ -719,8 +719,8 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixsfdi@plt
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s1, zero
; RV32I-NEXT: mv s5, zero
; RV32I-NEXT: li s1, 0
; RV32I-NEXT: li s5, 0
; RV32I-NEXT: bltz s3, .LBB12_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s5, a0
Expand All @@ -730,7 +730,7 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s4
; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: addi s6, zero, -1
; RV32I-NEXT: li s6, -1
; RV32I-NEXT: blt s1, a0, .LBB12_4
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s6, s5
Expand Down Expand Up @@ -794,8 +794,8 @@ define i64 @fcvt_l_s_sat(float %a) nounwind {
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixsfdi@plt
; RV64I-NEXT: mv s1, zero
; RV64I-NEXT: addi s4, zero, -1
; RV64I-NEXT: li s1, 0
; RV64I-NEXT: li s4, -1
; RV64I-NEXT: bltz s3, .LBB12_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s2, a0
Expand Down Expand Up @@ -884,14 +884,14 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV32IF-NEXT: mv a3, a0
; RV32IF-NEXT: bnez s0, .LBB14_2
; RV32IF-NEXT: # %bb.1: # %start
; RV32IF-NEXT: mv a3, zero
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: .LBB14_2: # %start
; RV32IF-NEXT: lui a0, %hi(.LCPI14_0)
; RV32IF-NEXT: flw ft0, %lo(.LCPI14_0)(a0)
; RV32IF-NEXT: flw ft1, 4(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flt.s a4, ft0, ft1
; RV32IF-NEXT: addi a2, zero, -1
; RV32IF-NEXT: addi a0, zero, -1
; RV32IF-NEXT: li a2, -1
; RV32IF-NEXT: li a0, -1
; RV32IF-NEXT: beqz a4, .LBB14_7
; RV32IF-NEXT: # %bb.3: # %start
; RV32IF-NEXT: beqz s0, .LBB14_8
Expand All @@ -909,7 +909,7 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV32IF-NEXT: mv a0, a3
; RV32IF-NEXT: bnez s0, .LBB14_4
; RV32IF-NEXT: .LBB14_8: # %start
; RV32IF-NEXT: mv a1, zero
; RV32IF-NEXT: li a1, 0
; RV32IF-NEXT: beqz a4, .LBB14_5
; RV32IF-NEXT: j .LBB14_6
;
Expand All @@ -919,7 +919,7 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV64IF-NEXT: feq.s a0, ft0, ft0
; RV64IF-NEXT: bnez a0, .LBB14_2
; RV64IF-NEXT: # %bb.1: # %start
; RV64IF-NEXT: mv a0, zero
; RV64IF-NEXT: li a0, 0
; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB14_2:
; RV64IF-NEXT: fcvt.lu.s a0, ft0, rtz
Expand All @@ -936,13 +936,13 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call __fixunssfdi@plt
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s5, zero
; RV32I-NEXT: li s5, 0
; RV32I-NEXT: bltz s1, .LBB14_2
; RV32I-NEXT: # %bb.1: # %start
; RV32I-NEXT: mv s5, a0
Expand All @@ -952,16 +952,16 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __gtsf2@plt
; RV32I-NEXT: addi s3, zero, -1
; RV32I-NEXT: addi s4, zero, -1
; RV32I-NEXT: li s3, -1
; RV32I-NEXT: li s4, -1
; RV32I-NEXT: bgtz a0, .LBB14_4
; RV32I-NEXT: # %bb.3: # %start
; RV32I-NEXT: mv s4, s5
; RV32I-NEXT: .LBB14_4: # %start
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: mv s5, zero
; RV32I-NEXT: li s5, 0
; RV32I-NEXT: bltz a0, .LBB14_6
; RV32I-NEXT: # %bb.5: # %start
; RV32I-NEXT: mv s5, s2
Expand Down Expand Up @@ -993,12 +993,12 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __gesf2@plt
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __fixunssfdi@plt
; RV64I-NEXT: mv s2, zero
; RV64I-NEXT: li s2, 0
; RV64I-NEXT: bltz s1, .LBB14_2
; RV64I-NEXT: # %bb.1: # %start
; RV64I-NEXT: mv s2, a0
Expand All @@ -1008,7 +1008,7 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind {
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call __gtsf2@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: li a0, -1
; RV64I-NEXT: bgtz a1, .LBB14_4
; RV64I-NEXT: # %bb.3: # %start
; RV64I-NEXT: mv a0, s2
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/float-fcmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,22 +11,22 @@
define i32 @fcmp_false(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_false:
; RV32IF: # %bb.0:
; RV32IF-NEXT: mv a0, zero
; RV32IF-NEXT: li a0, 0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_false:
; RV64IF: # %bb.0:
; RV64IF-NEXT: mv a0, zero
; RV64IF-NEXT: li a0, 0
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fcmp_false:
; RV32I: # %bb.0:
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: li a0, 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_false:
; RV64I: # %bb.0:
; RV64I-NEXT: mv a0, zero
; RV64I-NEXT: li a0, 0
; RV64I-NEXT: ret
%1 = fcmp false float %a, %b
%2 = zext i1 %1 to i32
Expand Down Expand Up @@ -131,7 +131,7 @@ define i32 @fcmp_oge(float %a, float %b) nounwind {
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __gesf2@plt
; RV32I-NEXT: addi a1, zero, -1
; RV32I-NEXT: li a1, -1
; RV32I-NEXT: slt a0, a1, a0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -142,7 +142,7 @@ define i32 @fcmp_oge(float %a, float %b) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __gesf2@plt
; RV64I-NEXT: addi a1, zero, -1
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -476,7 +476,7 @@ define i32 @fcmp_uge(float %a, float %b) nounwind {
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __ltsf2@plt
; RV32I-NEXT: addi a1, zero, -1
; RV32I-NEXT: li a1, -1
; RV32I-NEXT: slt a0, a1, a0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -487,7 +487,7 @@ define i32 @fcmp_uge(float %a, float %b) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __ltsf2@plt
; RV64I-NEXT: addi a1, zero, -1
; RV64I-NEXT: li a1, -1
; RV64I-NEXT: slt a0, a1, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -668,22 +668,22 @@ define i32 @fcmp_uno(float %a, float %b) nounwind {
define i32 @fcmp_true(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_true:
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi a0, zero, 1
; RV32IF-NEXT: li a0, 1
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_true:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi a0, zero, 1
; RV64IF-NEXT: li a0, 1
; RV64IF-NEXT: ret
;
; RV32I-LABEL: fcmp_true:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: li a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_true:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: ret
%1 = fcmp true float %a, %b
%2 = zext i1 %1 to i32
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/flt-rounds.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -9,12 +9,12 @@ declare i32 @llvm.flt.rounds()
define i32 @test_flt_rounds() nounwind {
; RV32I-LABEL: test_flt_rounds:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: li a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: test_flt_rounds:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: ret
%1 = call i32 @llvm.flt.rounds()
ret i32 %1
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/fp-imm.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -61,8 +61,8 @@ define float @f32_negative_zero(float *%pf) nounwind {
define double @f64_positive_zero(double *%pd) nounwind {
; RV32F-LABEL: f64_positive_zero:
; RV32F: # %bb.0:
; RV32F-NEXT: mv a0, zero
; RV32F-NEXT: mv a1, zero
; RV32F-NEXT: li a0, 0
; RV32F-NEXT: li a1, 0
; RV32F-NEXT: ret
;
; RV32D-LABEL: f64_positive_zero:
Expand All @@ -72,7 +72,7 @@ define double @f64_positive_zero(double *%pd) nounwind {
;
; RV64F-LABEL: f64_positive_zero:
; RV64F: # %bb.0:
; RV64F-NEXT: mv a0, zero
; RV64F-NEXT: li a0, 0
; RV64F-NEXT: ret
;
; RV64D-LABEL: f64_positive_zero:
Expand All @@ -86,7 +86,7 @@ define double @f64_negative_zero(double *%pd) nounwind {
; RV32F-LABEL: f64_negative_zero:
; RV32F: # %bb.0:
; RV32F-NEXT: lui a1, 524288
; RV32F-NEXT: mv a0, zero
; RV32F-NEXT: li a0, 0
; RV32F-NEXT: ret
;
; RV32D-LABEL: f64_negative_zero:
Expand All @@ -97,7 +97,7 @@ define double @f64_negative_zero(double *%pd) nounwind {
;
; RV64F-LABEL: f64_negative_zero:
; RV64F: # %bb.0:
; RV64F-NEXT: addi a0, zero, -1
; RV64F-NEXT: li a0, -1
; RV64F-NEXT: slli a0, a0, 63
; RV64F-NEXT: ret
;
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/frame.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@ define i32 @test() nounwind {
; RV32I-FPELIM-NEXT: sw zero, 8(sp)
; RV32I-FPELIM-NEXT: addi a0, sp, 12
; RV32I-FPELIM-NEXT: call test1@plt
; RV32I-FPELIM-NEXT: mv a0, zero
; RV32I-FPELIM-NEXT: li a0, 0
; RV32I-FPELIM-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 32
; RV32I-FPELIM-NEXT: ret
Expand All @@ -36,7 +36,7 @@ define i32 @test() nounwind {
; RV32I-WITHFP-NEXT: sw zero, -32(s0)
; RV32I-WITHFP-NEXT: addi a0, s0, -28
; RV32I-WITHFP-NEXT: call test1@plt
; RV32I-WITHFP-NEXT: mv a0, zero
; RV32I-WITHFP-NEXT: li a0, 0
; RV32I-WITHFP-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 32
Expand Down
52 changes: 26 additions & 26 deletions llvm/test/CodeGen/RISCV/half-arith.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1090,7 +1090,7 @@ define half @fmsub_s(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and a0, a2, s0
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: and a0, a0, s0
Expand Down Expand Up @@ -1136,7 +1136,7 @@ define half @fmsub_s(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and a0, a2, s0
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: and a0, a0, s0
Expand Down Expand Up @@ -1204,13 +1204,13 @@ define half @fnmadd_s(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi s1, a1, -1
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: and a0, s3, s1
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s0, a0
Expand Down Expand Up @@ -1262,13 +1262,13 @@ define half @fnmadd_s(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addiw s1, a1, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: and a0, s3, s1
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s0, a0
Expand Down Expand Up @@ -1344,13 +1344,13 @@ define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi s1, a0, -1
; RV32I-NEXT: and a0, a1, s1
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: and a0, s3, s1
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s0, a0
Expand Down Expand Up @@ -1402,13 +1402,13 @@ define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addiw s1, a0, -1
; RV64I-NEXT: and a0, a1, s1
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: and a0, s3, s1
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s0, a0
Expand Down Expand Up @@ -1482,7 +1482,7 @@ define half @fnmsub_s(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi s0, a1, -1
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: and a0, a0, s0
Expand Down Expand Up @@ -1527,7 +1527,7 @@ define half @fnmsub_s(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addiw s0, a1, -1
; RV64I-NEXT: and a0, a0, s0
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: and a0, a0, s0
Expand Down Expand Up @@ -1592,7 +1592,7 @@ define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and a0, a1, s0
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: and a0, a0, s0
Expand Down Expand Up @@ -1638,7 +1638,7 @@ define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and a0, a1, s0
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: and a0, a0, s0
Expand Down Expand Up @@ -1794,7 +1794,7 @@ define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi s0, a0, -1
; RV32I-NEXT: and a0, a2, s0
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s2, a0
Expand Down Expand Up @@ -1838,7 +1838,7 @@ define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addiw s0, a0, -1
; RV64I-NEXT: and a0, a2, s0
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s2, a0
Expand Down Expand Up @@ -1907,19 +1907,19 @@ define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi s1, a1, -1
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: and a0, s0, s1
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s4, a0
; RV32I-NEXT: and a0, s2, s1
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s2, a0
Expand Down Expand Up @@ -1970,19 +1970,19 @@ define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addiw s1, a1, -1
; RV64I-NEXT: and a0, a0, s1
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: and a0, s0, s1
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s4, a0
; RV64I-NEXT: and a0, s2, s1
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s2, a0
Expand Down Expand Up @@ -2057,13 +2057,13 @@ define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
; RV32I-NEXT: addi s0, a1, -1
; RV32I-NEXT: and a0, a0, s0
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: and a0, s1, s0
; RV32I-NEXT: call __gnu_h2f_ieee@plt
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __addsf3@plt
; RV32I-NEXT: call __gnu_f2h_ieee@plt
; RV32I-NEXT: mv s1, a0
Expand Down Expand Up @@ -2108,13 +2108,13 @@ define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
; RV64I-NEXT: addiw s0, a1, -1
; RV64I-NEXT: and a0, a0, s0
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s3, a0
; RV64I-NEXT: and a0, s1, s0
; RV64I-NEXT: call __gnu_h2f_ieee@plt
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __addsf3@plt
; RV64I-NEXT: call __gnu_f2h_ieee@plt
; RV64I-NEXT: mv s1, a0
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/half-br-fcmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ declare half @dummy(half)
define void @br_fcmp_false(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_false:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi a0, zero, 1
; RV32IZFH-NEXT: li a0, 1
; RV32IZFH-NEXT: bnez a0, .LBB0_2
; RV32IZFH-NEXT: # %bb.1: # %if.then
; RV32IZFH-NEXT: ret
Expand All @@ -22,7 +22,7 @@ define void @br_fcmp_false(half %a, half %b) nounwind {
;
; RV64IZFH-LABEL: br_fcmp_false:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi a0, zero, 1
; RV64IZFH-NEXT: li a0, 1
; RV64IZFH-NEXT: bnez a0, .LBB0_2
; RV64IZFH-NEXT: # %bb.1: # %if.then
; RV64IZFH-NEXT: ret
Expand Down Expand Up @@ -527,7 +527,7 @@ if.then:
define void @br_fcmp_true(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_true:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi a0, zero, 1
; RV32IZFH-NEXT: li a0, 1
; RV32IZFH-NEXT: bnez a0, .LBB16_2
; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: ret
Expand All @@ -538,7 +538,7 @@ define void @br_fcmp_true(half %a, half %b) nounwind {
;
; RV64IZFH-LABEL: br_fcmp_true:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi a0, zero, 1
; RV64IZFH-NEXT: li a0, 1
; RV64IZFH-NEXT: bnez a0, .LBB16_2
; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ret
Expand Down
132 changes: 66 additions & 66 deletions llvm/test/CodeGen/RISCV/half-convert.ll
View file

Large diffs are not rendered by default.

16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/half-fcmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,22 +11,22 @@
define i32 @fcmp_false(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_false:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: mv a0, zero
; RV32IZFH-NEXT: li a0, 0
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_false:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: mv a0, zero
; RV64IZFH-NEXT: li a0, 0
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_false:
; RV32I: # %bb.0:
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: li a0, 0
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_false:
; RV64I: # %bb.0:
; RV64I-NEXT: mv a0, zero
; RV64I-NEXT: li a0, 0
; RV64I-NEXT: ret
%1 = fcmp false half %a, %b
%2 = zext i1 %1 to i32
Expand Down Expand Up @@ -502,22 +502,22 @@ define i32 @fcmp_uno(half %a, half %b) nounwind {
define i32 @fcmp_true(half %a, half %b) nounwind {
; RV32IZFH-LABEL: fcmp_true:
; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi a0, zero, 1
; RV32IZFH-NEXT: li a0, 1
; RV32IZFH-NEXT: ret
;
; RV64IZFH-LABEL: fcmp_true:
; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi a0, zero, 1
; RV64IZFH-NEXT: li a0, 1
; RV64IZFH-NEXT: ret
;
; RV32I-LABEL: fcmp_true:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: li a0, 1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fcmp_true:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: ret
%1 = fcmp true half %a, %b
%2 = zext i1 %1 to i32
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/hoist-global-addr-base.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -13,9 +13,9 @@ define dso_local void @multiple_stores() local_unnamed_addr nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s)
; CHECK-NEXT: addi a0, a0, %lo(s)
; CHECK-NEXT: addi a1, zero, 10
; CHECK-NEXT: li a1, 10
; CHECK-NEXT: sw a1, 160(a0)
; CHECK-NEXT: addi a1, zero, 20
; CHECK-NEXT: li a1, 20
; CHECK-NEXT: sw a1, 164(a0)
; CHECK-NEXT: ret
entry:
Expand All @@ -32,7 +32,7 @@ define dso_local void @control_flow_with_mem_access() local_unnamed_addr nounwin
; CHECK-NEXT: lw a1, 164(a0)
; CHECK-NEXT: blez a1, .LBB1_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: addi a1, zero, 10
; CHECK-NEXT: li a1, 10
; CHECK-NEXT: sw a1, 160(a0)
; CHECK-NEXT: .LBB1_2: # %if.end
; CHECK-NEXT: ret
Expand Down Expand Up @@ -149,10 +149,10 @@ define dso_local i32 @load_half() nounwind {
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: lui a0, %hi(foo+8)
; RV32-NEXT: lhu a0, %lo(foo+8)(a0)
; RV32-NEXT: addi a1, zero, 140
; RV32-NEXT: li a1, 140
; RV32-NEXT: bne a0, a1, .LBB7_2
; RV32-NEXT: # %bb.1: # %if.end
; RV32-NEXT: mv a0, zero
; RV32-NEXT: li a0, 0
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
Expand All @@ -165,10 +165,10 @@ define dso_local i32 @load_half() nounwind {
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: lui a0, %hi(foo+8)
; RV64-NEXT: lhu a0, %lo(foo+8)(a0)
; RV64-NEXT: addi a1, zero, 140
; RV64-NEXT: li a1, 140
; RV64-NEXT: bne a0, a1, .LBB7_2
; RV64-NEXT: # %bb.1: # %if.end
; RV64-NEXT: mv a0, zero
; RV64-NEXT: li a0, 0
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret
Expand All @@ -193,7 +193,7 @@ define dso_local void @one_store() local_unnamed_addr nounwind {
; CHECK-LABEL: one_store:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: lui a0, %hi(s+160)
; CHECK-NEXT: addi a1, zero, 10
; CHECK-NEXT: li a1, 10
; CHECK-NEXT: sw a1, %lo(s+160)(a0)
; CHECK-NEXT: ret
entry:
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/i32-icmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ define i32 @icmp_eq_constant_2048(i32 %a) nounwind {
define i32 @icmp_eq_constant_neg_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_eq_constant_neg_2048:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, -2048
; RV32I-NEXT: li a1, -2048
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: ret
Expand Down Expand Up @@ -107,7 +107,7 @@ define i32 @icmp_ne_constant_2048(i32 %a) nounwind {
define i32 @icmp_ne_constant_neg_2048(i32 %a) nounwind {
; RV32I-LABEL: icmp_ne_constant_neg_2048:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, -2048
; RV32I-NEXT: li a1, -2048
; RV32I-NEXT: xor a0, a0, a1
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: ret
Expand Down
180 changes: 90 additions & 90 deletions llvm/test/CodeGen/RISCV/imm.ll
View file

Large diffs are not rendered by default.

4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/indirectbr.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ define i32 @indirectbr(i8* %target) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: jr a0
; RV32I-NEXT: .LBB0_1: # %test_label
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: li a0, 0
; RV32I-NEXT: ret
indirectbr i8* %target, [label %test_label]
test_label:
Expand All @@ -21,7 +21,7 @@ define i32 @indirectbr_with_offset(i8* %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: jr 1380(a0)
; RV32I-NEXT: .LBB1_1: # %test_label
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: li a0, 0
; RV32I-NEXT: ret
%target = getelementptr inbounds i8, i8* %a, i32 1380
indirectbr i8* %target, [label %test_label]
Expand Down
128 changes: 64 additions & 64 deletions llvm/test/CodeGen/RISCV/jumptable.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,63 +11,63 @@
define void @below_threshold(i32 %in, i32* %out) nounwind {
; RV32I-SMALL-LABEL: below_threshold:
; RV32I-SMALL: # %bb.0: # %entry
; RV32I-SMALL-NEXT: addi a2, zero, 2
; RV32I-SMALL-NEXT: li a2, 2
; RV32I-SMALL-NEXT: blt a2, a0, .LBB0_4
; RV32I-SMALL-NEXT: # %bb.1: # %entry
; RV32I-SMALL-NEXT: addi a2, zero, 1
; RV32I-SMALL-NEXT: li a2, 1
; RV32I-SMALL-NEXT: beq a0, a2, .LBB0_7
; RV32I-SMALL-NEXT: # %bb.2: # %entry
; RV32I-SMALL-NEXT: addi a2, zero, 2
; RV32I-SMALL-NEXT: li a2, 2
; RV32I-SMALL-NEXT: bne a0, a2, .LBB0_10
; RV32I-SMALL-NEXT: # %bb.3: # %bb2
; RV32I-SMALL-NEXT: addi a0, zero, 3
; RV32I-SMALL-NEXT: li a0, 3
; RV32I-SMALL-NEXT: j .LBB0_9
; RV32I-SMALL-NEXT: .LBB0_4: # %entry
; RV32I-SMALL-NEXT: addi a2, zero, 3
; RV32I-SMALL-NEXT: li a2, 3
; RV32I-SMALL-NEXT: beq a0, a2, .LBB0_8
; RV32I-SMALL-NEXT: # %bb.5: # %entry
; RV32I-SMALL-NEXT: addi a2, zero, 4
; RV32I-SMALL-NEXT: li a2, 4
; RV32I-SMALL-NEXT: bne a0, a2, .LBB0_10
; RV32I-SMALL-NEXT: # %bb.6: # %bb4
; RV32I-SMALL-NEXT: addi a0, zero, 1
; RV32I-SMALL-NEXT: li a0, 1
; RV32I-SMALL-NEXT: j .LBB0_9
; RV32I-SMALL-NEXT: .LBB0_7: # %bb1
; RV32I-SMALL-NEXT: addi a0, zero, 4
; RV32I-SMALL-NEXT: li a0, 4
; RV32I-SMALL-NEXT: j .LBB0_9
; RV32I-SMALL-NEXT: .LBB0_8: # %bb3
; RV32I-SMALL-NEXT: addi a0, zero, 2
; RV32I-SMALL-NEXT: li a0, 2
; RV32I-SMALL-NEXT: .LBB0_9: # %exit
; RV32I-SMALL-NEXT: sw a0, 0(a1)
; RV32I-SMALL-NEXT: .LBB0_10: # %exit
; RV32I-SMALL-NEXT: ret
;
; RV32I-MEDIUM-LABEL: below_threshold:
; RV32I-MEDIUM: # %bb.0: # %entry
; RV32I-MEDIUM-NEXT: addi a2, zero, 2
; RV32I-MEDIUM-NEXT: li a2, 2
; RV32I-MEDIUM-NEXT: blt a2, a0, .LBB0_4
; RV32I-MEDIUM-NEXT: # %bb.1: # %entry
; RV32I-MEDIUM-NEXT: addi a2, zero, 1
; RV32I-MEDIUM-NEXT: li a2, 1
; RV32I-MEDIUM-NEXT: beq a0, a2, .LBB0_7
; RV32I-MEDIUM-NEXT: # %bb.2: # %entry
; RV32I-MEDIUM-NEXT: addi a2, zero, 2
; RV32I-MEDIUM-NEXT: li a2, 2
; RV32I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
; RV32I-MEDIUM-NEXT: # %bb.3: # %bb2
; RV32I-MEDIUM-NEXT: addi a0, zero, 3
; RV32I-MEDIUM-NEXT: li a0, 3
; RV32I-MEDIUM-NEXT: j .LBB0_9
; RV32I-MEDIUM-NEXT: .LBB0_4: # %entry
; RV32I-MEDIUM-NEXT: addi a2, zero, 3
; RV32I-MEDIUM-NEXT: li a2, 3
; RV32I-MEDIUM-NEXT: beq a0, a2, .LBB0_8
; RV32I-MEDIUM-NEXT: # %bb.5: # %entry
; RV32I-MEDIUM-NEXT: addi a2, zero, 4
; RV32I-MEDIUM-NEXT: li a2, 4
; RV32I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
; RV32I-MEDIUM-NEXT: # %bb.6: # %bb4
; RV32I-MEDIUM-NEXT: addi a0, zero, 1
; RV32I-MEDIUM-NEXT: li a0, 1
; RV32I-MEDIUM-NEXT: j .LBB0_9
; RV32I-MEDIUM-NEXT: .LBB0_7: # %bb1
; RV32I-MEDIUM-NEXT: addi a0, zero, 4
; RV32I-MEDIUM-NEXT: li a0, 4
; RV32I-MEDIUM-NEXT: j .LBB0_9
; RV32I-MEDIUM-NEXT: .LBB0_8: # %bb3
; RV32I-MEDIUM-NEXT: addi a0, zero, 2
; RV32I-MEDIUM-NEXT: li a0, 2
; RV32I-MEDIUM-NEXT: .LBB0_9: # %exit
; RV32I-MEDIUM-NEXT: sw a0, 0(a1)
; RV32I-MEDIUM-NEXT: .LBB0_10: # %exit
Expand All @@ -76,31 +76,31 @@ define void @below_threshold(i32 %in, i32* %out) nounwind {
; RV64I-SMALL-LABEL: below_threshold:
; RV64I-SMALL: # %bb.0: # %entry
; RV64I-SMALL-NEXT: sext.w a0, a0
; RV64I-SMALL-NEXT: addi a2, zero, 2
; RV64I-SMALL-NEXT: li a2, 2
; RV64I-SMALL-NEXT: blt a2, a0, .LBB0_4
; RV64I-SMALL-NEXT: # %bb.1: # %entry
; RV64I-SMALL-NEXT: addi a2, zero, 1
; RV64I-SMALL-NEXT: li a2, 1
; RV64I-SMALL-NEXT: beq a0, a2, .LBB0_7
; RV64I-SMALL-NEXT: # %bb.2: # %entry
; RV64I-SMALL-NEXT: addi a2, zero, 2
; RV64I-SMALL-NEXT: li a2, 2
; RV64I-SMALL-NEXT: bne a0, a2, .LBB0_10
; RV64I-SMALL-NEXT: # %bb.3: # %bb2
; RV64I-SMALL-NEXT: addi a0, zero, 3
; RV64I-SMALL-NEXT: li a0, 3
; RV64I-SMALL-NEXT: j .LBB0_9
; RV64I-SMALL-NEXT: .LBB0_4: # %entry
; RV64I-SMALL-NEXT: addi a2, zero, 3
; RV64I-SMALL-NEXT: li a2, 3
; RV64I-SMALL-NEXT: beq a0, a2, .LBB0_8
; RV64I-SMALL-NEXT: # %bb.5: # %entry
; RV64I-SMALL-NEXT: addi a2, zero, 4
; RV64I-SMALL-NEXT: li a2, 4
; RV64I-SMALL-NEXT: bne a0, a2, .LBB0_10
; RV64I-SMALL-NEXT: # %bb.6: # %bb4
; RV64I-SMALL-NEXT: addi a0, zero, 1
; RV64I-SMALL-NEXT: li a0, 1
; RV64I-SMALL-NEXT: j .LBB0_9
; RV64I-SMALL-NEXT: .LBB0_7: # %bb1
; RV64I-SMALL-NEXT: addi a0, zero, 4
; RV64I-SMALL-NEXT: li a0, 4
; RV64I-SMALL-NEXT: j .LBB0_9
; RV64I-SMALL-NEXT: .LBB0_8: # %bb3
; RV64I-SMALL-NEXT: addi a0, zero, 2
; RV64I-SMALL-NEXT: li a0, 2
; RV64I-SMALL-NEXT: .LBB0_9: # %exit
; RV64I-SMALL-NEXT: sw a0, 0(a1)
; RV64I-SMALL-NEXT: .LBB0_10: # %exit
Expand All @@ -109,31 +109,31 @@ define void @below_threshold(i32 %in, i32* %out) nounwind {
; RV64I-MEDIUM-LABEL: below_threshold:
; RV64I-MEDIUM: # %bb.0: # %entry
; RV64I-MEDIUM-NEXT: sext.w a0, a0
; RV64I-MEDIUM-NEXT: addi a2, zero, 2
; RV64I-MEDIUM-NEXT: li a2, 2
; RV64I-MEDIUM-NEXT: blt a2, a0, .LBB0_4
; RV64I-MEDIUM-NEXT: # %bb.1: # %entry
; RV64I-MEDIUM-NEXT: addi a2, zero, 1
; RV64I-MEDIUM-NEXT: li a2, 1
; RV64I-MEDIUM-NEXT: beq a0, a2, .LBB0_7
; RV64I-MEDIUM-NEXT: # %bb.2: # %entry
; RV64I-MEDIUM-NEXT: addi a2, zero, 2
; RV64I-MEDIUM-NEXT: li a2, 2
; RV64I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
; RV64I-MEDIUM-NEXT: # %bb.3: # %bb2
; RV64I-MEDIUM-NEXT: addi a0, zero, 3
; RV64I-MEDIUM-NEXT: li a0, 3
; RV64I-MEDIUM-NEXT: j .LBB0_9
; RV64I-MEDIUM-NEXT: .LBB0_4: # %entry
; RV64I-MEDIUM-NEXT: addi a2, zero, 3
; RV64I-MEDIUM-NEXT: li a2, 3
; RV64I-MEDIUM-NEXT: beq a0, a2, .LBB0_8
; RV64I-MEDIUM-NEXT: # %bb.5: # %entry
; RV64I-MEDIUM-NEXT: addi a2, zero, 4
; RV64I-MEDIUM-NEXT: li a2, 4
; RV64I-MEDIUM-NEXT: bne a0, a2, .LBB0_10
; RV64I-MEDIUM-NEXT: # %bb.6: # %bb4
; RV64I-MEDIUM-NEXT: addi a0, zero, 1
; RV64I-MEDIUM-NEXT: li a0, 1
; RV64I-MEDIUM-NEXT: j .LBB0_9
; RV64I-MEDIUM-NEXT: .LBB0_7: # %bb1
; RV64I-MEDIUM-NEXT: addi a0, zero, 4
; RV64I-MEDIUM-NEXT: li a0, 4
; RV64I-MEDIUM-NEXT: j .LBB0_9
; RV64I-MEDIUM-NEXT: .LBB0_8: # %bb3
; RV64I-MEDIUM-NEXT: addi a0, zero, 2
; RV64I-MEDIUM-NEXT: li a0, 2
; RV64I-MEDIUM-NEXT: .LBB0_9: # %exit
; RV64I-MEDIUM-NEXT: sw a0, 0(a1)
; RV64I-MEDIUM-NEXT: .LBB0_10: # %exit
Expand Down Expand Up @@ -165,7 +165,7 @@ define void @above_threshold(i32 %in, i32* %out) nounwind {
; RV32I-SMALL-LABEL: above_threshold:
; RV32I-SMALL: # %bb.0: # %entry
; RV32I-SMALL-NEXT: addi a0, a0, -1
; RV32I-SMALL-NEXT: addi a2, zero, 5
; RV32I-SMALL-NEXT: li a2, 5
; RV32I-SMALL-NEXT: bltu a2, a0, .LBB1_9
; RV32I-SMALL-NEXT: # %bb.1: # %entry
; RV32I-SMALL-NEXT: slli a0, a0, 2
Expand All @@ -175,22 +175,22 @@ define void @above_threshold(i32 %in, i32* %out) nounwind {
; RV32I-SMALL-NEXT: lw a0, 0(a0)
; RV32I-SMALL-NEXT: jr a0
; RV32I-SMALL-NEXT: .LBB1_2: # %bb1
; RV32I-SMALL-NEXT: addi a0, zero, 4
; RV32I-SMALL-NEXT: li a0, 4
; RV32I-SMALL-NEXT: j .LBB1_8
; RV32I-SMALL-NEXT: .LBB1_3: # %bb2
; RV32I-SMALL-NEXT: addi a0, zero, 3
; RV32I-SMALL-NEXT: li a0, 3
; RV32I-SMALL-NEXT: j .LBB1_8
; RV32I-SMALL-NEXT: .LBB1_4: # %bb3
; RV32I-SMALL-NEXT: addi a0, zero, 2
; RV32I-SMALL-NEXT: li a0, 2
; RV32I-SMALL-NEXT: j .LBB1_8
; RV32I-SMALL-NEXT: .LBB1_5: # %bb4
; RV32I-SMALL-NEXT: addi a0, zero, 1
; RV32I-SMALL-NEXT: li a0, 1
; RV32I-SMALL-NEXT: j .LBB1_8
; RV32I-SMALL-NEXT: .LBB1_6: # %bb5
; RV32I-SMALL-NEXT: addi a0, zero, 100
; RV32I-SMALL-NEXT: li a0, 100
; RV32I-SMALL-NEXT: j .LBB1_8
; RV32I-SMALL-NEXT: .LBB1_7: # %bb6
; RV32I-SMALL-NEXT: addi a0, zero, 200
; RV32I-SMALL-NEXT: li a0, 200
; RV32I-SMALL-NEXT: .LBB1_8: # %exit
; RV32I-SMALL-NEXT: sw a0, 0(a1)
; RV32I-SMALL-NEXT: .LBB1_9: # %exit
Expand All @@ -199,7 +199,7 @@ define void @above_threshold(i32 %in, i32* %out) nounwind {
; RV32I-MEDIUM-LABEL: above_threshold:
; RV32I-MEDIUM: # %bb.0: # %entry
; RV32I-MEDIUM-NEXT: addi a0, a0, -1
; RV32I-MEDIUM-NEXT: addi a2, zero, 5
; RV32I-MEDIUM-NEXT: li a2, 5
; RV32I-MEDIUM-NEXT: bltu a2, a0, .LBB1_9
; RV32I-MEDIUM-NEXT: # %bb.1: # %entry
; RV32I-MEDIUM-NEXT: slli a0, a0, 2
Expand All @@ -211,22 +211,22 @@ define void @above_threshold(i32 %in, i32* %out) nounwind {
; RV32I-MEDIUM-NEXT: lw a0, 0(a0)
; RV32I-MEDIUM-NEXT: jr a0
; RV32I-MEDIUM-NEXT: .LBB1_2: # %bb1
; RV32I-MEDIUM-NEXT: addi a0, zero, 4
; RV32I-MEDIUM-NEXT: li a0, 4
; RV32I-MEDIUM-NEXT: j .LBB1_8
; RV32I-MEDIUM-NEXT: .LBB1_3: # %bb2
; RV32I-MEDIUM-NEXT: addi a0, zero, 3
; RV32I-MEDIUM-NEXT: li a0, 3
; RV32I-MEDIUM-NEXT: j .LBB1_8
; RV32I-MEDIUM-NEXT: .LBB1_4: # %bb3
; RV32I-MEDIUM-NEXT: addi a0, zero, 2
; RV32I-MEDIUM-NEXT: li a0, 2
; RV32I-MEDIUM-NEXT: j .LBB1_8
; RV32I-MEDIUM-NEXT: .LBB1_5: # %bb4
; RV32I-MEDIUM-NEXT: addi a0, zero, 1
; RV32I-MEDIUM-NEXT: li a0, 1
; RV32I-MEDIUM-NEXT: j .LBB1_8
; RV32I-MEDIUM-NEXT: .LBB1_6: # %bb5
; RV32I-MEDIUM-NEXT: addi a0, zero, 100
; RV32I-MEDIUM-NEXT: li a0, 100
; RV32I-MEDIUM-NEXT: j .LBB1_8
; RV32I-MEDIUM-NEXT: .LBB1_7: # %bb6
; RV32I-MEDIUM-NEXT: addi a0, zero, 200
; RV32I-MEDIUM-NEXT: li a0, 200
; RV32I-MEDIUM-NEXT: .LBB1_8: # %exit
; RV32I-MEDIUM-NEXT: sw a0, 0(a1)
; RV32I-MEDIUM-NEXT: .LBB1_9: # %exit
Expand All @@ -236,7 +236,7 @@ define void @above_threshold(i32 %in, i32* %out) nounwind {
; RV64I-SMALL: # %bb.0: # %entry
; RV64I-SMALL-NEXT: sext.w a0, a0
; RV64I-SMALL-NEXT: addi a0, a0, -1
; RV64I-SMALL-NEXT: addi a2, zero, 5
; RV64I-SMALL-NEXT: li a2, 5
; RV64I-SMALL-NEXT: bltu a2, a0, .LBB1_9
; RV64I-SMALL-NEXT: # %bb.1: # %entry
; RV64I-SMALL-NEXT: slli a0, a0, 3
Expand All @@ -246,22 +246,22 @@ define void @above_threshold(i32 %in, i32* %out) nounwind {
; RV64I-SMALL-NEXT: ld a0, 0(a0)
; RV64I-SMALL-NEXT: jr a0
; RV64I-SMALL-NEXT: .LBB1_2: # %bb1
; RV64I-SMALL-NEXT: addi a0, zero, 4
; RV64I-SMALL-NEXT: li a0, 4
; RV64I-SMALL-NEXT: j .LBB1_8
; RV64I-SMALL-NEXT: .LBB1_3: # %bb2
; RV64I-SMALL-NEXT: addi a0, zero, 3
; RV64I-SMALL-NEXT: li a0, 3
; RV64I-SMALL-NEXT: j .LBB1_8
; RV64I-SMALL-NEXT: .LBB1_4: # %bb3
; RV64I-SMALL-NEXT: addi a0, zero, 2
; RV64I-SMALL-NEXT: li a0, 2
; RV64I-SMALL-NEXT: j .LBB1_8
; RV64I-SMALL-NEXT: .LBB1_5: # %bb4
; RV64I-SMALL-NEXT: addi a0, zero, 1
; RV64I-SMALL-NEXT: li a0, 1
; RV64I-SMALL-NEXT: j .LBB1_8
; RV64I-SMALL-NEXT: .LBB1_6: # %bb5
; RV64I-SMALL-NEXT: addi a0, zero, 100
; RV64I-SMALL-NEXT: li a0, 100
; RV64I-SMALL-NEXT: j .LBB1_8
; RV64I-SMALL-NEXT: .LBB1_7: # %bb6
; RV64I-SMALL-NEXT: addi a0, zero, 200
; RV64I-SMALL-NEXT: li a0, 200
; RV64I-SMALL-NEXT: .LBB1_8: # %exit
; RV64I-SMALL-NEXT: sw a0, 0(a1)
; RV64I-SMALL-NEXT: .LBB1_9: # %exit
Expand All @@ -271,7 +271,7 @@ define void @above_threshold(i32 %in, i32* %out) nounwind {
; RV64I-MEDIUM: # %bb.0: # %entry
; RV64I-MEDIUM-NEXT: sext.w a0, a0
; RV64I-MEDIUM-NEXT: addi a0, a0, -1
; RV64I-MEDIUM-NEXT: addi a2, zero, 5
; RV64I-MEDIUM-NEXT: li a2, 5
; RV64I-MEDIUM-NEXT: bltu a2, a0, .LBB1_9
; RV64I-MEDIUM-NEXT: # %bb.1: # %entry
; RV64I-MEDIUM-NEXT: slli a0, a0, 3
Expand All @@ -283,22 +283,22 @@ define void @above_threshold(i32 %in, i32* %out) nounwind {
; RV64I-MEDIUM-NEXT: ld a0, 0(a0)
; RV64I-MEDIUM-NEXT: jr a0
; RV64I-MEDIUM-NEXT: .LBB1_2: # %bb1
; RV64I-MEDIUM-NEXT: addi a0, zero, 4
; RV64I-MEDIUM-NEXT: li a0, 4
; RV64I-MEDIUM-NEXT: j .LBB1_8
; RV64I-MEDIUM-NEXT: .LBB1_3: # %bb2
; RV64I-MEDIUM-NEXT: addi a0, zero, 3
; RV64I-MEDIUM-NEXT: li a0, 3
; RV64I-MEDIUM-NEXT: j .LBB1_8
; RV64I-MEDIUM-NEXT: .LBB1_4: # %bb3
; RV64I-MEDIUM-NEXT: addi a0, zero, 2
; RV64I-MEDIUM-NEXT: li a0, 2
; RV64I-MEDIUM-NEXT: j .LBB1_8
; RV64I-MEDIUM-NEXT: .LBB1_5: # %bb4
; RV64I-MEDIUM-NEXT: addi a0, zero, 1
; RV64I-MEDIUM-NEXT: li a0, 1
; RV64I-MEDIUM-NEXT: j .LBB1_8
; RV64I-MEDIUM-NEXT: .LBB1_6: # %bb5
; RV64I-MEDIUM-NEXT: addi a0, zero, 100
; RV64I-MEDIUM-NEXT: li a0, 100
; RV64I-MEDIUM-NEXT: j .LBB1_8
; RV64I-MEDIUM-NEXT: .LBB1_7: # %bb6
; RV64I-MEDIUM-NEXT: addi a0, zero, 200
; RV64I-MEDIUM-NEXT: li a0, 200
; RV64I-MEDIUM-NEXT: .LBB1_8: # %exit
; RV64I-MEDIUM-NEXT: sw a0, 0(a1)
; RV64I-MEDIUM-NEXT: .LBB1_9: # %exit
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/legalize-fneg.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ define void @test1(float* %a, float* %b) nounwind {
; RV64-LABEL: test1:
; RV64: # %bb.0: # %entry
; RV64-NEXT: lw a1, 0(a1)
; RV64-NEXT: addi a2, zero, 1
; RV64-NEXT: li a2, 1
; RV64-NEXT: slli a2, a2, 31
; RV64-NEXT: xor a1, a1, a2
; RV64-NEXT: sw a1, 0(a0)
Expand All @@ -42,7 +42,7 @@ define void @test2(double* %a, double* %b) nounwind {
; RV64-LABEL: test2:
; RV64: # %bb.0: # %entry
; RV64-NEXT: ld a1, 0(a1)
; RV64-NEXT: addi a2, zero, -1
; RV64-NEXT: li a2, -1
; RV64-NEXT: slli a2, a2, 63
; RV64-NEXT: xor a1, a1, a2
; RV64-NEXT: sd a1, 0(a0)
Expand Down Expand Up @@ -73,7 +73,7 @@ define void @test3(fp128* %a, fp128* %b) nounwind {
; RV64: # %bb.0: # %entry
; RV64-NEXT: ld a2, 8(a1)
; RV64-NEXT: ld a1, 0(a1)
; RV64-NEXT: addi a3, zero, -1
; RV64-NEXT: li a3, -1
; RV64-NEXT: slli a3, a3, 63
; RV64-NEXT: xor a2, a2, a3
; RV64-NEXT: sd a1, 0(a0)
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/lsr-legaladdimm.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@
define i32 @main() nounwind {
; RV32I-LABEL: main:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: li a0, 0
; RV32I-NEXT: lui a1, %hi(b)
; RV32I-NEXT: addi a1, a1, %lo(b)
; RV32I-NEXT: lui a2, %hi(a)
Expand All @@ -27,7 +27,7 @@ define i32 @main() nounwind {
; RV32I-NEXT: addi a2, a2, 4
; RV32I-NEXT: bne a0, a3, .LBB0_1
; RV32I-NEXT: # %bb.2: # %for.end
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: li a0, 0
; RV32I-NEXT: ret
entry:
br label %for.body
Expand Down
62 changes: 31 additions & 31 deletions llvm/test/CodeGen/RISCV/mul.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -181,7 +181,7 @@ define i64 @mul64_constant(i64 %a) nounwind {
;
; RV32IM-LABEL: mul64_constant:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a2, zero, 5
; RV32IM-NEXT: li a2, 5
; RV32IM-NEXT: mulhu a2, a0, a2
; RV32IM-NEXT: slli a3, a1, 2
; RV32IM-NEXT: add a1, a3, a1
Expand Down Expand Up @@ -267,7 +267,7 @@ define i32 @mulhs_positive_constant(i32 %a) nounwind {
;
; RV32IM-LABEL: mulhs_positive_constant:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a1, zero, 5
; RV32IM-NEXT: li a1, 5
; RV32IM-NEXT: mulh a0, a0, a1
; RV32IM-NEXT: ret
;
Expand Down Expand Up @@ -312,7 +312,7 @@ define i32 @mulhs_negative_constant(i32 %a) nounwind {
;
; RV32IM-LABEL: mulhs_negative_constant:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a1, zero, -5
; RV32IM-NEXT: li a1, -5
; RV32IM-NEXT: mulh a0, a0, a1
; RV32IM-NEXT: ret
;
Expand Down Expand Up @@ -346,8 +346,8 @@ define zeroext i32 @mulhu(i32 zeroext %a, i32 zeroext %b) nounwind {
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -389,7 +389,7 @@ define i32 @mulhsu(i32 %a, i32 %b) nounwind {
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a2, a1
; RV32I-NEXT: srai a3, a1, 31
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -442,7 +442,7 @@ define i32 @mulhu_constant(i32 %a) nounwind {
;
; RV32IM-LABEL: mulhu_constant:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a1, zero, 5
; RV32IM-NEXT: li a1, 5
; RV32IM-NEXT: mulhu a0, a0, a1
; RV32IM-NEXT: ret
;
Expand Down Expand Up @@ -542,7 +542,7 @@ define i64 @muli64_p65(i64 %a) nounwind {
;
; RV32IM-LABEL: muli64_p65:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a2, zero, 65
; RV32IM-NEXT: li a2, 65
; RV32IM-NEXT: mulhu a2, a0, a2
; RV32IM-NEXT: slli a3, a1, 6
; RV32IM-NEXT: add a1, a3, a1
Expand Down Expand Up @@ -581,7 +581,7 @@ define i64 @muli64_p63(i64 %a) nounwind {
;
; RV32IM-LABEL: muli64_p63:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a2, zero, 63
; RV32IM-NEXT: li a2, 63
; RV32IM-NEXT: mulhu a2, a0, a2
; RV32IM-NEXT: slli a3, a1, 6
; RV32IM-NEXT: sub a1, a3, a1
Expand Down Expand Up @@ -682,7 +682,7 @@ define i64 @muli64_m63(i64 %a) nounwind {
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a2, a1, 6
; RV32IM-NEXT: sub a1, a1, a2
; RV32IM-NEXT: addi a2, zero, -63
; RV32IM-NEXT: li a2, -63
; RV32IM-NEXT: mulhu a2, a0, a2
; RV32IM-NEXT: sub a2, a2, a0
; RV32IM-NEXT: add a1, a2, a1
Expand Down Expand Up @@ -726,7 +726,7 @@ define i64 @muli64_m65(i64 %a) nounwind {
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a2, a1, 6
; RV32IM-NEXT: add a1, a2, a1
; RV32IM-NEXT: addi a2, zero, -65
; RV32IM-NEXT: li a2, -65
; RV32IM-NEXT: mulhu a2, a0, a2
; RV32IM-NEXT: sub a2, a2, a0
; RV32IM-NEXT: sub a1, a2, a1
Expand Down Expand Up @@ -757,31 +757,31 @@ define i32 @muli32_p384(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: addi a1, zero, 384
; RV32I-NEXT: li a1, 384
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IM-LABEL: muli32_p384:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a1, zero, 384
; RV32IM-NEXT: li a1, 384
; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: ret
;
; RV64I-LABEL: muli32_p384:
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a1, zero, 384
; RV64I-NEXT: li a1, 384
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IM-LABEL: muli32_p384:
; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, 384
; RV64IM-NEXT: li a1, 384
; RV64IM-NEXT: mulw a0, a0, a1
; RV64IM-NEXT: ret
%1 = mul i32 %a, 384
Expand Down Expand Up @@ -1055,7 +1055,7 @@ define i64 @muli64_m4352(i64 %a) nounwind {
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a2, 1048575
; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: addi a3, zero, -1
; RV32I-NEXT: li a3, -1
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -1208,7 +1208,7 @@ define i128 @muli128_m3840(i128 %a) nounwind {
; RV32IM-NEXT: sub t0, a2, a4
; RV32IM-NEXT: neg t4, a4
; RV32IM-NEXT: sltu t1, t0, t4
; RV32IM-NEXT: addi t2, zero, -1
; RV32IM-NEXT: li t2, -1
; RV32IM-NEXT: mulhu t3, a4, t2
; RV32IM-NEXT: add a2, t3, t1
; RV32IM-NEXT: add t1, t5, a2
Expand Down Expand Up @@ -1323,7 +1323,7 @@ define i128 @muli128_m63(i128 %a) nounwind {
; RV32IM-NEXT: lw a3, 0(a1)
; RV32IM-NEXT: lw a4, 4(a1)
; RV32IM-NEXT: lw t5, 8(a1)
; RV32IM-NEXT: addi a6, zero, -63
; RV32IM-NEXT: li a6, -63
; RV32IM-NEXT: mulhu a5, a3, a6
; RV32IM-NEXT: slli a2, a4, 6
; RV32IM-NEXT: sub a2, a2, a4
Expand All @@ -1335,7 +1335,7 @@ define i128 @muli128_m63(i128 %a) nounwind {
; RV32IM-NEXT: sub t0, a5, a3
; RV32IM-NEXT: neg t1, a3
; RV32IM-NEXT: sltu a5, t0, t1
; RV32IM-NEXT: addi t2, zero, -1
; RV32IM-NEXT: li t2, -1
; RV32IM-NEXT: mulhu t3, a3, t2
; RV32IM-NEXT: add a5, t3, a5
; RV32IM-NEXT: add a5, t4, a5
Expand Down Expand Up @@ -1391,7 +1391,7 @@ define i128 @muli128_m63(i128 %a) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a2, a1, 6
; RV64IM-NEXT: sub a1, a1, a2
; RV64IM-NEXT: addi a2, zero, -63
; RV64IM-NEXT: li a2, -63
; RV64IM-NEXT: mulhu a2, a0, a2
; RV64IM-NEXT: sub a2, a2, a0
; RV64IM-NEXT: add a1, a2, a1
Expand Down Expand Up @@ -1422,39 +1422,39 @@ define i64 @mulhsu_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: srai s4, a3, 31
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: mv s1, a1
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: mv a2, s5
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: add s1, a0, s1
; RV32I-NEXT: sltu a0, s1, a0
; RV32I-NEXT: add s7, a1, a0
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: add a2, a0, s1
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: add s8, s7, a0
; RV32I-NEXT: mv a0, s2
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: mv a2, s0
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: mv s9, a0
; RV32I-NEXT: mv s6, a1
; RV32I-NEXT: add s1, a0, s8
; RV32I-NEXT: mv a0, s5
; RV32I-NEXT: mv a1, s0
; RV32I-NEXT: mv a2, zero
; RV32I-NEXT: mv a3, zero
; RV32I-NEXT: li a2, 0
; RV32I-NEXT: li a3, 0
; RV32I-NEXT: call __muldi3@plt
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: mv s5, a1
Expand Down Expand Up @@ -1530,7 +1530,7 @@ define i64 @mulhsu_i64(i64 %a, i64 %b) nounwind {
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a2, a1
; RV64I-NEXT: srai a3, a1, 63
; RV64I-NEXT: mv a1, zero
; RV64I-NEXT: li a1, 0
; RV64I-NEXT: call __multi3@plt
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/pr51206.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -29,13 +29,13 @@ define signext i32 @wobble() nounwind {
; CHECK-NEXT: mul a1, a1, a2
; CHECK-NEXT: srli a1, a1, 18
; CHECK-NEXT: lui a2, %hi(global.3)
; CHECK-NEXT: addi a3, zero, 5
; CHECK-NEXT: li a3, 5
; CHECK-NEXT: sw a1, %lo(global.3)(a2)
; CHECK-NEXT: bltu a0, a3, .LBB0_2
; CHECK-NEXT: # %bb.1: # %bb10
; CHECK-NEXT: call quux@plt
; CHECK-NEXT: .LBB0_2: # %bb12
; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: ret
Expand Down
72 changes: 36 additions & 36 deletions llvm/test/CodeGen/RISCV/rem.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -50,15 +50,15 @@ define i32 @urem_constant_lhs(i32 %a) nounwind {
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: addi a0, zero, 10
; RV32I-NEXT: li a0, 10
; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IM-LABEL: urem_constant_lhs:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a1, zero, 10
; RV32IM-NEXT: li a1, 10
; RV32IM-NEXT: remu a0, a1, a0
; RV32IM-NEXT: ret
;
Expand All @@ -68,15 +68,15 @@ define i32 @urem_constant_lhs(i32 %a) nounwind {
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a1, a0, 32
; RV64I-NEXT: addi a0, zero, 10
; RV64I-NEXT: li a0, 10
; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IM-LABEL: urem_constant_lhs:
; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, 10
; RV64IM-NEXT: li a1, 10
; RV64IM-NEXT: remuw a0, a1, a0
; RV64IM-NEXT: ret
%1 = urem i32 10, %a
Expand Down Expand Up @@ -207,15 +207,15 @@ define i32 @srem_constant_lhs(i32 %a) nounwind {
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a1, a0
; RV32I-NEXT: addi a0, zero, -10
; RV32I-NEXT: li a0, -10
; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
;
; RV32IM-LABEL: srem_constant_lhs:
; RV32IM: # %bb.0:
; RV32IM-NEXT: addi a1, zero, -10
; RV32IM-NEXT: li a1, -10
; RV32IM-NEXT: rem a0, a1, a0
; RV32IM-NEXT: ret
;
Expand All @@ -224,15 +224,15 @@ define i32 @srem_constant_lhs(i32 %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sext.w a1, a0
; RV64I-NEXT: addi a0, zero, -10
; RV64I-NEXT: li a0, -10
; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IM-LABEL: srem_constant_lhs:
; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, -10
; RV64IM-NEXT: li a1, -10
; RV64IM-NEXT: remw a0, a1, a0
; RV64IM-NEXT: ret
%1 = srem i32 -10, %a
Expand Down Expand Up @@ -282,8 +282,8 @@ define i64 @urem64_constant_lhs(i64 %a) nounwind {
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, a1
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: addi a0, zero, 10
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a0, 10
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: call __umoddi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -295,8 +295,8 @@ define i64 @urem64_constant_lhs(i64 %a) nounwind {
; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: mv a3, a1
; RV32IM-NEXT: mv a2, a0
; RV32IM-NEXT: addi a0, zero, 10
; RV32IM-NEXT: mv a1, zero
; RV32IM-NEXT: li a0, 10
; RV32IM-NEXT: li a1, 0
; RV32IM-NEXT: call __umoddi3@plt
; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 16
Expand All @@ -307,15 +307,15 @@ define i64 @urem64_constant_lhs(i64 %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: addi a0, zero, 10
; RV64I-NEXT: li a0, 10
; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IM-LABEL: urem64_constant_lhs:
; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, 10
; RV64IM-NEXT: li a1, 10
; RV64IM-NEXT: remu a0, a1, a0
; RV64IM-NEXT: ret
%1 = urem i64 10, %a
Expand Down Expand Up @@ -365,8 +365,8 @@ define i64 @srem64_constant_lhs(i64 %a) nounwind {
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv a3, a1
; RV32I-NEXT: mv a2, a0
; RV32I-NEXT: addi a0, zero, -10
; RV32I-NEXT: addi a1, zero, -1
; RV32I-NEXT: li a0, -10
; RV32I-NEXT: li a1, -1
; RV32I-NEXT: call __moddi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -378,8 +378,8 @@ define i64 @srem64_constant_lhs(i64 %a) nounwind {
; RV32IM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IM-NEXT: mv a3, a1
; RV32IM-NEXT: mv a2, a0
; RV32IM-NEXT: addi a0, zero, -10
; RV32IM-NEXT: addi a1, zero, -1
; RV32IM-NEXT: li a0, -10
; RV32IM-NEXT: li a1, -1
; RV32IM-NEXT: call __moddi3@plt
; RV32IM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IM-NEXT: addi sp, sp, 16
Expand All @@ -390,15 +390,15 @@ define i64 @srem64_constant_lhs(i64 %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: addi a0, zero, -10
; RV64I-NEXT: li a0, -10
; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
;
; RV64IM-LABEL: srem64_constant_lhs:
; RV64IM: # %bb.0:
; RV64IM-NEXT: addi a1, zero, -10
; RV64IM-NEXT: li a1, -10
; RV64IM-NEXT: rem a0, a1, a0
; RV64IM-NEXT: ret
%1 = srem i64 -10, %a
Expand Down Expand Up @@ -451,7 +451,7 @@ define i8 @urem8_constant_lhs(i8 %a) nounwind {
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a1, a0, 255
; RV32I-NEXT: addi a0, zero, 10
; RV32I-NEXT: li a0, 10
; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -460,7 +460,7 @@ define i8 @urem8_constant_lhs(i8 %a) nounwind {
; RV32IM-LABEL: urem8_constant_lhs:
; RV32IM: # %bb.0:
; RV32IM-NEXT: andi a0, a0, 255
; RV32IM-NEXT: addi a1, zero, 10
; RV32IM-NEXT: li a1, 10
; RV32IM-NEXT: remu a0, a1, a0
; RV32IM-NEXT: ret
;
Expand All @@ -469,7 +469,7 @@ define i8 @urem8_constant_lhs(i8 %a) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: andi a1, a0, 255
; RV64I-NEXT: addi a0, zero, 10
; RV64I-NEXT: li a0, 10
; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand All @@ -478,7 +478,7 @@ define i8 @urem8_constant_lhs(i8 %a) nounwind {
; RV64IM-LABEL: urem8_constant_lhs:
; RV64IM: # %bb.0:
; RV64IM-NEXT: andi a0, a0, 255
; RV64IM-NEXT: addi a1, zero, 10
; RV64IM-NEXT: li a1, 10
; RV64IM-NEXT: remuw a0, a1, a0
; RV64IM-NEXT: ret
%1 = urem i8 10, %a
Expand Down Expand Up @@ -541,7 +541,7 @@ define i8 @srem8_constant_lhs(i8 %a) nounwind {
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a1, a0, 24
; RV32I-NEXT: addi a0, zero, -10
; RV32I-NEXT: li a0, -10
; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -551,7 +551,7 @@ define i8 @srem8_constant_lhs(i8 %a) nounwind {
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a0, a0, 24
; RV32IM-NEXT: srai a0, a0, 24
; RV32IM-NEXT: addi a1, zero, -10
; RV32IM-NEXT: li a1, -10
; RV32IM-NEXT: rem a0, a1, a0
; RV32IM-NEXT: ret
;
Expand All @@ -561,7 +561,7 @@ define i8 @srem8_constant_lhs(i8 %a) nounwind {
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a1, a0, 56
; RV64I-NEXT: addi a0, zero, -10
; RV64I-NEXT: li a0, -10
; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand All @@ -571,7 +571,7 @@ define i8 @srem8_constant_lhs(i8 %a) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 56
; RV64IM-NEXT: srai a0, a0, 56
; RV64IM-NEXT: addi a1, zero, -10
; RV64IM-NEXT: li a1, -10
; RV64IM-NEXT: remw a0, a1, a0
; RV64IM-NEXT: ret
%1 = srem i8 -10, %a
Expand Down Expand Up @@ -635,7 +635,7 @@ define i16 @urem16_constant_lhs(i16 %a) nounwind {
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a1, a0, a1
; RV32I-NEXT: addi a0, zero, 10
; RV32I-NEXT: li a0, 10
; RV32I-NEXT: call __umodsi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -646,7 +646,7 @@ define i16 @urem16_constant_lhs(i16 %a) nounwind {
; RV32IM-NEXT: lui a1, 16
; RV32IM-NEXT: addi a1, a1, -1
; RV32IM-NEXT: and a0, a0, a1
; RV32IM-NEXT: addi a1, zero, 10
; RV32IM-NEXT: li a1, 10
; RV32IM-NEXT: remu a0, a1, a0
; RV32IM-NEXT: ret
;
Expand All @@ -657,7 +657,7 @@ define i16 @urem16_constant_lhs(i16 %a) nounwind {
; RV64I-NEXT: lui a1, 16
; RV64I-NEXT: addiw a1, a1, -1
; RV64I-NEXT: and a1, a0, a1
; RV64I-NEXT: addi a0, zero, 10
; RV64I-NEXT: li a0, 10
; RV64I-NEXT: call __umoddi3@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand All @@ -668,7 +668,7 @@ define i16 @urem16_constant_lhs(i16 %a) nounwind {
; RV64IM-NEXT: lui a1, 16
; RV64IM-NEXT: addiw a1, a1, -1
; RV64IM-NEXT: and a0, a0, a1
; RV64IM-NEXT: addi a1, zero, 10
; RV64IM-NEXT: li a1, 10
; RV64IM-NEXT: remuw a0, a1, a0
; RV64IM-NEXT: ret
%1 = urem i16 10, %a
Expand Down Expand Up @@ -730,7 +730,7 @@ define i16 @srem16_constant_lhs(i16 %a) nounwind {
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srai a1, a0, 16
; RV32I-NEXT: addi a0, zero, -10
; RV32I-NEXT: li a0, -10
; RV32I-NEXT: call __modsi3@plt
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -740,7 +740,7 @@ define i16 @srem16_constant_lhs(i16 %a) nounwind {
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a0, a0, 16
; RV32IM-NEXT: srai a0, a0, 16
; RV32IM-NEXT: addi a1, zero, -10
; RV32IM-NEXT: li a1, -10
; RV32IM-NEXT: rem a0, a1, a0
; RV32IM-NEXT: ret
;
Expand All @@ -750,7 +750,7 @@ define i16 @srem16_constant_lhs(i16 %a) nounwind {
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a1, a0, 48
; RV64I-NEXT: addi a0, zero, -10
; RV64I-NEXT: li a0, -10
; RV64I-NEXT: call __moddi3@plt
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand All @@ -760,7 +760,7 @@ define i16 @srem16_constant_lhs(i16 %a) nounwind {
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: srai a0, a0, 48
; RV64IM-NEXT: addi a1, zero, -10
; RV64IM-NEXT: li a1, -10
; RV64IM-NEXT: remw a0, a1, a0
; RV64IM-NEXT: ret
%1 = srem i16 -10, %a
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/remat.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -69,7 +69,7 @@ define i32 @test() nounwind {
; RV32I-NEXT: lw a2, %lo(c)(s10)
; RV32I-NEXT: lw a3, %lo(d)(s1)
; RV32I-NEXT: lw a4, %lo(e)(s0)
; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: li a5, 32
; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .LBB0_5: # %if.end
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
Expand All @@ -82,7 +82,7 @@ define i32 @test() nounwind {
; RV32I-NEXT: lw a2, %lo(d)(s1)
; RV32I-NEXT: lw a3, %lo(e)(s0)
; RV32I-NEXT: lw a4, %lo(f)(s7)
; RV32I-NEXT: addi a5, zero, 64
; RV32I-NEXT: li a5, 64
; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .LBB0_7: # %if.end5
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
Expand All @@ -95,7 +95,7 @@ define i32 @test() nounwind {
; RV32I-NEXT: lw a2, %lo(e)(s0)
; RV32I-NEXT: lw a3, %lo(f)(s7)
; RV32I-NEXT: lw a4, %lo(g)(s8)
; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: li a5, 32
; RV32I-NEXT: call foo@plt
; RV32I-NEXT: .LBB0_9: # %if.end9
; RV32I-NEXT: # in Loop: Header=BB0_3 Depth=1
Expand All @@ -108,11 +108,11 @@ define i32 @test() nounwind {
; RV32I-NEXT: lw a2, %lo(f)(s7)
; RV32I-NEXT: lw a3, %lo(g)(s8)
; RV32I-NEXT: lw a4, %lo(h)(s9)
; RV32I-NEXT: addi a5, zero, 32
; RV32I-NEXT: li a5, 32
; RV32I-NEXT: call foo@plt
; RV32I-NEXT: j .LBB0_2
; RV32I-NEXT: .LBB0_11: # %for.end
; RV32I-NEXT: addi a0, zero, 1
; RV32I-NEXT: li a0, 1
; RV32I-NEXT: lw s11, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s10, 16(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s9, 20(sp) # 4-byte Folded Reload
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rotl-rotr.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,7 @@
define i32 @rotl(i32 %x, i32 %y) nounwind {
; RV32I-LABEL: rotl:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 32
; RV32I-NEXT: li a2, 32
; RV32I-NEXT: sub a2, a2, a1
; RV32I-NEXT: sll a1, a0, a1
; RV32I-NEXT: srl a0, a0, a2
Expand All @@ -24,7 +24,7 @@ define i32 @rotl(i32 %x, i32 %y) nounwind {
define i32 @rotr(i32 %x, i32 %y) nounwind {
; RV32I-LABEL: rotr:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 32
; RV32I-NEXT: li a2, 32
; RV32I-NEXT: sub a2, a2, a1
; RV32I-NEXT: srl a1, a0, a1
; RV32I-NEXT: sll a0, a0, a2
Expand Down
62 changes: 31 additions & 31 deletions llvm/test/CodeGen/RISCV/rv32zba.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,7 @@ define i64 @sh3add(i64 %0, i64* %1) {
define i32 @addmul6(i32 %a, i32 %b) {
; RV32I-LABEL: addmul6:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 6
; RV32I-NEXT: li a2, 6
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
Expand All @@ -81,7 +81,7 @@ define i32 @addmul6(i32 %a, i32 %b) {
define i32 @addmul10(i32 %a, i32 %b) {
; RV32I-LABEL: addmul10:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 10
; RV32I-NEXT: li a2, 10
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
Expand All @@ -99,7 +99,7 @@ define i32 @addmul10(i32 %a, i32 %b) {
define i32 @addmul12(i32 %a, i32 %b) {
; RV32I-LABEL: addmul12:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 12
; RV32I-NEXT: li a2, 12
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
Expand All @@ -117,7 +117,7 @@ define i32 @addmul12(i32 %a, i32 %b) {
define i32 @addmul18(i32 %a, i32 %b) {
; RV32I-LABEL: addmul18:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 18
; RV32I-NEXT: li a2, 18
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
Expand All @@ -135,7 +135,7 @@ define i32 @addmul18(i32 %a, i32 %b) {
define i32 @addmul20(i32 %a, i32 %b) {
; RV32I-LABEL: addmul20:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 20
; RV32I-NEXT: li a2, 20
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
Expand All @@ -153,7 +153,7 @@ define i32 @addmul20(i32 %a, i32 %b) {
define i32 @addmul24(i32 %a, i32 %b) {
; RV32I-LABEL: addmul24:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 24
; RV32I-NEXT: li a2, 24
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
Expand All @@ -171,7 +171,7 @@ define i32 @addmul24(i32 %a, i32 %b) {
define i32 @addmul36(i32 %a, i32 %b) {
; RV32I-LABEL: addmul36:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 36
; RV32I-NEXT: li a2, 36
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
Expand All @@ -189,7 +189,7 @@ define i32 @addmul36(i32 %a, i32 %b) {
define i32 @addmul40(i32 %a, i32 %b) {
; RV32I-LABEL: addmul40:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 40
; RV32I-NEXT: li a2, 40
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
Expand All @@ -207,7 +207,7 @@ define i32 @addmul40(i32 %a, i32 %b) {
define i32 @addmul72(i32 %a, i32 %b) {
; RV32I-LABEL: addmul72:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 72
; RV32I-NEXT: li a2, 72
; RV32I-NEXT: mul a0, a0, a2
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: ret
Expand All @@ -225,7 +225,7 @@ define i32 @addmul72(i32 %a, i32 %b) {
define i32 @mul96(i32 %a) {
; RV32I-LABEL: mul96:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 96
; RV32I-NEXT: li a1, 96
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
Expand All @@ -241,7 +241,7 @@ define i32 @mul96(i32 %a) {
define i32 @mul160(i32 %a) {
; RV32I-LABEL: mul160:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 160
; RV32I-NEXT: li a1, 160
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
Expand All @@ -257,7 +257,7 @@ define i32 @mul160(i32 %a) {
define i32 @mul288(i32 %a) {
; RV32I-LABEL: mul288:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 288
; RV32I-NEXT: li a1, 288
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
Expand All @@ -273,13 +273,13 @@ define i32 @mul288(i32 %a) {
define i32 @mul258(i32 %a) {
; RV32I-LABEL: mul258:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 258
; RV32I-NEXT: li a1, 258
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
; RV32ZBA-LABEL: mul258:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: addi a1, zero, 258
; RV32ZBA-NEXT: li a1, 258
; RV32ZBA-NEXT: mul a0, a0, a1
; RV32ZBA-NEXT: ret
%c = mul i32 %a, 258
Expand All @@ -289,13 +289,13 @@ define i32 @mul258(i32 %a) {
define i32 @mul260(i32 %a) {
; RV32I-LABEL: mul260:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 260
; RV32I-NEXT: li a1, 260
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
; RV32ZBA-LABEL: mul260:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: addi a1, zero, 260
; RV32ZBA-NEXT: li a1, 260
; RV32ZBA-NEXT: mul a0, a0, a1
; RV32ZBA-NEXT: ret
%c = mul i32 %a, 260
Expand All @@ -305,13 +305,13 @@ define i32 @mul260(i32 %a) {
define i32 @mul264(i32 %a) {
; RV32I-LABEL: mul264:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 264
; RV32I-NEXT: li a1, 264
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
; RV32ZBA-LABEL: mul264:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: addi a1, zero, 264
; RV32ZBA-NEXT: li a1, 264
; RV32ZBA-NEXT: mul a0, a0, a1
; RV32ZBA-NEXT: ret
%c = mul i32 %a, 264
Expand All @@ -321,7 +321,7 @@ define i32 @mul264(i32 %a) {
define i32 @mul11(i32 %a) {
; RV32I-LABEL: mul11:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 11
; RV32I-NEXT: li a1, 11
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
Expand All @@ -337,7 +337,7 @@ define i32 @mul11(i32 %a) {
define i32 @mul19(i32 %a) {
; RV32I-LABEL: mul19:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 19
; RV32I-NEXT: li a1, 19
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
Expand All @@ -353,7 +353,7 @@ define i32 @mul19(i32 %a) {
define i32 @mul13(i32 %a) {
; RV32I-LABEL: mul13:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 13
; RV32I-NEXT: li a1, 13
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
Expand All @@ -369,7 +369,7 @@ define i32 @mul13(i32 %a) {
define i32 @mul21(i32 %a) {
; RV32I-LABEL: mul21:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 21
; RV32I-NEXT: li a1, 21
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
Expand All @@ -385,7 +385,7 @@ define i32 @mul21(i32 %a) {
define i32 @mul37(i32 %a) {
; RV32I-LABEL: mul37:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 37
; RV32I-NEXT: li a1, 37
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
Expand All @@ -401,7 +401,7 @@ define i32 @mul37(i32 %a) {
define i32 @mul25(i32 %a) {
; RV32I-LABEL: mul25:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 25
; RV32I-NEXT: li a1, 25
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
Expand All @@ -417,7 +417,7 @@ define i32 @mul25(i32 %a) {
define i32 @mul41(i32 %a) {
; RV32I-LABEL: mul41:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 41
; RV32I-NEXT: li a1, 41
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
Expand All @@ -433,7 +433,7 @@ define i32 @mul41(i32 %a) {
define i32 @mul73(i32 %a) {
; RV32I-LABEL: mul73:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 73
; RV32I-NEXT: li a1, 73
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
Expand All @@ -449,7 +449,7 @@ define i32 @mul73(i32 %a) {
define i32 @mul27(i32 %a) {
; RV32I-LABEL: mul27:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 27
; RV32I-NEXT: li a1, 27
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
Expand All @@ -465,7 +465,7 @@ define i32 @mul27(i32 %a) {
define i32 @mul45(i32 %a) {
; RV32I-LABEL: mul45:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 45
; RV32I-NEXT: li a1, 45
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
Expand All @@ -481,7 +481,7 @@ define i32 @mul45(i32 %a) {
define i32 @mul81(i32 %a) {
; RV32I-LABEL: mul81:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 81
; RV32I-NEXT: li a1, 81
; RV32I-NEXT: mul a0, a0, a1
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -555,7 +555,7 @@ define i32 @add4104(i32 %a) {
;
; RV32ZBA-LABEL: add4104:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: addi a1, zero, 1026
; RV32ZBA-NEXT: li a1, 1026
; RV32ZBA-NEXT: sh2add a0, a1, a0
; RV32ZBA-NEXT: ret
%c = add i32 %a, 4104
Expand All @@ -572,7 +572,7 @@ define i32 @add8208(i32 %a) {
;
; RV32ZBA-LABEL: add8208:
; RV32ZBA: # %bb.0:
; RV32ZBA-NEXT: addi a1, zero, 1026
; RV32ZBA-NEXT: li a1, 1026
; RV32ZBA-NEXT: sh3add a0, a1, a0
; RV32ZBA-NEXT: ret
%c = add i32 %a, 8208
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/rv32zbb.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@ define i32 @ctlz_i32(i32 %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: li a0, 32
; RV32I-NEXT: ret
;
; RV32ZBB-LABEL: ctlz_i32:
Expand Down Expand Up @@ -138,7 +138,7 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: srli a0, s2, 24
; RV32I-NEXT: .LBB1_3:
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
Expand All @@ -156,11 +156,11 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: clz a0, a0
; RV32ZBB-NEXT: addi a0, a0, 32
; RV32ZBB-NEXT: mv a1, zero
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: ret
; RV32ZBB-NEXT: .LBB1_2:
; RV32ZBB-NEXT: clz a0, a1
; RV32ZBB-NEXT: mv a1, zero
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: ret
%1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false)
ret i64 %1
Expand Down Expand Up @@ -202,7 +202,7 @@ define i32 @cttz_i32(i32 %a) nounwind {
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB2_2:
; RV32I-NEXT: addi a0, zero, 32
; RV32I-NEXT: li a0, 32
; RV32I-NEXT: ret
;
; RV32ZBB-LABEL: cttz_i32:
Expand Down Expand Up @@ -276,7 +276,7 @@ define i64 @cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: .LBB3_2:
; RV32I-NEXT: srli a0, s2, 24
; RV32I-NEXT: .LBB3_3:
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
Expand All @@ -294,11 +294,11 @@ define i64 @cttz_i64(i64 %a) nounwind {
; RV32ZBB-NEXT: # %bb.1:
; RV32ZBB-NEXT: ctz a0, a1
; RV32ZBB-NEXT: addi a0, a0, 32
; RV32ZBB-NEXT: mv a1, zero
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: ret
; RV32ZBB-NEXT: .LBB3_2:
; RV32ZBB-NEXT: ctz a0, a0
; RV32ZBB-NEXT: mv a1, zero
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: ret
%1 = call i64 @llvm.cttz.i64(i64 %a, i1 false)
ret i64 %1
Expand Down Expand Up @@ -392,7 +392,7 @@ define i64 @ctpop_i64(i64 %a) nounwind {
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: add a0, a0, s5
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload
Expand All @@ -408,7 +408,7 @@ define i64 @ctpop_i64(i64 %a) nounwind {
; RV32ZBB-NEXT: cpop a1, a1
; RV32ZBB-NEXT: cpop a0, a0
; RV32ZBB-NEXT: add a0, a0, a1
; RV32ZBB-NEXT: mv a1, zero
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: ret
%1 = call i64 @llvm.ctpop.i64(i64 %a)
ret i64 %1
Expand Down Expand Up @@ -795,13 +795,13 @@ define i64 @zexth_i64(i64 %a) nounwind {
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: ret
;
; RV32ZBB-LABEL: zexth_i64:
; RV32ZBB: # %bb.0:
; RV32ZBB-NEXT: zext.h a0, a0
; RV32ZBB-NEXT: mv a1, zero
; RV32ZBB-NEXT: li a1, 0
; RV32ZBB-NEXT: ret
%and = and i64 %a, 65535
ret i64 %and
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/rv32zbp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -2944,13 +2944,13 @@ define i64 @packh_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: slli a1, a2, 24
; RV32I-NEXT: srli a1, a1, 16
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: packh_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: packh a0, a0, a2
; RV32ZBP-NEXT: mv a1, zero
; RV32ZBP-NEXT: li a1, 0
; RV32ZBP-NEXT: ret
%and = and i64 %a, 255
%and1 = shl i64 %b, 8
Expand Down Expand Up @@ -2981,13 +2981,13 @@ define i64 @zexth_i64(i64 %a) nounwind {
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -1
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: ret
;
; RV32ZBP-LABEL: zexth_i64:
; RV32ZBP: # %bb.0:
; RV32ZBP-NEXT: zext.h a0, a0
; RV32ZBP-NEXT: mv a1, zero
; RV32ZBP-NEXT: li a1, 0
; RV32ZBP-NEXT: ret
%and = and i64 %a, 65535
ret i64 %and
Expand Down
40 changes: 20 additions & 20 deletions llvm/test/CodeGen/RISCV/rv32zbs.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@
define i32 @sbclr_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sbclr_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 1
; RV32I-NEXT: li a2, 1
; RV32I-NEXT: sll a1, a2, a1
; RV32I-NEXT: not a1, a1
; RV32I-NEXT: and a0, a1, a0
Expand All @@ -27,7 +27,7 @@ define i32 @sbclr_i32(i32 %a, i32 %b) nounwind {
define i32 @sbclr_i32_no_mask(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sbclr_i32_no_mask:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 1
; RV32I-NEXT: li a2, 1
; RV32I-NEXT: sll a1, a2, a1
; RV32I-NEXT: not a1, a1
; RV32I-NEXT: and a0, a1, a0
Expand All @@ -48,7 +48,7 @@ define i64 @sbclr_i64(i64 %a, i64 %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: andi a3, a2, 63
; RV32I-NEXT: addi a4, a3, -32
; RV32I-NEXT: addi a3, zero, 1
; RV32I-NEXT: li a3, 1
; RV32I-NEXT: bltz a4, .LBB2_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: sll a2, a3, a4
Expand Down Expand Up @@ -82,7 +82,7 @@ define i64 @sbclr_i64(i64 %a, i64 %b) nounwind {
define i32 @sbset_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sbset_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 1
; RV32I-NEXT: li a2, 1
; RV32I-NEXT: sll a1, a2, a1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
Expand All @@ -100,7 +100,7 @@ define i32 @sbset_i32(i32 %a, i32 %b) nounwind {
define i32 @sbset_i32_no_mask(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sbset_i32_no_mask:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 1
; RV32I-NEXT: li a2, 1
; RV32I-NEXT: sll a1, a2, a1
; RV32I-NEXT: or a0, a1, a0
; RV32I-NEXT: ret
Expand All @@ -118,7 +118,7 @@ define i32 @sbset_i32_no_mask(i32 %a, i32 %b) nounwind {
define signext i32 @sbset_i32_zero(i32 signext %a) nounwind {
; RV32I-LABEL: sbset_i32_zero:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, zero, 1
; RV32I-NEXT: li a1, 1
; RV32I-NEXT: sll a0, a1, a0
; RV32I-NEXT: ret
;
Expand All @@ -138,7 +138,7 @@ define signext i32 @sbset_i32_zero(i32 signext %a) nounwind {
define i64 @sbset_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: sbset_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a3, zero, 1
; RV32I-NEXT: li a3, 1
; RV32I-NEXT: sll a2, a3, a2
; RV32I-NEXT: srai a3, a2, 31
; RV32I-NEXT: or a0, a2, a0
Expand All @@ -164,14 +164,14 @@ define signext i64 @sbset_i64_zero(i64 signext %a) nounwind {
; RV32I-LABEL: sbset_i64_zero:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a1, a0, -32
; RV32I-NEXT: addi a2, zero, 1
; RV32I-NEXT: li a2, 1
; RV32I-NEXT: bltz a1, .LBB7_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a0, zero
; RV32I-NEXT: li a0, 0
; RV32I-NEXT: sll a1, a2, a1
; RV32I-NEXT: ret
; RV32I-NEXT: .LBB7_2:
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: sll a0, a2, a0
; RV32I-NEXT: ret
;
Expand All @@ -180,11 +180,11 @@ define signext i64 @sbset_i64_zero(i64 signext %a) nounwind {
; RV32ZBS-NEXT: addi a1, a0, -32
; RV32ZBS-NEXT: bltz a1, .LBB7_2
; RV32ZBS-NEXT: # %bb.1:
; RV32ZBS-NEXT: mv a0, zero
; RV32ZBS-NEXT: li a0, 0
; RV32ZBS-NEXT: bset a1, zero, a1
; RV32ZBS-NEXT: ret
; RV32ZBS-NEXT: .LBB7_2:
; RV32ZBS-NEXT: mv a1, zero
; RV32ZBS-NEXT: li a1, 0
; RV32ZBS-NEXT: bset a0, zero, a0
; RV32ZBS-NEXT: ret
%shl = shl i64 1, %a
Expand All @@ -194,7 +194,7 @@ define signext i64 @sbset_i64_zero(i64 signext %a) nounwind {
define i32 @sbinv_i32(i32 %a, i32 %b) nounwind {
; RV32I-LABEL: sbinv_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a2, zero, 1
; RV32I-NEXT: li a2, 1
; RV32I-NEXT: sll a1, a2, a1
; RV32I-NEXT: xor a0, a1, a0
; RV32I-NEXT: ret
Expand All @@ -217,7 +217,7 @@ define i32 @sbinv_i32(i32 %a, i32 %b) nounwind {
define i64 @sbinv_i64(i64 %a, i64 %b) nounwind {
; RV32I-LABEL: sbinv_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: addi a3, zero, 1
; RV32I-NEXT: li a3, 1
; RV32I-NEXT: sll a2, a3, a2
; RV32I-NEXT: srai a3, a2, 31
; RV32I-NEXT: xor a0, a2, a0
Expand Down Expand Up @@ -288,14 +288,14 @@ define i64 @sbext_i64(i64 %a, i64 %b) nounwind {
; RV32I-NEXT: j .LBB12_3
; RV32I-NEXT: .LBB12_2:
; RV32I-NEXT: srl a0, a0, a2
; RV32I-NEXT: addi a2, zero, 31
; RV32I-NEXT: li a2, 31
; RV32I-NEXT: sub a2, a2, a3
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: sll a1, a1, a2
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: .LBB12_3:
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: ret
;
; RV32ZBS-LABEL: sbext_i64:
Expand All @@ -308,14 +308,14 @@ define i64 @sbext_i64(i64 %a, i64 %b) nounwind {
; RV32ZBS-NEXT: j .LBB12_3
; RV32ZBS-NEXT: .LBB12_2:
; RV32ZBS-NEXT: srl a0, a0, a2
; RV32ZBS-NEXT: addi a2, zero, 31
; RV32ZBS-NEXT: li a2, 31
; RV32ZBS-NEXT: sub a2, a2, a3
; RV32ZBS-NEXT: slli a1, a1, 1
; RV32ZBS-NEXT: sll a1, a1, a2
; RV32ZBS-NEXT: or a0, a0, a1
; RV32ZBS-NEXT: .LBB12_3:
; RV32ZBS-NEXT: andi a0, a0, 1
; RV32ZBS-NEXT: mv a1, zero
; RV32ZBS-NEXT: li a1, 0
; RV32ZBS-NEXT: ret
%conv = and i64 %b, 63
%shr = lshr i64 %a, %conv
Expand Down Expand Up @@ -344,13 +344,13 @@ define i64 @sbexti_i64(i64 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: srli a0, a0, 5
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: mv a1, zero
; RV32I-NEXT: li a1, 0
; RV32I-NEXT: ret
;
; RV32ZBS-LABEL: sbexti_i64:
; RV32ZBS: # %bb.0:
; RV32ZBS-NEXT: bexti a0, a0, 5
; RV32ZBS-NEXT: mv a1, zero
; RV32ZBS-NEXT: li a1, 0
; RV32ZBS-NEXT: ret
%shr = lshr i64 %a, 5
%and = and i64 %shr, 1
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rv64i-w-insts-legalization.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ define signext i32 @addw(i32 signext %s, i32 signext %n, i32 signext %k) nounwin
; CHECK-NEXT: addw a0, a0, a1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB0_2:
; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret
entry:
%cmp6 = icmp slt i32 %s, %n
Expand Down Expand Up @@ -65,7 +65,7 @@ define signext i32 @subw(i32 signext %s, i32 signext %n, i32 signext %k) nounwin
; CHECK-NEXT: subw a0, a0, a1
; CHECK-NEXT: ret
; CHECK-NEXT: .LBB1_2:
; CHECK-NEXT: mv a0, zero
; CHECK-NEXT: li a0, 0
; CHECK-NEXT: ret
entry:
%cmp6 = icmp slt i32 %s, %n
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/rv64m-w-insts-legalization.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -4,10 +4,10 @@
define signext i32 @mulw(i32 signext %s, i32 signext %n, i32 signext %k) nounwind {
; CHECK-LABEL: mulw:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi a2, zero, 1
; CHECK-NEXT: li a2, 1
; CHECK-NEXT: bge a0, a1, .LBB0_3
; CHECK-NEXT: # %bb.1: # %for.body.preheader
; CHECK-NEXT: addi a2, zero, 1
; CHECK-NEXT: li a2, 1
; CHECK-NEXT: .LBB0_2: # %for.body
; CHECK-NEXT: # =>This Inner Loop Header: Depth=1
; CHECK-NEXT: mulw a2, a0, a2
Expand Down
72 changes: 36 additions & 36 deletions llvm/test/CodeGen/RISCV/rv64zba.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -318,7 +318,7 @@ define i64 @sh2add_extra_sext(i32 %x, i32 %y, i32 %z) {
define i64 @addmul6(i64 %a, i64 %b) {
; RV64I-LABEL: addmul6:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 6
; RV64I-NEXT: li a2, 6
; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
Expand All @@ -336,7 +336,7 @@ define i64 @addmul6(i64 %a, i64 %b) {
define i64 @addmul10(i64 %a, i64 %b) {
; RV64I-LABEL: addmul10:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 10
; RV64I-NEXT: li a2, 10
; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
Expand All @@ -354,7 +354,7 @@ define i64 @addmul10(i64 %a, i64 %b) {
define i64 @addmul12(i64 %a, i64 %b) {
; RV64I-LABEL: addmul12:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 12
; RV64I-NEXT: li a2, 12
; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
Expand All @@ -372,7 +372,7 @@ define i64 @addmul12(i64 %a, i64 %b) {
define i64 @addmul18(i64 %a, i64 %b) {
; RV64I-LABEL: addmul18:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 18
; RV64I-NEXT: li a2, 18
; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
Expand All @@ -390,7 +390,7 @@ define i64 @addmul18(i64 %a, i64 %b) {
define i64 @addmul20(i64 %a, i64 %b) {
; RV64I-LABEL: addmul20:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 20
; RV64I-NEXT: li a2, 20
; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
Expand All @@ -408,7 +408,7 @@ define i64 @addmul20(i64 %a, i64 %b) {
define i64 @addmul24(i64 %a, i64 %b) {
; RV64I-LABEL: addmul24:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 24
; RV64I-NEXT: li a2, 24
; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
Expand All @@ -426,7 +426,7 @@ define i64 @addmul24(i64 %a, i64 %b) {
define i64 @addmul36(i64 %a, i64 %b) {
; RV64I-LABEL: addmul36:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 36
; RV64I-NEXT: li a2, 36
; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
Expand All @@ -444,7 +444,7 @@ define i64 @addmul36(i64 %a, i64 %b) {
define i64 @addmul40(i64 %a, i64 %b) {
; RV64I-LABEL: addmul40:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 40
; RV64I-NEXT: li a2, 40
; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
Expand All @@ -462,7 +462,7 @@ define i64 @addmul40(i64 %a, i64 %b) {
define i64 @addmul72(i64 %a, i64 %b) {
; RV64I-LABEL: addmul72:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a2, zero, 72
; RV64I-NEXT: li a2, 72
; RV64I-NEXT: mul a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ret
Expand All @@ -480,7 +480,7 @@ define i64 @addmul72(i64 %a, i64 %b) {
define i64 @mul96(i64 %a) {
; RV64I-LABEL: mul96:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 96
; RV64I-NEXT: li a1, 96
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
Expand All @@ -496,7 +496,7 @@ define i64 @mul96(i64 %a) {
define i64 @mul160(i64 %a) {
; RV64I-LABEL: mul160:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 160
; RV64I-NEXT: li a1, 160
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
Expand All @@ -512,7 +512,7 @@ define i64 @mul160(i64 %a) {
define i64 @mul288(i64 %a) {
; RV64I-LABEL: mul288:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 288
; RV64I-NEXT: li a1, 288
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
Expand Down Expand Up @@ -654,13 +654,13 @@ define i64 @adduw_imm(i32 signext %0) nounwind {
define i64 @mul258(i64 %a) {
; RV64I-LABEL: mul258:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 258
; RV64I-NEXT: li a1, 258
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBA-LABEL: mul258:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a1, zero, 258
; RV64ZBA-NEXT: li a1, 258
; RV64ZBA-NEXT: mul a0, a0, a1
; RV64ZBA-NEXT: ret
%c = mul i64 %a, 258
Expand All @@ -670,13 +670,13 @@ define i64 @mul258(i64 %a) {
define i64 @mul260(i64 %a) {
; RV64I-LABEL: mul260:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 260
; RV64I-NEXT: li a1, 260
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBA-LABEL: mul260:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a1, zero, 260
; RV64ZBA-NEXT: li a1, 260
; RV64ZBA-NEXT: mul a0, a0, a1
; RV64ZBA-NEXT: ret
%c = mul i64 %a, 260
Expand All @@ -686,13 +686,13 @@ define i64 @mul260(i64 %a) {
define i64 @mul264(i64 %a) {
; RV64I-LABEL: mul264:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 264
; RV64I-NEXT: li a1, 264
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
; RV64ZBA-LABEL: mul264:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a1, zero, 264
; RV64ZBA-NEXT: li a1, 264
; RV64ZBA-NEXT: mul a0, a0, a1
; RV64ZBA-NEXT: ret
%c = mul i64 %a, 264
Expand All @@ -702,14 +702,14 @@ define i64 @mul264(i64 %a) {
define i64 @imm_zextw() nounwind {
; RV64I-LABEL: imm_zextw:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: addi a0, a0, -2
; RV64I-NEXT: ret
;
; RV64ZBA-LABEL: imm_zextw:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a0, zero, -2
; RV64ZBA-NEXT: li a0, -2
; RV64ZBA-NEXT: zext.w a0, a0
; RV64ZBA-NEXT: ret
ret i64 4294967294 ; -2 in 32 bits.
Expand All @@ -736,7 +736,7 @@ define i64 @imm_zextw2() nounwind {
define i64 @mul11(i64 %a) {
; RV64I-LABEL: mul11:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 11
; RV64I-NEXT: li a1, 11
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
Expand All @@ -752,7 +752,7 @@ define i64 @mul11(i64 %a) {
define i64 @mul19(i64 %a) {
; RV64I-LABEL: mul19:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 19
; RV64I-NEXT: li a1, 19
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
Expand All @@ -768,7 +768,7 @@ define i64 @mul19(i64 %a) {
define i64 @mul13(i64 %a) {
; RV64I-LABEL: mul13:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 13
; RV64I-NEXT: li a1, 13
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
Expand All @@ -784,7 +784,7 @@ define i64 @mul13(i64 %a) {
define i64 @mul21(i64 %a) {
; RV64I-LABEL: mul21:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 21
; RV64I-NEXT: li a1, 21
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
Expand All @@ -800,7 +800,7 @@ define i64 @mul21(i64 %a) {
define i64 @mul37(i64 %a) {
; RV64I-LABEL: mul37:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 37
; RV64I-NEXT: li a1, 37
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
Expand All @@ -816,7 +816,7 @@ define i64 @mul37(i64 %a) {
define i64 @mul25(i64 %a) {
; RV64I-LABEL: mul25:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 25
; RV64I-NEXT: li a1, 25
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
Expand All @@ -832,7 +832,7 @@ define i64 @mul25(i64 %a) {
define i64 @mul41(i64 %a) {
; RV64I-LABEL: mul41:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 41
; RV64I-NEXT: li a1, 41
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
Expand All @@ -848,7 +848,7 @@ define i64 @mul41(i64 %a) {
define i64 @mul73(i64 %a) {
; RV64I-LABEL: mul73:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 73
; RV64I-NEXT: li a1, 73
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
Expand All @@ -864,7 +864,7 @@ define i64 @mul73(i64 %a) {
define i64 @mul27(i64 %a) {
; RV64I-LABEL: mul27:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 27
; RV64I-NEXT: li a1, 27
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
Expand All @@ -880,7 +880,7 @@ define i64 @mul27(i64 %a) {
define i64 @mul45(i64 %a) {
; RV64I-LABEL: mul45:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 45
; RV64I-NEXT: li a1, 45
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
Expand All @@ -896,7 +896,7 @@ define i64 @mul45(i64 %a) {
define i64 @mul81(i64 %a) {
; RV64I-LABEL: mul81:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 81
; RV64I-NEXT: li a1, 81
; RV64I-NEXT: mul a0, a0, a1
; RV64I-NEXT: ret
;
Expand Down Expand Up @@ -963,7 +963,7 @@ define i64 @mul4104(i64 %a) {
define signext i32 @mulw192(i32 signext %a) {
; RV64I-LABEL: mulw192:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 192
; RV64I-NEXT: li a1, 192
; RV64I-NEXT: mulw a0, a0, a1
; RV64I-NEXT: ret
;
Expand All @@ -979,7 +979,7 @@ define signext i32 @mulw192(i32 signext %a) {
define signext i32 @mulw320(i32 signext %a) {
; RV64I-LABEL: mulw320:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 320
; RV64I-NEXT: li a1, 320
; RV64I-NEXT: mulw a0, a0, a1
; RV64I-NEXT: ret
;
Expand All @@ -995,7 +995,7 @@ define signext i32 @mulw320(i32 signext %a) {
define signext i32 @mulw576(i32 signext %a) {
; RV64I-LABEL: mulw576:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 576
; RV64I-NEXT: li a1, 576
; RV64I-NEXT: mulw a0, a0, a1
; RV64I-NEXT: ret
;
Expand All @@ -1018,7 +1018,7 @@ define i64 @add4104(i64 %a) {
;
; RV64ZBA-LABEL: add4104:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a1, zero, 1026
; RV64ZBA-NEXT: li a1, 1026
; RV64ZBA-NEXT: sh2add a0, a1, a0
; RV64ZBA-NEXT: ret
%c = add i64 %a, 4104
Expand All @@ -1035,7 +1035,7 @@ define i64 @add8208(i64 %a) {
;
; RV64ZBA-LABEL: add8208:
; RV64ZBA: # %bb.0:
; RV64ZBA-NEXT: addi a1, zero, 1026
; RV64ZBA-NEXT: li a1, 1026
; RV64ZBA-NEXT: sh3add a0, a1, a0
; RV64ZBA-NEXT: ret
%c = add i64 %a, 8208
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/rv64zbb-zbp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -186,7 +186,7 @@ define void @rol_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind {
define signext i32 @rol_i32_neg_constant_rhs(i32 signext %a) nounwind {
; RV64I-LABEL: rol_i32_neg_constant_rhs:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, -2
; RV64I-NEXT: li a1, -2
; RV64I-NEXT: sllw a2, a1, a0
; RV64I-NEXT: negw a0, a0
; RV64I-NEXT: srlw a0, a1, a0
Expand All @@ -195,13 +195,13 @@ define signext i32 @rol_i32_neg_constant_rhs(i32 signext %a) nounwind {
;
; RV64ZBB-LABEL: rol_i32_neg_constant_rhs:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addi a1, zero, -2
; RV64ZBB-NEXT: li a1, -2
; RV64ZBB-NEXT: rolw a0, a1, a0
; RV64ZBB-NEXT: ret
;
; RV64ZBP-LABEL: rol_i32_neg_constant_rhs:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: addi a1, zero, -2
; RV64ZBP-NEXT: li a1, -2
; RV64ZBP-NEXT: rolw a0, a1, a0
; RV64ZBP-NEXT: ret
%1 = tail call i32 @llvm.fshl.i32(i32 -2, i32 -2, i32 %a)
Expand Down Expand Up @@ -286,7 +286,7 @@ define void @ror_i32_nosext(i32 signext %a, i32 signext %b, i32* %x) nounwind {
define signext i32 @ror_i32_neg_constant_rhs(i32 signext %a) nounwind {
; RV64I-LABEL: ror_i32_neg_constant_rhs:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, -2
; RV64I-NEXT: li a1, -2
; RV64I-NEXT: srlw a2, a1, a0
; RV64I-NEXT: negw a0, a0
; RV64I-NEXT: sllw a0, a1, a0
Expand All @@ -295,13 +295,13 @@ define signext i32 @ror_i32_neg_constant_rhs(i32 signext %a) nounwind {
;
; RV64ZBB-LABEL: ror_i32_neg_constant_rhs:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addi a1, zero, -2
; RV64ZBB-NEXT: li a1, -2
; RV64ZBB-NEXT: rorw a0, a1, a0
; RV64ZBB-NEXT: ret
;
; RV64ZBP-LABEL: ror_i32_neg_constant_rhs:
; RV64ZBP: # %bb.0:
; RV64ZBP-NEXT: addi a1, zero, -2
; RV64ZBP-NEXT: li a1, -2
; RV64ZBP-NEXT: rorw a0, a1, a0
; RV64ZBP-NEXT: ret
%1 = tail call i32 @llvm.fshr.i32(i32 -2, i32 -2, i32 %a)
Expand Down
36 changes: 18 additions & 18 deletions llvm/test/CodeGen/RISCV/rv64zbb.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -48,7 +48,7 @@ define signext i32 @ctlz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB0_2:
; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: ret
;
; RV64ZBB-LABEL: ctlz_i32:
Expand Down Expand Up @@ -101,16 +101,16 @@ define signext i32 @log2_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: j .LBB1_3
; RV64I-NEXT: .LBB1_2:
; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: .LBB1_3: # %cond.end
; RV64I-NEXT: addi a1, zero, 31
; RV64I-NEXT: li a1, 31
; RV64I-NEXT: sub a0, a1, a0
; RV64I-NEXT: ret
;
; RV64ZBB-LABEL: log2_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: clzw a0, a0
; RV64ZBB-NEXT: addi a1, zero, 31
; RV64ZBB-NEXT: li a1, 31
; RV64ZBB-NEXT: sub a0, a1, a0
; RV64ZBB-NEXT: ret
%1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false)
Expand All @@ -125,8 +125,8 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: addi s0, zero, 32
; RV64I-NEXT: addi a1, zero, 32
; RV64I-NEXT: li s0, 32
; RV64I-NEXT: li a1, 32
; RV64I-NEXT: beqz a0, .LBB2_2
; RV64I-NEXT: # %bb.1: # %cond.false
; RV64I-NEXT: srliw a1, a0, 1
Expand Down Expand Up @@ -171,7 +171,7 @@ define signext i32 @log2_ceil_i32(i32 signext %a) nounwind {
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: addiw a0, a0, -1
; RV64ZBB-NEXT: clzw a0, a0
; RV64ZBB-NEXT: addi a1, zero, 32
; RV64ZBB-NEXT: li a1, 32
; RV64ZBB-NEXT: sub a0, a1, a0
; RV64ZBB-NEXT: ret
%1 = sub i32 %a, 1
Expand Down Expand Up @@ -218,7 +218,7 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: li a0, -1
; RV64I-NEXT: beqz s0, .LBB3_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: srliw a0, a1, 24
Expand All @@ -232,7 +232,7 @@ define signext i32 @findLastSet_i32(i32 signext %a) nounwind {
; RV64ZBB-LABEL: findLastSet_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: mv a1, a0
; RV64ZBB-NEXT: addi a0, zero, -1
; RV64ZBB-NEXT: li a0, -1
; RV64ZBB-NEXT: beqz a1, .LBB3_2
; RV64ZBB-NEXT: # %bb.1:
; RV64ZBB-NEXT: clzw a0, a1
Expand Down Expand Up @@ -293,7 +293,7 @@ define i32 @ctlz_lshr_i32(i32 signext %a) {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB4_2:
; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: ret
;
; RV64ZBB-LABEL: ctlz_lshr_i32:
Expand Down Expand Up @@ -374,7 +374,7 @@ define i64 @ctlz_i64(i64 %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB5_2:
; RV64I-NEXT: addi a0, zero, 64
; RV64I-NEXT: li a0, 64
; RV64I-NEXT: ret
;
; RV64ZBB-LABEL: ctlz_i64:
Expand Down Expand Up @@ -421,7 +421,7 @@ define signext i32 @cttz_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB6_2:
; RV64I-NEXT: addi a0, zero, 32
; RV64I-NEXT: li a0, 32
; RV64I-NEXT: ret
;
; RV64ZBB-LABEL: cttz_i32:
Expand Down Expand Up @@ -502,7 +502,7 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: addi a0, zero, -1
; RV64I-NEXT: li a0, -1
; RV64I-NEXT: beqz s0, .LBB8_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: srliw a0, a1, 24
Expand All @@ -515,7 +515,7 @@ define signext i32 @findFirstSet_i32(i32 signext %a) nounwind {
; RV64ZBB-LABEL: findFirstSet_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: mv a1, a0
; RV64ZBB-NEXT: addi a0, zero, -1
; RV64ZBB-NEXT: li a0, -1
; RV64ZBB-NEXT: beqz a1, .LBB8_2
; RV64ZBB-NEXT: # %bb.1:
; RV64ZBB-NEXT: ctzw a0, a1
Expand Down Expand Up @@ -557,7 +557,7 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind {
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: mv a1, a0
; RV64I-NEXT: mv a0, zero
; RV64I-NEXT: li a0, 0
; RV64I-NEXT: beqz s0, .LBB9_2
; RV64I-NEXT: # %bb.1:
; RV64I-NEXT: srliw a0, a1, 24
Expand All @@ -571,7 +571,7 @@ define signext i32 @ffs_i32(i32 signext %a) nounwind {
; RV64ZBB-LABEL: ffs_i32:
; RV64ZBB: # %bb.0:
; RV64ZBB-NEXT: mv a1, a0
; RV64ZBB-NEXT: mv a0, zero
; RV64ZBB-NEXT: li a0, 0
; RV64ZBB-NEXT: beqz a1, .LBB9_2
; RV64ZBB-NEXT: # %bb.1:
; RV64ZBB-NEXT: ctzw a0, a1
Expand Down Expand Up @@ -643,7 +643,7 @@ define i64 @cttz_i64(i64 %a) nounwind {
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
; RV64I-NEXT: .LBB10_2:
; RV64I-NEXT: addi a0, zero, 64
; RV64I-NEXT: li a0, 64
; RV64I-NEXT: ret
;
; RV64ZBB-LABEL: cttz_i64:
Expand Down Expand Up @@ -1141,7 +1141,7 @@ define i64 @bswap_i64(i64 %a) {
; RV64I-NEXT: lui a2, 4080
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a2, a0, 8
; RV64I-NEXT: addi a3, zero, 255
; RV64I-NEXT: li a3, 255
; RV64I-NEXT: slli a4, a3, 24
; RV64I-NEXT: and a2, a2, a4
; RV64I-NEXT: or a1, a2, a1
Expand Down
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