230 changes: 115 additions & 115 deletions llvm/test/CodeGen/RISCV/bittest.ll
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1,052 changes: 524 additions & 528 deletions llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
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32 changes: 16 additions & 16 deletions llvm/test/CodeGen/RISCV/calling-conv-half.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -333,15 +333,15 @@ define i32 @caller_half_on_stack() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: lui a0, 5
; RV32I-NEXT: addi t0, a0, -1792
; RV32I-NEXT: lui a7, 5
; RV32I-NEXT: li a0, 1
; RV32I-NEXT: li a1, 2
; RV32I-NEXT: li a2, 3
; RV32I-NEXT: li a3, 4
; RV32I-NEXT: li a4, 5
; RV32I-NEXT: li a5, 6
; RV32I-NEXT: li a6, 7
; RV32I-NEXT: addi t0, a7, -1792
; RV32I-NEXT: li a7, 8
; RV32I-NEXT: sw t0, 0(sp)
; RV32I-NEXT: call callee_half_on_stack
Expand All @@ -353,15 +353,15 @@ define i32 @caller_half_on_stack() nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: lui a0, 5
; RV64I-NEXT: addiw t0, a0, -1792
; RV64I-NEXT: lui a7, 5
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: li a1, 2
; RV64I-NEXT: li a2, 3
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 5
; RV64I-NEXT: li a5, 6
; RV64I-NEXT: li a6, 7
; RV64I-NEXT: addiw t0, a7, -1792
; RV64I-NEXT: li a7, 8
; RV64I-NEXT: sd t0, 0(sp)
; RV64I-NEXT: call callee_half_on_stack
Expand All @@ -373,15 +373,15 @@ define i32 @caller_half_on_stack() nounwind {
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: lui a0, 1048565
; RV32IF-NEXT: addi t0, a0, -1792
; RV32IF-NEXT: lui a7, 1048565
; RV32IF-NEXT: li a0, 1
; RV32IF-NEXT: li a1, 2
; RV32IF-NEXT: li a2, 3
; RV32IF-NEXT: li a3, 4
; RV32IF-NEXT: li a4, 5
; RV32IF-NEXT: li a5, 6
; RV32IF-NEXT: li a6, 7
; RV32IF-NEXT: addi t0, a7, -1792
; RV32IF-NEXT: li a7, 8
; RV32IF-NEXT: sw t0, 0(sp)
; RV32IF-NEXT: call callee_half_on_stack
Expand All @@ -393,15 +393,15 @@ define i32 @caller_half_on_stack() nounwind {
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: lui a0, 1048565
; RV64IF-NEXT: addi t0, a0, -1792
; RV64IF-NEXT: lui a7, 1048565
; RV64IF-NEXT: li a0, 1
; RV64IF-NEXT: li a1, 2
; RV64IF-NEXT: li a2, 3
; RV64IF-NEXT: li a3, 4
; RV64IF-NEXT: li a4, 5
; RV64IF-NEXT: li a5, 6
; RV64IF-NEXT: li a6, 7
; RV64IF-NEXT: addi t0, a7, -1792
; RV64IF-NEXT: li a7, 8
; RV64IF-NEXT: sw t0, 0(sp)
; RV64IF-NEXT: call callee_half_on_stack
Expand All @@ -413,12 +413,12 @@ define i32 @caller_half_on_stack() nounwind {
; RV32-ILP32F: # %bb.0:
; RV32-ILP32F-NEXT: addi sp, sp, -16
; RV32-ILP32F-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32F-NEXT: lui a0, %hi(.LCPI3_0)
; RV32-ILP32F-NEXT: flw fa0, %lo(.LCPI3_0)(a0)
; RV32-ILP32F-NEXT: lui a4, %hi(.LCPI3_0)
; RV32-ILP32F-NEXT: li a0, 1
; RV32-ILP32F-NEXT: li a1, 2
; RV32-ILP32F-NEXT: li a2, 3
; RV32-ILP32F-NEXT: li a3, 4
; RV32-ILP32F-NEXT: flw fa0, %lo(.LCPI3_0)(a4)
; RV32-ILP32F-NEXT: li a4, 5
; RV32-ILP32F-NEXT: li a5, 6
; RV32-ILP32F-NEXT: li a6, 7
Expand All @@ -432,12 +432,12 @@ define i32 @caller_half_on_stack() nounwind {
; RV64-LP64F: # %bb.0:
; RV64-LP64F-NEXT: addi sp, sp, -16
; RV64-LP64F-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-LP64F-NEXT: lui a0, %hi(.LCPI3_0)
; RV64-LP64F-NEXT: flw fa0, %lo(.LCPI3_0)(a0)
; RV64-LP64F-NEXT: lui a4, %hi(.LCPI3_0)
; RV64-LP64F-NEXT: li a0, 1
; RV64-LP64F-NEXT: li a1, 2
; RV64-LP64F-NEXT: li a2, 3
; RV64-LP64F-NEXT: li a3, 4
; RV64-LP64F-NEXT: flw fa0, %lo(.LCPI3_0)(a4)
; RV64-LP64F-NEXT: li a4, 5
; RV64-LP64F-NEXT: li a5, 6
; RV64-LP64F-NEXT: li a6, 7
Expand All @@ -451,12 +451,12 @@ define i32 @caller_half_on_stack() nounwind {
; RV32-ILP32ZFHMIN: # %bb.0:
; RV32-ILP32ZFHMIN-NEXT: addi sp, sp, -16
; RV32-ILP32ZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32ZFHMIN-NEXT: lui a0, %hi(.LCPI3_0)
; RV32-ILP32ZFHMIN-NEXT: flh fa0, %lo(.LCPI3_0)(a0)
; RV32-ILP32ZFHMIN-NEXT: lui a4, %hi(.LCPI3_0)
; RV32-ILP32ZFHMIN-NEXT: li a0, 1
; RV32-ILP32ZFHMIN-NEXT: li a1, 2
; RV32-ILP32ZFHMIN-NEXT: li a2, 3
; RV32-ILP32ZFHMIN-NEXT: li a3, 4
; RV32-ILP32ZFHMIN-NEXT: flh fa0, %lo(.LCPI3_0)(a4)
; RV32-ILP32ZFHMIN-NEXT: li a4, 5
; RV32-ILP32ZFHMIN-NEXT: li a5, 6
; RV32-ILP32ZFHMIN-NEXT: li a6, 7
Expand All @@ -470,12 +470,12 @@ define i32 @caller_half_on_stack() nounwind {
; RV64-LP64ZFHMIN: # %bb.0:
; RV64-LP64ZFHMIN-NEXT: addi sp, sp, -16
; RV64-LP64ZFHMIN-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-LP64ZFHMIN-NEXT: lui a0, %hi(.LCPI3_0)
; RV64-LP64ZFHMIN-NEXT: flh fa0, %lo(.LCPI3_0)(a0)
; RV64-LP64ZFHMIN-NEXT: lui a4, %hi(.LCPI3_0)
; RV64-LP64ZFHMIN-NEXT: li a0, 1
; RV64-LP64ZFHMIN-NEXT: li a1, 2
; RV64-LP64ZFHMIN-NEXT: li a2, 3
; RV64-LP64ZFHMIN-NEXT: li a3, 4
; RV64-LP64ZFHMIN-NEXT: flh fa0, %lo(.LCPI3_0)(a4)
; RV64-LP64ZFHMIN-NEXT: li a4, 5
; RV64-LP64ZFHMIN-NEXT: li a5, 6
; RV64-LP64ZFHMIN-NEXT: li a6, 7
Expand Down
100 changes: 52 additions & 48 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -145,43 +145,45 @@ define void @caller_aligned_stack() nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -64
; RV32I-FPELIM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: li a0, 18
; RV32I-FPELIM-NEXT: li a1, 17
; RV32I-FPELIM-NEXT: sw a1, 20(sp)
; RV32I-FPELIM-NEXT: sw a0, 24(sp)
; RV32I-FPELIM-NEXT: li a0, 16
; RV32I-FPELIM-NEXT: lui a1, 262236
; RV32I-FPELIM-NEXT: addi a1, a1, 655
; RV32I-FPELIM-NEXT: lui a2, 377487
; RV32I-FPELIM-NEXT: addi a2, a2, 1475
; RV32I-FPELIM-NEXT: li a3, 15
; RV32I-FPELIM-NEXT: sw a3, 0(sp)
; RV32I-FPELIM-NEXT: sw a2, 8(sp)
; RV32I-FPELIM-NEXT: sw a1, 12(sp)
; RV32I-FPELIM-NEXT: sw a0, 16(sp)
; RV32I-FPELIM-NEXT: lui a0, 262153
; RV32I-FPELIM-NEXT: addi t0, a0, 491
; RV32I-FPELIM-NEXT: lui a0, 545260
; RV32I-FPELIM-NEXT: addi t1, a0, -1967
; RV32I-FPELIM-NEXT: lui a0, 964690
; RV32I-FPELIM-NEXT: addi t2, a0, -328
; RV32I-FPELIM-NEXT: lui a0, 335544
; RV32I-FPELIM-NEXT: addi t3, a0, 1311
; RV32I-FPELIM-NEXT: lui a0, 688509
; RV32I-FPELIM-NEXT: addi a5, a0, -2048
; RV32I-FPELIM-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: li a5, 18
; RV32I-FPELIM-NEXT: li a6, 17
; RV32I-FPELIM-NEXT: li a7, 16
; RV32I-FPELIM-NEXT: lui t0, 262236
; RV32I-FPELIM-NEXT: lui t1, 377487
; RV32I-FPELIM-NEXT: li t2, 15
; RV32I-FPELIM-NEXT: lui t3, 262153
; RV32I-FPELIM-NEXT: lui t4, 545260
; RV32I-FPELIM-NEXT: lui t5, 964690
; RV32I-FPELIM-NEXT: lui t6, 335544
; RV32I-FPELIM-NEXT: lui s0, 688509
; RV32I-FPELIM-NEXT: li a0, 1
; RV32I-FPELIM-NEXT: li a1, 11
; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: li a3, 12
; RV32I-FPELIM-NEXT: li a4, 13
; RV32I-FPELIM-NEXT: sw a6, 20(sp)
; RV32I-FPELIM-NEXT: sw a5, 24(sp)
; RV32I-FPELIM-NEXT: li a6, 4
; RV32I-FPELIM-NEXT: addi a5, t0, 655
; RV32I-FPELIM-NEXT: addi t0, t1, 1475
; RV32I-FPELIM-NEXT: sw t2, 0(sp)
; RV32I-FPELIM-NEXT: sw t0, 8(sp)
; RV32I-FPELIM-NEXT: sw a5, 12(sp)
; RV32I-FPELIM-NEXT: sw a7, 16(sp)
; RV32I-FPELIM-NEXT: li a7, 14
; RV32I-FPELIM-NEXT: addi t0, t3, 491
; RV32I-FPELIM-NEXT: addi t1, t4, -1967
; RV32I-FPELIM-NEXT: addi t2, t5, -328
; RV32I-FPELIM-NEXT: addi t3, t6, 1311
; RV32I-FPELIM-NEXT: addi a5, s0, -2048
; RV32I-FPELIM-NEXT: sw t3, 32(sp)
; RV32I-FPELIM-NEXT: sw t2, 36(sp)
; RV32I-FPELIM-NEXT: sw t1, 40(sp)
; RV32I-FPELIM-NEXT: sw t0, 44(sp)
; RV32I-FPELIM-NEXT: call callee_aligned_stack
; RV32I-FPELIM-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 64
; RV32I-FPELIM-NEXT: ret
;
Expand All @@ -190,45 +192,47 @@ define void @caller_aligned_stack() nounwind {
; RV32I-WITHFP-NEXT: addi sp, sp, -64
; RV32I-WITHFP-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s1, 52(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 64
; RV32I-WITHFP-NEXT: li a0, 18
; RV32I-WITHFP-NEXT: li a1, 17
; RV32I-WITHFP-NEXT: sw a1, 20(sp)
; RV32I-WITHFP-NEXT: sw a0, 24(sp)
; RV32I-WITHFP-NEXT: li a0, 16
; RV32I-WITHFP-NEXT: lui a1, 262236
; RV32I-WITHFP-NEXT: addi a1, a1, 655
; RV32I-WITHFP-NEXT: lui a2, 377487
; RV32I-WITHFP-NEXT: addi a2, a2, 1475
; RV32I-WITHFP-NEXT: li a3, 15
; RV32I-WITHFP-NEXT: sw a3, 0(sp)
; RV32I-WITHFP-NEXT: sw a2, 8(sp)
; RV32I-WITHFP-NEXT: sw a1, 12(sp)
; RV32I-WITHFP-NEXT: sw a0, 16(sp)
; RV32I-WITHFP-NEXT: lui a0, 262153
; RV32I-WITHFP-NEXT: addi t0, a0, 491
; RV32I-WITHFP-NEXT: lui a0, 545260
; RV32I-WITHFP-NEXT: addi t1, a0, -1967
; RV32I-WITHFP-NEXT: lui a0, 964690
; RV32I-WITHFP-NEXT: addi t2, a0, -328
; RV32I-WITHFP-NEXT: lui a0, 335544
; RV32I-WITHFP-NEXT: addi t3, a0, 1311
; RV32I-WITHFP-NEXT: lui a0, 688509
; RV32I-WITHFP-NEXT: addi a5, a0, -2048
; RV32I-WITHFP-NEXT: li a5, 18
; RV32I-WITHFP-NEXT: li a6, 17
; RV32I-WITHFP-NEXT: li a7, 16
; RV32I-WITHFP-NEXT: lui t0, 262236
; RV32I-WITHFP-NEXT: lui t1, 377487
; RV32I-WITHFP-NEXT: li t2, 15
; RV32I-WITHFP-NEXT: lui t3, 262153
; RV32I-WITHFP-NEXT: lui t4, 545260
; RV32I-WITHFP-NEXT: lui t5, 964690
; RV32I-WITHFP-NEXT: lui t6, 335544
; RV32I-WITHFP-NEXT: lui s1, 688509
; RV32I-WITHFP-NEXT: li a0, 1
; RV32I-WITHFP-NEXT: li a1, 11
; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: li a3, 12
; RV32I-WITHFP-NEXT: li a4, 13
; RV32I-WITHFP-NEXT: sw a6, 20(sp)
; RV32I-WITHFP-NEXT: sw a5, 24(sp)
; RV32I-WITHFP-NEXT: li a6, 4
; RV32I-WITHFP-NEXT: addi a5, t0, 655
; RV32I-WITHFP-NEXT: addi t0, t1, 1475
; RV32I-WITHFP-NEXT: sw t2, 0(sp)
; RV32I-WITHFP-NEXT: sw t0, 8(sp)
; RV32I-WITHFP-NEXT: sw a5, 12(sp)
; RV32I-WITHFP-NEXT: sw a7, 16(sp)
; RV32I-WITHFP-NEXT: li a7, 14
; RV32I-WITHFP-NEXT: addi t0, t3, 491
; RV32I-WITHFP-NEXT: addi t1, t4, -1967
; RV32I-WITHFP-NEXT: addi t2, t5, -328
; RV32I-WITHFP-NEXT: addi t3, t6, 1311
; RV32I-WITHFP-NEXT: addi a5, s1, -2048
; RV32I-WITHFP-NEXT: sw t3, -32(s0)
; RV32I-WITHFP-NEXT: sw t2, -28(s0)
; RV32I-WITHFP-NEXT: sw t1, -24(s0)
; RV32I-WITHFP-NEXT: sw t0, -20(s0)
; RV32I-WITHFP-NEXT: call callee_aligned_stack
; RV32I-WITHFP-NEXT: lw ra, 60(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 56(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s1, 52(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 64
; RV32I-WITHFP-NEXT: ret
%1 = call i32 @callee_aligned_stack(i32 1, i32 11,
Expand Down
252 changes: 126 additions & 126 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -86,15 +86,15 @@ define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i64 %d, i32 %e, i32 %f, i
; RV32I-FPELIM-NEXT: lw t1, 0(sp)
; RV32I-FPELIM-NEXT: andi a0, a0, 255
; RV32I-FPELIM-NEXT: slli a1, a1, 16
; RV32I-FPELIM-NEXT: xor a3, a3, a7
; RV32I-FPELIM-NEXT: srli a1, a1, 16
; RV32I-FPELIM-NEXT: add a0, a0, a2
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: xor a1, a4, t1
; RV32I-FPELIM-NEXT: xor a2, a3, a7
; RV32I-FPELIM-NEXT: or a1, a2, a1
; RV32I-FPELIM-NEXT: seqz a1, a1
; RV32I-FPELIM-NEXT: add a0, a0, a5
; RV32I-FPELIM-NEXT: xor a1, a4, t1
; RV32I-FPELIM-NEXT: add a0, a0, a6
; RV32I-FPELIM-NEXT: or a1, a3, a1
; RV32I-FPELIM-NEXT: seqz a1, a1
; RV32I-FPELIM-NEXT: add a0, a0, t0
; RV32I-FPELIM-NEXT: add a0, a1, a0
; RV32I-FPELIM-NEXT: ret
Expand All @@ -109,15 +109,15 @@ define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i64 %d, i32 %e, i32 %f, i
; RV32I-WITHFP-NEXT: lw t1, 0(s0)
; RV32I-WITHFP-NEXT: andi a0, a0, 255
; RV32I-WITHFP-NEXT: slli a1, a1, 16
; RV32I-WITHFP-NEXT: xor a3, a3, a7
; RV32I-WITHFP-NEXT: srli a1, a1, 16
; RV32I-WITHFP-NEXT: add a0, a0, a2
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: xor a1, a4, t1
; RV32I-WITHFP-NEXT: xor a2, a3, a7
; RV32I-WITHFP-NEXT: or a1, a2, a1
; RV32I-WITHFP-NEXT: seqz a1, a1
; RV32I-WITHFP-NEXT: add a0, a0, a5
; RV32I-WITHFP-NEXT: xor a1, a4, t1
; RV32I-WITHFP-NEXT: add a0, a0, a6
; RV32I-WITHFP-NEXT: or a1, a3, a1
; RV32I-WITHFP-NEXT: seqz a1, a1
; RV32I-WITHFP-NEXT: add a0, a0, t0
; RV32I-WITHFP-NEXT: add a0, a1, a0
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -190,21 +190,21 @@ define i32 @caller_many_scalars() nounwind {
define i32 @callee_large_scalars(i128 %a, fp128 %b) nounwind {
; RV32I-FPELIM-LABEL: callee_large_scalars:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw a2, 0(a0)
; RV32I-FPELIM-NEXT: lw a3, 4(a0)
; RV32I-FPELIM-NEXT: lw a4, 12(a1)
; RV32I-FPELIM-NEXT: lw a2, 0(a1)
; RV32I-FPELIM-NEXT: lw a3, 4(a1)
; RV32I-FPELIM-NEXT: lw a4, 8(a1)
; RV32I-FPELIM-NEXT: lw a1, 12(a1)
; RV32I-FPELIM-NEXT: lw a5, 12(a0)
; RV32I-FPELIM-NEXT: lw a6, 0(a1)
; RV32I-FPELIM-NEXT: lw a7, 4(a1)
; RV32I-FPELIM-NEXT: lw a1, 8(a1)
; RV32I-FPELIM-NEXT: lw a0, 8(a0)
; RV32I-FPELIM-NEXT: xor a4, a5, a4
; RV32I-FPELIM-NEXT: xor a3, a3, a7
; RV32I-FPELIM-NEXT: or a3, a3, a4
; RV32I-FPELIM-NEXT: xor a0, a0, a1
; RV32I-FPELIM-NEXT: xor a1, a2, a6
; RV32I-FPELIM-NEXT: or a0, a1, a0
; RV32I-FPELIM-NEXT: or a0, a0, a3
; RV32I-FPELIM-NEXT: lw a6, 4(a0)
; RV32I-FPELIM-NEXT: lw a7, 8(a0)
; RV32I-FPELIM-NEXT: lw a0, 0(a0)
; RV32I-FPELIM-NEXT: xor a1, a5, a1
; RV32I-FPELIM-NEXT: xor a3, a6, a3
; RV32I-FPELIM-NEXT: xor a4, a7, a4
; RV32I-FPELIM-NEXT: xor a0, a0, a2
; RV32I-FPELIM-NEXT: or a1, a3, a1
; RV32I-FPELIM-NEXT: or a0, a0, a4
; RV32I-FPELIM-NEXT: or a0, a0, a1
; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: ret
;
Expand All @@ -214,21 +214,21 @@ define i32 @callee_large_scalars(i128 %a, fp128 %b) nounwind {
; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a2, 0(a0)
; RV32I-WITHFP-NEXT: lw a3, 4(a0)
; RV32I-WITHFP-NEXT: lw a4, 12(a1)
; RV32I-WITHFP-NEXT: lw a2, 0(a1)
; RV32I-WITHFP-NEXT: lw a3, 4(a1)
; RV32I-WITHFP-NEXT: lw a4, 8(a1)
; RV32I-WITHFP-NEXT: lw a1, 12(a1)
; RV32I-WITHFP-NEXT: lw a5, 12(a0)
; RV32I-WITHFP-NEXT: lw a6, 0(a1)
; RV32I-WITHFP-NEXT: lw a7, 4(a1)
; RV32I-WITHFP-NEXT: lw a1, 8(a1)
; RV32I-WITHFP-NEXT: lw a0, 8(a0)
; RV32I-WITHFP-NEXT: xor a4, a5, a4
; RV32I-WITHFP-NEXT: xor a3, a3, a7
; RV32I-WITHFP-NEXT: or a3, a3, a4
; RV32I-WITHFP-NEXT: xor a0, a0, a1
; RV32I-WITHFP-NEXT: xor a1, a2, a6
; RV32I-WITHFP-NEXT: or a0, a1, a0
; RV32I-WITHFP-NEXT: or a0, a0, a3
; RV32I-WITHFP-NEXT: lw a6, 4(a0)
; RV32I-WITHFP-NEXT: lw a7, 8(a0)
; RV32I-WITHFP-NEXT: lw a0, 0(a0)
; RV32I-WITHFP-NEXT: xor a1, a5, a1
; RV32I-WITHFP-NEXT: xor a3, a6, a3
; RV32I-WITHFP-NEXT: xor a4, a7, a4
; RV32I-WITHFP-NEXT: xor a0, a0, a2
; RV32I-WITHFP-NEXT: or a1, a3, a1
; RV32I-WITHFP-NEXT: or a0, a0, a4
; RV32I-WITHFP-NEXT: or a0, a0, a1
; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
Expand All @@ -245,13 +245,13 @@ define i32 @caller_large_scalars() nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -48
; RV32I-FPELIM-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: lui a0, 524272
; RV32I-FPELIM-NEXT: lui a1, 524272
; RV32I-FPELIM-NEXT: li a2, 1
; RV32I-FPELIM-NEXT: addi a0, sp, 24
; RV32I-FPELIM-NEXT: sw zero, 0(sp)
; RV32I-FPELIM-NEXT: sw zero, 4(sp)
; RV32I-FPELIM-NEXT: sw zero, 8(sp)
; RV32I-FPELIM-NEXT: sw a0, 12(sp)
; RV32I-FPELIM-NEXT: li a2, 1
; RV32I-FPELIM-NEXT: addi a0, sp, 24
; RV32I-FPELIM-NEXT: sw a1, 12(sp)
; RV32I-FPELIM-NEXT: mv a1, sp
; RV32I-FPELIM-NEXT: sw a2, 24(sp)
; RV32I-FPELIM-NEXT: sw zero, 28(sp)
Expand All @@ -268,13 +268,13 @@ define i32 @caller_large_scalars() nounwind {
; RV32I-WITHFP-NEXT: sw ra, 44(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 40(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 48
; RV32I-WITHFP-NEXT: lui a0, 524272
; RV32I-WITHFP-NEXT: lui a1, 524272
; RV32I-WITHFP-NEXT: li a2, 1
; RV32I-WITHFP-NEXT: addi a0, s0, -24
; RV32I-WITHFP-NEXT: sw zero, -48(s0)
; RV32I-WITHFP-NEXT: sw zero, -44(s0)
; RV32I-WITHFP-NEXT: sw zero, -40(s0)
; RV32I-WITHFP-NEXT: sw a0, -36(s0)
; RV32I-WITHFP-NEXT: li a2, 1
; RV32I-WITHFP-NEXT: addi a0, s0, -24
; RV32I-WITHFP-NEXT: sw a1, -36(s0)
; RV32I-WITHFP-NEXT: addi a1, s0, -48
; RV32I-WITHFP-NEXT: sw a2, -24(s0)
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
Expand All @@ -299,18 +299,18 @@ define i32 @callee_large_scalars_exhausted_regs(i32 %a, i32 %b, i32 %c, i32 %d,
; RV32I-FPELIM-NEXT: lw a0, 4(sp)
; RV32I-FPELIM-NEXT: lw a1, 0(a7)
; RV32I-FPELIM-NEXT: lw a2, 4(a7)
; RV32I-FPELIM-NEXT: lw a3, 12(a0)
; RV32I-FPELIM-NEXT: lw a3, 8(a7)
; RV32I-FPELIM-NEXT: lw a4, 12(a7)
; RV32I-FPELIM-NEXT: lw a5, 0(a0)
; RV32I-FPELIM-NEXT: lw a5, 12(a0)
; RV32I-FPELIM-NEXT: lw a6, 4(a0)
; RV32I-FPELIM-NEXT: lw a0, 8(a0)
; RV32I-FPELIM-NEXT: lw a7, 8(a7)
; RV32I-FPELIM-NEXT: xor a3, a4, a3
; RV32I-FPELIM-NEXT: lw a7, 8(a0)
; RV32I-FPELIM-NEXT: lw a0, 0(a0)
; RV32I-FPELIM-NEXT: xor a4, a4, a5
; RV32I-FPELIM-NEXT: xor a2, a2, a6
; RV32I-FPELIM-NEXT: or a2, a2, a3
; RV32I-FPELIM-NEXT: xor a0, a7, a0
; RV32I-FPELIM-NEXT: xor a1, a1, a5
; RV32I-FPELIM-NEXT: or a0, a1, a0
; RV32I-FPELIM-NEXT: xor a3, a3, a7
; RV32I-FPELIM-NEXT: xor a0, a1, a0
; RV32I-FPELIM-NEXT: or a2, a2, a4
; RV32I-FPELIM-NEXT: or a0, a0, a3
; RV32I-FPELIM-NEXT: or a0, a0, a2
; RV32I-FPELIM-NEXT: seqz a0, a0
; RV32I-FPELIM-NEXT: ret
Expand All @@ -324,18 +324,18 @@ define i32 @callee_large_scalars_exhausted_regs(i32 %a, i32 %b, i32 %c, i32 %d,
; RV32I-WITHFP-NEXT: lw a0, 4(s0)
; RV32I-WITHFP-NEXT: lw a1, 0(a7)
; RV32I-WITHFP-NEXT: lw a2, 4(a7)
; RV32I-WITHFP-NEXT: lw a3, 12(a0)
; RV32I-WITHFP-NEXT: lw a3, 8(a7)
; RV32I-WITHFP-NEXT: lw a4, 12(a7)
; RV32I-WITHFP-NEXT: lw a5, 0(a0)
; RV32I-WITHFP-NEXT: lw a5, 12(a0)
; RV32I-WITHFP-NEXT: lw a6, 4(a0)
; RV32I-WITHFP-NEXT: lw a0, 8(a0)
; RV32I-WITHFP-NEXT: lw a7, 8(a7)
; RV32I-WITHFP-NEXT: xor a3, a4, a3
; RV32I-WITHFP-NEXT: lw a7, 8(a0)
; RV32I-WITHFP-NEXT: lw a0, 0(a0)
; RV32I-WITHFP-NEXT: xor a4, a4, a5
; RV32I-WITHFP-NEXT: xor a2, a2, a6
; RV32I-WITHFP-NEXT: or a2, a2, a3
; RV32I-WITHFP-NEXT: xor a0, a7, a0
; RV32I-WITHFP-NEXT: xor a1, a1, a5
; RV32I-WITHFP-NEXT: or a0, a1, a0
; RV32I-WITHFP-NEXT: xor a3, a3, a7
; RV32I-WITHFP-NEXT: xor a0, a1, a0
; RV32I-WITHFP-NEXT: or a2, a2, a4
; RV32I-WITHFP-NEXT: or a0, a0, a3
; RV32I-WITHFP-NEXT: or a0, a0, a2
; RV32I-WITHFP-NEXT: seqz a0, a0
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -353,25 +353,25 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -64
; RV32I-FPELIM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: addi a0, sp, 16
; RV32I-FPELIM-NEXT: li a1, 9
; RV32I-FPELIM-NEXT: sw a1, 0(sp)
; RV32I-FPELIM-NEXT: sw a0, 4(sp)
; RV32I-FPELIM-NEXT: lui a0, 524272
; RV32I-FPELIM-NEXT: sw zero, 16(sp)
; RV32I-FPELIM-NEXT: sw zero, 20(sp)
; RV32I-FPELIM-NEXT: sw zero, 24(sp)
; RV32I-FPELIM-NEXT: sw a0, 28(sp)
; RV32I-FPELIM-NEXT: li t0, 8
; RV32I-FPELIM-NEXT: addi a6, sp, 16
; RV32I-FPELIM-NEXT: li a7, 9
; RV32I-FPELIM-NEXT: lui t0, 524272
; RV32I-FPELIM-NEXT: li t1, 8
; RV32I-FPELIM-NEXT: li a0, 1
; RV32I-FPELIM-NEXT: li a1, 2
; RV32I-FPELIM-NEXT: li a2, 3
; RV32I-FPELIM-NEXT: li a3, 4
; RV32I-FPELIM-NEXT: li a4, 5
; RV32I-FPELIM-NEXT: li a5, 6
; RV32I-FPELIM-NEXT: sw a7, 0(sp)
; RV32I-FPELIM-NEXT: sw a6, 4(sp)
; RV32I-FPELIM-NEXT: li a6, 7
; RV32I-FPELIM-NEXT: sw zero, 16(sp)
; RV32I-FPELIM-NEXT: sw zero, 20(sp)
; RV32I-FPELIM-NEXT: sw zero, 24(sp)
; RV32I-FPELIM-NEXT: sw t0, 28(sp)
; RV32I-FPELIM-NEXT: addi a7, sp, 40
; RV32I-FPELIM-NEXT: sw t0, 40(sp)
; RV32I-FPELIM-NEXT: sw t1, 40(sp)
; RV32I-FPELIM-NEXT: sw zero, 44(sp)
; RV32I-FPELIM-NEXT: sw zero, 48(sp)
; RV32I-FPELIM-NEXT: sw zero, 52(sp)
Expand All @@ -386,25 +386,25 @@ define i32 @caller_large_scalars_exhausted_regs() nounwind {
; RV32I-WITHFP-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 64
; RV32I-WITHFP-NEXT: addi a0, s0, -48
; RV32I-WITHFP-NEXT: li a1, 9
; RV32I-WITHFP-NEXT: sw a1, 0(sp)
; RV32I-WITHFP-NEXT: sw a0, 4(sp)
; RV32I-WITHFP-NEXT: lui a0, 524272
; RV32I-WITHFP-NEXT: sw zero, -48(s0)
; RV32I-WITHFP-NEXT: sw zero, -44(s0)
; RV32I-WITHFP-NEXT: sw zero, -40(s0)
; RV32I-WITHFP-NEXT: sw a0, -36(s0)
; RV32I-WITHFP-NEXT: li t0, 8
; RV32I-WITHFP-NEXT: addi a6, s0, -48
; RV32I-WITHFP-NEXT: li a7, 9
; RV32I-WITHFP-NEXT: lui t0, 524272
; RV32I-WITHFP-NEXT: li t1, 8
; RV32I-WITHFP-NEXT: li a0, 1
; RV32I-WITHFP-NEXT: li a1, 2
; RV32I-WITHFP-NEXT: li a2, 3
; RV32I-WITHFP-NEXT: li a3, 4
; RV32I-WITHFP-NEXT: li a4, 5
; RV32I-WITHFP-NEXT: li a5, 6
; RV32I-WITHFP-NEXT: sw a7, 0(sp)
; RV32I-WITHFP-NEXT: sw a6, 4(sp)
; RV32I-WITHFP-NEXT: li a6, 7
; RV32I-WITHFP-NEXT: sw zero, -48(s0)
; RV32I-WITHFP-NEXT: sw zero, -44(s0)
; RV32I-WITHFP-NEXT: sw zero, -40(s0)
; RV32I-WITHFP-NEXT: sw t0, -36(s0)
; RV32I-WITHFP-NEXT: addi a7, s0, -24
; RV32I-WITHFP-NEXT: sw t0, -24(s0)
; RV32I-WITHFP-NEXT: sw t1, -24(s0)
; RV32I-WITHFP-NEXT: sw zero, -20(s0)
; RV32I-WITHFP-NEXT: sw zero, -16(s0)
; RV32I-WITHFP-NEXT: sw zero, -12(s0)
Expand Down Expand Up @@ -664,34 +664,34 @@ define void @caller_aligned_stack() nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -64
; RV32I-FPELIM-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: li a0, 19
; RV32I-FPELIM-NEXT: li a1, 18
; RV32I-FPELIM-NEXT: sw a1, 20(sp)
; RV32I-FPELIM-NEXT: sw a0, 24(sp)
; RV32I-FPELIM-NEXT: li a0, 17
; RV32I-FPELIM-NEXT: li a1, 16
; RV32I-FPELIM-NEXT: li a2, 15
; RV32I-FPELIM-NEXT: sw a2, 0(sp)
; RV32I-FPELIM-NEXT: sw a1, 8(sp)
; RV32I-FPELIM-NEXT: sw zero, 12(sp)
; RV32I-FPELIM-NEXT: sw a0, 16(sp)
; RV32I-FPELIM-NEXT: lui a0, 262153
; RV32I-FPELIM-NEXT: addi t0, a0, 491
; RV32I-FPELIM-NEXT: lui a0, 545260
; RV32I-FPELIM-NEXT: addi t1, a0, -1967
; RV32I-FPELIM-NEXT: lui a0, 964690
; RV32I-FPELIM-NEXT: addi t2, a0, -328
; RV32I-FPELIM-NEXT: lui a0, 335544
; RV32I-FPELIM-NEXT: addi t3, a0, 1311
; RV32I-FPELIM-NEXT: lui a0, 688509
; RV32I-FPELIM-NEXT: addi a5, a0, -2048
; RV32I-FPELIM-NEXT: li a5, 19
; RV32I-FPELIM-NEXT: li a6, 18
; RV32I-FPELIM-NEXT: li a7, 17
; RV32I-FPELIM-NEXT: li t0, 16
; RV32I-FPELIM-NEXT: li t1, 15
; RV32I-FPELIM-NEXT: lui t2, 262153
; RV32I-FPELIM-NEXT: lui t3, 545260
; RV32I-FPELIM-NEXT: lui t4, 964690
; RV32I-FPELIM-NEXT: lui t5, 335544
; RV32I-FPELIM-NEXT: lui t6, 688509
; RV32I-FPELIM-NEXT: li a0, 1
; RV32I-FPELIM-NEXT: li a1, 11
; RV32I-FPELIM-NEXT: addi a2, sp, 32
; RV32I-FPELIM-NEXT: li a3, 12
; RV32I-FPELIM-NEXT: li a4, 13
; RV32I-FPELIM-NEXT: sw a6, 20(sp)
; RV32I-FPELIM-NEXT: sw a5, 24(sp)
; RV32I-FPELIM-NEXT: li a6, 4
; RV32I-FPELIM-NEXT: sw t1, 0(sp)
; RV32I-FPELIM-NEXT: sw t0, 8(sp)
; RV32I-FPELIM-NEXT: sw zero, 12(sp)
; RV32I-FPELIM-NEXT: sw a7, 16(sp)
; RV32I-FPELIM-NEXT: li a7, 14
; RV32I-FPELIM-NEXT: addi t0, t2, 491
; RV32I-FPELIM-NEXT: addi t1, t3, -1967
; RV32I-FPELIM-NEXT: addi t2, t4, -328
; RV32I-FPELIM-NEXT: addi t3, t5, 1311
; RV32I-FPELIM-NEXT: addi a5, t6, -2048
; RV32I-FPELIM-NEXT: sw t3, 32(sp)
; RV32I-FPELIM-NEXT: sw t2, 36(sp)
; RV32I-FPELIM-NEXT: sw t1, 40(sp)
Expand All @@ -707,34 +707,34 @@ define void @caller_aligned_stack() nounwind {
; RV32I-WITHFP-NEXT: sw ra, 60(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 56(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 64
; RV32I-WITHFP-NEXT: li a0, 19
; RV32I-WITHFP-NEXT: li a1, 18
; RV32I-WITHFP-NEXT: sw a1, 20(sp)
; RV32I-WITHFP-NEXT: sw a0, 24(sp)
; RV32I-WITHFP-NEXT: li a0, 17
; RV32I-WITHFP-NEXT: li a1, 16
; RV32I-WITHFP-NEXT: li a2, 15
; RV32I-WITHFP-NEXT: sw a2, 0(sp)
; RV32I-WITHFP-NEXT: sw a1, 8(sp)
; RV32I-WITHFP-NEXT: sw zero, 12(sp)
; RV32I-WITHFP-NEXT: sw a0, 16(sp)
; RV32I-WITHFP-NEXT: lui a0, 262153
; RV32I-WITHFP-NEXT: addi t0, a0, 491
; RV32I-WITHFP-NEXT: lui a0, 545260
; RV32I-WITHFP-NEXT: addi t1, a0, -1967
; RV32I-WITHFP-NEXT: lui a0, 964690
; RV32I-WITHFP-NEXT: addi t2, a0, -328
; RV32I-WITHFP-NEXT: lui a0, 335544
; RV32I-WITHFP-NEXT: addi t3, a0, 1311
; RV32I-WITHFP-NEXT: lui a0, 688509
; RV32I-WITHFP-NEXT: addi a5, a0, -2048
; RV32I-WITHFP-NEXT: li a5, 19
; RV32I-WITHFP-NEXT: li a6, 18
; RV32I-WITHFP-NEXT: li a7, 17
; RV32I-WITHFP-NEXT: li t0, 16
; RV32I-WITHFP-NEXT: li t1, 15
; RV32I-WITHFP-NEXT: lui t2, 262153
; RV32I-WITHFP-NEXT: lui t3, 545260
; RV32I-WITHFP-NEXT: lui t4, 964690
; RV32I-WITHFP-NEXT: lui t5, 335544
; RV32I-WITHFP-NEXT: lui t6, 688509
; RV32I-WITHFP-NEXT: li a0, 1
; RV32I-WITHFP-NEXT: li a1, 11
; RV32I-WITHFP-NEXT: addi a2, s0, -32
; RV32I-WITHFP-NEXT: li a3, 12
; RV32I-WITHFP-NEXT: li a4, 13
; RV32I-WITHFP-NEXT: sw a6, 20(sp)
; RV32I-WITHFP-NEXT: sw a5, 24(sp)
; RV32I-WITHFP-NEXT: li a6, 4
; RV32I-WITHFP-NEXT: sw t1, 0(sp)
; RV32I-WITHFP-NEXT: sw t0, 8(sp)
; RV32I-WITHFP-NEXT: sw zero, 12(sp)
; RV32I-WITHFP-NEXT: sw a7, 16(sp)
; RV32I-WITHFP-NEXT: li a7, 14
; RV32I-WITHFP-NEXT: addi t0, t2, 491
; RV32I-WITHFP-NEXT: addi t1, t3, -1967
; RV32I-WITHFP-NEXT: addi t2, t4, -328
; RV32I-WITHFP-NEXT: addi t3, t5, 1311
; RV32I-WITHFP-NEXT: addi a5, t6, -2048
; RV32I-WITHFP-NEXT: sw t3, -32(s0)
; RV32I-WITHFP-NEXT: sw t2, -28(s0)
; RV32I-WITHFP-NEXT: sw t1, -24(s0)
Expand Down
68 changes: 34 additions & 34 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -97,21 +97,21 @@ define i32 @caller_double_in_gpr_exhausted_fprs() nounwind {
; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_0)
; RV32-ILP32D-NEXT: lui a1, %hi(.LCPI5_1)
; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI5_0)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_1)
; RV32-ILP32D-NEXT: fld fa1, %lo(.LCPI5_1)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_2)
; RV32-ILP32D-NEXT: fld fa1, %lo(.LCPI5_1)(a1)
; RV32-ILP32D-NEXT: lui a1, %hi(.LCPI5_3)
; RV32-ILP32D-NEXT: fld fa2, %lo(.LCPI5_2)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_3)
; RV32-ILP32D-NEXT: fld fa3, %lo(.LCPI5_3)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_4)
; RV32-ILP32D-NEXT: fld fa3, %lo(.LCPI5_3)(a1)
; RV32-ILP32D-NEXT: lui a1, %hi(.LCPI5_5)
; RV32-ILP32D-NEXT: fld fa4, %lo(.LCPI5_4)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_5)
; RV32-ILP32D-NEXT: fld fa5, %lo(.LCPI5_5)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_6)
; RV32-ILP32D-NEXT: fld fa5, %lo(.LCPI5_5)(a1)
; RV32-ILP32D-NEXT: lui a1, %hi(.LCPI5_7)
; RV32-ILP32D-NEXT: fld fa6, %lo(.LCPI5_6)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_7)
; RV32-ILP32D-NEXT: fld fa7, %lo(.LCPI5_7)(a0)
; RV32-ILP32D-NEXT: fld fa7, %lo(.LCPI5_7)(a1)
; RV32-ILP32D-NEXT: lui a1, 262688
; RV32-ILP32D-NEXT: li a0, 0
; RV32-ILP32D-NEXT: call callee_double_in_gpr_exhausted_fprs
Expand Down Expand Up @@ -149,20 +149,20 @@ define i32 @caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs() nounwind
; RV32-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32D-NEXT: lui a1, 262816
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_0)
; RV32-ILP32D-NEXT: lui a2, %hi(.LCPI7_1)
; RV32-ILP32D-NEXT: lui a3, %hi(.LCPI7_2)
; RV32-ILP32D-NEXT: lui a4, %hi(.LCPI7_3)
; RV32-ILP32D-NEXT: lui a5, %hi(.LCPI7_4)
; RV32-ILP32D-NEXT: lui a6, %hi(.LCPI7_5)
; RV32-ILP32D-NEXT: lui a7, %hi(.LCPI7_6)
; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI7_0)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_1)
; RV32-ILP32D-NEXT: fld fa1, %lo(.LCPI7_1)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_2)
; RV32-ILP32D-NEXT: fld fa2, %lo(.LCPI7_2)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_3)
; RV32-ILP32D-NEXT: fld fa3, %lo(.LCPI7_3)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_4)
; RV32-ILP32D-NEXT: fld fa4, %lo(.LCPI7_4)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_5)
; RV32-ILP32D-NEXT: fld fa5, %lo(.LCPI7_5)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_6)
; RV32-ILP32D-NEXT: fld fa6, %lo(.LCPI7_6)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_7)
; RV32-ILP32D-NEXT: fld fa1, %lo(.LCPI7_1)(a2)
; RV32-ILP32D-NEXT: fld fa2, %lo(.LCPI7_2)(a3)
; RV32-ILP32D-NEXT: fld fa3, %lo(.LCPI7_3)(a4)
; RV32-ILP32D-NEXT: fld fa4, %lo(.LCPI7_4)(a5)
; RV32-ILP32D-NEXT: fld fa5, %lo(.LCPI7_5)(a6)
; RV32-ILP32D-NEXT: fld fa6, %lo(.LCPI7_6)(a7)
; RV32-ILP32D-NEXT: fld fa7, %lo(.LCPI7_7)(a0)
; RV32-ILP32D-NEXT: li a0, 1
; RV32-ILP32D-NEXT: li a2, 3
Expand Down Expand Up @@ -205,22 +205,22 @@ define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind {
; RV32-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32D-NEXT: lui a1, 262816
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_0)
; RV32-ILP32D-NEXT: lui a2, %hi(.LCPI9_1)
; RV32-ILP32D-NEXT: lui a3, %hi(.LCPI9_2)
; RV32-ILP32D-NEXT: lui a4, %hi(.LCPI9_3)
; RV32-ILP32D-NEXT: lui a5, %hi(.LCPI9_4)
; RV32-ILP32D-NEXT: lui a6, %hi(.LCPI9_5)
; RV32-ILP32D-NEXT: lui a7, %hi(.LCPI9_6)
; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI9_0)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_1)
; RV32-ILP32D-NEXT: fld fa1, %lo(.LCPI9_1)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_2)
; RV32-ILP32D-NEXT: fld fa2, %lo(.LCPI9_2)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_3)
; RV32-ILP32D-NEXT: fld fa3, %lo(.LCPI9_3)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_4)
; RV32-ILP32D-NEXT: fld fa4, %lo(.LCPI9_4)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_5)
; RV32-ILP32D-NEXT: fld fa5, %lo(.LCPI9_5)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_6)
; RV32-ILP32D-NEXT: fld fa6, %lo(.LCPI9_6)(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_7)
; RV32-ILP32D-NEXT: fld fa7, %lo(.LCPI9_7)(a0)
; RV32-ILP32D-NEXT: lui t0, %hi(.LCPI9_7)
; RV32-ILP32D-NEXT: fld fa1, %lo(.LCPI9_1)(a2)
; RV32-ILP32D-NEXT: li a0, 1
; RV32-ILP32D-NEXT: fld fa2, %lo(.LCPI9_2)(a3)
; RV32-ILP32D-NEXT: fld fa3, %lo(.LCPI9_3)(a4)
; RV32-ILP32D-NEXT: fld fa4, %lo(.LCPI9_4)(a5)
; RV32-ILP32D-NEXT: fld fa5, %lo(.LCPI9_5)(a6)
; RV32-ILP32D-NEXT: fld fa6, %lo(.LCPI9_6)(a7)
; RV32-ILP32D-NEXT: fld fa7, %lo(.LCPI9_7)(t0)
; RV32-ILP32D-NEXT: li a2, 3
; RV32-ILP32D-NEXT: li a4, 5
; RV32-ILP32D-NEXT: li a6, 7
Expand Down
616 changes: 308 additions & 308 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32e.ll
View file

Large diffs are not rendered by default.

48 changes: 24 additions & 24 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -55,11 +55,11 @@ define i32 @caller_float_in_fpr_exhausted_gprs() nounwind {
; RV32-ILP32FD-NEXT: addi sp, sp, -16
; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32FD-NEXT: li a1, 5
; RV32-ILP32FD-NEXT: lui a0, 265216
; RV32-ILP32FD-NEXT: fmv.w.x fa0, a0
; RV32-ILP32FD-NEXT: lui a3, 265216
; RV32-ILP32FD-NEXT: li a0, 1
; RV32-ILP32FD-NEXT: li a2, 2
; RV32-ILP32FD-NEXT: li a4, 3
; RV32-ILP32FD-NEXT: fmv.w.x fa0, a3
; RV32-ILP32FD-NEXT: li a6, 4
; RV32-ILP32FD-NEXT: sw a1, 0(sp)
; RV32-ILP32FD-NEXT: li a1, 0
Expand Down Expand Up @@ -96,21 +96,21 @@ define i32 @caller_float_in_gpr_exhausted_fprs() nounwind {
; RV32-ILP32FD-NEXT: addi sp, sp, -16
; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32FD-NEXT: lui a0, 260096
; RV32-ILP32FD-NEXT: lui a1, 262144
; RV32-ILP32FD-NEXT: fmv.w.x fa0, a0
; RV32-ILP32FD-NEXT: lui a0, 262144
; RV32-ILP32FD-NEXT: fmv.w.x fa1, a0
; RV32-ILP32FD-NEXT: lui a0, 263168
; RV32-ILP32FD-NEXT: fmv.w.x fa1, a1
; RV32-ILP32FD-NEXT: lui a1, 264192
; RV32-ILP32FD-NEXT: fmv.w.x fa2, a0
; RV32-ILP32FD-NEXT: lui a0, 264192
; RV32-ILP32FD-NEXT: fmv.w.x fa3, a0
; RV32-ILP32FD-NEXT: lui a0, 264704
; RV32-ILP32FD-NEXT: fmv.w.x fa3, a1
; RV32-ILP32FD-NEXT: lui a1, 265216
; RV32-ILP32FD-NEXT: fmv.w.x fa4, a0
; RV32-ILP32FD-NEXT: lui a0, 265216
; RV32-ILP32FD-NEXT: fmv.w.x fa5, a0
; RV32-ILP32FD-NEXT: lui a0, 265728
; RV32-ILP32FD-NEXT: fmv.w.x fa5, a1
; RV32-ILP32FD-NEXT: lui a1, 266240
; RV32-ILP32FD-NEXT: fmv.w.x fa6, a0
; RV32-ILP32FD-NEXT: lui a0, 266240
; RV32-ILP32FD-NEXT: fmv.w.x fa7, a0
; RV32-ILP32FD-NEXT: fmv.w.x fa7, a1
; RV32-ILP32FD-NEXT: lui a0, 266496
; RV32-ILP32FD-NEXT: call callee_float_in_gpr_exhausted_fprs
; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -143,24 +143,24 @@ define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind {
; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32FD-NEXT: lui a1, 267520
; RV32-ILP32FD-NEXT: lui a0, 262144
; RV32-ILP32FD-NEXT: lui a2, 264192
; RV32-ILP32FD-NEXT: lui a3, 265216
; RV32-ILP32FD-NEXT: lui a4, 266240
; RV32-ILP32FD-NEXT: lui a5, 266496
; RV32-ILP32FD-NEXT: lui a6, 266752
; RV32-ILP32FD-NEXT: lui a7, 267008
; RV32-ILP32FD-NEXT: fmv.w.x fa0, a0
; RV32-ILP32FD-NEXT: lui a0, 264192
; RV32-ILP32FD-NEXT: fmv.w.x fa1, a0
; RV32-ILP32FD-NEXT: lui a0, 265216
; RV32-ILP32FD-NEXT: fmv.w.x fa2, a0
; RV32-ILP32FD-NEXT: lui a0, 266240
; RV32-ILP32FD-NEXT: fmv.w.x fa3, a0
; RV32-ILP32FD-NEXT: lui a0, 266496
; RV32-ILP32FD-NEXT: fmv.w.x fa4, a0
; RV32-ILP32FD-NEXT: lui a0, 266752
; RV32-ILP32FD-NEXT: fmv.w.x fa5, a0
; RV32-ILP32FD-NEXT: lui a0, 267008
; RV32-ILP32FD-NEXT: fmv.w.x fa6, a0
; RV32-ILP32FD-NEXT: lui a0, 267264
; RV32-ILP32FD-NEXT: fmv.w.x fa7, a0
; RV32-ILP32FD-NEXT: lui t0, 267264
; RV32-ILP32FD-NEXT: fmv.w.x fa1, a2
; RV32-ILP32FD-NEXT: li a0, 1
; RV32-ILP32FD-NEXT: fmv.w.x fa2, a3
; RV32-ILP32FD-NEXT: li a2, 3
; RV32-ILP32FD-NEXT: fmv.w.x fa3, a4
; RV32-ILP32FD-NEXT: li a4, 5
; RV32-ILP32FD-NEXT: fmv.w.x fa4, a5
; RV32-ILP32FD-NEXT: fmv.w.x fa5, a6
; RV32-ILP32FD-NEXT: fmv.w.x fa6, a7
; RV32-ILP32FD-NEXT: fmv.w.x fa7, t0
; RV32-ILP32FD-NEXT: li a6, 7
; RV32-ILP32FD-NEXT: sw a1, 0(sp)
; RV32-ILP32FD-NEXT: li a1, 0
Expand Down
116 changes: 58 additions & 58 deletions llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -52,15 +52,15 @@ define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i128 %d, i32 %e, i32 %f,
; RV64I-NEXT: ld t1, 0(sp)
; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: slli a1, a1, 48
; RV64I-NEXT: xor a3, a3, a7
; RV64I-NEXT: srli a1, a1, 48
; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: xor a1, a4, t1
; RV64I-NEXT: xor a2, a3, a7
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: seqz a1, a1
; RV64I-NEXT: add a0, a0, a5
; RV64I-NEXT: xor a1, a4, t1
; RV64I-NEXT: add a0, a0, a6
; RV64I-NEXT: or a1, a3, a1
; RV64I-NEXT: seqz a1, a1
; RV64I-NEXT: add a0, a0, t0
; RV64I-NEXT: addw a0, a1, a0
; RV64I-NEXT: ret
Expand Down Expand Up @@ -106,21 +106,21 @@ define i32 @caller_many_scalars() nounwind {
define i64 @callee_large_scalars(i256 %a, i256 %b) nounwind {
; RV64I-LABEL: callee_large_scalars:
; RV64I: # %bb.0:
; RV64I-NEXT: ld a2, 0(a0)
; RV64I-NEXT: ld a3, 8(a0)
; RV64I-NEXT: ld a4, 24(a1)
; RV64I-NEXT: ld a2, 0(a1)
; RV64I-NEXT: ld a3, 8(a1)
; RV64I-NEXT: ld a4, 16(a1)
; RV64I-NEXT: ld a1, 24(a1)
; RV64I-NEXT: ld a5, 24(a0)
; RV64I-NEXT: ld a6, 0(a1)
; RV64I-NEXT: ld a7, 8(a1)
; RV64I-NEXT: ld a1, 16(a1)
; RV64I-NEXT: ld a0, 16(a0)
; RV64I-NEXT: xor a4, a5, a4
; RV64I-NEXT: xor a3, a3, a7
; RV64I-NEXT: or a3, a3, a4
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: xor a1, a2, a6
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: ld a6, 8(a0)
; RV64I-NEXT: ld a7, 16(a0)
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: xor a1, a5, a1
; RV64I-NEXT: xor a3, a6, a3
; RV64I-NEXT: xor a4, a7, a4
; RV64I-NEXT: xor a0, a0, a2
; RV64I-NEXT: or a1, a3, a1
; RV64I-NEXT: or a0, a0, a4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
%1 = icmp eq i256 %a, %b
Expand All @@ -133,15 +133,15 @@ define i64 @caller_large_scalars() nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -80
; RV64I-NEXT: sd ra, 72(sp) # 8-byte Folded Spill
; RV64I-NEXT: li a0, 2
; RV64I-NEXT: sd a0, 0(sp)
; RV64I-NEXT: li a2, 2
; RV64I-NEXT: li a3, 1
; RV64I-NEXT: addi a0, sp, 32
; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: sd a2, 0(sp)
; RV64I-NEXT: sd zero, 8(sp)
; RV64I-NEXT: sd zero, 16(sp)
; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: li a2, 1
; RV64I-NEXT: addi a0, sp, 32
; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: sd a2, 32(sp)
; RV64I-NEXT: sd a3, 32(sp)
; RV64I-NEXT: sd zero, 40(sp)
; RV64I-NEXT: sd zero, 48(sp)
; RV64I-NEXT: sd zero, 56(sp)
Expand All @@ -163,18 +163,18 @@ define i64 @callee_large_scalars_exhausted_regs(i64 %a, i64 %b, i64 %c, i64 %d,
; RV64I-NEXT: ld a0, 8(sp)
; RV64I-NEXT: ld a1, 0(a7)
; RV64I-NEXT: ld a2, 8(a7)
; RV64I-NEXT: ld a3, 24(a0)
; RV64I-NEXT: ld a3, 16(a7)
; RV64I-NEXT: ld a4, 24(a7)
; RV64I-NEXT: ld a5, 0(a0)
; RV64I-NEXT: ld a5, 24(a0)
; RV64I-NEXT: ld a6, 8(a0)
; RV64I-NEXT: ld a0, 16(a0)
; RV64I-NEXT: ld a7, 16(a7)
; RV64I-NEXT: xor a3, a4, a3
; RV64I-NEXT: ld a7, 16(a0)
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: xor a4, a4, a5
; RV64I-NEXT: xor a2, a2, a6
; RV64I-NEXT: or a2, a2, a3
; RV64I-NEXT: xor a0, a7, a0
; RV64I-NEXT: xor a1, a1, a5
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: xor a3, a3, a7
; RV64I-NEXT: xor a0, a1, a0
; RV64I-NEXT: or a2, a2, a4
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
Expand All @@ -188,25 +188,25 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -96
; RV64I-NEXT: sd ra, 88(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a0, sp, 16
; RV64I-NEXT: li a1, 9
; RV64I-NEXT: sd a1, 0(sp)
; RV64I-NEXT: sd a0, 8(sp)
; RV64I-NEXT: li a0, 10
; RV64I-NEXT: sd a0, 16(sp)
; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: sd zero, 32(sp)
; RV64I-NEXT: sd zero, 40(sp)
; RV64I-NEXT: li t0, 8
; RV64I-NEXT: addi a7, sp, 16
; RV64I-NEXT: li t0, 9
; RV64I-NEXT: li t1, 10
; RV64I-NEXT: li t2, 8
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: li a1, 2
; RV64I-NEXT: li a2, 3
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 5
; RV64I-NEXT: li a5, 6
; RV64I-NEXT: li a6, 7
; RV64I-NEXT: sd t0, 0(sp)
; RV64I-NEXT: sd a7, 8(sp)
; RV64I-NEXT: addi a7, sp, 48
; RV64I-NEXT: sd t0, 48(sp)
; RV64I-NEXT: sd t1, 16(sp)
; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: sd zero, 32(sp)
; RV64I-NEXT: sd zero, 40(sp)
; RV64I-NEXT: sd t2, 48(sp)
; RV64I-NEXT: sd zero, 56(sp)
; RV64I-NEXT: sd zero, 64(sp)
; RV64I-NEXT: sd zero, 72(sp)
Expand Down Expand Up @@ -356,24 +356,24 @@ define void @caller_aligned_stack() nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -64
; RV64I-NEXT: sd ra, 56(sp) # 8-byte Folded Spill
; RV64I-NEXT: li a0, 12
; RV64I-NEXT: li a1, 11
; RV64I-NEXT: sd a1, 40(sp)
; RV64I-NEXT: sd a0, 48(sp)
; RV64I-NEXT: li a6, 10
; RV64I-NEXT: li t0, 9
; RV64I-NEXT: li t1, 8
; RV64I-NEXT: li a6, 12
; RV64I-NEXT: li a7, 11
; RV64I-NEXT: li t0, 10
; RV64I-NEXT: li t1, 9
; RV64I-NEXT: li t2, 8
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: li a1, 2
; RV64I-NEXT: li a2, 3
; RV64I-NEXT: li a3, 4
; RV64I-NEXT: li a4, 5
; RV64I-NEXT: li a5, 6
; RV64I-NEXT: sd a7, 40(sp)
; RV64I-NEXT: sd a6, 48(sp)
; RV64I-NEXT: li a7, 7
; RV64I-NEXT: sd t1, 0(sp)
; RV64I-NEXT: sd t0, 16(sp)
; RV64I-NEXT: sd t2, 0(sp)
; RV64I-NEXT: sd t1, 16(sp)
; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: sd a6, 32(sp)
; RV64I-NEXT: sd t0, 32(sp)
; RV64I-NEXT: li a6, 0
; RV64I-NEXT: call callee_aligned_stack
; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -480,15 +480,15 @@ define void @callee_large_struct_ret(ptr noalias sret(%struct.large) %agg.result
; RV64I: # %bb.0:
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: li a2, 2
; RV64I-NEXT: li a3, 3
; RV64I-NEXT: li a4, 4
; RV64I-NEXT: sw a1, 0(a0)
; RV64I-NEXT: sw zero, 4(a0)
; RV64I-NEXT: sw a2, 8(a0)
; RV64I-NEXT: sw zero, 12(a0)
; RV64I-NEXT: li a1, 3
; RV64I-NEXT: li a2, 4
; RV64I-NEXT: sw a1, 16(a0)
; RV64I-NEXT: sw a3, 16(a0)
; RV64I-NEXT: sw zero, 20(a0)
; RV64I-NEXT: sw a2, 24(a0)
; RV64I-NEXT: sw a4, 24(a0)
; RV64I-NEXT: sw zero, 28(a0)
; RV64I-NEXT: ret
store i64 1, ptr %agg.result, align 4
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/cmov-branch-opt.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -87,25 +87,25 @@ define signext i32 @test3(i32 signext %v, i32 signext %w, i32 signext %x, i32 si
; NOCMOV-NEXT: seqz a4, a4
; NOCMOV-NEXT: addi a4, a4, -1
; NOCMOV-NEXT: and a1, a1, a4
; NOCMOV-NEXT: xor a0, a0, a1
; NOCMOV-NEXT: and a3, a3, a4
; NOCMOV-NEXT: xor a0, a0, a1
; NOCMOV-NEXT: xor a2, a2, a3
; NOCMOV-NEXT: addw a0, a0, a2
; NOCMOV-NEXT: ret
;
; CMOV-LABEL: test3:
; CMOV: # %bb.0:
; CMOV-NEXT: xor a1, a1, a0
; CMOV-NEXT: xor a3, a3, a2
; CMOV-NEXT: bnez a4, .LBB2_2
; CMOV-NEXT: # %bb.1:
; CMOV-NEXT: mv a1, a0
; CMOV-NEXT: .LBB2_2:
; CMOV-NEXT: xor a0, a2, a3
; CMOV-NEXT: bnez a4, .LBB2_4
; CMOV-NEXT: # %bb.3:
; CMOV-NEXT: mv a0, a2
; CMOV-NEXT: mv a3, a2
; CMOV-NEXT: .LBB2_4:
; CMOV-NEXT: addw a0, a0, a1
; CMOV-NEXT: addw a0, a1, a3
; CMOV-NEXT: ret
;
; SHORT_FORWARD-LABEL: test3:
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/compress.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -32,9 +32,9 @@
define i32 @simple_arith(i32 %a, i32 %b) #0 {
; RV32IC-LABEL: <simple_arith>:
; RV32IC: addi a2, a0, 0x1
; RV32IC-NEXT: c.srai a1, 0x9
; RV32IC-NEXT: c.andi a2, 0xb
; RV32IC-NEXT: c.slli a2, 0x7
; RV32IC-NEXT: c.srai a1, 0x9
; RV32IC-NEXT: sub a0, a1, a0
; RV32IC-NEXT: c.add a0, a2
; RV32IC-NEXT: c.jr ra
Expand Down
80 changes: 40 additions & 40 deletions llvm/test/CodeGen/RISCV/condbinops.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -453,19 +453,19 @@ define i64 @shl64(i64 %x, i64 %y, i1 %c) {
; RV32ZICOND-LABEL: shl64:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: andi a4, a4, 1
; RV32ZICOND-NEXT: srli a3, a0, 1
; RV32ZICOND-NEXT: czero.eqz a2, a2, a4
; RV32ZICOND-NEXT: sll a3, a0, a2
; RV32ZICOND-NEXT: sll a0, a0, a2
; RV32ZICOND-NEXT: addi a4, a2, -32
; RV32ZICOND-NEXT: slti a4, a4, 0
; RV32ZICOND-NEXT: czero.nez a5, a3, a4
; RV32ZICOND-NEXT: sll a1, a1, a2
; RV32ZICOND-NEXT: not a2, a2
; RV32ZICOND-NEXT: srli a0, a0, 1
; RV32ZICOND-NEXT: srl a0, a0, a2
; RV32ZICOND-NEXT: or a0, a1, a0
; RV32ZICOND-NEXT: czero.eqz a1, a0, a4
; RV32ZICOND-NEXT: or a1, a1, a5
; RV32ZICOND-NEXT: czero.eqz a0, a3, a4
; RV32ZICOND-NEXT: slti a4, a4, 0
; RV32ZICOND-NEXT: srl a2, a3, a2
; RV32ZICOND-NEXT: czero.nez a3, a0, a4
; RV32ZICOND-NEXT: or a1, a1, a2
; RV32ZICOND-NEXT: czero.eqz a1, a1, a4
; RV32ZICOND-NEXT: or a1, a1, a3
; RV32ZICOND-NEXT: czero.eqz a0, a0, a4
; RV32ZICOND-NEXT: ret
;
; RV64ZICOND-LABEL: shl64:
Expand Down Expand Up @@ -527,22 +527,22 @@ define i64 @ashr64(i64 %x, i64 %y, i1 %c) {
; RV32ZICOND-LABEL: ashr64:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: andi a4, a4, 1
; RV32ZICOND-NEXT: slli a3, a1, 1
; RV32ZICOND-NEXT: srai a5, a1, 31
; RV32ZICOND-NEXT: czero.eqz a2, a2, a4
; RV32ZICOND-NEXT: sra a3, a1, a2
; RV32ZICOND-NEXT: sra a1, a1, a2
; RV32ZICOND-NEXT: addi a4, a2, -32
; RV32ZICOND-NEXT: slti a4, a4, 0
; RV32ZICOND-NEXT: czero.nez a5, a3, a4
; RV32ZICOND-NEXT: srl a0, a0, a2
; RV32ZICOND-NEXT: not a2, a2
; RV32ZICOND-NEXT: slli a6, a1, 1
; RV32ZICOND-NEXT: sll a2, a6, a2
; RV32ZICOND-NEXT: slti a4, a4, 0
; RV32ZICOND-NEXT: sll a2, a3, a2
; RV32ZICOND-NEXT: czero.nez a3, a1, a4
; RV32ZICOND-NEXT: or a0, a0, a2
; RV32ZICOND-NEXT: czero.eqz a1, a1, a4
; RV32ZICOND-NEXT: czero.nez a2, a5, a4
; RV32ZICOND-NEXT: czero.eqz a0, a0, a4
; RV32ZICOND-NEXT: or a0, a0, a5
; RV32ZICOND-NEXT: czero.eqz a2, a3, a4
; RV32ZICOND-NEXT: srai a1, a1, 31
; RV32ZICOND-NEXT: czero.nez a1, a1, a4
; RV32ZICOND-NEXT: or a1, a2, a1
; RV32ZICOND-NEXT: or a0, a0, a3
; RV32ZICOND-NEXT: or a1, a1, a2
; RV32ZICOND-NEXT: ret
;
; RV64ZICOND-LABEL: ashr64:
Expand Down Expand Up @@ -604,19 +604,19 @@ define i64 @lshr64(i64 %x, i64 %y, i1 %c) {
; RV32ZICOND-LABEL: lshr64:
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: andi a4, a4, 1
; RV32ZICOND-NEXT: slli a3, a1, 1
; RV32ZICOND-NEXT: czero.eqz a2, a2, a4
; RV32ZICOND-NEXT: srl a3, a1, a2
; RV32ZICOND-NEXT: srl a1, a1, a2
; RV32ZICOND-NEXT: addi a4, a2, -32
; RV32ZICOND-NEXT: slti a4, a4, 0
; RV32ZICOND-NEXT: czero.nez a5, a3, a4
; RV32ZICOND-NEXT: srl a0, a0, a2
; RV32ZICOND-NEXT: not a2, a2
; RV32ZICOND-NEXT: slli a1, a1, 1
; RV32ZICOND-NEXT: sll a1, a1, a2
; RV32ZICOND-NEXT: or a0, a0, a1
; RV32ZICOND-NEXT: slti a4, a4, 0
; RV32ZICOND-NEXT: sll a2, a3, a2
; RV32ZICOND-NEXT: czero.nez a3, a1, a4
; RV32ZICOND-NEXT: or a0, a0, a2
; RV32ZICOND-NEXT: czero.eqz a0, a0, a4
; RV32ZICOND-NEXT: or a0, a0, a5
; RV32ZICOND-NEXT: czero.eqz a1, a3, a4
; RV32ZICOND-NEXT: or a0, a0, a3
; RV32ZICOND-NEXT: czero.eqz a1, a1, a4
; RV32ZICOND-NEXT: ret
;
; RV64ZICOND-LABEL: lshr64:
Expand All @@ -636,10 +636,10 @@ define i64 @sub64(i64 %x, i64 %y, i1 %c) {
; RV32I-NEXT: slli a4, a4, 31
; RV32I-NEXT: srai a4, a4, 31
; RV32I-NEXT: and a2, a4, a2
; RV32I-NEXT: sltu a5, a0, a2
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: sltu a4, a0, a2
; RV32I-NEXT: sub a1, a1, a3
; RV32I-NEXT: sub a1, a1, a5
; RV32I-NEXT: sub a1, a1, a4
; RV32I-NEXT: sub a0, a0, a2
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -669,10 +669,10 @@ define i64 @sub64(i64 %x, i64 %y, i1 %c) {
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: andi a4, a4, 1
; RV32ZICOND-NEXT: czero.eqz a2, a2, a4
; RV32ZICOND-NEXT: sltu a5, a0, a2
; RV32ZICOND-NEXT: czero.eqz a3, a3, a4
; RV32ZICOND-NEXT: sltu a4, a0, a2
; RV32ZICOND-NEXT: sub a1, a1, a3
; RV32ZICOND-NEXT: sub a1, a1, a5
; RV32ZICOND-NEXT: sub a1, a1, a4
; RV32ZICOND-NEXT: sub a0, a0, a2
; RV32ZICOND-NEXT: ret
;
Expand Down Expand Up @@ -728,8 +728,8 @@ define i64 @and64(i64 %x, i64 %y, i1 %c) {
; RV32ZICOND-NEXT: and a3, a1, a3
; RV32ZICOND-NEXT: and a2, a0, a2
; RV32ZICOND-NEXT: czero.nez a0, a0, a4
; RV32ZICOND-NEXT: or a0, a2, a0
; RV32ZICOND-NEXT: czero.nez a1, a1, a4
; RV32ZICOND-NEXT: or a0, a2, a0
; RV32ZICOND-NEXT: or a1, a3, a1
; RV32ZICOND-NEXT: ret
;
Expand All @@ -752,8 +752,8 @@ define i64 @add64(i64 %x, i64 %y, i1 %c) {
; RV32I-NEXT: slli a4, a4, 31
; RV32I-NEXT: srai a4, a4, 31
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: add a1, a1, a3
; RV32I-NEXT: and a2, a4, a2
; RV32I-NEXT: add a1, a1, a3
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
Expand Down Expand Up @@ -786,8 +786,8 @@ define i64 @add64(i64 %x, i64 %y, i1 %c) {
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: andi a4, a4, 1
; RV32ZICOND-NEXT: czero.eqz a3, a3, a4
; RV32ZICOND-NEXT: add a1, a1, a3
; RV32ZICOND-NEXT: czero.eqz a2, a2, a4
; RV32ZICOND-NEXT: add a1, a1, a3
; RV32ZICOND-NEXT: add a2, a0, a2
; RV32ZICOND-NEXT: sltu a0, a2, a0
; RV32ZICOND-NEXT: add a1, a1, a0
Expand All @@ -812,8 +812,8 @@ define i64 @or64(i64 %x, i64 %y, i1 %c) {
; RV32I-NEXT: slli a4, a4, 31
; RV32I-NEXT: srai a4, a4, 31
; RV32I-NEXT: and a2, a4, a2
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: or a0, a0, a2
; RV32I-NEXT: or a1, a1, a3
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -843,9 +843,9 @@ define i64 @or64(i64 %x, i64 %y, i1 %c) {
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: andi a4, a4, 1
; RV32ZICOND-NEXT: czero.eqz a2, a2, a4
; RV32ZICOND-NEXT: czero.eqz a3, a3, a4
; RV32ZICOND-NEXT: or a0, a0, a2
; RV32ZICOND-NEXT: czero.eqz a2, a3, a4
; RV32ZICOND-NEXT: or a1, a1, a2
; RV32ZICOND-NEXT: or a1, a1, a3
; RV32ZICOND-NEXT: ret
;
; RV64ZICOND-LABEL: or64:
Expand All @@ -865,8 +865,8 @@ define i64 @xor64(i64 %x, i64 %y, i1 %c) {
; RV32I-NEXT: slli a4, a4, 31
; RV32I-NEXT: srai a4, a4, 31
; RV32I-NEXT: and a2, a4, a2
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: and a3, a4, a3
; RV32I-NEXT: xor a0, a0, a2
; RV32I-NEXT: xor a1, a1, a3
; RV32I-NEXT: ret
;
Expand Down Expand Up @@ -896,9 +896,9 @@ define i64 @xor64(i64 %x, i64 %y, i1 %c) {
; RV32ZICOND: # %bb.0:
; RV32ZICOND-NEXT: andi a4, a4, 1
; RV32ZICOND-NEXT: czero.eqz a2, a2, a4
; RV32ZICOND-NEXT: czero.eqz a3, a3, a4
; RV32ZICOND-NEXT: xor a0, a0, a2
; RV32ZICOND-NEXT: czero.eqz a2, a3, a4
; RV32ZICOND-NEXT: xor a1, a1, a2
; RV32ZICOND-NEXT: xor a1, a1, a3
; RV32ZICOND-NEXT: ret
;
; RV64ZICOND-LABEL: xor64:
Expand Down
946 changes: 460 additions & 486 deletions llvm/test/CodeGen/RISCV/condops.ll
View file

Large diffs are not rendered by default.

96 changes: 48 additions & 48 deletions llvm/test/CodeGen/RISCV/copysign-casts.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -45,18 +45,18 @@ define double @fold_promote_d_s(double %a, float %b) nounwind {
; RV32I-LABEL: fold_promote_d_s:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a3, 524288
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: fold_promote_d_s:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 524288
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
Expand All @@ -65,8 +65,8 @@ define double @fold_promote_d_s(double %a, float %b) nounwind {
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.x.w a2, fa0
; RV32IF-NEXT: lui a3, 524288
; RV32IF-NEXT: and a2, a2, a3
; RV32IF-NEXT: slli a1, a1, 1
; RV32IF-NEXT: and a2, a2, a3
; RV32IF-NEXT: srli a1, a1, 1
; RV32IF-NEXT: or a1, a1, a2
; RV32IF-NEXT: ret
Expand All @@ -87,8 +87,8 @@ define double @fold_promote_d_s(double %a, float %b) nounwind {
; RV32IFZFH: # %bb.0:
; RV32IFZFH-NEXT: fmv.x.w a2, fa0
; RV32IFZFH-NEXT: lui a3, 524288
; RV32IFZFH-NEXT: and a2, a2, a3
; RV32IFZFH-NEXT: slli a1, a1, 1
; RV32IFZFH-NEXT: and a2, a2, a3
; RV32IFZFH-NEXT: srli a1, a1, 1
; RV32IFZFH-NEXT: or a1, a1, a2
; RV32IFZFH-NEXT: ret
Expand All @@ -109,8 +109,8 @@ define double @fold_promote_d_s(double %a, float %b) nounwind {
; RV32IFZFHMIN: # %bb.0:
; RV32IFZFHMIN-NEXT: fmv.x.w a2, fa0
; RV32IFZFHMIN-NEXT: lui a3, 524288
; RV32IFZFHMIN-NEXT: and a2, a2, a3
; RV32IFZFHMIN-NEXT: slli a1, a1, 1
; RV32IFZFHMIN-NEXT: and a2, a2, a3
; RV32IFZFHMIN-NEXT: srli a1, a1, 1
; RV32IFZFHMIN-NEXT: or a1, a1, a2
; RV32IFZFHMIN-NEXT: ret
Expand Down Expand Up @@ -147,19 +147,19 @@ define double @fold_promote_d_h(double %a, half %b) nounwind {
; RV32I-LABEL: fold_promote_d_h:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a3, 8
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: slli a2, a2, 16
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: fold_promote_d_h:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 8
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slli a1, a1, 48
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
Expand All @@ -168,9 +168,9 @@ define double @fold_promote_d_h(double %a, half %b) nounwind {
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.x.w a2, fa0
; RV32IF-NEXT: lui a3, 8
; RV32IF-NEXT: slli a1, a1, 1
; RV32IF-NEXT: and a2, a2, a3
; RV32IF-NEXT: slli a2, a2, 16
; RV32IF-NEXT: slli a1, a1, 1
; RV32IF-NEXT: srli a1, a1, 1
; RV32IF-NEXT: or a1, a1, a2
; RV32IF-NEXT: ret
Expand Down Expand Up @@ -209,9 +209,9 @@ define double @fold_promote_d_h(double %a, half %b) nounwind {
; RV32IFZFH: # %bb.0:
; RV32IFZFH-NEXT: fmv.x.h a2, fa0
; RV32IFZFH-NEXT: lui a3, 8
; RV32IFZFH-NEXT: slli a1, a1, 1
; RV32IFZFH-NEXT: and a2, a2, a3
; RV32IFZFH-NEXT: slli a2, a2, 16
; RV32IFZFH-NEXT: slli a1, a1, 1
; RV32IFZFH-NEXT: srli a1, a1, 1
; RV32IFZFH-NEXT: or a1, a1, a2
; RV32IFZFH-NEXT: ret
Expand All @@ -232,9 +232,9 @@ define double @fold_promote_d_h(double %a, half %b) nounwind {
; RV32IFZFHMIN: # %bb.0:
; RV32IFZFHMIN-NEXT: fmv.x.h a2, fa0
; RV32IFZFHMIN-NEXT: lui a3, 8
; RV32IFZFHMIN-NEXT: slli a1, a1, 1
; RV32IFZFHMIN-NEXT: and a2, a2, a3
; RV32IFZFHMIN-NEXT: slli a2, a2, 16
; RV32IFZFHMIN-NEXT: slli a1, a1, 1
; RV32IFZFHMIN-NEXT: srli a1, a1, 1
; RV32IFZFHMIN-NEXT: or a1, a1, a2
; RV32IFZFHMIN-NEXT: ret
Expand Down Expand Up @@ -292,19 +292,19 @@ define float @fold_promote_f_h(float %a, half %b) nounwind {
; RV32I-LABEL: fold_promote_f_h:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 8
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: slli a1, a1, 16
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fold_promote_f_h:
; RV64I: # %bb.0:
; RV64I-NEXT: lui a2, 8
; RV64I-NEXT: slli a0, a0, 33
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: slliw a1, a1, 16
; RV64I-NEXT: slli a0, a0, 33
; RV64I-NEXT: srli a0, a0, 33
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
Expand Down Expand Up @@ -423,17 +423,17 @@ define float @fold_demote_s_d(float %a, double %b) nounwind {
; RV32I-LABEL: fold_demote_s_d:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: slli a0, a0, 1
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: srli a0, a0, 1
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fold_demote_s_d:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 33
; RV64I-NEXT: srli a0, a0, 33
; RV64I-NEXT: srli a1, a1, 63
; RV64I-NEXT: srli a0, a0, 33
; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: or a0, a0, a1
Expand Down Expand Up @@ -515,18 +515,18 @@ define half @fold_demote_h_s(half %a, float %b) nounwind {
; RV32I-LABEL: fold_demote_h_s:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: slli a0, a0, 17
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a1, a1, 16
; RV32I-NEXT: slli a0, a0, 17
; RV32I-NEXT: srli a0, a0, 17
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fold_demote_h_s:
; RV64I: # %bb.0:
; RV64I-NEXT: srliw a1, a1, 31
; RV64I-NEXT: slli a1, a1, 15
; RV64I-NEXT: slli a0, a0, 49
; RV64I-NEXT: slli a1, a1, 15
; RV64I-NEXT: srli a0, a0, 49
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
Expand All @@ -537,8 +537,8 @@ define half @fold_demote_h_s(half %a, float %b) nounwind {
; RV32IF-NEXT: fmv.x.w a1, fa1
; RV32IF-NEXT: lui a2, 524288
; RV32IF-NEXT: and a1, a1, a2
; RV32IF-NEXT: srli a1, a1, 16
; RV32IF-NEXT: slli a0, a0, 17
; RV32IF-NEXT: srli a1, a1, 16
; RV32IF-NEXT: srli a0, a0, 17
; RV32IF-NEXT: or a0, a0, a1
; RV32IF-NEXT: lui a1, 1048560
Expand All @@ -552,8 +552,8 @@ define half @fold_demote_h_s(half %a, float %b) nounwind {
; RV32IFD-NEXT: fmv.x.w a1, fa1
; RV32IFD-NEXT: lui a2, 524288
; RV32IFD-NEXT: and a1, a1, a2
; RV32IFD-NEXT: srli a1, a1, 16
; RV32IFD-NEXT: slli a0, a0, 17
; RV32IFD-NEXT: srli a1, a1, 16
; RV32IFD-NEXT: srli a0, a0, 17
; RV32IFD-NEXT: or a0, a0, a1
; RV32IFD-NEXT: lui a1, 1048560
Expand All @@ -567,8 +567,8 @@ define half @fold_demote_h_s(half %a, float %b) nounwind {
; RV64IFD-NEXT: fmv.x.w a1, fa1
; RV64IFD-NEXT: lui a2, 524288
; RV64IFD-NEXT: and a1, a1, a2
; RV64IFD-NEXT: srli a1, a1, 16
; RV64IFD-NEXT: slli a0, a0, 49
; RV64IFD-NEXT: srli a1, a1, 16
; RV64IFD-NEXT: srli a0, a0, 49
; RV64IFD-NEXT: or a0, a0, a1
; RV64IFD-NEXT: lui a1, 1048560
Expand Down Expand Up @@ -597,10 +597,10 @@ define half @fold_demote_h_s(half %a, float %b) nounwind {
; RV32IFZFHMIN-LABEL: fold_demote_h_s:
; RV32IFZFHMIN: # %bb.0:
; RV32IFZFHMIN-NEXT: fmv.x.w a0, fa1
; RV32IFZFHMIN-NEXT: srli a0, a0, 31
; RV32IFZFHMIN-NEXT: slli a0, a0, 15
; RV32IFZFHMIN-NEXT: fmv.x.h a1, fa0
; RV32IFZFHMIN-NEXT: srli a0, a0, 31
; RV32IFZFHMIN-NEXT: slli a1, a1, 17
; RV32IFZFHMIN-NEXT: slli a0, a0, 15
; RV32IFZFHMIN-NEXT: srli a1, a1, 17
; RV32IFZFHMIN-NEXT: or a0, a1, a0
; RV32IFZFHMIN-NEXT: fmv.h.x fa0, a0
Expand All @@ -609,10 +609,10 @@ define half @fold_demote_h_s(half %a, float %b) nounwind {
; RV32IFDZFHMIN-LABEL: fold_demote_h_s:
; RV32IFDZFHMIN: # %bb.0:
; RV32IFDZFHMIN-NEXT: fmv.x.w a0, fa1
; RV32IFDZFHMIN-NEXT: srli a0, a0, 31
; RV32IFDZFHMIN-NEXT: slli a0, a0, 15
; RV32IFDZFHMIN-NEXT: fmv.x.h a1, fa0
; RV32IFDZFHMIN-NEXT: srli a0, a0, 31
; RV32IFDZFHMIN-NEXT: slli a1, a1, 17
; RV32IFDZFHMIN-NEXT: slli a0, a0, 15
; RV32IFDZFHMIN-NEXT: srli a1, a1, 17
; RV32IFDZFHMIN-NEXT: or a0, a1, a0
; RV32IFDZFHMIN-NEXT: fmv.h.x fa0, a0
Expand All @@ -621,10 +621,10 @@ define half @fold_demote_h_s(half %a, float %b) nounwind {
; RV64IFDZFHMIN-LABEL: fold_demote_h_s:
; RV64IFDZFHMIN: # %bb.0:
; RV64IFDZFHMIN-NEXT: fmv.x.w a0, fa1
; RV64IFDZFHMIN-NEXT: srli a0, a0, 31
; RV64IFDZFHMIN-NEXT: slli a0, a0, 15
; RV64IFDZFHMIN-NEXT: fmv.x.h a1, fa0
; RV64IFDZFHMIN-NEXT: srli a0, a0, 31
; RV64IFDZFHMIN-NEXT: slli a1, a1, 49
; RV64IFDZFHMIN-NEXT: slli a0, a0, 15
; RV64IFDZFHMIN-NEXT: srli a1, a1, 49
; RV64IFDZFHMIN-NEXT: or a0, a1, a0
; RV64IFDZFHMIN-NEXT: fmv.h.x fa0, a0
Expand All @@ -635,11 +635,11 @@ define half @fold_demote_h_s(half %a, float %b) nounwind {
; RV32IZDINX-NEXT: # kill: def $x11_w killed $x11_w def $x11
; RV32IZDINX-NEXT: # kill: def $x10_w killed $x10_w def $x10
; RV32IZDINX-NEXT: lui a2, 524288
; RV32IZDINX-NEXT: and a1, a1, a2
; RV32IZDINX-NEXT: srli a1, a1, 16
; RV32IZDINX-NEXT: slli a0, a0, 17
; RV32IZDINX-NEXT: srli a0, a0, 17
; RV32IZDINX-NEXT: and a1, a1, a2
; RV32IZDINX-NEXT: lui a2, 1048560
; RV32IZDINX-NEXT: srli a0, a0, 17
; RV32IZDINX-NEXT: srli a1, a1, 16
; RV32IZDINX-NEXT: or a0, a0, a2
; RV32IZDINX-NEXT: or a0, a0, a1
; RV32IZDINX-NEXT: # kill: def $x10_w killed $x10_w killed $x10
Expand All @@ -650,11 +650,11 @@ define half @fold_demote_h_s(half %a, float %b) nounwind {
; RV64IZDINX-NEXT: # kill: def $x11_w killed $x11_w def $x11
; RV64IZDINX-NEXT: # kill: def $x10_w killed $x10_w def $x10
; RV64IZDINX-NEXT: lui a2, 524288
; RV64IZDINX-NEXT: and a1, a1, a2
; RV64IZDINX-NEXT: srli a1, a1, 16
; RV64IZDINX-NEXT: slli a0, a0, 49
; RV64IZDINX-NEXT: srli a0, a0, 49
; RV64IZDINX-NEXT: and a1, a1, a2
; RV64IZDINX-NEXT: lui a2, 1048560
; RV64IZDINX-NEXT: srli a0, a0, 49
; RV64IZDINX-NEXT: srli a1, a1, 16
; RV64IZDINX-NEXT: or a0, a0, a2
; RV64IZDINX-NEXT: or a0, a0, a1
; RV64IZDINX-NEXT: # kill: def $x10_w killed $x10_w killed $x10
Expand All @@ -668,18 +668,18 @@ define half @fold_demote_h_d(half %a, double %b) nounwind {
; RV32I-LABEL: fold_demote_h_d:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 524288
; RV32I-NEXT: slli a0, a0, 17
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: srli a1, a1, 16
; RV32I-NEXT: slli a0, a0, 17
; RV32I-NEXT: srli a0, a0, 17
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: fold_demote_h_d:
; RV64I: # %bb.0:
; RV64I-NEXT: slli a0, a0, 49
; RV64I-NEXT: srli a0, a0, 49
; RV64I-NEXT: srli a1, a1, 63
; RV64I-NEXT: srli a0, a0, 49
; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: srli a1, a1, 48
; RV64I-NEXT: or a0, a0, a1
Expand All @@ -690,8 +690,8 @@ define half @fold_demote_h_d(half %a, double %b) nounwind {
; RV32IF-NEXT: fmv.x.w a0, fa0
; RV32IF-NEXT: lui a2, 524288
; RV32IF-NEXT: and a1, a1, a2
; RV32IF-NEXT: srli a1, a1, 16
; RV32IF-NEXT: slli a0, a0, 17
; RV32IF-NEXT: srli a1, a1, 16
; RV32IF-NEXT: srli a0, a0, 17
; RV32IF-NEXT: or a0, a0, a1
; RV32IF-NEXT: lui a1, 1048560
Expand All @@ -707,10 +707,10 @@ define half @fold_demote_h_d(half %a, double %b) nounwind {
; RV32IFD-NEXT: fmv.x.w a1, fa0
; RV32IFD-NEXT: lui a2, 524288
; RV32IFD-NEXT: and a0, a0, a2
; RV32IFD-NEXT: srli a0, a0, 16
; RV32IFD-NEXT: lui a2, 1048560
; RV32IFD-NEXT: slli a1, a1, 17
; RV32IFD-NEXT: srli a1, a1, 17
; RV32IFD-NEXT: lui a2, 1048560
; RV32IFD-NEXT: srli a0, a0, 16
; RV32IFD-NEXT: or a1, a1, a2
; RV32IFD-NEXT: or a0, a1, a0
; RV32IFD-NEXT: fmv.w.x fa0, a0
Expand All @@ -721,12 +721,12 @@ define half @fold_demote_h_d(half %a, double %b) nounwind {
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.x.d a0, fa1
; RV64IFD-NEXT: fmv.x.w a1, fa0
; RV64IFD-NEXT: lui a2, 1048560
; RV64IFD-NEXT: slli a1, a1, 49
; RV64IFD-NEXT: srli a1, a1, 49
; RV64IFD-NEXT: srli a0, a0, 63
; RV64IFD-NEXT: srli a1, a1, 49
; RV64IFD-NEXT: slli a0, a0, 63
; RV64IFD-NEXT: srli a0, a0, 48
; RV64IFD-NEXT: lui a2, 1048560
; RV64IFD-NEXT: or a1, a1, a2
; RV64IFD-NEXT: or a0, a1, a0
; RV64IFD-NEXT: fmv.w.x fa0, a0
Expand Down Expand Up @@ -754,8 +754,8 @@ define half @fold_demote_h_d(half %a, double %b) nounwind {
; RV32IFZFHMIN-LABEL: fold_demote_h_d:
; RV32IFZFHMIN: # %bb.0:
; RV32IFZFHMIN-NEXT: srli a1, a1, 31
; RV32IFZFHMIN-NEXT: slli a1, a1, 15
; RV32IFZFHMIN-NEXT: fmv.x.h a0, fa0
; RV32IFZFHMIN-NEXT: slli a1, a1, 15
; RV32IFZFHMIN-NEXT: slli a0, a0, 17
; RV32IFZFHMIN-NEXT: srli a0, a0, 17
; RV32IFZFHMIN-NEXT: or a0, a0, a1
Expand All @@ -767,10 +767,10 @@ define half @fold_demote_h_d(half %a, double %b) nounwind {
; RV32IFDZFHMIN-NEXT: addi sp, sp, -16
; RV32IFDZFHMIN-NEXT: fsd fa1, 8(sp)
; RV32IFDZFHMIN-NEXT: lw a0, 12(sp)
; RV32IFDZFHMIN-NEXT: srli a0, a0, 31
; RV32IFDZFHMIN-NEXT: slli a0, a0, 15
; RV32IFDZFHMIN-NEXT: fmv.x.h a1, fa0
; RV32IFDZFHMIN-NEXT: slli a1, a1, 17
; RV32IFDZFHMIN-NEXT: srli a0, a0, 31
; RV32IFDZFHMIN-NEXT: slli a0, a0, 15
; RV32IFDZFHMIN-NEXT: srli a1, a1, 17
; RV32IFDZFHMIN-NEXT: or a0, a1, a0
; RV32IFDZFHMIN-NEXT: fmv.h.x fa0, a0
Expand All @@ -780,10 +780,10 @@ define half @fold_demote_h_d(half %a, double %b) nounwind {
; RV64IFDZFHMIN-LABEL: fold_demote_h_d:
; RV64IFDZFHMIN: # %bb.0:
; RV64IFDZFHMIN-NEXT: fmv.x.d a0, fa1
; RV64IFDZFHMIN-NEXT: srli a0, a0, 63
; RV64IFDZFHMIN-NEXT: slli a0, a0, 15
; RV64IFDZFHMIN-NEXT: fmv.x.h a1, fa0
; RV64IFDZFHMIN-NEXT: srli a0, a0, 63
; RV64IFDZFHMIN-NEXT: slli a1, a1, 49
; RV64IFDZFHMIN-NEXT: slli a0, a0, 15
; RV64IFDZFHMIN-NEXT: srli a1, a1, 49
; RV64IFDZFHMIN-NEXT: or a0, a1, a0
; RV64IFDZFHMIN-NEXT: fmv.h.x fa0, a0
Expand All @@ -793,11 +793,11 @@ define half @fold_demote_h_d(half %a, double %b) nounwind {
; RV32IZDINX: # %bb.0:
; RV32IZDINX-NEXT: # kill: def $x10_w killed $x10_w def $x10
; RV32IZDINX-NEXT: lui a1, 524288
; RV32IZDINX-NEXT: and a1, a2, a1
; RV32IZDINX-NEXT: srli a1, a1, 16
; RV32IZDINX-NEXT: slli a0, a0, 17
; RV32IZDINX-NEXT: srli a0, a0, 17
; RV32IZDINX-NEXT: and a1, a2, a1
; RV32IZDINX-NEXT: lui a2, 1048560
; RV32IZDINX-NEXT: srli a0, a0, 17
; RV32IZDINX-NEXT: srli a1, a1, 16
; RV32IZDINX-NEXT: or a0, a0, a2
; RV32IZDINX-NEXT: or a0, a0, a1
; RV32IZDINX-NEXT: # kill: def $x10_w killed $x10_w killed $x10
Expand All @@ -807,11 +807,11 @@ define half @fold_demote_h_d(half %a, double %b) nounwind {
; RV64IZDINX: # %bb.0:
; RV64IZDINX-NEXT: # kill: def $x10_w killed $x10_w def $x10
; RV64IZDINX-NEXT: slli a0, a0, 49
; RV64IZDINX-NEXT: srli a0, a0, 49
; RV64IZDINX-NEXT: srli a1, a1, 63
; RV64IZDINX-NEXT: lui a2, 1048560
; RV64IZDINX-NEXT: srli a0, a0, 49
; RV64IZDINX-NEXT: slli a1, a1, 63
; RV64IZDINX-NEXT: srli a1, a1, 48
; RV64IZDINX-NEXT: lui a2, 1048560
; RV64IZDINX-NEXT: or a0, a0, a2
; RV64IZDINX-NEXT: or a0, a0, a1
; RV64IZDINX-NEXT: # kill: def $x10_w killed $x10_w killed $x10
Expand Down
1,166 changes: 583 additions & 583 deletions llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
View file

Large diffs are not rendered by default.

62 changes: 31 additions & 31 deletions llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -603,11 +603,11 @@ define signext i32 @ctlz(i64 %b) nounwind {
; RV32I-LABEL: ctlz:
; RV32I: # %bb.0: # %entry
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: lui a3, 209715
; RV32I-NEXT: lui a5, 61681
; RV32I-NEXT: addi a4, a2, 1365
; RV32I-NEXT: lui a2, 209715
; RV32I-NEXT: addi a3, a2, 819
; RV32I-NEXT: lui a2, 61681
; RV32I-NEXT: addi a2, a2, -241
; RV32I-NEXT: addi a3, a3, 819
; RV32I-NEXT: addi a2, a5, -241
; RV32I-NEXT: bnez a1, .LBB7_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: srli a1, a0, 1
Expand Down Expand Up @@ -672,40 +672,40 @@ define signext i32 @ctlz(i64 %b) nounwind {
; RV64I-LABEL: ctlz:
; RV64I: # %bb.0: # %entry
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 2
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 8
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 16
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: srli a1, a0, 32
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a1, a0, 1
; RV64I-NEXT: lui a2, 349525
; RV64I-NEXT: addiw a2, a2, 1365
; RV64I-NEXT: lui a3, 209715
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: addiw a1, a2, 1365
; RV64I-NEXT: addiw a2, a3, 819
; RV64I-NEXT: srli a3, a0, 2
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: slli a3, a1, 32
; RV64I-NEXT: add a1, a1, a3
; RV64I-NEXT: slli a3, a2, 32
; RV64I-NEXT: add a2, a2, a3
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: srli a3, a0, 4
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: srli a3, a0, 8
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: srli a3, a0, 16
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: srli a3, a0, 32
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: not a0, a0
; RV64I-NEXT: srli a3, a0, 1
; RV64I-NEXT: and a1, a3, a1
; RV64I-NEXT: lui a3, 61681
; RV64I-NEXT: addiw a3, a3, -241
; RV64I-NEXT: sub a0, a0, a1
; RV64I-NEXT: lui a1, 209715
; RV64I-NEXT: addiw a1, a1, 819
; RV64I-NEXT: slli a2, a1, 32
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: and a2, a0, a1
; RV64I-NEXT: and a1, a0, a2
; RV64I-NEXT: srli a0, a0, 2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: add a0, a2, a0
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slli a2, a3, 32
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: srli a1, a0, 4
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: lui a1, 61681
; RV64I-NEXT: addiw a1, a1, -241
; RV64I-NEXT: slli a2, a1, 32
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: add a2, a3, a2
; RV64I-NEXT: and a0, a0, a2
; RV64I-NEXT: slli a1, a0, 8
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: slli a1, a0, 16
Expand Down
62 changes: 31 additions & 31 deletions llvm/test/CodeGen/RISCV/div-by-constant.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -80,25 +80,25 @@ define i64 @udiv64_constant_no_add(i64 %a) nounwind {
; RV32-LABEL: udiv64_constant_no_add:
; RV32: # %bb.0:
; RV32-NEXT: add a2, a0, a1
; RV32-NEXT: sltu a3, a2, a0
; RV32-NEXT: add a2, a2, a3
; RV32-NEXT: lui a3, 838861
; RV32-NEXT: addi a4, a3, -819
; RV32-NEXT: mulhu a5, a2, a4
; RV32-NEXT: srli a6, a5, 2
; RV32-NEXT: andi a5, a5, -4
; RV32-NEXT: add a5, a5, a6
; RV32-NEXT: sub a2, a2, a5
; RV32-NEXT: sub a5, a0, a2
; RV32-NEXT: sltu a4, a2, a0
; RV32-NEXT: addi a5, a3, -819
; RV32-NEXT: addi a3, a3, -820
; RV32-NEXT: mul a3, a5, a3
; RV32-NEXT: mulhu a6, a5, a4
; RV32-NEXT: add a3, a6, a3
; RV32-NEXT: add a2, a2, a4
; RV32-NEXT: mulhu a4, a2, a5
; RV32-NEXT: srli a6, a4, 2
; RV32-NEXT: andi a4, a4, -4
; RV32-NEXT: add a4, a4, a6
; RV32-NEXT: sub a2, a2, a4
; RV32-NEXT: sub a4, a0, a2
; RV32-NEXT: sltu a0, a0, a2
; RV32-NEXT: mul a2, a4, a3
; RV32-NEXT: mulhu a3, a4, a5
; RV32-NEXT: sub a1, a1, a0
; RV32-NEXT: mul a1, a1, a4
; RV32-NEXT: add a1, a3, a1
; RV32-NEXT: mul a0, a5, a4
; RV32-NEXT: add a2, a3, a2
; RV32-NEXT: mul a1, a1, a5
; RV32-NEXT: add a1, a2, a1
; RV32-NEXT: mul a0, a4, a5
; RV32-NEXT: ret
;
; RV64-LABEL: udiv64_constant_no_add:
Expand Down Expand Up @@ -485,8 +485,8 @@ define i8 @sdiv8_constant_no_srai(i8 %a) nounwind {
; RV32IM-LABEL: sdiv8_constant_no_srai:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a0, a0, 24
; RV32IM-NEXT: srai a0, a0, 24
; RV32IM-NEXT: li a1, 86
; RV32IM-NEXT: srai a0, a0, 24
; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: srli a1, a0, 31
; RV32IM-NEXT: srli a0, a0, 8
Expand All @@ -506,8 +506,8 @@ define i8 @sdiv8_constant_no_srai(i8 %a) nounwind {
; RV64IM-LABEL: sdiv8_constant_no_srai:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 56
; RV64IM-NEXT: srai a0, a0, 56
; RV64IM-NEXT: li a1, 86
; RV64IM-NEXT: srai a0, a0, 56
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srli a1, a0, 63
; RV64IM-NEXT: srli a0, a0, 8
Expand All @@ -531,8 +531,8 @@ define i8 @sdiv8_constant_srai(i8 %a) nounwind {
; RV32IM-LABEL: sdiv8_constant_srai:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a0, a0, 24
; RV32IM-NEXT: srai a0, a0, 24
; RV32IM-NEXT: li a1, 103
; RV32IM-NEXT: srai a0, a0, 24
; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: srli a1, a0, 31
; RV32IM-NEXT: srai a0, a0, 9
Expand All @@ -552,8 +552,8 @@ define i8 @sdiv8_constant_srai(i8 %a) nounwind {
; RV64IM-LABEL: sdiv8_constant_srai:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 56
; RV64IM-NEXT: srai a0, a0, 56
; RV64IM-NEXT: li a1, 103
; RV64IM-NEXT: srai a0, a0, 56
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srli a1, a0, 63
; RV64IM-NEXT: srai a0, a0, 9
Expand All @@ -577,8 +577,8 @@ define i8 @sdiv8_constant_add_srai(i8 %a) nounwind {
; RV32IM-LABEL: sdiv8_constant_add_srai:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a1, a0, 24
; RV32IM-NEXT: srai a1, a1, 24
; RV32IM-NEXT: li a2, -109
; RV32IM-NEXT: srai a1, a1, 24
; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: srli a1, a1, 8
; RV32IM-NEXT: add a0, a1, a0
Expand All @@ -604,8 +604,8 @@ define i8 @sdiv8_constant_add_srai(i8 %a) nounwind {
; RV64IM-LABEL: sdiv8_constant_add_srai:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a0, 56
; RV64IM-NEXT: srai a1, a1, 56
; RV64IM-NEXT: li a2, -109
; RV64IM-NEXT: srai a1, a1, 56
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 8
; RV64IM-NEXT: add a0, a1, a0
Expand Down Expand Up @@ -635,8 +635,8 @@ define i8 @sdiv8_constant_sub_srai(i8 %a) nounwind {
; RV32IM-LABEL: sdiv8_constant_sub_srai:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a1, a0, 24
; RV32IM-NEXT: srai a1, a1, 24
; RV32IM-NEXT: li a2, 109
; RV32IM-NEXT: srai a1, a1, 24
; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: srli a1, a1, 8
; RV32IM-NEXT: sub a1, a1, a0
Expand All @@ -662,8 +662,8 @@ define i8 @sdiv8_constant_sub_srai(i8 %a) nounwind {
; RV64IM-LABEL: sdiv8_constant_sub_srai:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a0, 56
; RV64IM-NEXT: srai a1, a1, 56
; RV64IM-NEXT: li a2, 109
; RV64IM-NEXT: srai a1, a1, 56
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 8
; RV64IM-NEXT: subw a1, a1, a0
Expand Down Expand Up @@ -693,8 +693,8 @@ define i16 @sdiv16_constant_no_srai(i16 %a) nounwind {
; RV32IM-LABEL: sdiv16_constant_no_srai:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a0, a0, 16
; RV32IM-NEXT: srai a0, a0, 16
; RV32IM-NEXT: lui a1, 5
; RV32IM-NEXT: srai a0, a0, 16
; RV32IM-NEXT: addi a1, a1, 1366
; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: srli a1, a0, 31
Expand All @@ -716,8 +716,8 @@ define i16 @sdiv16_constant_no_srai(i16 %a) nounwind {
; RV64IM-LABEL: sdiv16_constant_no_srai:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: srai a0, a0, 48
; RV64IM-NEXT: lui a1, 5
; RV64IM-NEXT: srai a0, a0, 48
; RV64IM-NEXT: addiw a1, a1, 1366
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srli a1, a0, 63
Expand All @@ -743,8 +743,8 @@ define i16 @sdiv16_constant_srai(i16 %a) nounwind {
; RV32IM-LABEL: sdiv16_constant_srai:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a0, a0, 16
; RV32IM-NEXT: srai a0, a0, 16
; RV32IM-NEXT: lui a1, 6
; RV32IM-NEXT: srai a0, a0, 16
; RV32IM-NEXT: addi a1, a1, 1639
; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: srli a1, a0, 31
Expand All @@ -766,8 +766,8 @@ define i16 @sdiv16_constant_srai(i16 %a) nounwind {
; RV64IM-LABEL: sdiv16_constant_srai:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: srai a0, a0, 48
; RV64IM-NEXT: lui a1, 6
; RV64IM-NEXT: srai a0, a0, 48
; RV64IM-NEXT: addiw a1, a1, 1639
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srli a1, a0, 63
Expand All @@ -793,8 +793,8 @@ define i16 @sdiv16_constant_add_srai(i16 %a) nounwind {
; RV32IM-LABEL: sdiv16_constant_add_srai:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a1, a0, 16
; RV32IM-NEXT: srai a1, a1, 16
; RV32IM-NEXT: lui a2, 1048569
; RV32IM-NEXT: srai a1, a1, 16
; RV32IM-NEXT: addi a2, a2, -1911
; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: srli a1, a1, 16
Expand Down Expand Up @@ -822,8 +822,8 @@ define i16 @sdiv16_constant_add_srai(i16 %a) nounwind {
; RV64IM-LABEL: sdiv16_constant_add_srai:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a0, 48
; RV64IM-NEXT: srai a1, a1, 48
; RV64IM-NEXT: lui a2, 1048569
; RV64IM-NEXT: srai a1, a1, 48
; RV64IM-NEXT: addiw a2, a2, -1911
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 16
Expand Down Expand Up @@ -855,8 +855,8 @@ define i16 @sdiv16_constant_sub_srai(i16 %a) nounwind {
; RV32IM-LABEL: sdiv16_constant_sub_srai:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a1, a0, 16
; RV32IM-NEXT: srai a1, a1, 16
; RV32IM-NEXT: lui a2, 7
; RV32IM-NEXT: srai a1, a1, 16
; RV32IM-NEXT: addi a2, a2, 1911
; RV32IM-NEXT: mul a1, a1, a2
; RV32IM-NEXT: srli a1, a1, 16
Expand Down Expand Up @@ -884,8 +884,8 @@ define i16 @sdiv16_constant_sub_srai(i16 %a) nounwind {
; RV64IM-LABEL: sdiv16_constant_sub_srai:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a0, 48
; RV64IM-NEXT: srai a1, a1, 48
; RV64IM-NEXT: lui a2, 7
; RV64IM-NEXT: srai a1, a1, 48
; RV64IM-NEXT: addiw a2, a2, 1911
; RV64IM-NEXT: mul a1, a1, a2
; RV64IM-NEXT: srli a1, a1, 16
Expand Down
64 changes: 32 additions & 32 deletions llvm/test/CodeGen/RISCV/div-pow2.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -207,14 +207,14 @@ define i64 @sdiv64_pow2_negative_2(i64 %a) {
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: srli a3, a2, 1
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
; RV32I-NEXT: slli a0, a1, 31
; RV32I-NEXT: or a3, a3, a0
; RV32I-NEXT: neg a0, a3
; RV32I-NEXT: snez a2, a3
; RV32I-NEXT: srai a1, a1, 1
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: slli a1, a0, 31
; RV32I-NEXT: srai a2, a0, 1
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: neg a0, a1
; RV32I-NEXT: snez a1, a1
; RV32I-NEXT: neg a2, a2
; RV32I-NEXT: sub a1, a2, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv64_pow2_negative_2:
Expand Down Expand Up @@ -263,14 +263,14 @@ define i64 @sdiv64_pow2_negative_2048(i64 %a) {
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: srli a3, a2, 11
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
; RV32I-NEXT: slli a0, a1, 21
; RV32I-NEXT: or a3, a3, a0
; RV32I-NEXT: neg a0, a3
; RV32I-NEXT: snez a2, a3
; RV32I-NEXT: srai a1, a1, 11
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: slli a1, a0, 21
; RV32I-NEXT: srai a2, a0, 11
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: neg a0, a1
; RV32I-NEXT: snez a1, a1
; RV32I-NEXT: neg a2, a2
; RV32I-NEXT: sub a1, a2, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv64_pow2_negative_2048:
Expand Down Expand Up @@ -320,14 +320,14 @@ define i64 @sdiv64_pow2_negative_4096(i64 %a) {
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: srli a3, a2, 12
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
; RV32I-NEXT: slli a0, a1, 20
; RV32I-NEXT: or a3, a3, a0
; RV32I-NEXT: neg a0, a3
; RV32I-NEXT: snez a2, a3
; RV32I-NEXT: srai a1, a1, 12
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: slli a1, a0, 20
; RV32I-NEXT: srai a2, a0, 12
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: neg a0, a1
; RV32I-NEXT: snez a1, a1
; RV32I-NEXT: neg a2, a2
; RV32I-NEXT: sub a1, a2, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv64_pow2_negative_4096:
Expand Down Expand Up @@ -377,14 +377,14 @@ define i64 @sdiv64_pow2_negative_65536(i64 %a) {
; RV32I-NEXT: add a2, a0, a2
; RV32I-NEXT: srli a3, a2, 16
; RV32I-NEXT: sltu a0, a2, a0
; RV32I-NEXT: add a1, a1, a0
; RV32I-NEXT: slli a0, a1, 16
; RV32I-NEXT: or a3, a3, a0
; RV32I-NEXT: neg a0, a3
; RV32I-NEXT: snez a2, a3
; RV32I-NEXT: srai a1, a1, 16
; RV32I-NEXT: neg a1, a1
; RV32I-NEXT: sub a1, a1, a2
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: slli a1, a0, 16
; RV32I-NEXT: srai a2, a0, 16
; RV32I-NEXT: or a1, a3, a1
; RV32I-NEXT: neg a0, a1
; RV32I-NEXT: snez a1, a1
; RV32I-NEXT: neg a2, a2
; RV32I-NEXT: sub a1, a2, a1
; RV32I-NEXT: ret
;
; RV64I-LABEL: sdiv64_pow2_negative_65536:
Expand Down
56 changes: 28 additions & 28 deletions llvm/test/CodeGen/RISCV/div.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,8 +23,8 @@ define i32 @udiv(i32 %a, i32 %b) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: slli a1, a1, 32
; RV64I-NEXT: srli a0, a0, 32
; RV64I-NEXT: srli a1, a1, 32
; RV64I-NEXT: call __udivdi3
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -182,25 +182,25 @@ define i64 @udiv64_constant(i64 %a) nounwind {
; RV32IM-LABEL: udiv64_constant:
; RV32IM: # %bb.0:
; RV32IM-NEXT: add a2, a0, a1
; RV32IM-NEXT: sltu a3, a2, a0
; RV32IM-NEXT: add a2, a2, a3
; RV32IM-NEXT: lui a3, 838861
; RV32IM-NEXT: addi a4, a3, -819
; RV32IM-NEXT: mulhu a5, a2, a4
; RV32IM-NEXT: srli a6, a5, 2
; RV32IM-NEXT: andi a5, a5, -4
; RV32IM-NEXT: add a5, a5, a6
; RV32IM-NEXT: sub a2, a2, a5
; RV32IM-NEXT: sub a5, a0, a2
; RV32IM-NEXT: sltu a4, a2, a0
; RV32IM-NEXT: addi a5, a3, -819
; RV32IM-NEXT: addi a3, a3, -820
; RV32IM-NEXT: mul a3, a5, a3
; RV32IM-NEXT: mulhu a6, a5, a4
; RV32IM-NEXT: add a3, a6, a3
; RV32IM-NEXT: add a2, a2, a4
; RV32IM-NEXT: mulhu a4, a2, a5
; RV32IM-NEXT: srli a6, a4, 2
; RV32IM-NEXT: andi a4, a4, -4
; RV32IM-NEXT: add a4, a4, a6
; RV32IM-NEXT: sub a2, a2, a4
; RV32IM-NEXT: sub a4, a0, a2
; RV32IM-NEXT: sltu a0, a0, a2
; RV32IM-NEXT: mul a2, a4, a3
; RV32IM-NEXT: mulhu a3, a4, a5
; RV32IM-NEXT: sub a1, a1, a0
; RV32IM-NEXT: mul a1, a1, a4
; RV32IM-NEXT: add a1, a3, a1
; RV32IM-NEXT: mul a0, a5, a4
; RV32IM-NEXT: add a2, a3, a2
; RV32IM-NEXT: mul a1, a1, a5
; RV32IM-NEXT: add a1, a2, a1
; RV32IM-NEXT: mul a0, a4, a5
; RV32IM-NEXT: ret
;
; RV64I-LABEL: udiv64_constant:
Expand Down Expand Up @@ -919,8 +919,8 @@ define i8 @sdiv8(i8 %a, i8 %b) nounwind {
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: slli a1, a1, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: srai a1, a1, 24
; RV32I-NEXT: call __divsi3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -930,8 +930,8 @@ define i8 @sdiv8(i8 %a, i8 %b) nounwind {
; RV32IM-LABEL: sdiv8:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a1, a1, 24
; RV32IM-NEXT: srai a1, a1, 24
; RV32IM-NEXT: slli a0, a0, 24
; RV32IM-NEXT: srai a1, a1, 24
; RV32IM-NEXT: srai a0, a0, 24
; RV32IM-NEXT: div a0, a0, a1
; RV32IM-NEXT: ret
Expand All @@ -941,8 +941,8 @@ define i8 @sdiv8(i8 %a, i8 %b) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 56
; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: slli a1, a1, 56
; RV64I-NEXT: srai a0, a0, 56
; RV64I-NEXT: srai a1, a1, 56
; RV64I-NEXT: call __divdi3
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand All @@ -952,8 +952,8 @@ define i8 @sdiv8(i8 %a, i8 %b) nounwind {
; RV64IM-LABEL: sdiv8:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a1, 56
; RV64IM-NEXT: srai a1, a1, 56
; RV64IM-NEXT: slli a0, a0, 56
; RV64IM-NEXT: srai a1, a1, 56
; RV64IM-NEXT: srai a0, a0, 56
; RV64IM-NEXT: divw a0, a0, a1
; RV64IM-NEXT: ret
Expand All @@ -977,8 +977,8 @@ define i8 @sdiv8_constant(i8 %a) nounwind {
; RV32IM-LABEL: sdiv8_constant:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a0, a0, 24
; RV32IM-NEXT: srai a0, a0, 24
; RV32IM-NEXT: li a1, 103
; RV32IM-NEXT: srai a0, a0, 24
; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: srli a1, a0, 31
; RV32IM-NEXT: srai a0, a0, 9
Expand All @@ -1000,8 +1000,8 @@ define i8 @sdiv8_constant(i8 %a) nounwind {
; RV64IM-LABEL: sdiv8_constant:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 56
; RV64IM-NEXT: srai a0, a0, 56
; RV64IM-NEXT: li a1, 103
; RV64IM-NEXT: srai a0, a0, 56
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srli a1, a0, 63
; RV64IM-NEXT: srai a0, a0, 9
Expand Down Expand Up @@ -1105,8 +1105,8 @@ define i16 @sdiv16(i16 %a, i16 %b) nounwind {
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 16
; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: slli a1, a1, 16
; RV32I-NEXT: srai a0, a0, 16
; RV32I-NEXT: srai a1, a1, 16
; RV32I-NEXT: call __divsi3
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -1116,8 +1116,8 @@ define i16 @sdiv16(i16 %a, i16 %b) nounwind {
; RV32IM-LABEL: sdiv16:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a1, a1, 16
; RV32IM-NEXT: srai a1, a1, 16
; RV32IM-NEXT: slli a0, a0, 16
; RV32IM-NEXT: srai a1, a1, 16
; RV32IM-NEXT: srai a0, a0, 16
; RV32IM-NEXT: div a0, a0, a1
; RV32IM-NEXT: ret
Expand All @@ -1127,8 +1127,8 @@ define i16 @sdiv16(i16 %a, i16 %b) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: slli a0, a0, 48
; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: slli a1, a1, 48
; RV64I-NEXT: srai a0, a0, 48
; RV64I-NEXT: srai a1, a1, 48
; RV64I-NEXT: call __divdi3
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand All @@ -1138,8 +1138,8 @@ define i16 @sdiv16(i16 %a, i16 %b) nounwind {
; RV64IM-LABEL: sdiv16:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a1, a1, 48
; RV64IM-NEXT: srai a1, a1, 48
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: srai a1, a1, 48
; RV64IM-NEXT: srai a0, a0, 48
; RV64IM-NEXT: divw a0, a0, a1
; RV64IM-NEXT: ret
Expand All @@ -1163,8 +1163,8 @@ define i16 @sdiv16_constant(i16 %a) nounwind {
; RV32IM-LABEL: sdiv16_constant:
; RV32IM: # %bb.0:
; RV32IM-NEXT: slli a0, a0, 16
; RV32IM-NEXT: srai a0, a0, 16
; RV32IM-NEXT: lui a1, 6
; RV32IM-NEXT: srai a0, a0, 16
; RV32IM-NEXT: addi a1, a1, 1639
; RV32IM-NEXT: mul a0, a0, a1
; RV32IM-NEXT: srli a1, a0, 31
Expand All @@ -1187,8 +1187,8 @@ define i16 @sdiv16_constant(i16 %a) nounwind {
; RV64IM-LABEL: sdiv16_constant:
; RV64IM: # %bb.0:
; RV64IM-NEXT: slli a0, a0, 48
; RV64IM-NEXT: srai a0, a0, 48
; RV64IM-NEXT: lui a1, 6
; RV64IM-NEXT: srai a0, a0, 48
; RV64IM-NEXT: addiw a1, a1, 1639
; RV64IM-NEXT: mul a0, a0, a1
; RV64IM-NEXT: srli a1, a0, 63
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/double-arith.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -225,17 +225,17 @@ define double @fsgnj_d(double %a, double %b) nounwind {
; RV32I-LABEL: fsgnj_d:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 524288
; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: and a2, a3, a2
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret
;
; RV64I-LABEL: fsgnj_d:
; RV64I: # %bb.0:
; RV64I-NEXT: srli a1, a1, 63
; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: slli a0, a0, 1
; RV64I-NEXT: slli a1, a1, 63
; RV64I-NEXT: srli a0, a0, 1
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: ret
Expand Down Expand Up @@ -327,8 +327,8 @@ define double @fsgnjn_d(double %a, double %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: not a2, a3
; RV32I-NEXT: lui a3, 524288
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret
Expand Down Expand Up @@ -1524,8 +1524,8 @@ define double @fsgnjx_f64(double %x, double %y) nounwind {
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: srli a0, a0, 63
; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: li a2, 1023
; RV64I-NEXT: slli a0, a0, 63
; RV64I-NEXT: slli a2, a2, 52
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: call __muldf3
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -112,8 +112,8 @@ define double @fcopysign_fneg(double %a, double %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: not a2, a3
; RV32I-NEXT: lui a3, 524288
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: slli a1, a1, 1
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: srli a1, a1, 1
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: ret
Expand Down
64 changes: 32 additions & 32 deletions llvm/test/CodeGen/RISCV/double-calling-conv.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -42,11 +42,11 @@ define double @caller_double_inreg() nounwind {
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: lui a0, 262236
; RV32IFD-NEXT: lui a2, 377487
; RV32IFD-NEXT: lui a3, 262364
; RV32IFD-NEXT: addi a1, a0, 655
; RV32IFD-NEXT: lui a0, 377487
; RV32IFD-NEXT: addi a0, a0, 1475
; RV32IFD-NEXT: lui a2, 262364
; RV32IFD-NEXT: addi a3, a2, 655
; RV32IFD-NEXT: addi a0, a2, 1475
; RV32IFD-NEXT: addi a3, a3, 655
; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: call callee_double_inreg
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -58,11 +58,11 @@ define double @caller_double_inreg() nounwind {
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: lui a0, 262236
; RV32IZFINXZDINX-NEXT: lui a2, 377487
; RV32IZFINXZDINX-NEXT: lui a3, 262364
; RV32IZFINXZDINX-NEXT: addi a1, a0, 655
; RV32IZFINXZDINX-NEXT: lui a0, 377487
; RV32IZFINXZDINX-NEXT: addi a0, a0, 1475
; RV32IZFINXZDINX-NEXT: lui a2, 262364
; RV32IZFINXZDINX-NEXT: addi a3, a2, 655
; RV32IZFINXZDINX-NEXT: addi a0, a2, 1475
; RV32IZFINXZDINX-NEXT: addi a3, a3, 655
; RV32IZFINXZDINX-NEXT: mv a2, a0
; RV32IZFINXZDINX-NEXT: call callee_double_inreg
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -107,14 +107,14 @@ define double @caller_double_split_reg_stack() nounwind {
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: lui a0, 262510
; RV32IFD-NEXT: addi a2, a0, 327
; RV32IFD-NEXT: lui a0, 262446
; RV32IFD-NEXT: addi a6, a0, 327
; RV32IFD-NEXT: lui a0, 713032
; RV32IFD-NEXT: addi a5, a0, -1311
; RV32IFD-NEXT: lui a2, 262510
; RV32IFD-NEXT: lui a3, 262446
; RV32IFD-NEXT: lui a4, 713032
; RV32IFD-NEXT: li a0, 1
; RV32IFD-NEXT: li a1, 2
; RV32IFD-NEXT: addi a2, a2, 327
; RV32IFD-NEXT: addi a6, a3, 327
; RV32IFD-NEXT: addi a5, a4, -1311
; RV32IFD-NEXT: li a3, 3
; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: li a2, 0
Expand All @@ -129,14 +129,14 @@ define double @caller_double_split_reg_stack() nounwind {
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: lui a0, 262510
; RV32IZFINXZDINX-NEXT: addi a2, a0, 327
; RV32IZFINXZDINX-NEXT: lui a0, 262446
; RV32IZFINXZDINX-NEXT: addi a6, a0, 327
; RV32IZFINXZDINX-NEXT: lui a0, 713032
; RV32IZFINXZDINX-NEXT: addi a5, a0, -1311
; RV32IZFINXZDINX-NEXT: lui a2, 262510
; RV32IZFINXZDINX-NEXT: lui a3, 262446
; RV32IZFINXZDINX-NEXT: lui a4, 713032
; RV32IZFINXZDINX-NEXT: li a0, 1
; RV32IZFINXZDINX-NEXT: li a1, 2
; RV32IZFINXZDINX-NEXT: addi a2, a2, 327
; RV32IZFINXZDINX-NEXT: addi a6, a3, 327
; RV32IZFINXZDINX-NEXT: addi a5, a4, -1311
; RV32IZFINXZDINX-NEXT: li a3, 3
; RV32IZFINXZDINX-NEXT: sw a2, 0(sp)
; RV32IZFINXZDINX-NEXT: li a2, 0
Expand Down Expand Up @@ -180,16 +180,16 @@ define double @caller_double_stack() nounwind {
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: lui a0, 262510
; RV32IFD-NEXT: addi a1, a0, 327
; RV32IFD-NEXT: lui a0, 713032
; RV32IFD-NEXT: addi a3, a0, -1311
; RV32IFD-NEXT: lui a0, 262574
; RV32IFD-NEXT: addi a5, a0, 327
; RV32IFD-NEXT: lui a1, 262510
; RV32IFD-NEXT: lui a3, 713032
; RV32IFD-NEXT: lui a5, 262574
; RV32IFD-NEXT: li a0, 1
; RV32IFD-NEXT: li a2, 2
; RV32IFD-NEXT: li a4, 3
; RV32IFD-NEXT: li a6, 4
; RV32IFD-NEXT: addi a1, a1, 327
; RV32IFD-NEXT: addi a3, a3, -1311
; RV32IFD-NEXT: addi a5, a5, 327
; RV32IFD-NEXT: sw a3, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: sw a3, 8(sp)
Expand All @@ -207,16 +207,16 @@ define double @caller_double_stack() nounwind {
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: addi sp, sp, -32
; RV32IZFINXZDINX-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: lui a0, 262510
; RV32IZFINXZDINX-NEXT: addi a1, a0, 327
; RV32IZFINXZDINX-NEXT: lui a0, 713032
; RV32IZFINXZDINX-NEXT: addi a3, a0, -1311
; RV32IZFINXZDINX-NEXT: lui a0, 262574
; RV32IZFINXZDINX-NEXT: addi a5, a0, 327
; RV32IZFINXZDINX-NEXT: lui a1, 262510
; RV32IZFINXZDINX-NEXT: lui a3, 713032
; RV32IZFINXZDINX-NEXT: lui a5, 262574
; RV32IZFINXZDINX-NEXT: li a0, 1
; RV32IZFINXZDINX-NEXT: li a2, 2
; RV32IZFINXZDINX-NEXT: li a4, 3
; RV32IZFINXZDINX-NEXT: li a6, 4
; RV32IZFINXZDINX-NEXT: addi a1, a1, 327
; RV32IZFINXZDINX-NEXT: addi a3, a3, -1311
; RV32IZFINXZDINX-NEXT: addi a5, a5, 327
; RV32IZFINXZDINX-NEXT: sw a3, 0(sp)
; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: sw a3, 8(sp)
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