300 changes: 300 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/fadd.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,300 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-f16f16 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST

fadd za.h[w8, 0, vgx2], {z0.h, z1.h} // 11000001-10100100-00011100-00000000
// CHECK-INST: fadd za.h[w8, 0, vgx2], { z0.h, z1.h }
// CHECK-ENCODING: [0x00,0x1c,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41c00 <unknown>

fadd za.h[w8, 0], {z0.h - z1.h} // 11000001-10100100-00011100-00000000
// CHECK-INST: fadd za.h[w8, 0, vgx2], { z0.h, z1.h }
// CHECK-ENCODING: [0x00,0x1c,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41c00 <unknown>

fadd za.h[w10, 5, vgx2], {z10.h, z11.h} // 11000001-10100100-01011101-01000101
// CHECK-INST: fadd za.h[w10, 5, vgx2], { z10.h, z11.h }
// CHECK-ENCODING: [0x45,0x5d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a45d45 <unknown>

fadd za.h[w10, 5], {z10.h - z11.h} // 11000001-10100100-01011101-01000101
// CHECK-INST: fadd za.h[w10, 5, vgx2], { z10.h, z11.h }
// CHECK-ENCODING: [0x45,0x5d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a45d45 <unknown>

fadd za.h[w11, 7, vgx2], {z12.h, z13.h} // 11000001-10100100-01111101-10000111
// CHECK-INST: fadd za.h[w11, 7, vgx2], { z12.h, z13.h }
// CHECK-ENCODING: [0x87,0x7d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a47d87 <unknown>

fadd za.h[w11, 7], {z12.h - z13.h} // 11000001-10100100-01111101-10000111
// CHECK-INST: fadd za.h[w11, 7, vgx2], { z12.h, z13.h }
// CHECK-ENCODING: [0x87,0x7d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a47d87 <unknown>

fadd za.h[w11, 7, vgx2], {z30.h, z31.h} // 11000001-10100100-01111111-11000111
// CHECK-INST: fadd za.h[w11, 7, vgx2], { z30.h, z31.h }
// CHECK-ENCODING: [0xc7,0x7f,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a47fc7 <unknown>

fadd za.h[w11, 7], {z30.h - z31.h} // 11000001-10100100-01111111-11000111
// CHECK-INST: fadd za.h[w11, 7, vgx2], { z30.h, z31.h }
// CHECK-ENCODING: [0xc7,0x7f,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a47fc7 <unknown>

fadd za.h[w8, 5, vgx2], {z16.h, z17.h} // 11000001-10100100-00011110-00000101
// CHECK-INST: fadd za.h[w8, 5, vgx2], { z16.h, z17.h }
// CHECK-ENCODING: [0x05,0x1e,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41e05 <unknown>

fadd za.h[w8, 5], {z16.h - z17.h} // 11000001-10100100-00011110-00000101
// CHECK-INST: fadd za.h[w8, 5, vgx2], { z16.h, z17.h }
// CHECK-ENCODING: [0x05,0x1e,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41e05 <unknown>

fadd za.h[w8, 1, vgx2], {z0.h, z1.h} // 11000001-10100100-00011100-00000001
// CHECK-INST: fadd za.h[w8, 1, vgx2], { z0.h, z1.h }
// CHECK-ENCODING: [0x01,0x1c,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41c01 <unknown>

fadd za.h[w8, 1], {z0.h - z1.h} // 11000001-10100100-00011100-00000001
// CHECK-INST: fadd za.h[w8, 1, vgx2], { z0.h, z1.h }
// CHECK-ENCODING: [0x01,0x1c,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41c01 <unknown>

fadd za.h[w10, 0, vgx2], {z18.h, z19.h} // 11000001-10100100-01011110, 01000000
// CHECK-INST: fadd za.h[w10, 0, vgx2], { z18.h, z19.h }
// CHECK-ENCODING: [0x40,0x5e,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a45e40 <unknown>

fadd za.h[w10, 0], {z18.h - z19.h} // 11000001-10100100-01011110-01000000
// CHECK-INST: fadd za.h[w10, 0, vgx2], { z18.h, z19.h }
// CHECK-ENCODING: [0x40,0x5e,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a45e40 <unknown>

fadd za.h[w8, 0, vgx2], {z12.h, z13.h} // 11000001-10100100-00011101-10000000
// CHECK-INST: fadd za.h[w8, 0, vgx2], { z12.h, z13.h }
// CHECK-ENCODING: [0x80,0x1d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41d80 <unknown>

fadd za.h[w8, 0], {z12.h - z13.h} // 11000001-10100100-00011101-10000000
// CHECK-INST: fadd za.h[w8, 0, vgx2], { z12.h, z13.h }
// CHECK-ENCODING: [0x80,0x1d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41d80 <unknown>

fadd za.h[w10, 1, vgx2], {z0.h, z1.h} // 11000001-10100100-01011100-00000001
// CHECK-INST: fadd za.h[w10, 1, vgx2], { z0.h, z1.h }
// CHECK-ENCODING: [0x01,0x5c,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a45c01 <unknown>

fadd za.h[w10, 1], {z0.h - z1.h} // 11000001-10100100-01011100-00000001
// CHECK-INST: fadd za.h[w10, 1, vgx2], { z0.h, z1.h }
// CHECK-ENCODING: [0x01,0x5c,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a45c01 <unknown>

fadd za.h[w8, 5, vgx2], {z22.h, z23.h} // 11000001-10100100-00011110, 11000101
// CHECK-INST: fadd za.h[w8, 5, vgx2], { z22.h, z23.h }
// CHECK-ENCODING: [0xc5,0x1e,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41ec5 <unknown>

fadd za.h[w8, 5], {z22.h - z23.h} // 11000001-10100100-00011110-11000101
// CHECK-INST: fadd za.h[w8, 5, vgx2], { z22.h, z23.h }
// CHECK-ENCODING: [0xc5,0x1e,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41ec5 <unknown>

fadd za.h[w11, 2, vgx2], {z8.h, z9.h} // 11000001-10100100-01111101-00000010
// CHECK-INST: fadd za.h[w11, 2, vgx2], { z8.h, z9.h }
// CHECK-ENCODING: [0x02,0x7d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a47d02 <unknown>

fadd za.h[w11, 2], {z8.h - z9.h} // 11000001-10100100-01111101-00000010
// CHECK-INST: fadd za.h[w11, 2, vgx2], { z8.h, z9.h }
// CHECK-ENCODING: [0x02,0x7d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a47d02 <unknown>

fadd za.h[w9, 7, vgx2], {z12.h, z13.h} // 11000001-10100100-00111101-10000111
// CHECK-INST: fadd za.h[w9, 7, vgx2], { z12.h, z13.h }
// CHECK-ENCODING: [0x87,0x3d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a43d87 <unknown>

fadd za.h[w9, 7], {z12.h - z13.h} // 11000001-10100100-00111101-10000111
// CHECK-INST: fadd za.h[w9, 7, vgx2], { z12.h, z13.h }
// CHECK-ENCODING: [0x87,0x3d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a43d87 <unknown>

fadd za.h[w8, 0, vgx4], {z0.h - z3.h} // 11000001-10100101-00011100-00000000
// CHECK-INST: fadd za.h[w8, 0, vgx4], { z0.h - z3.h }
// CHECK-ENCODING: [0x00,0x1c,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51c00 <unknown>

fadd za.h[w8, 0], {z0.h - z3.h} // 11000001-10100101-00011100-00000000
// CHECK-INST: fadd za.h[w8, 0, vgx4], { z0.h - z3.h }
// CHECK-ENCODING: [0x00,0x1c,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51c00 <unknown>

fadd za.h[w10, 5, vgx4], {z8.h - z11.h} // 11000001-10100101-01011101-00000101
// CHECK-INST: fadd za.h[w10, 5, vgx4], { z8.h - z11.h }
// CHECK-ENCODING: [0x05,0x5d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a55d05 <unknown>

fadd za.h[w10, 5], {z8.h - z11.h} // 11000001-10100101-01011101-00000101
// CHECK-INST: fadd za.h[w10, 5, vgx4], { z8.h - z11.h }
// CHECK-ENCODING: [0x05,0x5d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a55d05 <unknown>

fadd za.h[w11, 7, vgx4], {z12.h - z15.h} // 11000001-10100101-01111101-10000111
// CHECK-INST: fadd za.h[w11, 7, vgx4], { z12.h - z15.h }
// CHECK-ENCODING: [0x87,0x7d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a57d87 <unknown>

fadd za.h[w11, 7], {z12.h - z15.h} // 11000001-10100101-01111101-10000111
// CHECK-INST: fadd za.h[w11, 7, vgx4], { z12.h - z15.h }
// CHECK-ENCODING: [0x87,0x7d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a57d87 <unknown>

fadd za.h[w11, 7, vgx4], {z28.h - z31.h} // 11000001-10100101-01111111-10000111
// CHECK-INST: fadd za.h[w11, 7, vgx4], { z28.h - z31.h }
// CHECK-ENCODING: [0x87,0x7f,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a57f87 <unknown>

fadd za.h[w11, 7], {z28.h - z31.h} // 11000001-10100101-01111111-10000111
// CHECK-INST: fadd za.h[w11, 7, vgx4], { z28.h - z31.h }
// CHECK-ENCODING: [0x87,0x7f,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a57f87 <unknown>

fadd za.h[w8, 5, vgx4], {z16.h - z19.h} // 11000001-10100101-00011110-00000101
// CHECK-INST: fadd za.h[w8, 5, vgx4], { z16.h - z19.h }
// CHECK-ENCODING: [0x05,0x1e,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51e05 <unknown>

fadd za.h[w8, 5], {z16.h - z19.h} // 11000001-10100101-00011110-00000101
// CHECK-INST: fadd za.h[w8, 5, vgx4], { z16.h - z19.h }
// CHECK-ENCODING: [0x05,0x1e,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51e05 <unknown>

fadd za.h[w8, 1, vgx4], {z0.h - z3.h} // 11000001-10100101-00011100-00000001
// CHECK-INST: fadd za.h[w8, 1, vgx4], { z0.h - z3.h }
// CHECK-ENCODING: [0x01,0x1c,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51c01 <unknown>

fadd za.h[w8, 1], {z0.h - z3.h} // 11000001-10100101-00011100-00000001
// CHECK-INST: fadd za.h[w8, 1, vgx4], { z0.h - z3.h }
// CHECK-ENCODING: [0x01,0x1c,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51c01 <unknown>

fadd za.h[w10, 0, vgx4], {z16.h - z19.h} // 11000001-10100101-01011110-00000000
// CHECK-INST: fadd za.h[w10, 0, vgx4], { z16.h - z19.h }
// CHECK-ENCODING: [0x00,0x5e,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a55e00 <unknown>

fadd za.h[w10, 0], {z16.h - z19.h} // 11000001-10100101-01011110-00000000
// CHECK-INST: fadd za.h[w10, 0, vgx4], { z16.h - z19.h }
// CHECK-ENCODING: [0x00,0x5e,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a55e00 <unknown>

fadd za.h[w8, 0, vgx4], {z12.h - z15.h} // 11000001-10100101-00011101-10000000
// CHECK-INST: fadd za.h[w8, 0, vgx4], { z12.h - z15.h }
// CHECK-ENCODING: [0x80,0x1d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51d80 <unknown>

fadd za.h[w8, 0], {z12.h - z15.h} // 11000001-10100101-00011101-10000000
// CHECK-INST: fadd za.h[w8, 0, vgx4], { z12.h - z15.h }
// CHECK-ENCODING: [0x80,0x1d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51d80 <unknown>

fadd za.h[w10, 1, vgx4], {z0.h - z3.h} // 11000001-10100101-01011100-00000001
// CHECK-INST: fadd za.h[w10, 1, vgx4], { z0.h - z3.h }
// CHECK-ENCODING: [0x01,0x5c,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a55c01 <unknown>

fadd za.h[w10, 1], {z0.h - z3.h} // 11000001-10100101-01011100-00000001
// CHECK-INST: fadd za.h[w10, 1, vgx4], { z0.h - z3.h }
// CHECK-ENCODING: [0x01,0x5c,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a55c01 <unknown>

fadd za.h[w8, 5, vgx4], {z20.h - z23.h} // 11000001-10100101-00011110-10000101
// CHECK-INST: fadd za.h[w8, 5, vgx4], { z20.h - z23.h }
// CHECK-ENCODING: [0x85,0x1e,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51e85 <unknown>

fadd za.h[w8, 5], {z20.h - z23.h} // 11000001-10100101-00011110-10000101
// CHECK-INST: fadd za.h[w8, 5, vgx4], { z20.h - z23.h }
// CHECK-ENCODING: [0x85,0x1e,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51e85 <unknown>

fadd za.h[w11, 2, vgx4], {z8.h - z11.h} // 11000001-10100101-01111101-00000010
// CHECK-INST: fadd za.h[w11, 2, vgx4], { z8.h - z11.h }
// CHECK-ENCODING: [0x02,0x7d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a57d02 <unknown>

fadd za.h[w11, 2], {z8.h - z11.h} // 11000001-10100101-01111101-00000010
// CHECK-INST: fadd za.h[w11, 2, vgx4], { z8.h - z11.h }
// CHECK-ENCODING: [0x02,0x7d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a57d02 <unknown>

fadd za.h[w9, 7, vgx4], {z12.h - z15.h} // 11000001-10100101-00111101-10000111
// CHECK-INST: fadd za.h[w9, 7, vgx4], { z12.h - z15.h }
// CHECK-ENCODING: [0x87,0x3d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a53d87 <unknown>

fadd za.h[w9, 7], {z12.h - z15.h} // 11000001-10100101-00111101-10000111
// CHECK-INST: fadd za.h[w9, 7, vgx4], { z12.h - z15.h }
// CHECK-ENCODING: [0x87,0x3d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a53d87 <unknown>
47 changes: 47 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/fcvt-diagnostics.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,47 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

fcvt z0.h, {z0.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvt z0.h, {z0.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fcvt {z0.s-z2.s}, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvt {z0.s-z2.s}, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fcvt z0.h, {z1.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: fcvt z0.h, {z1.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fcvt {z1.s-z2.s}, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: fcvt {z1.s-z2.s}, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

fcvt z0.s, {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvt z0.s, {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fcvt z0.h, {z0.h-z1.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvt z0.h, {z0.h-z1.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fcvt {z0.s-z1.s}, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvt {z0.s-z1.s}, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fcvt {z0.h-z1.h}, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvt {z0.h-z1.h}, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
36 changes: 36 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/fcvt.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,36 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-f16f16 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST

fcvt {z0.s, z1.s}, z0.h // 11000001-10100000-11100000-00000000
// CHECK-INST: fcvt { z0.s, z1.s }, z0.h
// CHECK-ENCODING: [0x00,0xe0,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: c1a0e000 <unknown>

fcvt {z20.s, z21.s}, z10.h // 11000001-10100000-11100001-01010100
// CHECK-INST: fcvt { z20.s, z21.s }, z10.h
// CHECK-ENCODING: [0x54,0xe1,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: c1a0e154 <unknown>

fcvt {z22.s, z23.s}, z13.h // 11000001-10100000-11100001-10110110
// CHECK-INST: fcvt { z22.s, z23.s }, z13.h
// CHECK-ENCODING: [0xb6,0xe1,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: c1a0e1b6 <unknown>

fcvt {z30.s, z31.s}, z31.h // 11000001-10100000-11100011-11111110
// CHECK-INST: fcvt { z30.s, z31.s }, z31.h
// CHECK-ENCODING: [0xfe,0xe3,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: c1a0e3fe <unknown>
32 changes: 32 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/fcvtl-diagnostics.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,32 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

fcvtl {z0.s-z2.s}, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvtl {z0.s-z2.s}, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fcvtl z0.h, {z1.s-z2.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector register expected
// CHECK-NEXT: fcvtl z0.h, {z1.s-z2.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fcvtl {z1.s-z2.s}, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: fcvtl {z1.s-z2.s}, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

fcvtl {z0.s-z1.s}, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fcvtl {z0.s-z1.s}, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fcvtl {z0.h-z1.h}, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fcvtl {z0.h-z1.h}, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
36 changes: 36 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/fcvtl.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,36 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-f16f16 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST

fcvtl {z0.s, z1.s}, z0.h // 11000001-10100000-11100000-00000001
// CHECK-INST: fcvtl { z0.s, z1.s }, z0.h
// CHECK-ENCODING: [0x01,0xe0,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: c1a0e001 <unknown>

fcvtl {z20.s, z21.s}, z10.h // 11000001-10100000-11100001-01010101
// CHECK-INST: fcvtl { z20.s, z21.s }, z10.h
// CHECK-ENCODING: [0x55,0xe1,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: c1a0e155 <unknown>

fcvtl {z22.s, z23.s}, z13.h // 11000001-10100000-11100001-10110111
// CHECK-INST: fcvtl { z22.s, z23.s }, z13.h
// CHECK-ENCODING: [0xb7,0xe1,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: c1a0e1b7 <unknown>

fcvtl {z30.s, z31.s}, z31.h // 11000001-10100000-11100011-11111111
// CHECK-INST: fcvtl { z30.s, z31.s }, z31.h
// CHECK-ENCODING: [0xff,0xe3,0xa0,0xc1]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: c1a0e3ff <unknown>
94 changes: 94 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,94 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

fmla za.h[w11, 2, vgx2], {z12.h-z14.h}, z8.h[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmla za.h[w11, 2, vgx2], {z12.h-z14.h}, z8.h[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmla za.h[w11, 2, vgx4], {z12.h-z17.h}, z7.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: fmla za.h[w11, 2, vgx4], {z12.h-z17.h}, z7.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmla za.h[w10, 3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: fmla za.h[w10, 3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmla za.h[w11, 7, vgx4], {z12.h-z15.h}, {z9.h-z12.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: fmla za.h[w11, 7, vgx4], {z12.h-z15.h}, {z9.h-z12.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid indexed-vector or single-vector register

fmla za.h[w8, 0], {z0.h-z1.h}, z16.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: fmla za.h[w8, 0], {z0.h-z1.h}, z16.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmla za.h[w8, 1], {z0.h-z3.h}, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: fmla za.h[w8, 1], {z0.h-z3.h}, z16.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select register

fmla za.h[w7, 7, vgx4], {z12.h-z15.h}, {z8.h-z11.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: fmla za.h[w7, 7, vgx4], {z12.h-z15.h}, {z8.h-z11.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmla za.h[w12, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: fmla za.h[w12, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select offset

fmla za.h[w8, -1, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: fmla za.h[w8, -1, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmla za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: fmla za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

fmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
// CHECK-NEXT: fmla za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector lane index

fmla za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: fmla za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmla za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: fmla za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmla za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: fmla za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmla za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: fmla za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
877 changes: 877 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/fmla.s
View file

Large diffs are not rendered by default.

94 changes: 94 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,94 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid vector list

fmls za.h[w11, 2, vgx2], {z12.h-z14.h}, z8.h[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmls za.h[w11, 2, vgx2], {z12.h-z14.h}, z8.h[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmls za.h[w11, 2, vgx4], {z12.h-z17.h}, z7.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: fmls za.h[w11, 2, vgx4], {z12.h-z17.h}, z7.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmls za.h[w10, 3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: fmls za.h[w10, 3, vgx2], {z10.h-z11.h}, {z21.h-z22.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmls za.h[w11, 7, vgx4], {z12.h-z15.h}, {z9.h-z12.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: fmls za.h[w11, 7, vgx4], {z12.h-z15.h}, {z9.h-z12.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid indexed-vector or single-vector register

fmls za.h[w8, 0], {z0.h-z1.h}, z16.h[0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: fmls za.h[w8, 0], {z0.h-z1.h}, z16.h[0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmls za.h[w8, 1], {z0.h-z3.h}, z16.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.h..z15.h
// CHECK-NEXT: fmls za.h[w8, 1], {z0.h-z3.h}, z16.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select register

fmls za.h[w7, 7, vgx4], {z12.h-z15.h}, {z8.h-z11.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: fmls za.h[w7, 7, vgx4], {z12.h-z15.h}, {z8.h-z11.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmls za.h[w12, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: fmls za.h[w12, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select offset

fmls za.h[w8, -1, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: fmls za.h[w8, -1, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmls za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: fmls za.h[w8, 8, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid Register Suffix

fmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
// CHECK-NEXT: fmls za.d[w8, 7, vgx2], {z12.h-z13.h}, {z8.h-z9.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector lane index

fmls za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: fmls za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmls za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: fmls za.h[w11, 6, vgx2], {z12.h-z13.h}, z8.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmls za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: fmls za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmls za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: fmls za.h[w11, 7, vgx4], {z12.h-z15.h}, z8.h[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
878 changes: 878 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/fmls.s
View file

Large diffs are not rendered by default.

35 changes: 35 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/fmopa-diagnostics.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid predicate register

fmopa za1.h, p8/m, p5/m, z12.h, z11.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmopa za1.h, p8/m, p5/m, z12.h, z11.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmopa za1.h, p5/m, p8/m, z12.h, z11.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmopa za1.h, p5/m, p8/m, z12.h, z11.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmopa za1.h, p5.h, p5/m, z12.h, z11.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmopa za1.h, p5.h, p5/m, z12.h, z11.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid matrix operand

fmopa za2.h, p5/m, p5/m, z12.h, z11.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmopa za2.h, p5/m, p5/m, z12.h, z11.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid register suffixes

fmopa za1.h, p5/m, p5/m, z12.h, z11.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmopa za1.h, p5/m, p5/m, z12.h, z11.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
85 changes: 85 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/fmopa.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,85 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-f16f16 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST

fmopa za0.h, p0/m, p0/m, z0.h, z0.h // 10000001-10000000-00000000-00001000
// CHECK-INST: fmopa za0.h, p0/m, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x08,0x00,0x80,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 81800008 <unknown>

fmopa za1.h, p5/m, p2/m, z10.h, z21.h // 10000001-10010101-01010101-01001001
// CHECK-INST: fmopa za1.h, p5/m, p2/m, z10.h, z21.h
// CHECK-ENCODING: [0x49,0x55,0x95,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 81955549 <unknown>

fmopa za1.h, p3/m, p7/m, z13.h, z8.h // 10000001-10001000-11101101-10101001
// CHECK-INST: fmopa za1.h, p3/m, p7/m, z13.h, z8.h
// CHECK-ENCODING: [0xa9,0xed,0x88,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 8188eda9 <unknown>

fmopa za1.h, p7/m, p7/m, z31.h, z31.h // 10000001-10011111-11111111-11101001
// CHECK-INST: fmopa za1.h, p7/m, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xe9,0xff,0x9f,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 819fffe9 <unknown>

fmopa za1.h, p3/m, p0/m, z17.h, z16.h // 10000001-10010000-00001110-00101001
// CHECK-INST: fmopa za1.h, p3/m, p0/m, z17.h, z16.h
// CHECK-ENCODING: [0x29,0x0e,0x90,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 81900e29 <unknown>

fmopa za1.h, p1/m, p4/m, z1.h, z30.h // 10000001-10011110-10000100-00101001
// CHECK-INST: fmopa za1.h, p1/m, p4/m, z1.h, z30.h
// CHECK-ENCODING: [0x29,0x84,0x9e,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 819e8429 <unknown>

fmopa za0.h, p5/m, p2/m, z19.h, z20.h // 10000001-10010100-01010110-01101000
// CHECK-INST: fmopa za0.h, p5/m, p2/m, z19.h, z20.h
// CHECK-ENCODING: [0x68,0x56,0x94,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 81945668 <unknown>

fmopa za0.h, p6/m, p0/m, z12.h, z2.h // 10000001-10000010-00011001-10001000
// CHECK-INST: fmopa za0.h, p6/m, p0/m, z12.h, z2.h
// CHECK-ENCODING: [0x88,0x19,0x82,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 81821988 <unknown>

fmopa za1.h, p2/m, p6/m, z1.h, z26.h // 10000001-10011010-11001000-00101001
// CHECK-INST: fmopa za1.h, p2/m, p6/m, z1.h, z26.h
// CHECK-ENCODING: [0x29,0xc8,0x9a,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 819ac829 <unknown>

fmopa za1.h, p2/m, p0/m, z22.h, z30.h // 10000001-10011110-00001010-11001001
// CHECK-INST: fmopa za1.h, p2/m, p0/m, z22.h, z30.h
// CHECK-ENCODING: [0xc9,0x0a,0x9e,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 819e0ac9 <unknown>

fmopa za0.h, p5/m, p7/m, z9.h, z1.h // 10000001-10000001-11110101-00101000
// CHECK-INST: fmopa za0.h, p5/m, p7/m, z9.h, z1.h
// CHECK-ENCODING: [0x28,0xf5,0x81,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 8181f528 <unknown>

fmopa za1.h, p2/m, p5/m, z12.h, z11.h // 10000001-10001011-10101001-10001001
// CHECK-INST: fmopa za1.h, p2/m, p5/m, z12.h, z11.h
// CHECK-ENCODING: [0x89,0xa9,0x8b,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 818ba989 <unknown>

35 changes: 35 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/fmops-diagnostics.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid predicate register

fmops za1.h, p8/m, p5/m, z12.h, z11.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmops za1.h, p8/m, p5/m, z12.h, z11.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmops za1.h, p5/m, p8/m, z12.h, z11.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmops za1.h, p5/m, p8/m, z12.h, z11.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fmops za1.h, p5.h, p5/m, z12.h, z11.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: fmops za1.h, p5.h, p5/m, z12.h, z11.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid matrix operand

fmops za2.h, p5/m, p5/m, z12.h, z11.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: fmops za2.h, p5/m, p5/m, z12.h, z11.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid register suffixes

fmops za1.h, p5/m, p5/m, z12.h, z11.b
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: fmops za1.h, p5/m, p5/m, z12.h, z11.b
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
84 changes: 84 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/fmops.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,84 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-f16f16 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST

fmops za0.h, p0/m, p0/m, z0.h, z0.h // 10000001-10000000-00000000-00011000
// CHECK-INST: fmops za0.h, p0/m, p0/m, z0.h, z0.h
// CHECK-ENCODING: [0x18,0x00,0x80,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 81800018 <unknown>

fmops za1.h, p5/m, p2/m, z10.h, z21.h // 10000001-10010101-01010101-01011001
// CHECK-INST: fmops za1.h, p5/m, p2/m, z10.h, z21.h
// CHECK-ENCODING: [0x59,0x55,0x95,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 81955559 <unknown>

fmops za1.h, p3/m, p7/m, z13.h, z8.h // 10000001-10001000-11101101-10111001
// CHECK-INST: fmops za1.h, p3/m, p7/m, z13.h, z8.h
// CHECK-ENCODING: [0xb9,0xed,0x88,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 8188edb9 <unknown>

fmops za1.h, p7/m, p7/m, z31.h, z31.h // 10000001-10011111-11111111-11111001
// CHECK-INST: fmops za1.h, p7/m, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xf9,0xff,0x9f,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 819ffff9 <unknown>

fmops za1.h, p3/m, p0/m, z17.h, z16.h // 10000001-10010000-00001110-00111001
// CHECK-INST: fmops za1.h, p3/m, p0/m, z17.h, z16.h
// CHECK-ENCODING: [0x39,0x0e,0x90,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 81900e39 <unknown>

fmops za1.h, p1/m, p4/m, z1.h, z30.h // 10000001-10011110-10000100-00111001
// CHECK-INST: fmops za1.h, p1/m, p4/m, z1.h, z30.h
// CHECK-ENCODING: [0x39,0x84,0x9e,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 819e8439 <unknown>

fmops za0.h, p5/m, p2/m, z19.h, z20.h // 10000001-10010100-01010110-01111000
// CHECK-INST: fmops za0.h, p5/m, p2/m, z19.h, z20.h
// CHECK-ENCODING: [0x78,0x56,0x94,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 81945678 <unknown>

fmops za0.h, p6/m, p0/m, z12.h, z2.h // 10000001-10000010-00011001-10011000
// CHECK-INST: fmops za0.h, p6/m, p0/m, z12.h, z2.h
// CHECK-ENCODING: [0x98,0x19,0x82,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 81821998 <unknown>

fmops za1.h, p2/m, p6/m, z1.h, z26.h // 10000001-10011010-11001000-00111001
// CHECK-INST: fmops za1.h, p2/m, p6/m, z1.h, z26.h
// CHECK-ENCODING: [0x39,0xc8,0x9a,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 819ac839 <unknown>

fmops za1.h, p2/m, p0/m, z22.h, z30.h // 10000001-10011110-00001010-11011001
// CHECK-INST: fmops za1.h, p2/m, p0/m, z22.h, z30.h
// CHECK-ENCODING: [0xd9,0x0a,0x9e,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 819e0ad9 <unknown>

fmops za0.h, p5/m, p7/m, z9.h, z1.h // 10000001-10000001-11110101-00111000
// CHECK-INST: fmops za0.h, p5/m, p7/m, z9.h, z1.h
// CHECK-ENCODING: [0x38,0xf5,0x81,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 8181f538 <unknown>

fmops za1.h, p2/m, p5/m, z12.h, z11.h // 10000001-10001011-10101001-10011001
// CHECK-INST: fmops za1.h, p2/m, p5/m, z12.h, z11.h
// CHECK-ENCODING: [0x99,0xa9,0x8b,0x81]
// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16
// CHECK-UNKNOWN: 818ba999 <unknown>
45 changes: 45 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/fsub-diagnostics.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,45 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Out of range index offset

fsub za.d[w8, 8, vgx2], {z0.d-z1.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .s
// CHECK-NEXT: fsub za.d[w8, 8, vgx2], {z0.d-z1.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fsub za.s[w8, -1, vgx4], {z0.s-z3.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: fsub za.s[w8, -1, vgx4], {z0.s-z3.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select register

fsub za.h[w7, 7, vgx4], {z0.h-z3.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: fsub za.h[w7, 7, vgx4], {z0.h-z3.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fsub za.s[w12, 7, vgx2], {z0.s-z1.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: fsub za.s[w12, 7, vgx2], {z0.s-z1.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector list

fsub za.d[w8, 0, vgx4], {z0.d-z4.d}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
// CHECK-NEXT: fsub za.d[w8, 0, vgx4], {z0.d-z4.d}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fsub za.h[w8, 0, vgx2], {z1.h-z2.h}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
// CHECK-NEXT: fsub za.h[w8, 0, vgx2], {z1.h-z2.h}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

fsub za.s[w8, 0, vgx4], {z1.s-z4.s}
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: fsub za.s[w8, 0, vgx4], {z1.s-z4.s}
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
296 changes: 296 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/fsub.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,296 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-f16f16 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST


fsub za.h[w8, 0], {z0.h - z1.h} // 11000001-10100100-00011100-00001000
// CHECK-INST: fsub za.h[w8, 0, vgx2], { z0.h, z1.h }
// CHECK-ENCODING: [0x08,0x1c,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41c08 <unknown>

fsub za.h[w10, 5, vgx2], {z10.h, z11.h} // 11000001-10100100-01011101-01001101
// CHECK-INST: fsub za.h[w10, 5, vgx2], { z10.h, z11.h }
// CHECK-ENCODING: [0x4d,0x5d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a45d4d <unknown>

fsub za.h[w10, 5], {z10.h - z11.h} // 11000001-10100100-01011101-01001101
// CHECK-INST: fsub za.h[w10, 5, vgx2], { z10.h, z11.h }
// CHECK-ENCODING: [0x4d,0x5d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a45d4d <unknown>

fsub za.h[w11, 7, vgx2], {z12.h, z13.h} // 11000001-10100100-01111101-10001111
// CHECK-INST: fsub za.h[w11, 7, vgx2], { z12.h, z13.h }
// CHECK-ENCODING: [0x8f,0x7d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a47d8f <unknown>

fsub za.h[w11, 7], {z12.h - z13.h} // 11000001-10100100-01111101-10001111
// CHECK-INST: fsub za.h[w11, 7, vgx2], { z12.h, z13.h }
// CHECK-ENCODING: [0x8f,0x7d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a47d8f <unknown>

fsub za.h[w11, 7, vgx2], {z30.h, z31.h} // 11000001-10100100-01111111-11001111
// CHECK-INST: fsub za.h[w11, 7, vgx2], { z30.h, z31.h }
// CHECK-ENCODING: [0xcf,0x7f,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a47fcf <unknown>

fsub za.h[w11, 7], {z30.h - z31.h} // 11000001-10100100-01111111-11001111
// CHECK-INST: fsub za.h[w11, 7, vgx2], { z30.h, z31.h }
// CHECK-ENCODING: [0xcf,0x7f,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a47fcf <unknown>

fsub za.h[w8, 5, vgx2], {z16.h, z17.h} // 11000001-10100100-00011110-00001101
// CHECK-INST: fsub za.h[w8, 5, vgx2], { z16.h, z17.h }
// CHECK-ENCODING: [0x0d,0x1e,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41e0d <unknown>

fsub za.h[w8, 5], {z16.h - z17.h} // 11000001-10100100-00011110-00001101
// CHECK-INST: fsub za.h[w8, 5, vgx2], { z16.h, z17.h }
// CHECK-ENCODING: [0x0d,0x1e,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41e0d <unknown>

fsub za.h[w8, 1, vgx2], {z0.h, z1.h} // 11000001-10100100-00011100-00001001
// CHECK-INST: fsub za.h[w8, 1, vgx2], { z0.h, z1.h }
// CHECK-ENCODING: [0x09,0x1c,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41c09 <unknown>

fsub za.h[w8, 1], {z0.h - z1.h} // 11000001-10100100-00011100-00001001
// CHECK-INST: fsub za.h[w8, 1, vgx2], { z0.h, z1.h }
// CHECK-ENCODING: [0x09,0x1c,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41c09 <unknown>

fsub za.h[w10, 0, vgx2], {z18.h, z19.h} // 11000001-10100100-01011110, 01001000
// CHECK-INST: fsub za.h[w10, 0, vgx2], { z18.h, z19.h }
// CHECK-ENCODING: [0x48,0x5e,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a45e48 <unknown>

fsub za.h[w10, 0], {z18.h - z19.h} // 11000001-10100100-01011110-01001000
// CHECK-INST: fsub za.h[w10, 0, vgx2], { z18.h, z19.h }
// CHECK-ENCODING: [0x48,0x5e,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a45e48 <unknown>

fsub za.h[w8, 0, vgx2], {z12.h, z13.h} // 11000001-10100100-00011101-10001000
// CHECK-INST: fsub za.h[w8, 0, vgx2], { z12.h, z13.h }
// CHECK-ENCODING: [0x88,0x1d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41d88 <unknown>

fsub za.h[w8, 0], {z12.h - z13.h} // 11000001-10100100-00011101-10001000
// CHECK-INST: fsub za.h[w8, 0, vgx2], { z12.h, z13.h }
// CHECK-ENCODING: [0x88,0x1d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41d88 <unknown>

fsub za.h[w10, 1, vgx2], {z0.h, z1.h} // 11000001-10100100-01011100-00001001
// CHECK-INST: fsub za.h[w10, 1, vgx2], { z0.h, z1.h }
// CHECK-ENCODING: [0x09,0x5c,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a45c09 <unknown>

fsub za.h[w10, 1], {z0.h - z1.h} // 11000001-10100100-01011100-00001001
// CHECK-INST: fsub za.h[w10, 1, vgx2], { z0.h, z1.h }
// CHECK-ENCODING: [0x09,0x5c,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a45c09 <unknown>

fsub za.h[w8, 5, vgx2], {z22.h, z23.h} // 11000001-10100100-00011110, 11001101
// CHECK-INST: fsub za.h[w8, 5, vgx2], { z22.h, z23.h }
// CHECK-ENCODING: [0xcd,0x1e,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41ecd <unknown>

fsub za.h[w8, 5], {z22.h - z23.h} // 11000001-10100100-00011110-11001101
// CHECK-INST: fsub za.h[w8, 5, vgx2], { z22.h, z23.h }
// CHECK-ENCODING: [0xcd,0x1e,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a41ecd <unknown>

fsub za.h[w11, 2, vgx2], {z8.h, z9.h} // 11000001-10100100-01111101-00001010
// CHECK-INST: fsub za.h[w11, 2, vgx2], { z8.h, z9.h }
// CHECK-ENCODING: [0x0a,0x7d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a47d0a <unknown>

fsub za.h[w11, 2], {z8.h - z9.h} // 11000001-10100100-01111101-00001010
// CHECK-INST: fsub za.h[w11, 2, vgx2], { z8.h, z9.h }
// CHECK-ENCODING: [0x0a,0x7d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a47d0a <unknown>

fsub za.h[w9, 7, vgx2], {z12.h, z13.h} // 11000001-10100100-00111101-10001111
// CHECK-INST: fsub za.h[w9, 7, vgx2], { z12.h, z13.h }
// CHECK-ENCODING: [0x8f,0x3d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a43d8f <unknown>

fsub za.h[w9, 7], {z12.h - z13.h} // 11000001-10100100-00111101-10001111
// CHECK-INST: fsub za.h[w9, 7, vgx2], { z12.h, z13.h }
// CHECK-ENCODING: [0x8f,0x3d,0xa4,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a43d8f <unknown>


fsub za.h[w8, 0, vgx4], {z0.h - z3.h} // 11000001-10100101-00011100-00001000
// CHECK-INST: fsub za.h[w8, 0, vgx4], { z0.h - z3.h }
// CHECK-ENCODING: [0x08,0x1c,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51c08 <unknown>

fsub za.h[w8, 0], {z0.h - z3.h} // 11000001-10100101-00011100-00001000
// CHECK-INST: fsub za.h[w8, 0, vgx4], { z0.h - z3.h }
// CHECK-ENCODING: [0x08,0x1c,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51c08 <unknown>

fsub za.h[w10, 5, vgx4], {z8.h - z11.h} // 11000001-10100101-01011101-00001101
// CHECK-INST: fsub za.h[w10, 5, vgx4], { z8.h - z11.h }
// CHECK-ENCODING: [0x0d,0x5d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a55d0d <unknown>

fsub za.h[w10, 5], {z8.h - z11.h} // 11000001-10100101-01011101-00001101
// CHECK-INST: fsub za.h[w10, 5, vgx4], { z8.h - z11.h }
// CHECK-ENCODING: [0x0d,0x5d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a55d0d <unknown>

fsub za.h[w11, 7, vgx4], {z12.h - z15.h} // 11000001-10100101-01111101-10001111
// CHECK-INST: fsub za.h[w11, 7, vgx4], { z12.h - z15.h }
// CHECK-ENCODING: [0x8f,0x7d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a57d8f <unknown>

fsub za.h[w11, 7], {z12.h - z15.h} // 11000001-10100101-01111101-10001111
// CHECK-INST: fsub za.h[w11, 7, vgx4], { z12.h - z15.h }
// CHECK-ENCODING: [0x8f,0x7d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a57d8f <unknown>

fsub za.h[w11, 7, vgx4], {z28.h - z31.h} // 11000001-10100101-01111111-10001111
// CHECK-INST: fsub za.h[w11, 7, vgx4], { z28.h - z31.h }
// CHECK-ENCODING: [0x8f,0x7f,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a57f8f <unknown>

fsub za.h[w11, 7], {z28.h - z31.h} // 11000001-10100101-01111111-10001111
// CHECK-INST: fsub za.h[w11, 7, vgx4], { z28.h - z31.h }
// CHECK-ENCODING: [0x8f,0x7f,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a57f8f <unknown>

fsub za.h[w8, 5, vgx4], {z16.h - z19.h} // 11000001-10100101-00011110-00001101
// CHECK-INST: fsub za.h[w8, 5, vgx4], { z16.h - z19.h }
// CHECK-ENCODING: [0x0d,0x1e,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51e0d <unknown>

fsub za.h[w8, 5], {z16.h - z19.h} // 11000001-10100101-00011110-00001101
// CHECK-INST: fsub za.h[w8, 5, vgx4], { z16.h - z19.h }
// CHECK-ENCODING: [0x0d,0x1e,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51e0d <unknown>

fsub za.h[w8, 1, vgx4], {z0.h - z3.h} // 11000001-10100101-00011100-00001001
// CHECK-INST: fsub za.h[w8, 1, vgx4], { z0.h - z3.h }
// CHECK-ENCODING: [0x09,0x1c,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51c09 <unknown>

fsub za.h[w8, 1], {z0.h - z3.h} // 11000001-10100101-00011100-00001001
// CHECK-INST: fsub za.h[w8, 1, vgx4], { z0.h - z3.h }
// CHECK-ENCODING: [0x09,0x1c,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51c09 <unknown>

fsub za.h[w10, 0, vgx4], {z16.h - z19.h} // 11000001-10100101-01011110-00001000
// CHECK-INST: fsub za.h[w10, 0, vgx4], { z16.h - z19.h }
// CHECK-ENCODING: [0x08,0x5e,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a55e08 <unknown>

fsub za.h[w10, 0], {z16.h - z19.h} // 11000001-10100101-01011110-00001000
// CHECK-INST: fsub za.h[w10, 0, vgx4], { z16.h - z19.h }
// CHECK-ENCODING: [0x08,0x5e,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a55e08 <unknown>

fsub za.h[w8, 0, vgx4], {z12.h - z15.h} // 11000001-10100101-00011101-10001000
// CHECK-INST: fsub za.h[w8, 0, vgx4], { z12.h - z15.h }
// CHECK-ENCODING: [0x88,0x1d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51d88 <unknown>

fsub za.h[w8, 0], {z12.h - z15.h} // 11000001-10100101-00011101-10001000
// CHECK-INST: fsub za.h[w8, 0, vgx4], { z12.h - z15.h }
// CHECK-ENCODING: [0x88,0x1d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51d88 <unknown>

fsub za.h[w10, 1, vgx4], {z0.h - z3.h} // 11000001-10100101-01011100-00001001
// CHECK-INST: fsub za.h[w10, 1, vgx4], { z0.h - z3.h }
// CHECK-ENCODING: [0x09,0x5c,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a55c09 <unknown>

fsub za.h[w10, 1], {z0.h - z3.h} // 11000001-10100101-01011100-00001001
// CHECK-INST: fsub za.h[w10, 1, vgx4], { z0.h - z3.h }
// CHECK-ENCODING: [0x09,0x5c,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a55c09 <unknown>

fsub za.h[w8, 5, vgx4], {z20.h - z23.h} // 11000001-10100101-00011110-10001101
// CHECK-INST: fsub za.h[w8, 5, vgx4], { z20.h - z23.h }
// CHECK-ENCODING: [0x8d,0x1e,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51e8d <unknown>

fsub za.h[w8, 5], {z20.h - z23.h} // 11000001-10100101-00011110-10001101
// CHECK-INST: fsub za.h[w8, 5, vgx4], { z20.h - z23.h }
// CHECK-ENCODING: [0x8d,0x1e,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a51e8d <unknown>

fsub za.h[w11, 2, vgx4], {z8.h - z11.h} // 11000001-10100101-01111101-00001010
// CHECK-INST: fsub za.h[w11, 2, vgx4], { z8.h - z11.h }
// CHECK-ENCODING: [0x0a,0x7d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a57d0a <unknown>

fsub za.h[w11, 2], {z8.h - z11.h} // 11000001-10100101-01111101-00001010
// CHECK-INST: fsub za.h[w11, 2, vgx4], { z8.h - z11.h }
// CHECK-ENCODING: [0x0a,0x7d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a57d0a <unknown>

fsub za.h[w9, 7, vgx4], {z12.h - z15.h} // 11000001-10100101-00111101-10001111
// CHECK-INST: fsub za.h[w9, 7, vgx4], { z12.h - z15.h }
// CHECK-ENCODING: [0x8f,0x3d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a53d8f <unknown>

fsub za.h[w9, 7], {z12.h - z15.h} // 11000001-10100101-00111101-10001111
// CHECK-INST: fsub za.h[w9, 7, vgx4], { z12.h - z15.h }
// CHECK-ENCODING: [0x8f,0x3d,0xa5,0xc1]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c1a53d8f <unknown>
70 changes: 70 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/luti2-diagnostics.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,70 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid lane indices

luti2 {z0.h, z8.h}, zt0, z0[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: luti2 {z0.h, z8.h}, zt0, z0[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti2 {z0.h, z8.h}, zt0, z0[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: luti2 {z0.h, z8.h}, zt0, z0[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti2 {z0.h, z8.h}, zt0, z0[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: luti2 {z0.h, z8.h}, zt0, z0[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti2 {z0.h, z8.h}, zt0, z0[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: luti2 {z0.h, z8.h}, zt0, z0[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti2 {z0.b, z8.b}, zt0, z0[8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: luti2 {z0.b, z8.b}, zt0, z0[8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti2 {z0.b, z8.b}, zt0, z0[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 7].
// CHECK-NEXT: luti2 {z0.b, z8.b}, zt0, z0[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti2 {z19.h, z23.h, z27.h, z31.h}, zt0, z31[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: luti2 {z19.h, z23.h, z27.h, z31.h}, zt0, z31[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti2 {z19.h, z23.h, z27.h, z31.h}, zt0, z31[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: luti2 {z19.h, z23.h, z27.h, z31.h}, zt0, z31[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti2 {z19.b, z23.b, z27.b, z31.b}, zt0, z31[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: luti2 {z19.b, z23.b, z27.b, z31.b}, zt0, z31[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti2 {z19.b, z23.b, z27.b, z31.b}, zt0, z31[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: luti2 {z19.b, z23.b, z27.b, z31.b}, zt0, z31[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector lists

luti2 {z0.h, z9.h}, zt0, z0[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: luti2 {z0.h, z9.h}, zt0, z0[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector suffix

luti2 {z0.d, z2.d}, zt0, z0[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: luti2 {z0.d, z2.d}, zt0, z0[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
115 changes: 115 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/luti2.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,115 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sme2p1 - \
// RUN: | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sme2p1 - \
// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST


luti2 {z0.h, z8.h}, zt0, z0[0] // 11000000-10011100-01010000-00000000
// CHECK-INST: luti2 { z0.h, z8.h }, zt0, z0[0]
// CHECK-ENCODING: [0x00,0x50,0x9c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09c5000 <unknown>

luti2 {z21.h, z29.h}, zt0, z10[2] // 11000000-10011101-01010001-01010101
// CHECK-INST: luti2 { z21.h, z29.h }, zt0, z10[2]
// CHECK-ENCODING: [0x55,0x51,0x9d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09d5155 <unknown>

luti2 {z23.h, z31.h}, zt0, z13[1] // 11000000-10011100-11010001-10110111
// CHECK-INST: luti2 { z23.h, z31.h }, zt0, z13[1]
// CHECK-ENCODING: [0xb7,0xd1,0x9c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09cd1b7 <unknown>

luti2 {z23.h, z31.h}, zt0, z31[7] // 11000000-10011111-11010011-11110111
// CHECK-INST: luti2 { z23.h, z31.h }, zt0, z31[7]
// CHECK-ENCODING: [0xf7,0xd3,0x9f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09fd3f7 <unknown>


luti2 {z0.b, z8.b}, zt0, z0[0] // 11000000-10011100-01000000-00000000
// CHECK-INST: luti2 { z0.b, z8.b }, zt0, z0[0]
// CHECK-ENCODING: [0x00,0x40,0x9c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09c4000 <unknown>

luti2 {z21.b, z29.b}, zt0, z10[2] // 11000000-10011101-01000001-01010101
// CHECK-INST: luti2 { z21.b, z29.b }, zt0, z10[2]
// CHECK-ENCODING: [0x55,0x41,0x9d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09d4155 <unknown>

luti2 {z23.b, z31.b}, zt0, z13[1] // 11000000-10011100-11000001-10110111
// CHECK-INST: luti2 { z23.b, z31.b }, zt0, z13[1]
// CHECK-ENCODING: [0xb7,0xc1,0x9c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09cc1b7 <unknown>

luti2 {z23.b, z31.b}, zt0, z31[7] // 11000000-10011111-11000011-11110111
// CHECK-INST: luti2 { z23.b, z31.b }, zt0, z31[7]
// CHECK-ENCODING: [0xf7,0xc3,0x9f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09fc3f7 <unknown>


luti2 {z0.h, z4.h, z8.h, z12.h}, zt0, z0[0] // 11000000-10011100-10010000-00000000
// CHECK-INST: luti2 { z0.h, z4.h, z8.h, z12.h }, zt0, z0[0]
// CHECK-ENCODING: [0x00,0x90,0x9c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09c9000 <unknown>

luti2 {z17.h, z21.h, z25.h, z29.h}, zt0, z10[1] // 11000000-10011101-10010001-01010001
// CHECK-INST: luti2 { z17.h, z21.h, z25.h, z29.h }, zt0, z10[1]
// CHECK-ENCODING: [0x51,0x91,0x9d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09d9151 <unknown>

luti2 {z19.h, z23.h, z27.h, z31.h}, zt0, z13[0] // 11000000-10011100-10010001-10110011
// CHECK-INST: luti2 { z19.h, z23.h, z27.h, z31.h }, zt0, z13[0]
// CHECK-ENCODING: [0xb3,0x91,0x9c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09c91b3 <unknown>

luti2 {z19.h, z23.h, z27.h, z31.h}, zt0, z31[3] // 11000000-10011111-10010011-11110011
// CHECK-INST: luti2 { z19.h, z23.h, z27.h, z31.h }, zt0, z31[3]
// CHECK-ENCODING: [0xf3,0x93,0x9f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09f93f3 <unknown>


luti2 {z0.b, z4.b, z8.b, z12.b}, zt0, z0[0] // 11000000-10011100-10000000-00000000
// CHECK-INST: luti2 { z0.b, z4.b, z8.b, z12.b }, zt0, z0[0]
// CHECK-ENCODING: [0x00,0x80,0x9c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09c8000 <unknown>

luti2 {z17.b, z21.b, z25.b, z29.b}, zt0, z10[1] // 11000000-10011101-10000001-01010001
// CHECK-INST: luti2 { z17.b, z21.b, z25.b, z29.b }, zt0, z10[1]
// CHECK-ENCODING: [0x51,0x81,0x9d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09d8151 <unknown>

luti2 {z19.b, z23.b, z27.b, z31.b}, zt0, z13[0] // 11000000-10011100-10000001-10110011
// CHECK-INST: luti2 { z19.b, z23.b, z27.b, z31.b }, zt0, z13[0]
// CHECK-ENCODING: [0xb3,0x81,0x9c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09c81b3 <unknown>

luti2 {z19.b, z23.b, z27.b, z31.b}, zt0, z31[3] // 11000000-10011111-10000011-11110011
// CHECK-INST: luti2 { z19.b, z23.b, z27.b, z31.b }, zt0, z31[3]
// CHECK-ENCODING: [0xf3,0x83,0x9f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09f83f3 <unknown>

63 changes: 63 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/luti4-diagnostics.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,63 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Invalid lane indices

luti4 {z0.h, z8.h}, zt0, z0[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: luti4 {z0.h, z8.h}, zt0, z0[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti4 {z0.h, z8.h}, zt0, z0[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: luti4 {z0.h, z8.h}, zt0, z0[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti4 {z0.h, z8.h}, zt0, z0[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: luti4 {z0.h, z8.h}, zt0, z0[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti4 {z0.h, z8.h}, zt0, z0[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: luti4 {z0.h, z8.h}, zt0, z0[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti4 {z0.b, z8.b}, zt0, z0[4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: luti4 {z0.b, z8.b}, zt0, z0[4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti4 {z0.b, z8.b}, zt0, z0[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 3].
// CHECK-NEXT: luti4 {z0.b, z8.b}, zt0, z0[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti4 {z19.h, z23.h, z27.h, z31.h}, zt0, z31[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: luti4 {z19.h, z23.h, z27.h, z31.h}, zt0, z31[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti4 {z19.h, z23.h, z27.h, z31.h}, zt0, z31[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: luti4 {z19.h, z23.h, z27.h, z31.h}, zt0, z31[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti4 {z19.h, z23.h, z27.h, z31.h}, zt0, z31[2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: luti4 {z19.h, z23.h, z27.h, z31.h}, zt0, z31[2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

luti4 {z19.h, z23.h, z27.h, z31.h}, zt0, z31[-1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector lane must be an integer in range [0, 1].
// CHECK-NEXT: luti4 {z19.h, z23.h, z27.h, z31.h}, zt0, z31[-1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector lists

luti4 {z1.s-z4.s}, zt0, z0[3]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
// CHECK-NEXT: luti4 {z1.s-z4.s}, zt0, z0[3]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

89 changes: 89 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/luti4.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,89 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sme2p1 - \
// RUN: | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sme2p1 - \
// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST


luti4 {z0.h, z8.h}, zt0, z0[0] // 11000000-10011010-01010000-00000000
// CHECK-INST: luti4 { z0.h, z8.h }, zt0, z0[0]
// CHECK-ENCODING: [0x00,0x50,0x9a,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09a5000 <unknown>

luti4 {z21.h, z29.h}, zt0, z10[2] // 11000000-10011011-01010001-01010101
// CHECK-INST: luti4 { z21.h, z29.h }, zt0, z10[2]
// CHECK-ENCODING: [0x55,0x51,0x9b,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09b5155 <unknown>

luti4 {z23.h, z31.h}, zt0, z13[1] // 11000000-10011010-11010001-10110111
// CHECK-INST: luti4 { z23.h, z31.h }, zt0, z13[1]
// CHECK-ENCODING: [0xb7,0xd1,0x9a,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09ad1b7 <unknown>

luti4 {z23.h, z31.h}, zt0, z31[3] // 11000000-10011011-11010011-11110111
// CHECK-INST: luti4 { z23.h, z31.h }, zt0, z31[3]
// CHECK-ENCODING: [0xf7,0xd3,0x9b,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09bd3f7 <unknown>


luti4 {z0.b, z8.b}, zt0, z0[0] // 11000000-10011010-01000000-00000000
// CHECK-INST: luti4 { z0.b, z8.b }, zt0, z0[0]
// CHECK-ENCODING: [0x00,0x40,0x9a,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09a4000 <unknown>

luti4 {z21.b, z29.b}, zt0, z10[2] // 11000000-10011011-01000001-01010101
// CHECK-INST: luti4 { z21.b, z29.b }, zt0, z10[2]
// CHECK-ENCODING: [0x55,0x41,0x9b,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09b4155 <unknown>

luti4 {z23.b, z31.b}, zt0, z13[1] // 11000000-10011010-11000001-10110111
// CHECK-INST: luti4 { z23.b, z31.b }, zt0, z13[1]
// CHECK-ENCODING: [0xb7,0xc1,0x9a,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09ac1b7 <unknown>

luti4 {z23.b, z31.b}, zt0, z31[3] // 11000000-10011011-11000011-11110111
// CHECK-INST: luti4 { z23.b, z31.b }, zt0, z31[3]
// CHECK-ENCODING: [0xf7,0xc3,0x9b,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09bc3f7 <unknown>


luti4 {z0.h, z4.h, z8.h, z12.h}, zt0, z0[0] // 11000000-10011010-10010000-00000000
// CHECK-INST: luti4 { z0.h, z4.h, z8.h, z12.h }, zt0, z0[0]
// CHECK-ENCODING: [0x00,0x90,0x9a,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09a9000 <unknown>

luti4 {z17.h, z21.h, z25.h, z29.h}, zt0, z10[1] // 11000000-10011011-10010001-01010001
// CHECK-INST: luti4 { z17.h, z21.h, z25.h, z29.h }, zt0, z10[1]
// CHECK-ENCODING: [0x51,0x91,0x9b,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09b9151 <unknown>

luti4 {z19.h, z23.h, z27.h, z31.h}, zt0, z13[0] // 11000000-10011010-10010001-10110011
// CHECK-INST: luti4 { z19.h, z23.h, z27.h, z31.h }, zt0, z13[0]
// CHECK-ENCODING: [0xb3,0x91,0x9a,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09a91b3 <unknown>

luti4 {z19.h, z23.h, z27.h, z31.h}, zt0, z31[1] // 11000000-10011011-10010011-11110011
// CHECK-INST: luti4 { z19.h, z23.h, z27.h, z31.h }, zt0, z31[1]
// CHECK-ENCODING: [0xf3,0x93,0x9b,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c09b93f3 <unknown>
100 changes: 100 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/movaz-diagnostics.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,100 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Out of range index offset

movaz {z0.h-z1.h}, za0h.h[w12, 1:2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 2 in the range [0, 6] or [0, 14] depending on the instruction, and the second immediate is immf + 1.
// CHECK-NEXT: movaz {z0.h-z1.h}, za0h.h[w12, 1:2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movaz {z0.b-z3.b}, za0v.b[w12, 1:4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 4 in the range [0, 4] or [0, 12] depending on the instruction, and the second immediate is immf + 3.
// CHECK-NEXT: movaz {z0.b-z3.b}, za0v.b[w12, 1:4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movaz {z0.s-z1.s}, za0h.s[w12, 0:2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: movaz {z0.s-z1.s}, za0h.s[w12, 0:2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movaz {z0.d-z3.d}, za0h.d[w12, 0:4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: movaz {z0.d-z3.d}, za0h.d[w12, 0:4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movaz {z4.d-z7.d}, za.d[w9, 8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: movaz {z4.d-z7.d}, za.d[w9, 8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movaz {z4.d-z7.d}, za.d[w9, -1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: movaz {z4.d-z7.d}, za.d[w9, -1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movaz z1.q, za1h.q[w12, 1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be 0.
// CHECK-NEXT: movaz z1.q, za1h.q[w12, 1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movaz z31.h, za1h.h[w15, 8]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: movaz z31.h, za1h.h[w15, 8]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movaz z31.h, za1h.h[w15, -1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: movaz z31.h, za1h.h[w15, -1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movaz z2.b, za0v.b[w15, -1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
// CHECK-NEXT: movaz z2.b, za0v.b[w15, -1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movaz z2.b, za0v.b[w15, 16]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
// CHECK-NEXT: movaz z2.b, za0v.b[w15, 16]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movaz z31.s, za1h.s[w15, 4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3].
// CHECK-NEXT: movaz z31.s, za1h.s[w15, 4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movaz z31.s, za1h.s[w15, -1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3].
// CHECK-NEXT: movaz z31.s, za1h.s[w15, -1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movaz z31.d, za1v.d[w15, 2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
// CHECK-NEXT: movaz z31.d, za1v.d[w15, 2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movaz z31.d, za1h.d[w15, -1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
// CHECK-NEXT: movaz z31.d, za1h.d[w15, -1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid vector select register

movaz z0.h, za0v.h[w11, 0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: movaz z0.h, za0v.h[w11, 0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

movaz z0.h, za0v.h[w16, 0]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w12, w15]
// CHECK-NEXT: movaz z0.h, za0v.h[w16, 0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid matrix operand

movaz z31.s, za1h.d[w15, -1]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected za[0-3]h.s or za[0-3]v.s
// CHECK-NEXT: movaz z31.s, za1h.d[w15, -1]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
1,022 changes: 1,022 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/movaz.s
View file

Large diffs are not rendered by default.

60 changes: 60 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/zero-diagnostics.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,60 @@
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 2>&1 < %s | FileCheck %s

// --------------------------------------------------------------------------//
// Out of range index offset

zero za.d[w11, 8, vgx2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: zero za.d[w11, 8, vgx2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

zero za.d[w11, -1, vgx4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: zero za.d[w11, -1, vgx4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

zero za.d[w11, 5:8, vgx4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 4 in the range [0, 4] or [0, 12] depending on the instruction, and the second immediate is immf + 3.
// CHECK-NEXT: zero za.d[w11, 5:8, vgx4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

zero za.d[w11, 5:8, vgx2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: vector select offset must be an immediate range of the form <immf>:<imml>, where the first immediate is a multiple of 4 in the range [0, 4] or [0, 12] depending on the instruction, and the second immediate is immf + 3.
// CHECK-NEXT: zero za.d[w11, 5:8, vgx2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

zero za.d[w11, 0:4, vgx4]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: zero za.d[w11, 0:4, vgx4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

zero za.d[w11, 0:4, vgx2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: zero za.d[w11, 0:4, vgx2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

zero za.d[w11, 11:15]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
// CHECK-NEXT: zero za.d[w11, 11:15]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid select register

zero za.d[w7, 7, vgx2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: zero za.d[w7, 7, vgx2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

zero za.d[w12, 7, vgx2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
// CHECK-NEXT: zero za.d[w12, 7, vgx2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

// --------------------------------------------------------------------------//
// Invalid suffix

zero za.s[w11, 7, vgx2]
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .d
// CHECK-NEXT: zero za.s[w11, 7, vgx2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
394 changes: 394 additions & 0 deletions llvm/test/MC/AArch64/SME2p1/zero.s
View file
Original file line number Diff line number Diff line change
@@ -0,0 +1,394 @@
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=+sme2p1 - \
// RUN: | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump --no-print-imm-hex -d --mattr=-sme2p1 - \
// RUN: | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST

zero za.d[w8, 0:1] // 11000000-00001100-10000000-00000000
// CHECK-INST: zero za.d[w8, 0:1]
// CHECK-ENCODING: [0x00,0x80,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00c8000 <unknown>

zero za.d[w10, 10:11] // 11000000-00001100-11000000-00000101
// CHECK-INST: zero za.d[w10, 10:11]
// CHECK-ENCODING: [0x05,0xc0,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00cc005 <unknown>

zero za.d[w11, 14:15] // 11000000-00001100-11100000-00000111
// CHECK-INST: zero za.d[w11, 14:15]
// CHECK-ENCODING: [0x07,0xe0,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00ce007 <unknown>

zero za.d[w8, 10:11] // 11000000-00001100-10000000-00000101
// CHECK-INST: zero za.d[w8, 10:11]
// CHECK-ENCODING: [0x05,0x80,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00c8005 <unknown>

zero za.d[w8, 2:3] // 11000000-00001100-10000000-00000001
// CHECK-INST: zero za.d[w8, 2:3]
// CHECK-ENCODING: [0x01,0x80,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00c8001 <unknown>

zero za.d[w10, 0:1] // 11000000-00001100-11000000-00000000
// CHECK-INST: zero za.d[w10, 0:1]
// CHECK-ENCODING: [0x00,0xc0,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00cc000 <unknown>

zero za.d[w10, 2:3] // 11000000-00001100-11000000-00000001
// CHECK-INST: zero za.d[w10, 2:3]
// CHECK-ENCODING: [0x01,0xc0,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00cc001 <unknown>

zero za.d[w11, 4:5] // 11000000-00001100-11100000-00000010
// CHECK-INST: zero za.d[w11, 4:5]
// CHECK-ENCODING: [0x02,0xe0,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00ce002 <unknown>

zero za.d[w9, 14:15] // 11000000-00001100-10100000-00000111
// CHECK-INST: zero za.d[w9, 14:15]
// CHECK-ENCODING: [0x07,0xa0,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00ca007 <unknown>


zero za.d[w8, 0:3] // 11000000-00001110-10000000-00000000
// CHECK-INST: zero za.d[w8, 0:3]
// CHECK-ENCODING: [0x00,0x80,0x0e,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00e8000 <unknown>

zero za.d[w10, 4:7] // 11000000-00001110-11000000-00000001
// CHECK-INST: zero za.d[w10, 4:7]
// CHECK-ENCODING: [0x01,0xc0,0x0e,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00ec001 <unknown>

zero za.d[w11, 12:15] // 11000000-00001110-11100000-00000011
// CHECK-INST: zero za.d[w11, 12:15]
// CHECK-ENCODING: [0x03,0xe0,0x0e,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00ee003 <unknown>

zero za.d[w8, 4:7] // 11000000-00001110-10000000-00000001
// CHECK-INST: zero za.d[w8, 4:7]
// CHECK-ENCODING: [0x01,0x80,0x0e,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00e8001 <unknown>

zero za.d[w10, 0:3] // 11000000-00001110-11000000-00000000
// CHECK-INST: zero za.d[w10, 0:3]
// CHECK-ENCODING: [0x00,0xc0,0x0e,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00ec000 <unknown>

zero za.d[w11, 8:11] // 11000000-00001110-11100000-00000010
// CHECK-INST: zero za.d[w11, 8:11]
// CHECK-ENCODING: [0x02,0xe0,0x0e,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00ee002 <unknown>

zero za.d[w9, 12:15] // 11000000-00001110-10100000-00000011
// CHECK-INST: zero za.d[w9, 12:15]
// CHECK-ENCODING: [0x03,0xa0,0x0e,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00ea003 <unknown>


zero za.d[w8, 0, vgx2] // 11000000-00001100-00000000-00000000
// CHECK-INST: zero za.d[w8, 0, vgx2]
// CHECK-ENCODING: [0x00,0x00,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00c0000 <unknown>

zero za.d[w10, 5, vgx2] // 11000000-00001100-01000000-00000101
// CHECK-INST: zero za.d[w10, 5, vgx2]
// CHECK-ENCODING: [0x05,0x40,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00c4005 <unknown>

zero za.d[w11, 7, vgx2] // 11000000-00001100-01100000-00000111
// CHECK-INST: zero za.d[w11, 7, vgx2]
// CHECK-ENCODING: [0x07,0x60,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00c6007 <unknown>

zero za.d[w8, 5, vgx2] // 11000000-00001100-00000000-00000101
// CHECK-INST: zero za.d[w8, 5, vgx2]
// CHECK-ENCODING: [0x05,0x00,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00c0005 <unknown>

zero za.d[w8, 1, vgx2] // 11000000-00001100-00000000-00000001
// CHECK-INST: zero za.d[w8, 1, vgx2]
// CHECK-ENCODING: [0x01,0x00,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00c0001 <unknown>

zero za.d[w10, 0, vgx2] // 11000000-00001100-01000000-00000000
// CHECK-INST: zero za.d[w10, 0, vgx2]
// CHECK-ENCODING: [0x00,0x40,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00c4000 <unknown>

zero za.d[w10, 1, vgx2] // 11000000-00001100-01000000-00000001
// CHECK-INST: zero za.d[w10, 1, vgx2]
// CHECK-ENCODING: [0x01,0x40,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00c4001 <unknown>

zero za.d[w11, 2, vgx2] // 11000000-00001100-01100000-00000010
// CHECK-INST: zero za.d[w11, 2, vgx2]
// CHECK-ENCODING: [0x02,0x60,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00c6002 <unknown>

zero za.d[w9, 7, vgx2] // 11000000-00001100-00100000-00000111
// CHECK-INST: zero za.d[w9, 7, vgx2]
// CHECK-ENCODING: [0x07,0x20,0x0c,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00c2007 <unknown>


zero za.d[w8, 0:1, vgx2] // 11000000-00001101-00000000-00000000
// CHECK-INST: zero za.d[w8, 0:1, vgx2]
// CHECK-ENCODING: [0x00,0x00,0x0d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00d0000 <unknown>

zero za.d[w10, 2:3, vgx2] // 11000000-00001101-01000000-00000001
// CHECK-INST: zero za.d[w10, 2:3, vgx2]
// CHECK-ENCODING: [0x01,0x40,0x0d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00d4001 <unknown>

zero za.d[w11, 6:7, vgx2] // 11000000-00001101-01100000-00000011
// CHECK-INST: zero za.d[w11, 6:7, vgx2]
// CHECK-ENCODING: [0x03,0x60,0x0d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00d6003 <unknown>

zero za.d[w8, 2:3, vgx2] // 11000000-00001101-00000000-00000001
// CHECK-INST: zero za.d[w8, 2:3, vgx2]
// CHECK-ENCODING: [0x01,0x00,0x0d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00d0001 <unknown>

zero za.d[w10, 0:1, vgx2] // 11000000-00001101-01000000-00000000
// CHECK-INST: zero za.d[w10, 0:1, vgx2]
// CHECK-ENCODING: [0x00,0x40,0x0d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00d4000 <unknown>

zero za.d[w11, 4:5, vgx2] // 11000000-00001101-01100000-00000010
// CHECK-INST: zero za.d[w11, 4:5, vgx2]
// CHECK-ENCODING: [0x02,0x60,0x0d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00d6002 <unknown>

zero za.d[w9, 6:7, vgx2] // 11000000-00001101-00100000-00000011
// CHECK-INST: zero za.d[w9, 6:7, vgx2]
// CHECK-ENCODING: [0x03,0x20,0x0d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00d2003 <unknown>


zero za.d[w8, 0:3, vgx2] // 11000000-00001111-00000000-00000000
// CHECK-INST: zero za.d[w8, 0:3, vgx2]
// CHECK-ENCODING: [0x00,0x00,0x0f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00f0000 <unknown>

zero za.d[w10, 4:7, vgx2] // 11000000-00001111-01000000-00000001
// CHECK-INST: zero za.d[w10, 4:7, vgx2]
// CHECK-ENCODING: [0x01,0x40,0x0f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00f4001 <unknown>

zero za.d[w11, 4:7, vgx2] // 11000000-00001111-01100000-00000001
// CHECK-INST: zero za.d[w11, 4:7, vgx2]
// CHECK-ENCODING: [0x01,0x60,0x0f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00f6001 <unknown>

zero za.d[w8, 4:7, vgx2] // 11000000-00001111-00000000-00000001
// CHECK-INST: zero za.d[w8, 4:7, vgx2]
// CHECK-ENCODING: [0x01,0x00,0x0f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00f0001 <unknown>

zero za.d[w10, 0:3, vgx2] // 11000000-00001111-01000000-00000000
// CHECK-INST: zero za.d[w10, 0:3, vgx2]
// CHECK-ENCODING: [0x00,0x40,0x0f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00f4000 <unknown>

zero za.d[w11, 0:3, vgx2] // 11000000-00001111-01100000-00000000
// CHECK-INST: zero za.d[w11, 0:3, vgx2]
// CHECK-ENCODING: [0x00,0x60,0x0f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00f6000 <unknown>

zero za.d[w9, 4:7, vgx2] // 11000000-00001111-00100000-00000001
// CHECK-INST: zero za.d[w9, 4:7, vgx2]
// CHECK-ENCODING: [0x01,0x20,0x0f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00f2001 <unknown>


zero za.d[w8, 0, vgx4] // 11000000-00001110-00000000-00000000
// CHECK-INST: zero za.d[w8, 0, vgx4]
// CHECK-ENCODING: [0x00,0x00,0x0e,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00e0000 <unknown>

zero za.d[w10, 5, vgx4] // 11000000-00001110-01000000-00000101
// CHECK-INST: zero za.d[w10, 5, vgx4]
// CHECK-ENCODING: [0x05,0x40,0x0e,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00e4005 <unknown>

zero za.d[w11, 7, vgx4] // 11000000-00001110-01100000-00000111
// CHECK-INST: zero za.d[w11, 7, vgx4]
// CHECK-ENCODING: [0x07,0x60,0x0e,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00e6007 <unknown>

zero za.d[w8, 5, vgx4] // 11000000-00001110-00000000-00000101
// CHECK-INST: zero za.d[w8, 5, vgx4]
// CHECK-ENCODING: [0x05,0x00,0x0e,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00e0005 <unknown>

zero za.d[w8, 1, vgx4] // 11000000-00001110-00000000-00000001
// CHECK-INST: zero za.d[w8, 1, vgx4]
// CHECK-ENCODING: [0x01,0x00,0x0e,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00e0001 <unknown>

zero za.d[w10, 0, vgx4] // 11000000-00001110-01000000-00000000
// CHECK-INST: zero za.d[w10, 0, vgx4]
// CHECK-ENCODING: [0x00,0x40,0x0e,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00e4000 <unknown>

zero za.d[w10, 1, vgx4] // 11000000-00001110-01000000-00000001
// CHECK-INST: zero za.d[w10, 1, vgx4]
// CHECK-ENCODING: [0x01,0x40,0x0e,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00e4001 <unknown>

zero za.d[w11, 2, vgx4] // 11000000-00001110-01100000-00000010
// CHECK-INST: zero za.d[w11, 2, vgx4]
// CHECK-ENCODING: [0x02,0x60,0x0e,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00e6002 <unknown>

zero za.d[w9, 7, vgx4] // 11000000-00001110-00100000-00000111
// CHECK-INST: zero za.d[w9, 7, vgx4]
// CHECK-ENCODING: [0x07,0x20,0x0e,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00e2007 <unknown>


zero za.d[w8, 0:1, vgx4] // 11000000-00001101-10000000-00000000
// CHECK-INST: zero za.d[w8, 0:1, vgx4]
// CHECK-ENCODING: [0x00,0x80,0x0d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00d8000 <unknown>

zero za.d[w10, 2:3, vgx4] // 11000000-00001101-11000000-00000001
// CHECK-INST: zero za.d[w10, 2:3, vgx4]
// CHECK-ENCODING: [0x01,0xc0,0x0d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00dc001 <unknown>

zero za.d[w11, 6:7, vgx4] // 11000000-00001101-11100000-00000011
// CHECK-INST: zero za.d[w11, 6:7, vgx4]
// CHECK-ENCODING: [0x03,0xe0,0x0d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00de003 <unknown>

zero za.d[w8, 2:3, vgx4] // 11000000-00001101-10000000-00000001
// CHECK-INST: zero za.d[w8, 2:3, vgx4]
// CHECK-ENCODING: [0x01,0x80,0x0d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00d8001 <unknown>

zero za.d[w10, 0:1, vgx4] // 11000000-00001101-11000000-00000000
// CHECK-INST: zero za.d[w10, 0:1, vgx4]
// CHECK-ENCODING: [0x00,0xc0,0x0d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00dc000 <unknown>

zero za.d[w11, 4:5, vgx4] // 11000000-00001101-11100000-00000010
// CHECK-INST: zero za.d[w11, 4:5, vgx4]
// CHECK-ENCODING: [0x02,0xe0,0x0d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00de002 <unknown>

zero za.d[w9, 6:7, vgx4] // 11000000-00001101-10100000-00000011
// CHECK-INST: zero za.d[w9, 6:7, vgx4]
// CHECK-ENCODING: [0x03,0xa0,0x0d,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00da003 <unknown>


zero za.d[w8, 0:3, vgx4] // 11000000-00001111-10000000-00000000
// CHECK-INST: zero za.d[w8, 0:3, vgx4]
// CHECK-ENCODING: [0x00,0x80,0x0f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00f8000 <unknown>

zero za.d[w10, 4:7, vgx4] // 11000000-00001111-11000000-00000001
// CHECK-INST: zero za.d[w10, 4:7, vgx4]
// CHECK-ENCODING: [0x01,0xc0,0x0f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00fc001 <unknown>

zero za.d[w11, 4:7, vgx4] // 11000000-00001111-11100000-00000001
// CHECK-INST: zero za.d[w11, 4:7, vgx4]
// CHECK-ENCODING: [0x01,0xe0,0x0f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00fe001 <unknown>

zero za.d[w8, 4:7, vgx4] // 11000000-00001111-10000000-00000001
// CHECK-INST: zero za.d[w8, 4:7, vgx4]
// CHECK-ENCODING: [0x01,0x80,0x0f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00f8001 <unknown>

zero za.d[w10, 0:3, vgx4] // 11000000-00001111-11000000-00000000
// CHECK-INST: zero za.d[w10, 0:3, vgx4]
// CHECK-ENCODING: [0x00,0xc0,0x0f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00fc000 <unknown>

zero za.d[w11, 0:3, vgx4] // 11000000-00001111-11100000-00000000
// CHECK-INST: zero za.d[w11, 0:3, vgx4]
// CHECK-ENCODING: [0x00,0xe0,0x0f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00fe000 <unknown>

zero za.d[w9, 4:7, vgx4] // 11000000-00001111-10100000-00000001
// CHECK-INST: zero za.d[w9, 4:7, vgx4]
// CHECK-ENCODING: [0x01,0xa0,0x0f,0xc0]
// CHECK-ERROR: instruction requires: sme2p1
// CHECK-UNKNOWN: c00fa001 <unknown>

4 changes: 3 additions & 1 deletion llvm/unittests/Support/TargetParserTest.cpp
View file
Original file line number Diff line number Diff line change
Expand Up @@ -1598,7 +1598,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
AArch64::AEK_SME, AArch64::AEK_SMEF64F64, AArch64::AEK_SMEI16I64,
AArch64::AEK_SME2, AArch64::AEK_HBC, AArch64::AEK_MOPS,
AArch64::AEK_PERFMON, AArch64::AEK_SVE2p1, AArch64::AEK_SME2p1,
AArch64::AEK_B16B16};
AArch64::AEK_B16B16, AArch64::AEK_SMEF16F16};

std::vector<StringRef> Features;

Expand Down Expand Up @@ -1657,6 +1657,7 @@ TEST(TargetParserTest, AArch64ExtensionFeatures) {
EXPECT_TRUE(llvm::is_contained(Features, "+sme"));
EXPECT_TRUE(llvm::is_contained(Features, "+sme-f64f64"));
EXPECT_TRUE(llvm::is_contained(Features, "+sme-i16i64"));
EXPECT_TRUE(llvm::is_contained(Features, "+sme-f16f16"));
EXPECT_TRUE(llvm::is_contained(Features, "+sme2"));
EXPECT_TRUE(llvm::is_contained(Features, "+sme2p1"));
EXPECT_TRUE(llvm::is_contained(Features, "+hbc"));
Expand Down Expand Up @@ -1739,6 +1740,7 @@ TEST(TargetParserTest, AArch64ArchExtFeature) {
{"sme", "nosme", "+sme", "-sme"},
{"sme-f64f64", "nosme-f64f64", "+sme-f64f64", "-sme-f64f64"},
{"sme-i16i64", "nosme-i16i64", "+sme-i16i64", "-sme-i16i64"},
{"sme-f16f16", "nosme-f16f16", "+sme-f16f16", "-sme-f16f16"},
{"sme2", "nosme2", "+sme2", "-sme2"},
{"sme2p1", "nosme2p1", "+sme2p1", "-sme2p1"},
{"hbc", "nohbc", "+hbc", "-hbc"},
Expand Down