1,290 changes: 654 additions & 636 deletions llvm/test/CodeGen/RISCV/atomic-cmpxchg.ll
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10,598 changes: 5,359 additions & 5,239 deletions llvm/test/CodeGen/RISCV/atomic-rmw.ll
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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/bare-select.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -5,12 +5,12 @@
define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
; RV32I-LABEL: bare_select:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: bnez a0, .LBB0_2
; RV32I-NEXT: andi a3, a0, 1
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: bnez a3, .LBB0_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB0_2:
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
%1 = select i1 %a, i32 %b, i32 %c
ret i32 %1
Expand All @@ -19,12 +19,12 @@ define i32 @bare_select(i1 %a, i32 %b, i32 %c) nounwind {
define float @bare_select_float(i1 %a, float %b, float %c) nounwind {
; RV32I-LABEL: bare_select_float:
; RV32I: # %bb.0:
; RV32I-NEXT: andi a0, a0, 1
; RV32I-NEXT: bnez a0, .LBB1_2
; RV32I-NEXT: andi a3, a0, 1
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: bnez a3, .LBB1_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: mv a1, a2
; RV32I-NEXT: mv a0, a2
; RV32I-NEXT: .LBB1_2:
; RV32I-NEXT: mv a0, a1
; RV32I-NEXT: ret
%1 = select i1 %a, float %b, float %c
ret float %1
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/blockaddress.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -9,11 +9,11 @@ define void @test_blockaddress() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: lui a0, %hi(.Ltmp0)
; RV32I-NEXT: addi a0, a0, %lo(.Ltmp0)
; RV32I-NEXT: lui a1, %hi(addr)
; RV32I-NEXT: sw a0, %lo(addr)(a1)
; RV32I-NEXT: lw a0, %lo(addr)(a1)
; RV32I-NEXT: lui a0, %hi(addr)
; RV32I-NEXT: lui a1, %hi(.Ltmp0)
; RV32I-NEXT: addi a1, a1, %lo(.Ltmp0)
; RV32I-NEXT: sw a1, %lo(addr)(a0)
; RV32I-NEXT: lw a0, %lo(addr)(a0)
; RV32I-NEXT: jr a0
; RV32I-NEXT: .Ltmp0: # Block address taken
; RV32I-NEXT: .LBB0_1: # %block
Expand Down
112 changes: 56 additions & 56 deletions llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -29,10 +29,10 @@ define i16 @test_bswap_i16(i16 %a) nounwind {
define i32 @test_bswap_i32(i32 %a) nounwind {
; RV32I-LABEL: test_bswap_i32:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a1, 16
; RV32I-NEXT: addi a1, a1, -256
; RV32I-NEXT: srli a2, a0, 8
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: srli a1, a0, 8
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a2, a2, -256
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: srli a2, a0, 24
; RV32I-NEXT: or a1, a1, a2
; RV32I-NEXT: slli a2, a0, 8
Expand All @@ -49,9 +49,9 @@ define i32 @test_bswap_i32(i32 %a) nounwind {
define i64 @test_bswap_i64(i64 %a) nounwind {
; RV32I-LABEL: test_bswap_i64:
; RV32I: # %bb.0:
; RV32I-NEXT: lui a2, 16
; RV32I-NEXT: addi a3, a2, -256
; RV32I-NEXT: srli a2, a1, 8
; RV32I-NEXT: lui a3, 16
; RV32I-NEXT: addi a3, a3, -256
; RV32I-NEXT: and a2, a2, a3
; RV32I-NEXT: srli a4, a1, 24
; RV32I-NEXT: or a2, a2, a4
Expand Down Expand Up @@ -87,10 +87,10 @@ define i8 @test_cttz_i8(i8 %a) nounwind {
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: srli a2, a0, 1
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819
Expand Down Expand Up @@ -131,10 +131,10 @@ define i16 @test_cttz_i16(i16 %a) nounwind {
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: srli a2, a0, 1
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819
Expand Down Expand Up @@ -172,10 +172,10 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: srli a2, a0, 1
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819
Expand Down Expand Up @@ -220,11 +220,11 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: srli a1, a0, 16
; RV32I-NEXT: or a0, a0, a1
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: srli a2, a0, 1
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819
Expand Down Expand Up @@ -269,9 +269,9 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: not a1, s4
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi s5, a1, 1365
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s5, a2, 1365
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
Expand All @@ -282,12 +282,12 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s6, a1, 257
; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s1, a1, -241
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: mv a1, s6
; RV32I-NEXT: addi s6, a1, -241
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, s3, -1
Expand All @@ -302,8 +302,8 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: mv a1, s6
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: bnez s4, .LBB7_2
; RV32I-NEXT: # %bb.1:
Expand Down Expand Up @@ -336,10 +336,10 @@ define i8 @test_cttz_i8_zero_undef(i8 %a) nounwind {
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: srli a2, a0, 1
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819
Expand Down Expand Up @@ -371,10 +371,10 @@ define i16 @test_cttz_i16_zero_undef(i16 %a) nounwind {
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: srli a2, a0, 1
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819
Expand Down Expand Up @@ -406,10 +406,10 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV32I-NEXT: addi a1, a0, -1
; RV32I-NEXT: not a0, a0
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: srli a2, a0, 1
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819
Expand Down Expand Up @@ -450,9 +450,9 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: addi a0, a0, -1
; RV32I-NEXT: not a1, s4
; RV32I-NEXT: and a0, a1, a0
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi s5, a1, 1365
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi s5, a2, 1365
; RV32I-NEXT: and a1, a1, s5
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
Expand All @@ -463,12 +463,12 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s6, a1, 257
; RV32I-NEXT: lui a1, 61681
; RV32I-NEXT: addi s1, a1, -241
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: mv a1, s6
; RV32I-NEXT: addi s6, a1, -241
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s2, a0
; RV32I-NEXT: addi a0, s3, -1
Expand All @@ -483,8 +483,8 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: add a0, a1, a0
; RV32I-NEXT: srli a1, a0, 4
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s1
; RV32I-NEXT: mv a1, s6
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: bnez s4, .LBB11_2
; RV32I-NEXT: # %bb.1:
Expand Down Expand Up @@ -514,10 +514,10 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp)
; RV32I-NEXT: lui a1, 349525
; RV32I-NEXT: addi a1, a1, 1365
; RV32I-NEXT: srli a2, a0, 1
; RV32I-NEXT: and a1, a2, a1
; RV32I-NEXT: srli a1, a0, 1
; RV32I-NEXT: lui a2, 349525
; RV32I-NEXT: addi a2, a2, 1365
; RV32I-NEXT: and a1, a1, a2
; RV32I-NEXT: sub a0, a0, a1
; RV32I-NEXT: lui a1, 209715
; RV32I-NEXT: addi a1, a1, 819
Expand Down
20 changes: 11 additions & 9 deletions llvm/test/CodeGen/RISCV/callee-saved-fpr32s.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,8 +23,8 @@ define void @callee() nounwind {
; ILP32-LP64-LABEL: callee:
; ILP32-LP64: # %bb.0:
; ILP32-LP64-NEXT: lui a0, %hi(var)
; ILP32-LP64-NEXT: addi a1, a0, %lo(var)
; ILP32-LP64-NEXT: flw ft0, %lo(var)(a0)
; ILP32-LP64-NEXT: addi a1, a0, %lo(var)
; ILP32-LP64-NEXT: flw ft1, 4(a1)
; ILP32-LP64-NEXT: flw ft2, 8(a1)
; ILP32-LP64-NEXT: flw ft3, 12(a1)
Expand Down Expand Up @@ -52,14 +52,14 @@ define void @callee() nounwind {
; ILP32-LP64-NEXT: flw fs5, 100(a1)
; ILP32-LP64-NEXT: flw fs6, 104(a1)
; ILP32-LP64-NEXT: flw fs7, 108(a1)
; ILP32-LP64-NEXT: flw fs8, 112(a1)
; ILP32-LP64-NEXT: flw fs9, 116(a1)
; ILP32-LP64-NEXT: flw fs10, 120(a1)
; ILP32-LP64-NEXT: flw fs11, 124(a1)
; ILP32-LP64-NEXT: fsw fs11, 124(a1)
; ILP32-LP64-NEXT: fsw fs10, 120(a1)
; ILP32-LP64-NEXT: fsw fs9, 116(a1)
; ILP32-LP64-NEXT: fsw fs8, 112(a1)
; ILP32-LP64-NEXT: flw fs8, 124(a1)
; ILP32-LP64-NEXT: flw fs9, 120(a1)
; ILP32-LP64-NEXT: flw fs10, 116(a1)
; ILP32-LP64-NEXT: flw fs11, 112(a1)
; ILP32-LP64-NEXT: fsw fs8, 124(a1)
; ILP32-LP64-NEXT: fsw fs9, 120(a1)
; ILP32-LP64-NEXT: fsw fs10, 116(a1)
; ILP32-LP64-NEXT: fsw fs11, 112(a1)
; ILP32-LP64-NEXT: fsw fs7, 108(a1)
; ILP32-LP64-NEXT: fsw fs6, 104(a1)
; ILP32-LP64-NEXT: fsw fs5, 100(a1)
Expand Down Expand Up @@ -106,6 +106,7 @@ define void @callee() nounwind {
; ILP32F-LP64F-NEXT: fsw fs10, 4(sp)
; ILP32F-LP64F-NEXT: fsw fs11, 0(sp)
; ILP32F-LP64F-NEXT: lui a0, %hi(var)
; ILP32F-LP64F-NEXT: flw ft0, %lo(var)(a0)
; ILP32F-LP64F-NEXT: addi a1, a0, %lo(var)
;
; ILP32D-LP64D-LABEL: callee:
Expand All @@ -124,6 +125,7 @@ define void @callee() nounwind {
; ILP32D-LP64D-NEXT: fsd fs10, 8(sp)
; ILP32D-LP64D-NEXT: fsd fs11, 0(sp)
; ILP32D-LP64D-NEXT: lui a0, %hi(var)
; ILP32D-LP64D-NEXT: flw ft0, %lo(var)(a0)
; ILP32D-LP64D-NEXT: addi a1, a0, %lo(var)
%val = load [32 x float], [32 x float]* @var
store volatile [32 x float] %val, [32 x float]* @var
Expand Down
19 changes: 10 additions & 9 deletions llvm/test/CodeGen/RISCV/callee-saved-fpr64s.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,8 +19,8 @@ define void @callee() nounwind {
; ILP32-LP64-LABEL: callee:
; ILP32-LP64: # %bb.0:
; ILP32-LP64-NEXT: lui a0, %hi(var)
; ILP32-LP64-NEXT: addi a1, a0, %lo(var)
; ILP32-LP64-NEXT: fld ft0, %lo(var)(a0)
; ILP32-LP64-NEXT: addi a1, a0, %lo(var)
; ILP32-LP64-NEXT: fld ft1, 8(a1)
; ILP32-LP64-NEXT: fld ft2, 16(a1)
; ILP32-LP64-NEXT: fld ft3, 24(a1)
Expand Down Expand Up @@ -48,14 +48,14 @@ define void @callee() nounwind {
; ILP32-LP64-NEXT: fld fs5, 200(a1)
; ILP32-LP64-NEXT: fld fs6, 208(a1)
; ILP32-LP64-NEXT: fld fs7, 216(a1)
; ILP32-LP64-NEXT: fld fs8, 224(a1)
; ILP32-LP64-NEXT: fld fs9, 232(a1)
; ILP32-LP64-NEXT: fld fs10, 240(a1)
; ILP32-LP64-NEXT: fld fs11, 248(a1)
; ILP32-LP64-NEXT: fsd fs11, 248(a1)
; ILP32-LP64-NEXT: fsd fs10, 240(a1)
; ILP32-LP64-NEXT: fsd fs9, 232(a1)
; ILP32-LP64-NEXT: fsd fs8, 224(a1)
; ILP32-LP64-NEXT: fld fs8, 248(a1)
; ILP32-LP64-NEXT: fld fs9, 240(a1)
; ILP32-LP64-NEXT: fld fs10, 232(a1)
; ILP32-LP64-NEXT: fld fs11, 224(a1)
; ILP32-LP64-NEXT: fsd fs8, 248(a1)
; ILP32-LP64-NEXT: fsd fs9, 240(a1)
; ILP32-LP64-NEXT: fsd fs10, 232(a1)
; ILP32-LP64-NEXT: fsd fs11, 224(a1)
; ILP32-LP64-NEXT: fsd fs7, 216(a1)
; ILP32-LP64-NEXT: fsd fs6, 208(a1)
; ILP32-LP64-NEXT: fsd fs5, 200(a1)
Expand Down Expand Up @@ -102,6 +102,7 @@ define void @callee() nounwind {
; ILP32D-LP64D-NEXT: fsd fs10, 8(sp)
; ILP32D-LP64D-NEXT: fsd fs11, 0(sp)
; ILP32D-LP64D-NEXT: lui a0, %hi(var)
; ILP32D-LP64D-NEXT: fld ft0, %lo(var)(a0)
; ILP32D-LP64D-NEXT: addi a1, a0, %lo(var)
%val = load [32 x double], [32 x double]* @var
store volatile [32 x double] %val, [32 x double]* @var
Expand Down
117 changes: 67 additions & 50 deletions llvm/test/CodeGen/RISCV/callee-saved-gprs.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,9 @@ define void @callee() nounwind {
; RV32I-NEXT: sw s10, 36(sp)
; RV32I-NEXT: sw s11, 32(sp)
; RV32I-NEXT: lui a0, %hi(var)
; RV32I-NEXT: addi a1, a0, %lo(var)
; RV32I-NEXT: lw a1, %lo(var)(a0)
; RV32I-NEXT: sw a1, 28(sp)
; RV32I-NEXT: addi a2, a0, %lo(var)
;
; RV32I-WITH-FP-LABEL: callee:
; RV32I-WITH-FP: # %bb.0:
Expand All @@ -61,7 +63,9 @@ define void @callee() nounwind {
; RV32I-WITH-FP-NEXT: sw s11, 28(sp)
; RV32I-WITH-FP-NEXT: addi s0, sp, 80
; RV32I-WITH-FP-NEXT: lui a0, %hi(var)
; RV32I-WITH-FP-NEXT: addi a1, a0, %lo(var)
; RV32I-WITH-FP-NEXT: lw a1, %lo(var)(a0)
; RV32I-WITH-FP-NEXT: sw a1, -56(s0)
; RV32I-WITH-FP-NEXT: addi a2, a0, %lo(var)
;
; RV64I-LABEL: callee:
; RV64I: # %bb.0:
Expand All @@ -79,7 +83,9 @@ define void @callee() nounwind {
; RV64I-NEXT: sd s10, 56(sp)
; RV64I-NEXT: sd s11, 48(sp)
; RV64I-NEXT: lui a0, %hi(var)
; RV64I-NEXT: addi a1, a0, %lo(var)
; RV64I-NEXT: lw a1, %lo(var)(a0)
; RV64I-NEXT: sd a1, 40(sp)
; RV64I-NEXT: addi a2, a0, %lo(var)
;
; RV64I-WITH-FP-LABEL: callee:
; RV64I-WITH-FP: # %bb.0:
Expand All @@ -99,7 +105,9 @@ define void @callee() nounwind {
; RV64I-WITH-FP-NEXT: sd s11, 56(sp)
; RV64I-WITH-FP-NEXT: addi s0, sp, 160
; RV64I-WITH-FP-NEXT: lui a0, %hi(var)
; RV64I-WITH-FP-NEXT: addi a1, a0, %lo(var)
; RV64I-WITH-FP-NEXT: lw a1, %lo(var)(a0)
; RV64I-WITH-FP-NEXT: sd a1, -112(s0)
; RV64I-WITH-FP-NEXT: addi a2, a0, %lo(var)
%val = load [32 x i32], [32 x i32]* @var
store volatile [32 x i32] %val, [32 x i32]* @var
ret void
Expand All @@ -111,36 +119,41 @@ define void @callee() nounwind {
define void @caller() nounwind {
; RV32I-LABEL: caller:
; RV32I: lui a0, %hi(var)
; RV32I-NEXT: addi s1, a0, %lo(var)
; RV32I-NEXT: lw a1, %lo(var)(a0)
; RV32I-NEXT: sw a1, 88(sp)
; RV32I-NEXT: addi s0, a0, %lo(var)

; RV32I: sw a0, 8(sp)
; RV32I-NEXT: lw s2, 84(s1)
; RV32I-NEXT: lw s3, 88(s1)
; RV32I-NEXT: lw s4, 92(s1)
; RV32I-NEXT: lw s5, 96(s1)
; RV32I-NEXT: lw s6, 100(s1)
; RV32I-NEXT: lw s7, 104(s1)
; RV32I-NEXT: lw s8, 108(s1)
; RV32I-NEXT: lw s9, 112(s1)
; RV32I-NEXT: lw s10, 116(s1)
; RV32I-NEXT: lw s11, 120(s1)
; RV32I-NEXT: lw s0, 124(s1)
; RV32I-NEXT: lw s2, 84(s0)
; RV32I-NEXT: lw s3, 88(s0)
; RV32I-NEXT: lw s4, 92(s0)
; RV32I-NEXT: lw s5, 96(s0)
; RV32I-NEXT: lw s6, 100(s0)
; RV32I-NEXT: lw s7, 104(s0)
; RV32I-NEXT: lw s8, 108(s0)
; RV32I-NEXT: lw s9, 112(s0)
; RV32I-NEXT: lw s10, 116(s0)
; RV32I-NEXT: lw s11, 120(s0)
; RV32I-NEXT: lw s1, 124(s0)
; RV32I-NEXT: call callee
; RV32I-NEXT: sw s0, 124(s1)
; RV32I-NEXT: sw s11, 120(s1)
; RV32I-NEXT: sw s10, 116(s1)
; RV32I-NEXT: sw s9, 112(s1)
; RV32I-NEXT: sw s8, 108(s1)
; RV32I-NEXT: sw s7, 104(s1)
; RV32I-NEXT: sw s6, 100(s1)
; RV32I-NEXT: sw s5, 96(s1)
; RV32I-NEXT: sw s4, 92(s1)
; RV32I-NEXT: sw s3, 88(s1)
; RV32I-NEXT: sw s2, 84(s1)
; RV32I-NEXT: sw s1, 124(s0)
; RV32I-NEXT: sw s11, 120(s0)
; RV32I-NEXT: sw s10, 116(s0)
; RV32I-NEXT: sw s9, 112(s0)
; RV32I-NEXT: sw s8, 108(s0)
; RV32I-NEXT: sw s7, 104(s0)
; RV32I-NEXT: sw s6, 100(s0)
; RV32I-NEXT: sw s5, 96(s0)
; RV32I-NEXT: sw s4, 92(s0)
; RV32I-NEXT: sw s3, 88(s0)
; RV32I-NEXT: sw s2, 84(s0)
; RV32I-NEXT: lw a0, 8(sp)
;
; RV32I-WITH-FP-LABEL: caller:
; RV32I-WITH-FP: addi s0, sp, 144
; RV32I-WITH-FP-NEXT: lui a0, %hi(var)
; RV32I-WITH-FP-NEXT: lw a1, %lo(var)(a0)
; RV32I-WITH-FP-NEXT: sw a1, -56(s0)
; RV32I-WITH-FP-NEXT: addi s1, a0, %lo(var)
; RV32I-WITH-FP: sw a0, -140(s0)
; RV32I-WITH-FP-NEXT: lw s5, 88(s1)
Expand Down Expand Up @@ -168,36 +181,40 @@ define void @caller() nounwind {
;
; RV64I-LABEL: caller:
; RV64I: lui a0, %hi(var)
; RV64I-NEXT: addi s1, a0, %lo(var)
; RV64I-NEXT: lw a1, %lo(var)(a0)
; RV64I-NEXT: sd a1, 160(sp)
; RV64I-NEXT: addi s0, a0, %lo(var)
; RV64I: sd a0, 0(sp)
; RV64I-NEXT: lw s2, 84(s1)
; RV64I-NEXT: lw s3, 88(s1)
; RV64I-NEXT: lw s4, 92(s1)
; RV64I-NEXT: lw s5, 96(s1)
; RV64I-NEXT: lw s6, 100(s1)
; RV64I-NEXT: lw s7, 104(s1)
; RV64I-NEXT: lw s8, 108(s1)
; RV64I-NEXT: lw s9, 112(s1)
; RV64I-NEXT: lw s10, 116(s1)
; RV64I-NEXT: lw s11, 120(s1)
; RV64I-NEXT: lw s0, 124(s1)
; RV64I-NEXT: lw s2, 84(s0)
; RV64I-NEXT: lw s3, 88(s0)
; RV64I-NEXT: lw s4, 92(s0)
; RV64I-NEXT: lw s5, 96(s0)
; RV64I-NEXT: lw s6, 100(s0)
; RV64I-NEXT: lw s7, 104(s0)
; RV64I-NEXT: lw s8, 108(s0)
; RV64I-NEXT: lw s9, 112(s0)
; RV64I-NEXT: lw s10, 116(s0)
; RV64I-NEXT: lw s11, 120(s0)
; RV64I-NEXT: lw s1, 124(s0)
; RV64I-NEXT: call callee
; RV64I-NEXT: sw s0, 124(s1)
; RV64I-NEXT: sw s11, 120(s1)
; RV64I-NEXT: sw s10, 116(s1)
; RV64I-NEXT: sw s9, 112(s1)
; RV64I-NEXT: sw s8, 108(s1)
; RV64I-NEXT: sw s7, 104(s1)
; RV64I-NEXT: sw s6, 100(s1)
; RV64I-NEXT: sw s5, 96(s1)
; RV64I-NEXT: sw s4, 92(s1)
; RV64I-NEXT: sw s3, 88(s1)
; RV64I-NEXT: sw s2, 84(s1)
; RV64I-NEXT: sw s1, 124(s0)
; RV64I-NEXT: sw s11, 120(s0)
; RV64I-NEXT: sw s10, 116(s0)
; RV64I-NEXT: sw s9, 112(s0)
; RV64I-NEXT: sw s8, 108(s0)
; RV64I-NEXT: sw s7, 104(s0)
; RV64I-NEXT: sw s6, 100(s0)
; RV64I-NEXT: sw s5, 96(s0)
; RV64I-NEXT: sw s4, 92(s0)
; RV64I-NEXT: sw s3, 88(s0)
; RV64I-NEXT: sw s2, 84(s0)
; RV64I-NEXT: ld a0, 0(sp)
;
; RV64I-WITH-FP-LABEL: caller:
; RV64I-WITH-FP: addi s0, sp, 288
; RV64I-WITH-FP-NEXT: lui a0, %hi(var)
; RV64I-WITH-FP-NEXT: lw a1, %lo(var)(a0)
; RV64I-WITH-FP-NEXT: sd a1, -112(s0)
; RV64I-WITH-FP-NEXT: addi s1, a0, %lo(var)
; RV64I-WITH-FP: sd a0, -280(s0)
; RV64I-WITH-FP-NEXT: lw s5, 88(s1)
Expand Down
44 changes: 22 additions & 22 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-common.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -61,8 +61,8 @@ define i32 @caller_double_in_regs() nounwind {
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: mv a1, zero
; RV32I-FPELIM-NEXT: lui a2, 262144
; RV32I-FPELIM-NEXT: mv a1, zero
; RV32I-FPELIM-NEXT: call callee_double_in_regs
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 16
Expand All @@ -75,8 +75,8 @@ define i32 @caller_double_in_regs() nounwind {
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: mv a1, zero
; RV32I-WITHFP-NEXT: lui a2, 262144
; RV32I-WITHFP-NEXT: mv a1, zero
; RV32I-WITHFP-NEXT: call callee_double_in_regs
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
Expand All @@ -94,14 +94,14 @@ define i32 @callee_aligned_stack(i32 %a, i32 %b, fp128 %c, i32 %d, i32 %e, i64 %
; RV32I-FPELIM-LABEL: callee_aligned_stack:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: lw a0, 0(a2)
; RV32I-FPELIM-NEXT: add a0, a0, a7
; RV32I-FPELIM-NEXT: lw a1, 0(sp)
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: lw a1, 8(sp)
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: lw a1, 16(sp)
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: lw a1, 20(sp)
; RV32I-FPELIM-NEXT: lw a2, 0(sp)
; RV32I-FPELIM-NEXT: lw a3, 8(sp)
; RV32I-FPELIM-NEXT: lw a4, 16(sp)
; RV32I-FPELIM-NEXT: add a0, a0, a7
; RV32I-FPELIM-NEXT: add a0, a0, a2
; RV32I-FPELIM-NEXT: add a0, a0, a3
; RV32I-FPELIM-NEXT: add a0, a0, a4
; RV32I-FPELIM-NEXT: add a0, a0, a1
; RV32I-FPELIM-NEXT: ret
;
Expand All @@ -112,14 +112,14 @@ define i32 @callee_aligned_stack(i32 %a, i32 %b, fp128 %c, i32 %d, i32 %e, i64 %
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lw a0, 0(a2)
; RV32I-WITHFP-NEXT: add a0, a0, a7
; RV32I-WITHFP-NEXT: lw a1, 0(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw a1, 8(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw a1, 16(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw a1, 20(s0)
; RV32I-WITHFP-NEXT: lw a2, 0(s0)
; RV32I-WITHFP-NEXT: lw a3, 8(s0)
; RV32I-WITHFP-NEXT: lw a4, 16(s0)
; RV32I-WITHFP-NEXT: add a0, a0, a7
; RV32I-WITHFP-NEXT: add a0, a0, a2
; RV32I-WITHFP-NEXT: add a0, a0, a3
; RV32I-WITHFP-NEXT: add a0, a0, a4
; RV32I-WITHFP-NEXT: add a0, a0, a1
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
Expand Down Expand Up @@ -169,8 +169,7 @@ define void @caller_aligned_stack() nounwind {
; RV32I-FPELIM-NEXT: addi a0, a0, -328
; RV32I-FPELIM-NEXT: sw a0, 36(sp)
; RV32I-FPELIM-NEXT: lui a0, 335544
; RV32I-FPELIM-NEXT: addi a0, a0, 1311
; RV32I-FPELIM-NEXT: sw a0, 32(sp)
; RV32I-FPELIM-NEXT: addi t0, a0, 1311
; RV32I-FPELIM-NEXT: lui a0, 688509
; RV32I-FPELIM-NEXT: addi a5, a0, -2048
; RV32I-FPELIM-NEXT: addi a2, sp, 32
Expand All @@ -180,6 +179,7 @@ define void @caller_aligned_stack() nounwind {
; RV32I-FPELIM-NEXT: addi a4, zero, 13
; RV32I-FPELIM-NEXT: addi a6, zero, 4
; RV32I-FPELIM-NEXT: addi a7, zero, 14
; RV32I-FPELIM-NEXT: sw t0, 32(sp)
; RV32I-FPELIM-NEXT: call callee_aligned_stack
; RV32I-FPELIM-NEXT: lw ra, 60(sp)
; RV32I-FPELIM-NEXT: addi sp, sp, 64
Expand Down Expand Up @@ -215,8 +215,7 @@ define void @caller_aligned_stack() nounwind {
; RV32I-WITHFP-NEXT: addi a0, a0, -328
; RV32I-WITHFP-NEXT: sw a0, -28(s0)
; RV32I-WITHFP-NEXT: lui a0, 335544
; RV32I-WITHFP-NEXT: addi a0, a0, 1311
; RV32I-WITHFP-NEXT: sw a0, -32(s0)
; RV32I-WITHFP-NEXT: addi t0, a0, 1311
; RV32I-WITHFP-NEXT: lui a0, 688509
; RV32I-WITHFP-NEXT: addi a5, a0, -2048
; RV32I-WITHFP-NEXT: addi a2, s0, -32
Expand All @@ -226,6 +225,7 @@ define void @caller_aligned_stack() nounwind {
; RV32I-WITHFP-NEXT: addi a4, zero, 13
; RV32I-WITHFP-NEXT: addi a6, zero, 4
; RV32I-WITHFP-NEXT: addi a7, zero, 14
; RV32I-WITHFP-NEXT: sw t0, -32(s0)
; RV32I-WITHFP-NEXT: call callee_aligned_stack
; RV32I-WITHFP-NEXT: lw s0, 56(sp)
; RV32I-WITHFP-NEXT: lw ra, 60(sp)
Expand All @@ -241,8 +241,8 @@ define void @caller_aligned_stack() nounwind {
define double @callee_small_scalar_ret() nounwind {
; RV32I-FPELIM-LABEL: callee_small_scalar_ret:
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: mv a0, zero
; RV32I-FPELIM-NEXT: lui a1, 261888
; RV32I-FPELIM-NEXT: mv a0, zero
; RV32I-FPELIM-NEXT: ret
;
; RV32I-WITHFP-LABEL: callee_small_scalar_ret:
Expand All @@ -251,8 +251,8 @@ define double @callee_small_scalar_ret() nounwind {
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: mv a0, zero
; RV32I-WITHFP-NEXT: lui a1, 261888
; RV32I-WITHFP-NEXT: mv a0, zero
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
; RV32I-WITHFP-NEXT: lw ra, 12(sp)
; RV32I-WITHFP-NEXT: addi sp, sp, 16
Expand Down
312 changes: 154 additions & 158 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32-ilp32f-ilp32d-common.ll
View file

Large diffs are not rendered by default.

20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -107,15 +107,15 @@ define i32 @caller_float_on_stack() nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp)
; RV32I-FPELIM-NEXT: lui a0, 264704
; RV32I-FPELIM-NEXT: sw a0, 0(sp)
; RV32I-FPELIM-NEXT: lui a1, 264704
; RV32I-FPELIM-NEXT: addi a0, zero, 1
; RV32I-FPELIM-NEXT: mv a1, zero
; RV32I-FPELIM-NEXT: addi a2, zero, 2
; RV32I-FPELIM-NEXT: mv a3, zero
; RV32I-FPELIM-NEXT: addi a4, zero, 3
; RV32I-FPELIM-NEXT: mv a5, zero
; RV32I-FPELIM-NEXT: addi a6, zero, 4
; RV32I-FPELIM-NEXT: sw a1, 0(sp)
; RV32I-FPELIM-NEXT: mv a1, zero
; RV32I-FPELIM-NEXT: mv a3, zero
; RV32I-FPELIM-NEXT: mv a5, zero
; RV32I-FPELIM-NEXT: mv a7, zero
; RV32I-FPELIM-NEXT: call callee_float_on_stack
; RV32I-FPELIM-NEXT: lw ra, 12(sp)
Expand All @@ -128,15 +128,15 @@ define i32 @caller_float_on_stack() nounwind {
; RV32I-WITHFP-NEXT: sw ra, 12(sp)
; RV32I-WITHFP-NEXT: sw s0, 8(sp)
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: lui a0, 264704
; RV32I-WITHFP-NEXT: sw a0, 0(sp)
; RV32I-WITHFP-NEXT: lui a1, 264704
; RV32I-WITHFP-NEXT: addi a0, zero, 1
; RV32I-WITHFP-NEXT: mv a1, zero
; RV32I-WITHFP-NEXT: addi a2, zero, 2
; RV32I-WITHFP-NEXT: mv a3, zero
; RV32I-WITHFP-NEXT: addi a4, zero, 3
; RV32I-WITHFP-NEXT: mv a5, zero
; RV32I-WITHFP-NEXT: addi a6, zero, 4
; RV32I-WITHFP-NEXT: sw a1, 0(sp)
; RV32I-WITHFP-NEXT: mv a1, zero
; RV32I-WITHFP-NEXT: mv a3, zero
; RV32I-WITHFP-NEXT: mv a5, zero
; RV32I-WITHFP-NEXT: mv a7, zero
; RV32I-WITHFP-NEXT: call callee_float_on_stack
; RV32I-WITHFP-NEXT: lw s0, 8(sp)
Expand Down
144 changes: 72 additions & 72 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,9 +38,9 @@ define i32 @caller_double_in_fpr() nounwind {
define i32 @callee_double_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, double %f) nounwind {
; RV32-ILP32D-LABEL: callee_double_in_fpr_exhausted_gprs:
; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: fcvt.w.d a0, fa0, rtz
; RV32-ILP32D-NEXT: lw a1, 0(sp)
; RV32-ILP32D-NEXT: add a0, a1, a0
; RV32-ILP32D-NEXT: lw a0, 0(sp)
; RV32-ILP32D-NEXT: fcvt.w.d a1, fa0, rtz
; RV32-ILP32D-NEXT: add a0, a0, a1
; RV32-ILP32D-NEXT: ret
%f_fptosi = fptosi double %f to i32
%1 = add i32 %e, %f_fptosi
Expand All @@ -52,18 +52,18 @@ define i32 @caller_double_in_fpr_exhausted_gprs() nounwind {
; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw ra, 12(sp)
; RV32-ILP32D-NEXT: addi a0, zero, 5
; RV32-ILP32D-NEXT: sw a0, 0(sp)
; RV32-ILP32D-NEXT: addi a1, zero, 5
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI3_0)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI3_0)
; RV32-ILP32D-NEXT: fld fa0, 0(a0)
; RV32-ILP32D-NEXT: addi a0, zero, 1
; RV32-ILP32D-NEXT: mv a1, zero
; RV32-ILP32D-NEXT: addi a2, zero, 2
; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: addi a4, zero, 3
; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: addi a6, zero, 4
; RV32-ILP32D-NEXT: sw a1, 0(sp)
; RV32-ILP32D-NEXT: mv a1, zero
; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: mv a7, zero
; RV32-ILP32D-NEXT: call callee_double_in_fpr_exhausted_gprs
; RV32-ILP32D-NEXT: lw ra, 12(sp)
Expand All @@ -82,9 +82,9 @@ define i32 @callee_double_in_gpr_exhausted_fprs(double %a, double %b, double %c,
; RV32-ILP32D-NEXT: sw a0, 8(sp)
; RV32-ILP32D-NEXT: sw a1, 12(sp)
; RV32-ILP32D-NEXT: fld ft0, 8(sp)
; RV32-ILP32D-NEXT: fcvt.w.d a0, ft0, rtz
; RV32-ILP32D-NEXT: fcvt.w.d a1, fa7, rtz
; RV32-ILP32D-NEXT: add a0, a1, a0
; RV32-ILP32D-NEXT: fcvt.w.d a0, fa7, rtz
; RV32-ILP32D-NEXT: fcvt.w.d a1, ft0, rtz
; RV32-ILP32D-NEXT: add a0, a0, a1
; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret
%h_fptosi = fptosi double %h to i32
Expand All @@ -100,30 +100,30 @@ define i32 @caller_double_in_gpr_exhausted_fprs() nounwind {
; RV32-ILP32D-NEXT: sw ra, 12(sp)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_0)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_0)
; RV32-ILP32D-NEXT: lui a1, %hi(.LCPI5_1)
; RV32-ILP32D-NEXT: addi a1, a1, %lo(.LCPI5_1)
; RV32-ILP32D-NEXT: lui a2, %hi(.LCPI5_2)
; RV32-ILP32D-NEXT: addi a2, a2, %lo(.LCPI5_2)
; RV32-ILP32D-NEXT: lui a3, %hi(.LCPI5_3)
; RV32-ILP32D-NEXT: addi a3, a3, %lo(.LCPI5_3)
; RV32-ILP32D-NEXT: lui a4, %hi(.LCPI5_4)
; RV32-ILP32D-NEXT: addi a4, a4, %lo(.LCPI5_4)
; RV32-ILP32D-NEXT: lui a5, %hi(.LCPI5_5)
; RV32-ILP32D-NEXT: addi a5, a5, %lo(.LCPI5_5)
; RV32-ILP32D-NEXT: fld fa0, 0(a5)
; RV32-ILP32D-NEXT: fld fa1, 0(a4)
; RV32-ILP32D-NEXT: fld fa2, 0(a3)
; RV32-ILP32D-NEXT: fld fa3, 0(a2)
; RV32-ILP32D-NEXT: fld fa4, 0(a1)
; RV32-ILP32D-NEXT: fld fa0, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_1)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_1)
; RV32-ILP32D-NEXT: fld fa1, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_2)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_2)
; RV32-ILP32D-NEXT: fld fa2, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_3)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_3)
; RV32-ILP32D-NEXT: fld fa3, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_4)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_4)
; RV32-ILP32D-NEXT: fld fa4, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_5)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_5)
; RV32-ILP32D-NEXT: fld fa5, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_6)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_6)
; RV32-ILP32D-NEXT: fld fa6, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI5_7)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI5_7)
; RV32-ILP32D-NEXT: fld fa7, 0(a0)
; RV32-ILP32D-NEXT: mv a0, zero
; RV32-ILP32D-NEXT: lui a1, 262688
; RV32-ILP32D-NEXT: mv a0, zero
; RV32-ILP32D-NEXT: call callee_double_in_gpr_exhausted_fprs
; RV32-ILP32D-NEXT: lw ra, 12(sp)
; RV32-ILP32D-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -157,39 +157,39 @@ define i32 @caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs() nounwind
; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw ra, 12(sp)
; RV32-ILP32D-NEXT: lui a0, 262816
; RV32-ILP32D-NEXT: sw a0, 0(sp)
; RV32-ILP32D-NEXT: lui a1, 262816
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_0)
; RV32-ILP32D-NEXT: addi a6, a0, %lo(.LCPI7_0)
; RV32-ILP32D-NEXT: lui a1, %hi(.LCPI7_1)
; RV32-ILP32D-NEXT: addi a1, a1, %lo(.LCPI7_1)
; RV32-ILP32D-NEXT: lui a2, %hi(.LCPI7_2)
; RV32-ILP32D-NEXT: addi a2, a2, %lo(.LCPI7_2)
; RV32-ILP32D-NEXT: lui a3, %hi(.LCPI7_3)
; RV32-ILP32D-NEXT: addi a3, a3, %lo(.LCPI7_3)
; RV32-ILP32D-NEXT: lui a4, %hi(.LCPI7_4)
; RV32-ILP32D-NEXT: addi a4, a4, %lo(.LCPI7_4)
; RV32-ILP32D-NEXT: lui a5, %hi(.LCPI7_5)
; RV32-ILP32D-NEXT: addi a5, a5, %lo(.LCPI7_5)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_0)
; RV32-ILP32D-NEXT: fld fa0, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_1)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_1)
; RV32-ILP32D-NEXT: fld fa1, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_2)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_2)
; RV32-ILP32D-NEXT: fld fa2, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_3)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_3)
; RV32-ILP32D-NEXT: fld fa3, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_4)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_4)
; RV32-ILP32D-NEXT: fld fa4, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_5)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_5)
; RV32-ILP32D-NEXT: fld fa5, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_6)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_6)
; RV32-ILP32D-NEXT: fld fa0, 0(a0)
; RV32-ILP32D-NEXT: fld fa1, 0(a5)
; RV32-ILP32D-NEXT: fld fa2, 0(a4)
; RV32-ILP32D-NEXT: fld fa3, 0(a3)
; RV32-ILP32D-NEXT: fld fa4, 0(a2)
; RV32-ILP32D-NEXT: fld fa5, 0(a1)
; RV32-ILP32D-NEXT: fld fa6, 0(a6)
; RV32-ILP32D-NEXT: fld fa6, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI7_7)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI7_7)
; RV32-ILP32D-NEXT: fld fa7, 0(a0)
; RV32-ILP32D-NEXT: addi a0, zero, 1
; RV32-ILP32D-NEXT: mv a1, zero
; RV32-ILP32D-NEXT: addi a2, zero, 3
; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: addi a4, zero, 5
; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: addi a6, zero, 7
; RV32-ILP32D-NEXT: sw a1, 0(sp)
; RV32-ILP32D-NEXT: mv a1, zero
; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: mv a7, zero
; RV32-ILP32D-NEXT: call callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs
; RV32-ILP32D-NEXT: lw ra, 12(sp)
Expand Down Expand Up @@ -223,38 +223,38 @@ define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind {
; RV32-ILP32D-NEXT: sw ra, 12(sp)
; RV32-ILP32D-NEXT: lui a0, 262816
; RV32-ILP32D-NEXT: sw a0, 4(sp)
; RV32-ILP32D-NEXT: sw zero, 0(sp)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_0)
; RV32-ILP32D-NEXT: addi a6, a0, %lo(.LCPI9_0)
; RV32-ILP32D-NEXT: lui a1, %hi(.LCPI9_1)
; RV32-ILP32D-NEXT: addi a1, a1, %lo(.LCPI9_1)
; RV32-ILP32D-NEXT: lui a2, %hi(.LCPI9_2)
; RV32-ILP32D-NEXT: addi a2, a2, %lo(.LCPI9_2)
; RV32-ILP32D-NEXT: lui a3, %hi(.LCPI9_3)
; RV32-ILP32D-NEXT: addi a3, a3, %lo(.LCPI9_3)
; RV32-ILP32D-NEXT: lui a4, %hi(.LCPI9_4)
; RV32-ILP32D-NEXT: addi a4, a4, %lo(.LCPI9_4)
; RV32-ILP32D-NEXT: lui a5, %hi(.LCPI9_5)
; RV32-ILP32D-NEXT: addi a5, a5, %lo(.LCPI9_5)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_0)
; RV32-ILP32D-NEXT: fld fa0, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_1)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_1)
; RV32-ILP32D-NEXT: fld fa1, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_2)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_2)
; RV32-ILP32D-NEXT: fld fa2, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_3)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_3)
; RV32-ILP32D-NEXT: fld fa3, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_4)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_4)
; RV32-ILP32D-NEXT: fld fa4, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_5)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_5)
; RV32-ILP32D-NEXT: fld fa5, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_6)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_6)
; RV32-ILP32D-NEXT: fld fa0, 0(a0)
; RV32-ILP32D-NEXT: fld fa1, 0(a5)
; RV32-ILP32D-NEXT: fld fa2, 0(a4)
; RV32-ILP32D-NEXT: fld fa3, 0(a3)
; RV32-ILP32D-NEXT: fld fa4, 0(a2)
; RV32-ILP32D-NEXT: fld fa5, 0(a1)
; RV32-ILP32D-NEXT: fld fa6, 0(a6)
; RV32-ILP32D-NEXT: fld fa6, 0(a0)
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI9_7)
; RV32-ILP32D-NEXT: addi a0, a0, %lo(.LCPI9_7)
; RV32-ILP32D-NEXT: fld fa7, 0(a0)
; RV32-ILP32D-NEXT: addi a0, zero, 1
; RV32-ILP32D-NEXT: mv a1, zero
; RV32-ILP32D-NEXT: addi a2, zero, 3
; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: addi a4, zero, 5
; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: addi a6, zero, 7
; RV32-ILP32D-NEXT: sw zero, 0(sp)
; RV32-ILP32D-NEXT: mv a1, zero
; RV32-ILP32D-NEXT: mv a3, zero
; RV32-ILP32D-NEXT: mv a5, zero
; RV32-ILP32D-NEXT: mv a7, zero
; RV32-ILP32D-NEXT: call callee_double_on_stack_exhausted_gprs_fprs
; RV32-ILP32D-NEXT: lw ra, 12(sp)
Expand Down
98 changes: 49 additions & 49 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -41,9 +41,9 @@ define i32 @caller_float_in_fpr() nounwind {
define i32 @callee_float_in_fpr_exhausted_gprs(i64 %a, i64 %b, i64 %c, i64 %d, i32 %e, float %f) nounwind {
; RV32-ILP32FD-LABEL: callee_float_in_fpr_exhausted_gprs:
; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: fcvt.w.s a0, fa0, rtz
; RV32-ILP32FD-NEXT: lw a1, 0(sp)
; RV32-ILP32FD-NEXT: add a0, a1, a0
; RV32-ILP32FD-NEXT: lw a0, 0(sp)
; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa0, rtz
; RV32-ILP32FD-NEXT: add a0, a0, a1
; RV32-ILP32FD-NEXT: ret
%f_fptosi = fptosi float %f to i32
%1 = add i32 %e, %f_fptosi
Expand All @@ -55,18 +55,18 @@ define i32 @caller_float_in_fpr_exhausted_gprs() nounwind {
; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: addi sp, sp, -16
; RV32-ILP32FD-NEXT: sw ra, 12(sp)
; RV32-ILP32FD-NEXT: addi a0, zero, 5
; RV32-ILP32FD-NEXT: sw a0, 0(sp)
; RV32-ILP32FD-NEXT: addi a1, zero, 5
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI3_0)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI3_0)
; RV32-ILP32FD-NEXT: flw fa0, 0(a0)
; RV32-ILP32FD-NEXT: addi a0, zero, 1
; RV32-ILP32FD-NEXT: mv a1, zero
; RV32-ILP32FD-NEXT: addi a2, zero, 2
; RV32-ILP32FD-NEXT: mv a3, zero
; RV32-ILP32FD-NEXT: addi a4, zero, 3
; RV32-ILP32FD-NEXT: mv a5, zero
; RV32-ILP32FD-NEXT: addi a6, zero, 4
; RV32-ILP32FD-NEXT: sw a1, 0(sp)
; RV32-ILP32FD-NEXT: mv a1, zero
; RV32-ILP32FD-NEXT: mv a3, zero
; RV32-ILP32FD-NEXT: mv a5, zero
; RV32-ILP32FD-NEXT: mv a7, zero
; RV32-ILP32FD-NEXT: call callee_float_in_fpr_exhausted_gprs
; RV32-ILP32FD-NEXT: lw ra, 12(sp)
Expand All @@ -81,10 +81,10 @@ define i32 @caller_float_in_fpr_exhausted_gprs() nounwind {
define i32 @callee_float_in_gpr_exhausted_fprs(float %a, float %b, float %c, float %d, float %e, float %f, float %g, float %h, float %i) nounwind {
; RV32-ILP32FD-LABEL: callee_float_in_gpr_exhausted_fprs:
; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: fcvt.w.s a1, fa7, rtz
; RV32-ILP32FD-NEXT: fmv.w.x ft0, a0
; RV32-ILP32FD-NEXT: fcvt.w.s a0, ft0, rtz
; RV32-ILP32FD-NEXT: add a0, a1, a0
; RV32-ILP32FD-NEXT: fcvt.w.s a0, fa7, rtz
; RV32-ILP32FD-NEXT: fcvt.w.s a1, ft0, rtz
; RV32-ILP32FD-NEXT: add a0, a0, a1
; RV32-ILP32FD-NEXT: ret
%h_fptosi = fptosi float %h to i32
%i_fptosi = fptosi float %i to i32
Expand All @@ -99,21 +99,21 @@ define i32 @caller_float_in_gpr_exhausted_fprs() nounwind {
; RV32-ILP32FD-NEXT: sw ra, 12(sp)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_0)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_0)
; RV32-ILP32FD-NEXT: lui a1, %hi(.LCPI5_1)
; RV32-ILP32FD-NEXT: addi a1, a1, %lo(.LCPI5_1)
; RV32-ILP32FD-NEXT: lui a2, %hi(.LCPI5_2)
; RV32-ILP32FD-NEXT: addi a2, a2, %lo(.LCPI5_2)
; RV32-ILP32FD-NEXT: lui a3, %hi(.LCPI5_3)
; RV32-ILP32FD-NEXT: addi a3, a3, %lo(.LCPI5_3)
; RV32-ILP32FD-NEXT: lui a4, %hi(.LCPI5_4)
; RV32-ILP32FD-NEXT: addi a4, a4, %lo(.LCPI5_4)
; RV32-ILP32FD-NEXT: lui a5, %hi(.LCPI5_5)
; RV32-ILP32FD-NEXT: addi a5, a5, %lo(.LCPI5_5)
; RV32-ILP32FD-NEXT: flw fa0, 0(a5)
; RV32-ILP32FD-NEXT: flw fa1, 0(a4)
; RV32-ILP32FD-NEXT: flw fa2, 0(a3)
; RV32-ILP32FD-NEXT: flw fa3, 0(a2)
; RV32-ILP32FD-NEXT: flw fa4, 0(a1)
; RV32-ILP32FD-NEXT: flw fa0, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_1)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_1)
; RV32-ILP32FD-NEXT: flw fa1, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_2)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_2)
; RV32-ILP32FD-NEXT: flw fa2, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_3)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_3)
; RV32-ILP32FD-NEXT: flw fa3, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_4)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_4)
; RV32-ILP32FD-NEXT: flw fa4, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_5)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_5)
; RV32-ILP32FD-NEXT: flw fa5, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI5_6)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI5_6)
Expand Down Expand Up @@ -151,39 +151,39 @@ define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind {
; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: addi sp, sp, -16
; RV32-ILP32FD-NEXT: sw ra, 12(sp)
; RV32-ILP32FD-NEXT: lui a0, 267520
; RV32-ILP32FD-NEXT: sw a0, 0(sp)
; RV32-ILP32FD-NEXT: lui a1, 267520
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_0)
; RV32-ILP32FD-NEXT: addi a6, a0, %lo(.LCPI7_0)
; RV32-ILP32FD-NEXT: lui a1, %hi(.LCPI7_1)
; RV32-ILP32FD-NEXT: addi a1, a1, %lo(.LCPI7_1)
; RV32-ILP32FD-NEXT: lui a2, %hi(.LCPI7_2)
; RV32-ILP32FD-NEXT: addi a2, a2, %lo(.LCPI7_2)
; RV32-ILP32FD-NEXT: lui a3, %hi(.LCPI7_3)
; RV32-ILP32FD-NEXT: addi a3, a3, %lo(.LCPI7_3)
; RV32-ILP32FD-NEXT: lui a4, %hi(.LCPI7_4)
; RV32-ILP32FD-NEXT: addi a4, a4, %lo(.LCPI7_4)
; RV32-ILP32FD-NEXT: lui a5, %hi(.LCPI7_5)
; RV32-ILP32FD-NEXT: addi a5, a5, %lo(.LCPI7_5)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_0)
; RV32-ILP32FD-NEXT: flw fa0, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_1)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_1)
; RV32-ILP32FD-NEXT: flw fa1, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_2)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_2)
; RV32-ILP32FD-NEXT: flw fa2, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_3)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_3)
; RV32-ILP32FD-NEXT: flw fa3, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_4)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_4)
; RV32-ILP32FD-NEXT: flw fa4, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_5)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_5)
; RV32-ILP32FD-NEXT: flw fa5, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_6)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_6)
; RV32-ILP32FD-NEXT: flw fa0, 0(a0)
; RV32-ILP32FD-NEXT: flw fa1, 0(a5)
; RV32-ILP32FD-NEXT: flw fa2, 0(a4)
; RV32-ILP32FD-NEXT: flw fa3, 0(a3)
; RV32-ILP32FD-NEXT: flw fa4, 0(a2)
; RV32-ILP32FD-NEXT: flw fa5, 0(a1)
; RV32-ILP32FD-NEXT: flw fa6, 0(a6)
; RV32-ILP32FD-NEXT: flw fa6, 0(a0)
; RV32-ILP32FD-NEXT: lui a0, %hi(.LCPI7_7)
; RV32-ILP32FD-NEXT: addi a0, a0, %lo(.LCPI7_7)
; RV32-ILP32FD-NEXT: flw fa7, 0(a0)
; RV32-ILP32FD-NEXT: addi a0, zero, 1
; RV32-ILP32FD-NEXT: mv a1, zero
; RV32-ILP32FD-NEXT: addi a2, zero, 3
; RV32-ILP32FD-NEXT: mv a3, zero
; RV32-ILP32FD-NEXT: addi a4, zero, 5
; RV32-ILP32FD-NEXT: mv a5, zero
; RV32-ILP32FD-NEXT: addi a6, zero, 7
; RV32-ILP32FD-NEXT: sw a1, 0(sp)
; RV32-ILP32FD-NEXT: mv a1, zero
; RV32-ILP32FD-NEXT: mv a3, zero
; RV32-ILP32FD-NEXT: mv a5, zero
; RV32-ILP32FD-NEXT: mv a7, zero
; RV32-ILP32FD-NEXT: call callee_float_on_stack_exhausted_gprs_fprs
; RV32-ILP32FD-NEXT: lw ra, 12(sp)
Expand Down
168 changes: 84 additions & 84 deletions llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -48,22 +48,22 @@ define i64 @caller_i128_in_regs() nounwind {
define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i128 %d, i32 %e, i32 %f, i128 %g, i32 %h) nounwind {
; RV64I-LABEL: callee_many_scalars:
; RV64I: # %bb.0:
; RV64I-NEXT: ld t0, 0(sp)
; RV64I-NEXT: xor a4, a4, t0
; RV64I-NEXT: xor a3, a3, a7
; RV64I-NEXT: or a3, a3, a4
; RV64I-NEXT: lui a4, 16
; RV64I-NEXT: addiw a4, a4, -1
; RV64I-NEXT: and a1, a1, a4
; RV64I-NEXT: andi a0, a0, 255
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: lw t0, 8(sp)
; RV64I-NEXT: ld t1, 0(sp)
; RV64I-NEXT: andi t2, a0, 255
; RV64I-NEXT: lui a0, 16
; RV64I-NEXT: addiw a0, a0, -1
; RV64I-NEXT: and a0, a1, a0
; RV64I-NEXT: add a0, t2, a0
; RV64I-NEXT: add a0, a0, a2
; RV64I-NEXT: seqz a1, a3
; RV64I-NEXT: xor a1, a4, t1
; RV64I-NEXT: xor a2, a3, a7
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: seqz a1, a1
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: add a0, a0, a5
; RV64I-NEXT: add a0, a0, a6
; RV64I-NEXT: lw a1, 8(sp)
; RV64I-NEXT: addw a0, a0, a1
; RV64I-NEXT: addw a0, a0, t0
; RV64I-NEXT: ret
%a_ext = zext i8 %a to i32
%b_ext = zext i16 %b to i32
Expand All @@ -85,15 +85,15 @@ define i32 @caller_many_scalars() nounwind {
; RV64I-NEXT: sd ra, 24(sp)
; RV64I-NEXT: addi a0, zero, 8
; RV64I-NEXT: sd a0, 8(sp)
; RV64I-NEXT: sd zero, 0(sp)
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: addi a5, zero, 5
; RV64I-NEXT: addi a6, zero, 6
; RV64I-NEXT: addi a7, zero, 7
; RV64I-NEXT: sd zero, 0(sp)
; RV64I-NEXT: mv a4, zero
; RV64I-NEXT: call callee_many_scalars
; RV64I-NEXT: ld ra, 24(sp)
; RV64I-NEXT: addi sp, sp, 32
Expand All @@ -107,20 +107,20 @@ define i32 @caller_many_scalars() nounwind {
define i64 @callee_large_scalars(i256 %a, i256 %b) nounwind {
; RV64I-LABEL: callee_large_scalars:
; RV64I: # %bb.0:
; RV64I-NEXT: ld a2, 24(a1)
; RV64I-NEXT: ld a3, 24(a0)
; RV64I-NEXT: xor a2, a3, a2
; RV64I-NEXT: ld a3, 8(a1)
; RV64I-NEXT: ld a4, 8(a0)
; RV64I-NEXT: xor a3, a4, a3
; RV64I-NEXT: ld a6, 0(a1)
; RV64I-NEXT: ld a7, 0(a0)
; RV64I-NEXT: ld a4, 8(a1)
; RV64I-NEXT: ld a5, 24(a1)
; RV64I-NEXT: ld a2, 24(a0)
; RV64I-NEXT: ld a3, 8(a0)
; RV64I-NEXT: ld a1, 16(a1)
; RV64I-NEXT: ld a0, 16(a0)
; RV64I-NEXT: xor a2, a2, a5
; RV64I-NEXT: xor a3, a3, a4
; RV64I-NEXT: or a2, a3, a2
; RV64I-NEXT: ld a3, 16(a1)
; RV64I-NEXT: ld a4, 16(a0)
; RV64I-NEXT: xor a3, a4, a3
; RV64I-NEXT: ld a1, 0(a1)
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: xor a0, a0, a1
; RV64I-NEXT: or a0, a0, a3
; RV64I-NEXT: xor a1, a7, a6
; RV64I-NEXT: or a0, a1, a0
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
Expand All @@ -134,18 +134,18 @@ define i64 @caller_large_scalars() nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -80
; RV64I-NEXT: sd ra, 72(sp)
; RV64I-NEXT: addi a0, zero, 2
; RV64I-NEXT: sd a0, 0(sp)
; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: sd zero, 16(sp)
; RV64I-NEXT: sd zero, 8(sp)
; RV64I-NEXT: addi a0, zero, 2
; RV64I-NEXT: sd a0, 0(sp)
; RV64I-NEXT: sd zero, 56(sp)
; RV64I-NEXT: sd zero, 48(sp)
; RV64I-NEXT: sd zero, 40(sp)
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: sd a0, 32(sp)
; RV64I-NEXT: addi a2, zero, 1
; RV64I-NEXT: addi a0, sp, 32
; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: sd a2, 32(sp)
; RV64I-NEXT: call callee_large_scalars
; RV64I-NEXT: ld ra, 72(sp)
; RV64I-NEXT: addi sp, sp, 80
Expand All @@ -162,20 +162,20 @@ define i64 @callee_large_scalars_exhausted_regs(i64 %a, i64 %b, i64 %c, i64 %d,
; RV64I-LABEL: callee_large_scalars_exhausted_regs:
; RV64I: # %bb.0:
; RV64I-NEXT: ld a0, 8(sp)
; RV64I-NEXT: ld a1, 24(a0)
; RV64I-NEXT: ld a2, 24(a7)
; RV64I-NEXT: xor a1, a2, a1
; RV64I-NEXT: ld a2, 8(a0)
; RV64I-NEXT: ld a3, 8(a7)
; RV64I-NEXT: xor a2, a3, a2
; RV64I-NEXT: or a1, a2, a1
; RV64I-NEXT: ld a2, 16(a0)
; RV64I-NEXT: ld a3, 16(a7)
; RV64I-NEXT: xor a2, a3, a2
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: ld a3, 0(a7)
; RV64I-NEXT: xor a0, a3, a0
; RV64I-NEXT: or a0, a0, a2
; RV64I-NEXT: ld a6, 0(a0)
; RV64I-NEXT: ld t0, 0(a7)
; RV64I-NEXT: ld a3, 8(a0)
; RV64I-NEXT: ld a4, 24(a0)
; RV64I-NEXT: ld a5, 24(a7)
; RV64I-NEXT: ld a1, 8(a7)
; RV64I-NEXT: ld a0, 16(a0)
; RV64I-NEXT: ld a2, 16(a7)
; RV64I-NEXT: xor a4, a5, a4
; RV64I-NEXT: xor a1, a1, a3
; RV64I-NEXT: or a1, a1, a4
; RV64I-NEXT: xor a0, a2, a0
; RV64I-NEXT: xor a2, t0, a6
; RV64I-NEXT: or a0, a2, a0
; RV64I-NEXT: or a0, a0, a1
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ret
Expand All @@ -193,16 +193,15 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
; RV64I-NEXT: sd a0, 8(sp)
; RV64I-NEXT: addi a0, zero, 9
; RV64I-NEXT: sd a0, 0(sp)
; RV64I-NEXT: addi a0, zero, 10
; RV64I-NEXT: sd a0, 16(sp)
; RV64I-NEXT: sd zero, 40(sp)
; RV64I-NEXT: sd zero, 32(sp)
; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: addi a0, zero, 10
; RV64I-NEXT: sd a0, 16(sp)
; RV64I-NEXT: sd zero, 72(sp)
; RV64I-NEXT: sd zero, 64(sp)
; RV64I-NEXT: sd zero, 56(sp)
; RV64I-NEXT: addi a0, zero, 8
; RV64I-NEXT: sd a0, 48(sp)
; RV64I-NEXT: addi t0, zero, 8
; RV64I-NEXT: addi a7, sp, 48
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: addi a1, zero, 2
Expand All @@ -211,6 +210,7 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: addi a5, zero, 6
; RV64I-NEXT: addi a6, zero, 7
; RV64I-NEXT: sd t0, 48(sp)
; RV64I-NEXT: call callee_large_scalars_exhausted_regs
; RV64I-NEXT: ld ra, 88(sp)
; RV64I-NEXT: addi sp, sp, 96
Expand Down Expand Up @@ -277,9 +277,9 @@ define i64 @caller_small_coerced_struct() nounwind {
define i64 @callee_large_struct(%struct.large* byval align 8 %a) nounwind {
; RV64I-LABEL: callee_large_struct:
; RV64I: # %bb.0:
; RV64I-NEXT: ld a1, 24(a0)
; RV64I-NEXT: ld a0, 0(a0)
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ld a1, 0(a0)
; RV64I-NEXT: ld a0, 24(a0)
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret
%1 = getelementptr inbounds %struct.large, %struct.large* %a, i64 0, i32 0
%2 = getelementptr inbounds %struct.large, %struct.large* %a, i64 0, i32 3
Expand All @@ -296,16 +296,16 @@ define i64 @caller_large_struct() nounwind {
; RV64I-NEXT: sd ra, 72(sp)
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: sd a0, 40(sp)
; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: sd a1, 48(sp)
; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: sd a2, 56(sp)
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: sd a3, 64(sp)
; RV64I-NEXT: sd a0, 8(sp)
; RV64I-NEXT: addi a0, zero, 2
; RV64I-NEXT: sd a0, 48(sp)
; RV64I-NEXT: sd a0, 16(sp)
; RV64I-NEXT: addi a0, zero, 3
; RV64I-NEXT: sd a0, 56(sp)
; RV64I-NEXT: sd a0, 24(sp)
; RV64I-NEXT: addi a0, zero, 4
; RV64I-NEXT: sd a0, 64(sp)
; RV64I-NEXT: sd a0, 32(sp)
; RV64I-NEXT: sd a1, 16(sp)
; RV64I-NEXT: sd a2, 24(sp)
; RV64I-NEXT: sd a3, 32(sp)
; RV64I-NEXT: addi a0, sp, 8
; RV64I-NEXT: call callee_large_struct
; RV64I-NEXT: ld ra, 72(sp)
Expand All @@ -332,15 +332,15 @@ define i64 @callee_aligned_stack(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e, i128 %f
; should only be 8-byte aligned
; RV64I-LABEL: callee_aligned_stack:
; RV64I: # %bb.0:
; RV64I-NEXT: add a0, a5, a7
; RV64I-NEXT: ld a0, 40(sp)
; RV64I-NEXT: ld a1, 0(sp)
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ld a1, 16(sp)
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ld a1, 32(sp)
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ld a1, 40(sp)
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ld a2, 16(sp)
; RV64I-NEXT: ld a3, 32(sp)
; RV64I-NEXT: add a4, a5, a7
; RV64I-NEXT: add a1, a4, a1
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: add a1, a1, a3
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ret
%f_trunc = trunc i128 %f to i64
%1 = add i64 %f_trunc, %g
Expand All @@ -366,19 +366,19 @@ define void @caller_aligned_stack() nounwind {
; RV64I-NEXT: sd a0, 40(sp)
; RV64I-NEXT: addi a0, zero, 10
; RV64I-NEXT: sd a0, 32(sp)
; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: addi a0, zero, 9
; RV64I-NEXT: sd a0, 16(sp)
; RV64I-NEXT: addi a0, zero, 8
; RV64I-NEXT: sd a0, 0(sp)
; RV64I-NEXT: sd zero, 24(sp)
; RV64I-NEXT: addi a6, zero, 8
; RV64I-NEXT: addi a0, zero, 1
; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: addi a2, zero, 3
; RV64I-NEXT: addi a3, zero, 4
; RV64I-NEXT: addi a4, zero, 5
; RV64I-NEXT: addi a5, zero, 6
; RV64I-NEXT: mv a6, zero
; RV64I-NEXT: addi a7, zero, 7
; RV64I-NEXT: sd a6, 0(sp)
; RV64I-NEXT: mv a6, zero
; RV64I-NEXT: call callee_aligned_stack
; RV64I-NEXT: ld ra, 56(sp)
; RV64I-NEXT: addi sp, sp, 64
Expand Down Expand Up @@ -482,18 +482,18 @@ define void @caller_large_scalar_ret() nounwind {
define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) nounwind {
; RV64I-LABEL: callee_large_struct_ret:
; RV64I: # %bb.0:
; RV64I-NEXT: addi a1, zero, 4
; RV64I-NEXT: sw a1, 24(a0)
; RV64I-NEXT: addi a1, zero, 3
; RV64I-NEXT: sw a1, 16(a0)
; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: sw a1, 8(a0)
; RV64I-NEXT: sw zero, 28(a0)
; RV64I-NEXT: sw zero, 20(a0)
; RV64I-NEXT: sw zero, 12(a0)
; RV64I-NEXT: sw zero, 4(a0)
; RV64I-NEXT: addi a1, zero, 1
; RV64I-NEXT: sw a1, 0(a0)
; RV64I-NEXT: sw zero, 12(a0)
; RV64I-NEXT: addi a1, zero, 2
; RV64I-NEXT: sw a1, 8(a0)
; RV64I-NEXT: sw zero, 20(a0)
; RV64I-NEXT: addi a1, zero, 3
; RV64I-NEXT: sw a1, 16(a0)
; RV64I-NEXT: sw zero, 28(a0)
; RV64I-NEXT: addi a1, zero, 4
; RV64I-NEXT: sw a1, 24(a0)
; RV64I-NEXT: ret
%a = getelementptr inbounds %struct.large, %struct.large* %agg.result, i64 0, i32 0
store i64 1, i64* %a, align 4
Expand All @@ -513,9 +513,9 @@ define i64 @caller_large_struct_ret() nounwind {
; RV64I-NEXT: sd ra, 40(sp)
; RV64I-NEXT: addi a0, sp, 8
; RV64I-NEXT: call callee_large_struct_ret
; RV64I-NEXT: ld a0, 32(sp)
; RV64I-NEXT: ld a1, 8(sp)
; RV64I-NEXT: add a0, a1, a0
; RV64I-NEXT: ld a0, 8(sp)
; RV64I-NEXT: ld a1, 32(sp)
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ld ra, 40(sp)
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -108,15 +108,15 @@ define i64 @caller_float_on_stack() nounwind {
; RV64I-FPELIM: # %bb.0:
; RV64I-FPELIM-NEXT: addi sp, sp, -16
; RV64I-FPELIM-NEXT: sd ra, 8(sp)
; RV64I-FPELIM-NEXT: lui a0, 264704
; RV64I-FPELIM-NEXT: sd a0, 0(sp)
; RV64I-FPELIM-NEXT: lui a1, 264704
; RV64I-FPELIM-NEXT: addi a0, zero, 1
; RV64I-FPELIM-NEXT: mv a1, zero
; RV64I-FPELIM-NEXT: addi a2, zero, 2
; RV64I-FPELIM-NEXT: mv a3, zero
; RV64I-FPELIM-NEXT: addi a4, zero, 3
; RV64I-FPELIM-NEXT: mv a5, zero
; RV64I-FPELIM-NEXT: addi a6, zero, 4
; RV64I-FPELIM-NEXT: sd a1, 0(sp)
; RV64I-FPELIM-NEXT: mv a1, zero
; RV64I-FPELIM-NEXT: mv a3, zero
; RV64I-FPELIM-NEXT: mv a5, zero
; RV64I-FPELIM-NEXT: mv a7, zero
; RV64I-FPELIM-NEXT: call callee_float_on_stack
; RV64I-FPELIM-NEXT: ld ra, 8(sp)
Expand All @@ -129,15 +129,15 @@ define i64 @caller_float_on_stack() nounwind {
; RV64I-WITHFP-NEXT: sd ra, 24(sp)
; RV64I-WITHFP-NEXT: sd s0, 16(sp)
; RV64I-WITHFP-NEXT: addi s0, sp, 32
; RV64I-WITHFP-NEXT: lui a0, 264704
; RV64I-WITHFP-NEXT: sd a0, 0(sp)
; RV64I-WITHFP-NEXT: lui a1, 264704
; RV64I-WITHFP-NEXT: addi a0, zero, 1
; RV64I-WITHFP-NEXT: mv a1, zero
; RV64I-WITHFP-NEXT: addi a2, zero, 2
; RV64I-WITHFP-NEXT: mv a3, zero
; RV64I-WITHFP-NEXT: addi a4, zero, 3
; RV64I-WITHFP-NEXT: mv a5, zero
; RV64I-WITHFP-NEXT: addi a6, zero, 4
; RV64I-WITHFP-NEXT: sd a1, 0(sp)
; RV64I-WITHFP-NEXT: mv a1, zero
; RV64I-WITHFP-NEXT: mv a3, zero
; RV64I-WITHFP-NEXT: mv a5, zero
; RV64I-WITHFP-NEXT: mv a7, zero
; RV64I-WITHFP-NEXT: call callee_float_on_stack
; RV64I-WITHFP-NEXT: ld s0, 16(sp)
Expand Down
28 changes: 14 additions & 14 deletions llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -33,15 +33,15 @@ define float @caller_onstack_f32_noop(float %a) nounwind {
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: sw a0, 4(sp)
; RV32IF-NEXT: lui a0, 264704
; RV32IF-NEXT: sw a0, 0(sp)
; RV32IF-NEXT: lui a1, 264704
; RV32IF-NEXT: addi a0, zero, 1
; RV32IF-NEXT: mv a1, zero
; RV32IF-NEXT: addi a2, zero, 2
; RV32IF-NEXT: mv a3, zero
; RV32IF-NEXT: addi a4, zero, 3
; RV32IF-NEXT: mv a5, zero
; RV32IF-NEXT: addi a6, zero, 4
; RV32IF-NEXT: sw a1, 0(sp)
; RV32IF-NEXT: mv a1, zero
; RV32IF-NEXT: mv a3, zero
; RV32IF-NEXT: mv a5, zero
; RV32IF-NEXT: mv a7, zero
; RV32IF-NEXT: call onstack_f32_noop
; RV32IF-NEXT: lw ra, 12(sp)
Expand All @@ -56,19 +56,19 @@ define float @caller_onstack_f32_fadd(float %a, float %b) nounwind {
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fsub.s ft2, ft1, ft0
; RV32IF-NEXT: fsw ft2, 4(sp)
; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: fsw ft0, 0(sp)
; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fadd.s ft2, ft1, ft0
; RV32IF-NEXT: fsub.s ft0, ft0, ft1
; RV32IF-NEXT: fsw ft0, 4(sp)
; RV32IF-NEXT: addi a0, zero, 1
; RV32IF-NEXT: mv a1, zero
; RV32IF-NEXT: addi a2, zero, 2
; RV32IF-NEXT: mv a3, zero
; RV32IF-NEXT: addi a4, zero, 3
; RV32IF-NEXT: mv a5, zero
; RV32IF-NEXT: addi a6, zero, 4
; RV32IF-NEXT: fsw ft2, 0(sp)
; RV32IF-NEXT: mv a1, zero
; RV32IF-NEXT: mv a3, zero
; RV32IF-NEXT: mv a5, zero
; RV32IF-NEXT: mv a7, zero
; RV32IF-NEXT: call onstack_f32_noop
; RV32IF-NEXT: lw ra, 12(sp)
Expand Down
18 changes: 9 additions & 9 deletions llvm/test/CodeGen/RISCV/codemodel-lowering.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -61,9 +61,9 @@ define signext i32 @lower_blockaddress_displ(i32 signext %w) nounwind {
; RV32I-SMALL-NEXT: sw ra, 12(sp)
; RV32I-SMALL-NEXT: lui a1, %hi(.Ltmp0)
; RV32I-SMALL-NEXT: addi a1, a1, %lo(.Ltmp0)
; RV32I-SMALL-NEXT: addi a2, zero, 101
; RV32I-SMALL-NEXT: sw a1, 8(sp)
; RV32I-SMALL-NEXT: addi a1, zero, 101
; RV32I-SMALL-NEXT: blt a0, a1, .LBB2_3
; RV32I-SMALL-NEXT: blt a0, a2, .LBB2_3
; RV32I-SMALL-NEXT: # %bb.1: # %if.then
; RV32I-SMALL-NEXT: lw a0, 8(sp)
; RV32I-SMALL-NEXT: jr a0
Expand All @@ -86,9 +86,9 @@ define signext i32 @lower_blockaddress_displ(i32 signext %w) nounwind {
; RV32I-MEDIUM-NEXT: # Label of block must be emitted
; RV32I-MEDIUM-NEXT: auipc a1, %pcrel_hi(.Ltmp0)
; RV32I-MEDIUM-NEXT: addi a1, a1, %pcrel_lo(.LBB2_5)
; RV32I-MEDIUM-NEXT: addi a2, zero, 101
; RV32I-MEDIUM-NEXT: sw a1, 8(sp)
; RV32I-MEDIUM-NEXT: addi a1, zero, 101
; RV32I-MEDIUM-NEXT: blt a0, a1, .LBB2_3
; RV32I-MEDIUM-NEXT: blt a0, a2, .LBB2_3
; RV32I-MEDIUM-NEXT: # %bb.1: # %if.then
; RV32I-MEDIUM-NEXT: lw a0, 8(sp)
; RV32I-MEDIUM-NEXT: jr a0
Expand Down Expand Up @@ -131,11 +131,11 @@ indirectgoto:
define float @lower_constantpool(float %a) nounwind {
; RV32I-SMALL-LABEL: lower_constantpool:
; RV32I-SMALL: # %bb.0:
; RV32I-SMALL-NEXT: fmv.w.x ft0, a0
; RV32I-SMALL-NEXT: lui a0, %hi(.LCPI3_0)
; RV32I-SMALL-NEXT: addi a0, a0, %lo(.LCPI3_0)
; RV32I-SMALL-NEXT: flw ft1, 0(a0)
; RV32I-SMALL-NEXT: fadd.s ft0, ft0, ft1
; RV32I-SMALL-NEXT: lui a1, %hi(.LCPI3_0)
; RV32I-SMALL-NEXT: addi a1, a1, %lo(.LCPI3_0)
; RV32I-SMALL-NEXT: flw ft0, 0(a1)
; RV32I-SMALL-NEXT: fmv.w.x ft1, a0
; RV32I-SMALL-NEXT: fadd.s ft0, ft1, ft0
; RV32I-SMALL-NEXT: fmv.x.w a0, ft0
; RV32I-SMALL-NEXT: ret
;
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/compress.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -19,10 +19,10 @@

define i32 @simple_arith(i32 %a, i32 %b) nounwind {
; RV32IC-LABEL: simple_arith:
; RV32IC: c.srai a1, 9
; RV32IC-NEXT: addi a2, a0, 1
; RV32IC: addi a2, a0, 1
; RV32IC-NEXT: c.andi a2, 11
; RV32IC-NEXT: c.slli a2, 7
; RV32IC-NEXT: c.srai a1, 9
; RV32IC-NEXT: c.add a1, a2
; RV32IC-NEXT: sub a0, a1, a0
; RV32IC-NEXT: c.jr ra
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/div.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -457,8 +457,8 @@ define i64 @sdiv64_sext_operands(i32 %a, i32 %b) nounwind {
;
; RV64IM-LABEL: sdiv64_sext_operands:
; RV64IM: # %bb.0:
; RV64IM-NEXT: sext.w a1, a1
; RV64IM-NEXT: sext.w a0, a0
; RV64IM-NEXT: sext.w a1, a1
; RV64IM-NEXT: div a0, a0, a1
; RV64IM-NEXT: ret
%1 = sext i32 %a to i64
Expand Down
46 changes: 23 additions & 23 deletions llvm/test/CodeGen/RISCV/double-arith.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -473,13 +473,13 @@ define double @fmsub_d(double %a, double %b, double %c) nounwind {
;
; RV64IFD-LABEL: fmsub_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a2
; RV64IFD-NEXT: lui a2, %hi(.LCPI15_0)
; RV64IFD-NEXT: addi a2, a2, %lo(.LCPI15_0)
; RV64IFD-NEXT: fld ft1, 0(a2)
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: lui a3, %hi(.LCPI15_0)
; RV64IFD-NEXT: addi a3, a3, %lo(.LCPI15_0)
; RV64IFD-NEXT: fld ft0, 0(a3)
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fmv.d.x ft2, a0
; RV64IFD-NEXT: fmv.d.x ft3, a2
; RV64IFD-NEXT: fadd.d ft0, ft3, ft0
; RV64IFD-NEXT: fmsub.d ft0, ft2, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
Expand All @@ -496,18 +496,18 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind {
; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: sw a4, 8(sp)
; RV32IFD-NEXT: sw a5, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft2, 8(sp)
; RV32IFD-NEXT: lui a0, %hi(.LCPI16_0)
; RV32IFD-NEXT: addi a0, a0, %lo(.LCPI16_0)
; RV32IFD-NEXT: fld ft3, 0(a0)
; RV32IFD-NEXT: fadd.d ft2, ft2, ft3
; RV32IFD-NEXT: fadd.d ft1, ft1, ft3
; RV32IFD-NEXT: fnmadd.d ft0, ft1, ft0, ft2
; RV32IFD-NEXT: fnmadd.d ft0, ft2, ft0, ft1
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
Expand All @@ -516,15 +516,15 @@ define double @fnmadd_d(double %a, double %b, double %c) nounwind {
;
; RV64IFD-LABEL: fnmadd_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a2
; RV64IFD-NEXT: lui a2, %hi(.LCPI16_0)
; RV64IFD-NEXT: addi a2, a2, %lo(.LCPI16_0)
; RV64IFD-NEXT: fld ft1, 0(a2)
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.d.x ft2, a0
; RV64IFD-NEXT: fadd.d ft1, ft2, ft1
; RV64IFD-NEXT: fmv.d.x ft2, a1
; RV64IFD-NEXT: fnmadd.d ft0, ft1, ft2, ft0
; RV64IFD-NEXT: lui a3, %hi(.LCPI16_0)
; RV64IFD-NEXT: addi a3, a3, %lo(.LCPI16_0)
; RV64IFD-NEXT: fld ft0, 0(a3)
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fmv.d.x ft2, a2
; RV64IFD-NEXT: fmv.d.x ft3, a0
; RV64IFD-NEXT: fadd.d ft3, ft3, ft0
; RV64IFD-NEXT: fadd.d ft0, ft2, ft0
; RV64IFD-NEXT: fnmadd.d ft0, ft3, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%a_ = fadd double 0.0, %a
Expand Down Expand Up @@ -561,13 +561,13 @@ define double @fnmsub_d(double %a, double %b, double %c) nounwind {
;
; RV64IFD-LABEL: fnmsub_d:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: lui a0, %hi(.LCPI17_0)
; RV64IFD-NEXT: addi a0, a0, %lo(.LCPI17_0)
; RV64IFD-NEXT: fld ft1, 0(a0)
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: lui a3, %hi(.LCPI17_0)
; RV64IFD-NEXT: addi a3, a3, %lo(.LCPI17_0)
; RV64IFD-NEXT: fld ft0, 0(a3)
; RV64IFD-NEXT: fmv.d.x ft1, a2
; RV64IFD-NEXT: fmv.d.x ft2, a1
; RV64IFD-NEXT: fmv.d.x ft3, a0
; RV64IFD-NEXT: fadd.d ft0, ft3, ft0
; RV64IFD-NEXT: fnmsub.d ft0, ft0, ft2, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/double-bitmanip-dagcombines.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -118,9 +118,9 @@ define double @fcopysign_fneg(double %a, double %b) nounwind {
;
; RV64I-LABEL: fcopysign_fneg:
; RV64I: # %bb.0:
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: addi a2, zero, -1
; RV64I-NEXT: slli a2, a2, 63
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: and a1, a1, a2
; RV64I-NEXT: addi a2, a2, -1
; RV64I-NEXT: and a0, a0, a2
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/double-br-fcmp.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -385,11 +385,11 @@ define void @br_fcmp_ord(double %a, double %b) nounwind {
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp)
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft0
; RV64IFD-NEXT: and a0, a0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: bnez a0, .LBB8_2
; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp)
Expand Down Expand Up @@ -712,11 +712,11 @@ define void @br_fcmp_uno(double %a, double %b) nounwind {
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp)
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft0
; RV64IFD-NEXT: and a0, a0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: seqz a0, a0
; RV64IFD-NEXT: bnez a0, .LBB15_2
; RV64IFD-NEXT: # %bb.1: # %if.else
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/double-calling-conv.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -76,16 +76,16 @@ define double @caller_double_split_reg_stack() nounwind {
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp)
; RV32IFD-NEXT: lui a0, 262510
; RV32IFD-NEXT: addi a0, a0, 327
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: addi a2, a0, 327
; RV32IFD-NEXT: lui a0, 262446
; RV32IFD-NEXT: addi a6, a0, 327
; RV32IFD-NEXT: lui a0, 713032
; RV32IFD-NEXT: addi a5, a0, -1311
; RV32IFD-NEXT: addi a0, zero, 1
; RV32IFD-NEXT: addi a1, zero, 2
; RV32IFD-NEXT: mv a2, zero
; RV32IFD-NEXT: addi a3, zero, 3
; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: mv a2, zero
; RV32IFD-NEXT: mv a4, zero
; RV32IFD-NEXT: mv a7, a5
; RV32IFD-NEXT: call callee_double_split_reg_stack
Expand Down Expand Up @@ -120,20 +120,20 @@ define double @caller_double_stack() nounwind {
; RV32IFD-NEXT: lui a0, 262510
; RV32IFD-NEXT: addi a0, a0, 327
; RV32IFD-NEXT: sw a0, 4(sp)
; RV32IFD-NEXT: lui a0, 713032
; RV32IFD-NEXT: addi a1, a0, -1311
; RV32IFD-NEXT: sw a1, 0(sp)
; RV32IFD-NEXT: lui a0, 262574
; RV32IFD-NEXT: addi a0, a0, 327
; RV32IFD-NEXT: sw a0, 12(sp)
; RV32IFD-NEXT: lui a0, 713032
; RV32IFD-NEXT: addi a0, a0, -1311
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: addi a0, zero, 1
; RV32IFD-NEXT: mv a1, zero
; RV32IFD-NEXT: addi a2, zero, 2
; RV32IFD-NEXT: mv a3, zero
; RV32IFD-NEXT: addi a4, zero, 3
; RV32IFD-NEXT: mv a5, zero
; RV32IFD-NEXT: addi a6, zero, 4
; RV32IFD-NEXT: sw a1, 8(sp)
; RV32IFD-NEXT: mv a1, zero
; RV32IFD-NEXT: mv a3, zero
; RV32IFD-NEXT: mv a5, zero
; RV32IFD-NEXT: mv a7, zero
; RV32IFD-NEXT: call callee_double_stack
; RV32IFD-NEXT: lw ra, 28(sp)
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/double-convert.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -257,9 +257,9 @@ define double @fmv_d_x(i64 %a, i64 %b) nounwind {
;
; RV64IFD-LABEL: fmv_d_x:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = bitcast i64 %a to double
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/double-fcmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -197,11 +197,11 @@ define i32 @fcmp_ord(double %a, double %b) nounwind {
;
; RV64IFD-LABEL: fcmp_ord:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft0
; RV64IFD-NEXT: and a0, a0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: ret
%1 = fcmp ord double %a, %b
%2 = zext i1 %1 to i32
Expand Down Expand Up @@ -397,11 +397,11 @@ define i32 @fcmp_uno(double %a, double %b) nounwind {
;
; RV64IFD-LABEL: fcmp_uno:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft0
; RV64IFD-NEXT: and a0, a0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: seqz a0, a0
; RV64IFD-NEXT: ret
%1 = fcmp uno double %a, %b
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/double-imm.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -49,11 +49,11 @@ define double @double_imm_op(double %a) nounwind {
;
; RV64IFD-LABEL: double_imm_op:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: lui a0, %hi(.LCPI1_0)
; RV64IFD-NEXT: addi a0, a0, %lo(.LCPI1_0)
; RV64IFD-NEXT: fld ft1, 0(a0)
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: lui a1, %hi(.LCPI1_0)
; RV64IFD-NEXT: addi a1, a1, %lo(.LCPI1_0)
; RV64IFD-NEXT: fld ft0, 0(a1)
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = fadd double %a, 1.0
Expand Down
55 changes: 25 additions & 30 deletions llvm/test/CodeGen/RISCV/double-intrinsics.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -111,28 +111,24 @@ define double @sincos_f64(double %a) nounwind {
; RV32IFD-NEXT: sw ra, 28(sp)
; RV32IFD-NEXT: sw s0, 24(sp)
; RV32IFD-NEXT: sw s1, 20(sp)
; RV32IFD-NEXT: sw s2, 16(sp)
; RV32IFD-NEXT: sw s3, 12(sp)
; RV32IFD-NEXT: mv s0, a1
; RV32IFD-NEXT: mv s1, a0
; RV32IFD-NEXT: call sin
; RV32IFD-NEXT: mv s2, a0
; RV32IFD-NEXT: mv s3, a1
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: fsd ft0, 0(sp)
; RV32IFD-NEXT: mv a0, s1
; RV32IFD-NEXT: mv a1, s0
; RV32IFD-NEXT: call cos
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw s2, 0(sp)
; RV32IFD-NEXT: sw s3, 4(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 0(sp)
; RV32IFD-NEXT: lw a0, 0(sp)
; RV32IFD-NEXT: lw a1, 4(sp)
; RV32IFD-NEXT: lw s3, 12(sp)
; RV32IFD-NEXT: lw s2, 16(sp)
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: lw s1, 20(sp)
; RV32IFD-NEXT: lw s0, 24(sp)
; RV32IFD-NEXT: lw ra, 28(sp)
Expand All @@ -144,17 +140,16 @@ define double @sincos_f64(double %a) nounwind {
; RV64IFD-NEXT: addi sp, sp, -32
; RV64IFD-NEXT: sd ra, 24(sp)
; RV64IFD-NEXT: sd s0, 16(sp)
; RV64IFD-NEXT: sd s1, 8(sp)
; RV64IFD-NEXT: mv s0, a0
; RV64IFD-NEXT: call sin
; RV64IFD-NEXT: mv s1, a0
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fsd ft0, 8(sp)
; RV64IFD-NEXT: mv a0, s0
; RV64IFD-NEXT: call cos
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, s1
; RV64IFD-NEXT: fld ft1, 8(sp)
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ld s1, 8(sp)
; RV64IFD-NEXT: ld s0, 16(sp)
; RV64IFD-NEXT: ld ra, 24(sp)
; RV64IFD-NEXT: addi sp, sp, 32
Expand Down Expand Up @@ -350,17 +345,17 @@ define double @fmuladd_f64(double %a, double %b, double %c) nounwind {
; RV32IFD-LABEL: fmuladd_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a4, 8(sp)
; RV32IFD-NEXT: sw a5, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: fmul.d ft0, ft1, ft0
; RV32IFD-NEXT: sw a4, 8(sp)
; RV32IFD-NEXT: sw a5, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; RV32IFD-NEXT: fld ft2, 8(sp)
; RV32IFD-NEXT: fmul.d ft1, ft2, ft1
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
Expand All @@ -369,11 +364,11 @@ define double @fmuladd_f64(double %a, double %b, double %c) nounwind {
;
; RV64IFD-LABEL: fmuladd_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fmul.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.d.x ft1, a2
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.d.x ft0, a2
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fmv.d.x ft2, a0
; RV64IFD-NEXT: fmul.d ft1, ft2, ft1
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = call double @llvm.fmuladd.f64(double %a, double %b, double %c)
Expand Down
73 changes: 34 additions & 39 deletions llvm/test/CodeGen/RISCV/double-mem.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -8,9 +8,9 @@ define double @fld(double *%a) nounwind {
; RV32IFD-LABEL: fld:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: fld ft0, 24(a0)
; RV32IFD-NEXT: fld ft1, 0(a0)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: fld ft0, 0(a0)
; RV32IFD-NEXT: fld ft1, 24(a0)
; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
Expand All @@ -19,9 +19,9 @@ define double @fld(double *%a) nounwind {
;
; RV64IFD-LABEL: fld:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fld ft0, 24(a0)
; RV64IFD-NEXT: fld ft1, 0(a0)
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fld ft0, 0(a0)
; RV64IFD-NEXT: fld ft1, 24(a0)
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ret
%1 = load double, double* %a
Expand All @@ -44,8 +44,8 @@ define void @fsd(double *%a, double %b, double %c) nounwind {
; RV32IFD-NEXT: sw a2, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: fsd ft0, 64(a0)
; RV32IFD-NEXT: fsd ft0, 0(a0)
; RV32IFD-NEXT: fsd ft0, 64(a0)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
Expand All @@ -54,8 +54,8 @@ define void @fsd(double *%a, double %b, double %c) nounwind {
; RV64IFD-NEXT: fmv.d.x ft0, a2
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fsd ft0, 64(a0)
; RV64IFD-NEXT: fsd ft0, 0(a0)
; RV64IFD-NEXT: fsd ft0, 64(a0)
; RV64IFD-NEXT: ret
; Use %b and %c in an FP op to ensure floating point registers are used, even
; for the soft float ABI
Expand Down Expand Up @@ -100,10 +100,10 @@ define double @fld_fsd_global(double %a, double %b) nounwind {
; RV64IFD-NEXT: lui a0, %hi(G)
; RV64IFD-NEXT: fld ft1, %lo(G)(a0)
; RV64IFD-NEXT: fsd ft0, %lo(G)(a0)
; RV64IFD-NEXT: addi a0, a0, %lo(G)
; RV64IFD-NEXT: fld ft1, 72(a0)
; RV64IFD-NEXT: fsd ft0, 72(a0)
; RV64IFD-NEXT: addi a1, a0, %lo(G)
; RV64IFD-NEXT: fld ft1, 72(a1)
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: fsd ft0, 72(a1)
; RV64IFD-NEXT: ret
; Use %a and %b in an FP op to ensure floating point registers are used, even
; for the soft float ABI
Expand Down Expand Up @@ -136,14 +136,14 @@ define double @fld_fsd_constant(double %a) nounwind {
;
; RV64IFD-LABEL: fld_fsd_constant:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: lui a0, 56
; RV64IFD-NEXT: addiw a0, a0, -1353
; RV64IFD-NEXT: slli a0, a0, 14
; RV64IFD-NEXT: fld ft1, -273(a0)
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fsd ft0, -273(a0)
; RV64IFD-NEXT: lui a1, 56
; RV64IFD-NEXT: addiw a1, a1, -1353
; RV64IFD-NEXT: slli a1, a1, 14
; RV64IFD-NEXT: fld ft0, -273(a1)
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: fsd ft0, -273(a1)
; RV64IFD-NEXT: ret
%1 = inttoptr i32 3735928559 to double*
%2 = load volatile double, double* %1
Expand All @@ -159,22 +159,18 @@ define double @fld_stack(double %a) nounwind {
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -32
; RV32IFD-NEXT: sw ra, 28(sp)
; RV32IFD-NEXT: sw s0, 24(sp)
; RV32IFD-NEXT: sw s1, 20(sp)
; RV32IFD-NEXT: mv s0, a1
; RV32IFD-NEXT: mv s1, a0
; RV32IFD-NEXT: addi a0, sp, 8
; RV32IFD-NEXT: call notdead
; RV32IFD-NEXT: sw s1, 0(sp)
; RV32IFD-NEXT: sw s0, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: fadd.d ft0, ft1, ft0
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: fsd ft0, 0(sp)
; RV32IFD-NEXT: lw a0, 0(sp)
; RV32IFD-NEXT: lw a1, 4(sp)
; RV32IFD-NEXT: lw s1, 20(sp)
; RV32IFD-NEXT: lw s0, 24(sp)
; RV32IFD-NEXT: addi a0, sp, 16
; RV32IFD-NEXT: call notdead
; RV32IFD-NEXT: fld ft0, 16(sp)
; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: fadd.d ft0, ft0, ft1
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: lw ra, 28(sp)
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
Expand All @@ -183,15 +179,14 @@ define double @fld_stack(double %a) nounwind {
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -32
; RV64IFD-NEXT: sd ra, 24(sp)
; RV64IFD-NEXT: sd s0, 16(sp)
; RV64IFD-NEXT: mv s0, a0
; RV64IFD-NEXT: addi a0, sp, 8
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fsd ft0, 8(sp)
; RV64IFD-NEXT: addi a0, sp, 16
; RV64IFD-NEXT: call notdead
; RV64IFD-NEXT: fmv.d.x ft0, s0
; RV64IFD-NEXT: fld ft0, 16(sp)
; RV64IFD-NEXT: fld ft1, 8(sp)
; RV64IFD-NEXT: fadd.d ft0, ft1, ft0
; RV64IFD-NEXT: fadd.d ft0, ft0, ft1
; RV64IFD-NEXT: fmv.x.d a0, ft0
; RV64IFD-NEXT: ld s0, 16(sp)
; RV64IFD-NEXT: ld ra, 24(sp)
; RV64IFD-NEXT: addi sp, sp, 32
; RV64IFD-NEXT: ret
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/double-previous-failure.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,8 +17,8 @@ define i32 @main() nounwind {
; RV32IFD: # %bb.0: # %entry
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw ra, 12(sp)
; RV32IFD-NEXT: mv a0, zero
; RV32IFD-NEXT: lui a1, 262144
; RV32IFD-NEXT: mv a0, zero
; RV32IFD-NEXT: call test
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp)
Expand Down
50 changes: 25 additions & 25 deletions llvm/test/CodeGen/RISCV/double-select-fcmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -298,38 +298,38 @@ define double @select_fcmp_ueq(double %a, double %b) nounwind {
; RV32IFD-LABEL: select_fcmp_ueq:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: addi sp, sp, -16
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a2, 8(sp)
; RV32IFD-NEXT: sw a3, 12(sp)
; RV32IFD-NEXT: fld ft0, 8(sp)
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft1
; RV32IFD-NEXT: feq.d a0, ft1, ft0
; RV32IFD-NEXT: feq.d a1, ft0, ft0
; RV32IFD-NEXT: and a0, a1, a0
; RV32IFD-NEXT: seqz a0, a0
; RV32IFD-NEXT: feq.d a1, ft0, ft1
; RV32IFD-NEXT: or a0, a1, a0
; RV32IFD-NEXT: feq.d a2, ft1, ft1
; RV32IFD-NEXT: and a1, a2, a1
; RV32IFD-NEXT: seqz a1, a1
; RV32IFD-NEXT: or a0, a0, a1
; RV32IFD-NEXT: bnez a0, .LBB8_2
; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: fmv.d ft0, ft1
; RV32IFD-NEXT: fmv.d ft1, ft0
; RV32IFD-NEXT: .LBB8_2:
; RV32IFD-NEXT: fsd ft0, 8(sp)
; RV32IFD-NEXT: fsd ft1, 8(sp)
; RV32IFD-NEXT: lw a0, 8(sp)
; RV32IFD-NEXT: lw a1, 12(sp)
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: select_fcmp_ueq:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: feq.d a0, ft1, ft1
; RV64IFD-NEXT: feq.d a1, ft0, ft0
; RV64IFD-NEXT: and a0, a1, a0
; RV64IFD-NEXT: seqz a0, a0
; RV64IFD-NEXT: feq.d a1, ft0, ft1
; RV64IFD-NEXT: or a0, a1, a0
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: feq.d a0, ft0, ft1
; RV64IFD-NEXT: feq.d a1, ft1, ft1
; RV64IFD-NEXT: feq.d a2, ft0, ft0
; RV64IFD-NEXT: and a1, a2, a1
; RV64IFD-NEXT: seqz a1, a1
; RV64IFD-NEXT: or a0, a0, a1
; RV64IFD-NEXT: bnez a0, .LBB8_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: fmv.d ft0, ft1
Expand Down Expand Up @@ -604,25 +604,25 @@ define i32 @i32_select_fcmp_oeq(double %a, double %b, i32 %c, i32 %d) nounwind {
; RV32IFD-NEXT: sw a0, 8(sp)
; RV32IFD-NEXT: sw a1, 12(sp)
; RV32IFD-NEXT: fld ft1, 8(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft0
; RV32IFD-NEXT: bnez a0, .LBB16_2
; RV32IFD-NEXT: feq.d a1, ft1, ft0
; RV32IFD-NEXT: mv a0, a4
; RV32IFD-NEXT: bnez a1, .LBB16_2
; RV32IFD-NEXT: # %bb.1:
; RV32IFD-NEXT: mv a4, a5
; RV32IFD-NEXT: mv a0, a5
; RV32IFD-NEXT: .LBB16_2:
; RV32IFD-NEXT: mv a0, a4
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
;
; RV64IFD-LABEL: i32_select_fcmp_oeq:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft0
; RV64IFD-NEXT: bnez a0, .LBB16_2
; RV64IFD-NEXT: feq.d a1, ft1, ft0
; RV64IFD-NEXT: mv a0, a2
; RV64IFD-NEXT: bnez a1, .LBB16_2
; RV64IFD-NEXT: # %bb.1:
; RV64IFD-NEXT: mv a2, a3
; RV64IFD-NEXT: mv a0, a3
; RV64IFD-NEXT: .LBB16_2:
; RV64IFD-NEXT: mv a0, a2
; RV64IFD-NEXT: ret
%1 = fcmp oeq double %a, %b
%2 = select i1 %1, i32 %c, i32 %d
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -37,10 +37,10 @@ define double @func(double %d, i32 %n) nounwind {
; RV64IFD: # %bb.0: # %entry
; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp)
; RV64IFD-NEXT: slli a2, a1, 32
; RV64IFD-NEXT: srli a2, a2, 32
; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: slli a0, a1, 32
; RV64IFD-NEXT: srli a0, a0, 32
; RV64IFD-NEXT: beqz a0, .LBB0_2
; RV64IFD-NEXT: beqz a2, .LBB0_2
; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: addi a1, a1, -1
; RV64IFD-NEXT: fmv.x.d a0, ft0
Expand Down
76 changes: 38 additions & 38 deletions llvm/test/CodeGen/RISCV/float-arith.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -339,26 +339,26 @@ define float @fmadd_s(float %a, float %b, float %c) nounwind {
define float @fmsub_s(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fmsub_s:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a2
; RV32IF-NEXT: lui a2, %hi(.LCPI15_0)
; RV32IF-NEXT: addi a2, a2, %lo(.LCPI15_0)
; RV32IF-NEXT: flw ft1, 0(a2)
; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: lui a3, %hi(.LCPI15_0)
; RV32IF-NEXT: addi a3, a3, %lo(.LCPI15_0)
; RV32IF-NEXT: flw ft0, 0(a3)
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fmv.w.x ft2, a0
; RV32IF-NEXT: fmv.w.x ft3, a2
; RV32IF-NEXT: fadd.s ft0, ft3, ft0
; RV32IF-NEXT: fmsub.s ft0, ft2, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fmsub_s:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a2
; RV64IF-NEXT: lui a2, %hi(.LCPI15_0)
; RV64IF-NEXT: addi a2, a2, %lo(.LCPI15_0)
; RV64IF-NEXT: flw ft1, 0(a2)
; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: lui a3, %hi(.LCPI15_0)
; RV64IF-NEXT: addi a3, a3, %lo(.LCPI15_0)
; RV64IF-NEXT: flw ft0, 0(a3)
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fmv.w.x ft2, a0
; RV64IF-NEXT: fmv.w.x ft3, a2
; RV64IF-NEXT: fadd.s ft0, ft3, ft0
; RV64IF-NEXT: fmsub.s ft0, ft2, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
Expand All @@ -371,29 +371,29 @@ define float @fmsub_s(float %a, float %b, float %c) nounwind {
define float @fnmadd_s(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmadd_s:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a2
; RV32IF-NEXT: lui a2, %hi(.LCPI16_0)
; RV32IF-NEXT: addi a2, a2, %lo(.LCPI16_0)
; RV32IF-NEXT: flw ft1, 0(a2)
; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: fmv.w.x ft2, a0
; RV32IF-NEXT: fadd.s ft1, ft2, ft1
; RV32IF-NEXT: fmv.w.x ft2, a1
; RV32IF-NEXT: fnmadd.s ft0, ft1, ft2, ft0
; RV32IF-NEXT: lui a3, %hi(.LCPI16_0)
; RV32IF-NEXT: addi a3, a3, %lo(.LCPI16_0)
; RV32IF-NEXT: flw ft0, 0(a3)
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fmv.w.x ft2, a2
; RV32IF-NEXT: fmv.w.x ft3, a0
; RV32IF-NEXT: fadd.s ft3, ft3, ft0
; RV32IF-NEXT: fadd.s ft0, ft2, ft0
; RV32IF-NEXT: fnmadd.s ft0, ft3, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fnmadd_s:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a2
; RV64IF-NEXT: lui a2, %hi(.LCPI16_0)
; RV64IF-NEXT: addi a2, a2, %lo(.LCPI16_0)
; RV64IF-NEXT: flw ft1, 0(a2)
; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: fmv.w.x ft2, a0
; RV64IF-NEXT: fadd.s ft1, ft2, ft1
; RV64IF-NEXT: fmv.w.x ft2, a1
; RV64IF-NEXT: fnmadd.s ft0, ft1, ft2, ft0
; RV64IF-NEXT: lui a3, %hi(.LCPI16_0)
; RV64IF-NEXT: addi a3, a3, %lo(.LCPI16_0)
; RV64IF-NEXT: flw ft0, 0(a3)
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fmv.w.x ft2, a2
; RV64IF-NEXT: fmv.w.x ft3, a0
; RV64IF-NEXT: fadd.s ft3, ft3, ft0
; RV64IF-NEXT: fadd.s ft0, ft2, ft0
; RV64IF-NEXT: fnmadd.s ft0, ft3, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
%a_ = fadd float 0.0, %a
Expand All @@ -407,26 +407,26 @@ define float @fnmadd_s(float %a, float %b, float %c) nounwind {
define float @fnmsub_s(float %a, float %b, float %c) nounwind {
; RV32IF-LABEL: fnmsub_s:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: lui a0, %hi(.LCPI17_0)
; RV32IF-NEXT: addi a0, a0, %lo(.LCPI17_0)
; RV32IF-NEXT: flw ft1, 0(a0)
; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: lui a3, %hi(.LCPI17_0)
; RV32IF-NEXT: addi a3, a3, %lo(.LCPI17_0)
; RV32IF-NEXT: flw ft0, 0(a3)
; RV32IF-NEXT: fmv.w.x ft1, a2
; RV32IF-NEXT: fmv.w.x ft2, a1
; RV32IF-NEXT: fmv.w.x ft3, a0
; RV32IF-NEXT: fadd.s ft0, ft3, ft0
; RV32IF-NEXT: fnmsub.s ft0, ft0, ft2, ft1
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fnmsub_s:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: lui a0, %hi(.LCPI17_0)
; RV64IF-NEXT: addi a0, a0, %lo(.LCPI17_0)
; RV64IF-NEXT: flw ft1, 0(a0)
; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: lui a3, %hi(.LCPI17_0)
; RV64IF-NEXT: addi a3, a3, %lo(.LCPI17_0)
; RV64IF-NEXT: flw ft0, 0(a3)
; RV64IF-NEXT: fmv.w.x ft1, a2
; RV64IF-NEXT: fmv.w.x ft2, a1
; RV64IF-NEXT: fmv.w.x ft3, a0
; RV64IF-NEXT: fadd.s ft0, ft3, ft0
; RV64IF-NEXT: fnmsub.s ft0, ft0, ft2, ft1
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/RISCV/float-br-fcmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -337,11 +337,11 @@ define void @br_fcmp_ord(float %a, float %b) nounwind {
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a0, ft0, ft0
; RV32IF-NEXT: and a0, a0, a1
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: bnez a0, .LBB8_2
; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp)
Expand All @@ -354,11 +354,11 @@ define void @br_fcmp_ord(float %a, float %b) nounwind {
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a0, ft0, ft0
; RV64IF-NEXT: and a0, a0, a1
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: bnez a0, .LBB8_2
; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp)
Expand Down Expand Up @@ -635,11 +635,11 @@ define void @br_fcmp_uno(float %a, float %b) nounwind {
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a0, ft0, ft0
; RV32IF-NEXT: and a0, a0, a1
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: seqz a0, a0
; RV32IF-NEXT: bnez a0, .LBB15_2
; RV32IF-NEXT: # %bb.1: # %if.else
Expand All @@ -653,11 +653,11 @@ define void @br_fcmp_uno(float %a, float %b) nounwind {
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a0, ft0, ft0
; RV64IF-NEXT: and a0, a0, a1
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: seqz a0, a0
; RV64IF-NEXT: bnez a0, .LBB15_2
; RV64IF-NEXT: # %bb.1: # %if.else
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/float-convert.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -97,17 +97,17 @@ define float @fcvt_s_wu(i32 %a) nounwind {
define float @fmv_w_x(i32 %a, i32 %b) nounwind {
; RV32IF-LABEL: fmv_w_x:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fmv_w_x:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
; Ensure fmv.w.x is generated even for a soft float calling convention
Expand Down
32 changes: 16 additions & 16 deletions llvm/test/CodeGen/RISCV/float-fcmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -146,20 +146,20 @@ define i32 @fcmp_one(float %a, float %b) nounwind {
define i32 @fcmp_ord(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_ord:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a0, ft0, ft0
; RV32IF-NEXT: and a0, a0, a1
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_ord:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a0, ft0, ft0
; RV64IF-NEXT: and a0, a0, a1
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: ret
%1 = fcmp ord float %a, %b
%2 = zext i1 %1 to i32
Expand Down Expand Up @@ -303,21 +303,21 @@ define i32 @fcmp_une(float %a, float %b) nounwind {
define i32 @fcmp_uno(float %a, float %b) nounwind {
; RV32IF-LABEL: fcmp_uno:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: feq.s a0, ft0, ft0
; RV32IF-NEXT: and a0, a0, a1
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: feq.s a0, ft1, ft1
; RV32IF-NEXT: feq.s a1, ft0, ft0
; RV32IF-NEXT: and a0, a1, a0
; RV32IF-NEXT: seqz a0, a0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fcmp_uno:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: feq.s a0, ft0, ft0
; RV64IF-NEXT: and a0, a0, a1
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: feq.s a0, ft1, ft1
; RV64IF-NEXT: feq.s a1, ft0, ft0
; RV64IF-NEXT: and a0, a1, a0
; RV64IF-NEXT: seqz a0, a0
; RV64IF-NEXT: ret
%1 = fcmp uno float %a, %b
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/float-imm.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -26,21 +26,21 @@ define float @float_imm_op(float %a) nounwind {
; TODO: addi should be folded in to the flw
; RV32IF-LABEL: float_imm_op:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: lui a0, %hi(.LCPI1_0)
; RV32IF-NEXT: addi a0, a0, %lo(.LCPI1_0)
; RV32IF-NEXT: flw ft1, 0(a0)
; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: lui a1, %hi(.LCPI1_0)
; RV32IF-NEXT: addi a1, a1, %lo(.LCPI1_0)
; RV32IF-NEXT: flw ft0, 0(a1)
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: float_imm_op:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: lui a0, %hi(.LCPI1_0)
; RV64IF-NEXT: addi a0, a0, %lo(.LCPI1_0)
; RV64IF-NEXT: flw ft1, 0(a0)
; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: lui a1, %hi(.LCPI1_0)
; RV64IF-NEXT: addi a1, a1, %lo(.LCPI1_0)
; RV64IF-NEXT: flw ft0, 0(a1)
; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
%1 = fadd float %a, 1.0
Expand Down
34 changes: 16 additions & 18 deletions llvm/test/CodeGen/RISCV/float-intrinsics.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -108,17 +108,16 @@ define float @sincos_f32(float %a) nounwind {
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: sw s0, 8(sp)
; RV32IF-NEXT: sw s1, 4(sp)
; RV32IF-NEXT: mv s0, a0
; RV32IF-NEXT: call sinf
; RV32IF-NEXT: mv s1, a0
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fsw ft0, 4(sp)
; RV32IF-NEXT: mv a0, s0
; RV32IF-NEXT: call cosf
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, s1
; RV32IF-NEXT: flw ft1, 4(sp)
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: lw s1, 4(sp)
; RV32IF-NEXT: lw s0, 8(sp)
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16
Expand All @@ -129,17 +128,16 @@ define float @sincos_f32(float %a) nounwind {
; RV64IF-NEXT: addi sp, sp, -32
; RV64IF-NEXT: sd ra, 24(sp)
; RV64IF-NEXT: sd s0, 16(sp)
; RV64IF-NEXT: sd s1, 8(sp)
; RV64IF-NEXT: mv s0, a0
; RV64IF-NEXT: call sinf
; RV64IF-NEXT: mv s1, a0
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fsw ft0, 12(sp)
; RV64IF-NEXT: mv a0, s0
; RV64IF-NEXT: call cosf
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, s1
; RV64IF-NEXT: flw ft1, 12(sp)
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ld s1, 8(sp)
; RV64IF-NEXT: ld s0, 16(sp)
; RV64IF-NEXT: ld ra, 24(sp)
; RV64IF-NEXT: addi sp, sp, 32
Expand Down Expand Up @@ -324,21 +322,21 @@ define float @fmuladd_f32(float %a, float %b, float %c) nounwind {
; Use of fmadd depends on TargetLowering::isFMAFasterthanFMulAndFAdd
; RV32IF-LABEL: fmuladd_f32:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fmul.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.w.x ft1, a2
; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: fmv.w.x ft0, a2
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fmv.w.x ft2, a0
; RV32IF-NEXT: fmul.s ft1, ft2, ft1
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fmuladd_f32:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fmul.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.w.x ft1, a2
; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: fmv.w.x ft0, a2
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fmv.w.x ft2, a0
; RV64IF-NEXT: fmul.s ft1, ft2, ft1
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
%1 = call float @llvm.fmuladd.f32(float %a, float %b, float %c)
Expand Down
84 changes: 41 additions & 43 deletions llvm/test/CodeGen/RISCV/float-mem.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -7,17 +7,17 @@
define float @flw(float *%a) nounwind {
; RV32IF-LABEL: flw:
; RV32IF: # %bb.0:
; RV32IF-NEXT: flw ft0, 12(a0)
; RV32IF-NEXT: flw ft1, 0(a0)
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: flw ft0, 0(a0)
; RV32IF-NEXT: flw ft1, 12(a0)
; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: flw:
; RV64IF: # %bb.0:
; RV64IF-NEXT: flw ft0, 12(a0)
; RV64IF-NEXT: flw ft1, 0(a0)
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: flw ft0, 0(a0)
; RV64IF-NEXT: flw ft1, 12(a0)
; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ret
%1 = load float, float* %a
Expand All @@ -37,17 +37,17 @@ define void @fsw(float *%a, float %b, float %c) nounwind {
; RV32IF-NEXT: fmv.w.x ft0, a2
; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fsw ft0, 32(a0)
; RV32IF-NEXT: fsw ft0, 0(a0)
; RV32IF-NEXT: fsw ft0, 32(a0)
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: fsw:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a2
; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fsw ft0, 32(a0)
; RV64IF-NEXT: fsw ft0, 0(a0)
; RV64IF-NEXT: fsw ft0, 32(a0)
; RV64IF-NEXT: ret
%1 = fadd float %b, %c
store float %1, float* %a
Expand All @@ -70,10 +70,10 @@ define float @flw_fsw_global(float %a, float %b) nounwind {
; RV32IF-NEXT: lui a0, %hi(G)
; RV32IF-NEXT: flw ft1, %lo(G)(a0)
; RV32IF-NEXT: fsw ft0, %lo(G)(a0)
; RV32IF-NEXT: addi a0, a0, %lo(G)
; RV32IF-NEXT: flw ft1, 36(a0)
; RV32IF-NEXT: fsw ft0, 36(a0)
; RV32IF-NEXT: addi a1, a0, %lo(G)
; RV32IF-NEXT: flw ft1, 36(a1)
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: fsw ft0, 36(a1)
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: flw_fsw_global:
Expand All @@ -84,10 +84,10 @@ define float @flw_fsw_global(float %a, float %b) nounwind {
; RV64IF-NEXT: lui a0, %hi(G)
; RV64IF-NEXT: flw ft1, %lo(G)(a0)
; RV64IF-NEXT: fsw ft0, %lo(G)(a0)
; RV64IF-NEXT: addi a0, a0, %lo(G)
; RV64IF-NEXT: flw ft1, 36(a0)
; RV64IF-NEXT: fsw ft0, 36(a0)
; RV64IF-NEXT: addi a1, a0, %lo(G)
; RV64IF-NEXT: flw ft1, 36(a1)
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: fsw ft0, 36(a1)
; RV64IF-NEXT: ret
%1 = fadd float %a, %b
%2 = load volatile float, float* @G
Expand All @@ -102,24 +102,24 @@ define float @flw_fsw_global(float %a, float %b) nounwind {
define float @flw_fsw_constant(float %a) nounwind {
; RV32IF-LABEL: flw_fsw_constant:
; RV32IF: # %bb.0:
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: lui a0, 912092
; RV32IF-NEXT: flw ft1, -273(a0)
; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: fsw ft0, -273(a0)
; RV32IF-NEXT: lui a1, 912092
; RV32IF-NEXT: flw ft0, -273(a1)
; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: fsw ft0, -273(a1)
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: flw_fsw_constant:
; RV64IF: # %bb.0:
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: lui a0, 56
; RV64IF-NEXT: addiw a0, a0, -1353
; RV64IF-NEXT: slli a0, a0, 14
; RV64IF-NEXT: flw ft1, -273(a0)
; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: fsw ft0, -273(a0)
; RV64IF-NEXT: lui a1, 56
; RV64IF-NEXT: addiw a1, a1, -1353
; RV64IF-NEXT: slli a1, a1, 14
; RV64IF-NEXT: flw ft0, -273(a1)
; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: fsw ft0, -273(a1)
; RV64IF-NEXT: ret
%1 = inttoptr i32 3735928559 to float*
%2 = load volatile float, float* %1
Expand All @@ -135,34 +135,32 @@ define float @flw_stack(float %a) nounwind {
; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp)
; RV32IF-NEXT: sw s0, 8(sp)
; RV32IF-NEXT: mv s0, a0
; RV32IF-NEXT: addi a0, sp, 4
; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fsw ft0, 4(sp)
; RV32IF-NEXT: addi a0, sp, 8
; RV32IF-NEXT: call notdead
; RV32IF-NEXT: fmv.w.x ft0, s0
; RV32IF-NEXT: flw ft0, 8(sp)
; RV32IF-NEXT: flw ft1, 4(sp)
; RV32IF-NEXT: fadd.s ft0, ft1, ft0
; RV32IF-NEXT: fadd.s ft0, ft0, ft1
; RV32IF-NEXT: fmv.x.w a0, ft0
; RV32IF-NEXT: lw s0, 8(sp)
; RV32IF-NEXT: lw ra, 12(sp)
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
;
; RV64IF-LABEL: flw_stack:
; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -32
; RV64IF-NEXT: sd ra, 24(sp)
; RV64IF-NEXT: sd s0, 16(sp)
; RV64IF-NEXT: mv s0, a0
; RV64IF-NEXT: addi a0, sp, 12
; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp)
; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fsw ft0, 0(sp)
; RV64IF-NEXT: addi a0, sp, 4
; RV64IF-NEXT: call notdead
; RV64IF-NEXT: fmv.w.x ft0, s0
; RV64IF-NEXT: flw ft1, 12(sp)
; RV64IF-NEXT: fadd.s ft0, ft1, ft0
; RV64IF-NEXT: flw ft0, 4(sp)
; RV64IF-NEXT: flw ft1, 0(sp)
; RV64IF-NEXT: fadd.s ft0, ft0, ft1
; RV64IF-NEXT: fmv.x.w a0, ft0
; RV64IF-NEXT: ld s0, 16(sp)
; RV64IF-NEXT: ld ra, 24(sp)
; RV64IF-NEXT: addi sp, sp, 32
; RV64IF-NEXT: ld ra, 8(sp)
; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret
%1 = alloca float, align 4
%2 = bitcast float* %1 to i8*
Expand Down
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