16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -20,7 +20,7 @@ define i32 @callee_float_in_regs(i32 %a, float %b) nounwind {
; RV32I-FPELIM-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: mv s0, a0
; RV32I-FPELIM-NEXT: mv a0, a1
; RV32I-FPELIM-NEXT: call __fixsfsi@plt
; RV32I-FPELIM-NEXT: call __fixsfsi
; RV32I-FPELIM-NEXT: add a0, s0, a0
; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
Expand All @@ -36,7 +36,7 @@ define i32 @callee_float_in_regs(i32 %a, float %b) nounwind {
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: mv s1, a0
; RV32I-WITHFP-NEXT: mv a0, a1
; RV32I-WITHFP-NEXT: call __fixsfsi@plt
; RV32I-WITHFP-NEXT: call __fixsfsi
; RV32I-WITHFP-NEXT: add a0, s1, a0
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
Expand All @@ -55,7 +55,7 @@ define i32 @caller_float_in_regs() nounwind {
; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: li a0, 1
; RV32I-FPELIM-NEXT: lui a1, 262144
; RV32I-FPELIM-NEXT: call callee_float_in_regs@plt
; RV32I-FPELIM-NEXT: call callee_float_in_regs
; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
Expand All @@ -68,7 +68,7 @@ define i32 @caller_float_in_regs() nounwind {
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: li a0, 1
; RV32I-WITHFP-NEXT: lui a1, 262144
; RV32I-WITHFP-NEXT: call callee_float_in_regs@plt
; RV32I-WITHFP-NEXT: call callee_float_in_regs
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -117,7 +117,7 @@ define i32 @caller_float_on_stack() nounwind {
; RV32I-FPELIM-NEXT: li a3, 0
; RV32I-FPELIM-NEXT: li a5, 0
; RV32I-FPELIM-NEXT: li a7, 0
; RV32I-FPELIM-NEXT: call callee_float_on_stack@plt
; RV32I-FPELIM-NEXT: call callee_float_on_stack
; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
Expand All @@ -138,7 +138,7 @@ define i32 @caller_float_on_stack() nounwind {
; RV32I-WITHFP-NEXT: li a3, 0
; RV32I-WITHFP-NEXT: li a5, 0
; RV32I-WITHFP-NEXT: li a7, 0
; RV32I-WITHFP-NEXT: call callee_float_on_stack@plt
; RV32I-WITHFP-NEXT: call callee_float_on_stack
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -172,7 +172,7 @@ define i32 @caller_tiny_scalar_ret() nounwind {
; RV32I-FPELIM: # %bb.0:
; RV32I-FPELIM-NEXT: addi sp, sp, -16
; RV32I-FPELIM-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-FPELIM-NEXT: call callee_tiny_scalar_ret@plt
; RV32I-FPELIM-NEXT: call callee_tiny_scalar_ret
; RV32I-FPELIM-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-FPELIM-NEXT: addi sp, sp, 16
; RV32I-FPELIM-NEXT: ret
Expand All @@ -183,7 +183,7 @@ define i32 @caller_tiny_scalar_ret() nounwind {
; RV32I-WITHFP-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-WITHFP-NEXT: addi s0, sp, 16
; RV32I-WITHFP-NEXT: call callee_tiny_scalar_ret@plt
; RV32I-WITHFP-NEXT: call callee_tiny_scalar_ret
; RV32I-WITHFP-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; RV32I-WITHFP-NEXT: addi sp, sp, 16
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32d.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ define i32 @caller_double_in_fpr() nounwind {
; RV32-ILP32D-NEXT: lui a0, %hi(.LCPI1_0)
; RV32-ILP32D-NEXT: fld fa0, %lo(.LCPI1_0)(a0)
; RV32-ILP32D-NEXT: li a0, 1
; RV32-ILP32D-NEXT: call callee_double_in_fpr@plt
; RV32-ILP32D-NEXT: call callee_double_in_fpr
; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret
Expand Down Expand Up @@ -63,7 +63,7 @@ define i32 @caller_double_in_fpr_exhausted_gprs() nounwind {
; RV32-ILP32D-NEXT: li a3, 0
; RV32-ILP32D-NEXT: li a5, 0
; RV32-ILP32D-NEXT: li a7, 0
; RV32-ILP32D-NEXT: call callee_double_in_fpr_exhausted_gprs@plt
; RV32-ILP32D-NEXT: call callee_double_in_fpr_exhausted_gprs
; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret
Expand Down Expand Up @@ -114,7 +114,7 @@ define i32 @caller_double_in_gpr_exhausted_fprs() nounwind {
; RV32-ILP32D-NEXT: fld fa7, %lo(.LCPI5_7)(a0)
; RV32-ILP32D-NEXT: lui a1, 262688
; RV32-ILP32D-NEXT: li a0, 0
; RV32-ILP32D-NEXT: call callee_double_in_gpr_exhausted_fprs@plt
; RV32-ILP32D-NEXT: call callee_double_in_gpr_exhausted_fprs
; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret
Expand Down Expand Up @@ -173,7 +173,7 @@ define i32 @caller_double_in_gpr_and_stack_almost_exhausted_gprs_fprs() nounwind
; RV32-ILP32D-NEXT: li a3, 0
; RV32-ILP32D-NEXT: li a5, 0
; RV32-ILP32D-NEXT: li a7, 0
; RV32-ILP32D-NEXT: call callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs@plt
; RV32-ILP32D-NEXT: call callee_double_in_gpr_and_stack_almost_exhausted_gprs_fprs
; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret
Expand Down Expand Up @@ -230,7 +230,7 @@ define i32 @caller_double_on_stack_exhausted_gprs_fprs() nounwind {
; RV32-ILP32D-NEXT: li a3, 0
; RV32-ILP32D-NEXT: li a5, 0
; RV32-ILP32D-NEXT: li a7, 0
; RV32-ILP32D-NEXT: call callee_double_on_stack_exhausted_gprs_fprs@plt
; RV32-ILP32D-NEXT: call callee_double_on_stack_exhausted_gprs_fprs
; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32D-NEXT: addi sp, sp, 16
; RV32-ILP32D-NEXT: ret
Expand All @@ -254,7 +254,7 @@ define i32 @caller_double_ret() nounwind {
; RV32-ILP32D: # %bb.0:
; RV32-ILP32D-NEXT: addi sp, sp, -16
; RV32-ILP32D-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32D-NEXT: call callee_double_ret@plt
; RV32-ILP32D-NEXT: call callee_double_ret
; RV32-ILP32D-NEXT: fsd fa0, 0(sp)
; RV32-ILP32D-NEXT: lw a0, 0(sp)
; RV32-ILP32D-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/calling-conv-ilp32f-ilp32d-common.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -28,7 +28,7 @@ define i32 @caller_float_in_fpr() nounwind {
; RV32-ILP32FD-NEXT: lui a0, 262144
; RV32-ILP32FD-NEXT: fmv.w.x fa0, a0
; RV32-ILP32FD-NEXT: li a0, 1
; RV32-ILP32FD-NEXT: call callee_float_in_fpr@plt
; RV32-ILP32FD-NEXT: call callee_float_in_fpr
; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32FD-NEXT: addi sp, sp, 16
; RV32-ILP32FD-NEXT: ret
Expand Down Expand Up @@ -66,7 +66,7 @@ define i32 @caller_float_in_fpr_exhausted_gprs() nounwind {
; RV32-ILP32FD-NEXT: li a3, 0
; RV32-ILP32FD-NEXT: li a5, 0
; RV32-ILP32FD-NEXT: li a7, 0
; RV32-ILP32FD-NEXT: call callee_float_in_fpr_exhausted_gprs@plt
; RV32-ILP32FD-NEXT: call callee_float_in_fpr_exhausted_gprs
; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32FD-NEXT: addi sp, sp, 16
; RV32-ILP32FD-NEXT: ret
Expand Down Expand Up @@ -112,7 +112,7 @@ define i32 @caller_float_in_gpr_exhausted_fprs() nounwind {
; RV32-ILP32FD-NEXT: lui a0, 266240
; RV32-ILP32FD-NEXT: fmv.w.x fa7, a0
; RV32-ILP32FD-NEXT: lui a0, 266496
; RV32-ILP32FD-NEXT: call callee_float_in_gpr_exhausted_fprs@plt
; RV32-ILP32FD-NEXT: call callee_float_in_gpr_exhausted_fprs
; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32FD-NEXT: addi sp, sp, 16
; RV32-ILP32FD-NEXT: ret
Expand Down Expand Up @@ -167,7 +167,7 @@ define i32 @caller_float_on_stack_exhausted_gprs_fprs() nounwind {
; RV32-ILP32FD-NEXT: li a3, 0
; RV32-ILP32FD-NEXT: li a5, 0
; RV32-ILP32FD-NEXT: li a7, 0
; RV32-ILP32FD-NEXT: call callee_float_on_stack_exhausted_gprs_fprs@plt
; RV32-ILP32FD-NEXT: call callee_float_on_stack_exhausted_gprs_fprs
; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32FD-NEXT: addi sp, sp, 16
; RV32-ILP32FD-NEXT: ret
Expand All @@ -191,7 +191,7 @@ define i32 @caller_float_ret() nounwind {
; RV32-ILP32FD: # %bb.0:
; RV32-ILP32FD-NEXT: addi sp, sp, -16
; RV32-ILP32FD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-ILP32FD-NEXT: call callee_float_ret@plt
; RV32-ILP32FD-NEXT: call callee_float_ret
; RV32-ILP32FD-NEXT: fmv.x.w a0, fa0
; RV32-ILP32FD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-ILP32FD-NEXT: addi sp, sp, 16
Expand Down
6 changes: 3 additions & 3 deletions llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-common.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -17,7 +17,7 @@ define i64 @callee_double_in_regs(i64 %a, double %b) nounwind {
; RV64I-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a0
; RV64I-NEXT: mv a0, a1
; RV64I-NEXT: call __fixdfdi@plt
; RV64I-NEXT: call __fixdfdi
; RV64I-NEXT: add a0, s0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
Expand All @@ -36,7 +36,7 @@ define i64 @caller_double_in_regs() nounwind {
; RV64I-NEXT: li a1, 1
; RV64I-NEXT: slli a1, a1, 62
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: call callee_double_in_regs@plt
; RV64I-NEXT: call callee_double_in_regs
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
Expand All @@ -58,7 +58,7 @@ define i64 @caller_double_ret() nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call callee_double_ret@plt
; RV64I-NEXT: call callee_double_ret
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
Expand Down
24 changes: 12 additions & 12 deletions llvm/test/CodeGen/RISCV/calling-conv-lp64-lp64f-lp64d-common.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -35,7 +35,7 @@ define i64 @caller_i128_in_regs() nounwind {
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: li a1, 2
; RV64I-NEXT: li a2, 0
; RV64I-NEXT: call callee_i128_in_regs@plt
; RV64I-NEXT: call callee_i128_in_regs
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
Expand Down Expand Up @@ -93,7 +93,7 @@ define i32 @caller_many_scalars() nounwind {
; RV64I-NEXT: li a7, 7
; RV64I-NEXT: sd zero, 0(sp)
; RV64I-NEXT: li a4, 0
; RV64I-NEXT: call callee_many_scalars@plt
; RV64I-NEXT: call callee_many_scalars
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 32
; RV64I-NEXT: ret
Expand Down Expand Up @@ -145,7 +145,7 @@ define i64 @caller_large_scalars() nounwind {
; RV64I-NEXT: addi a0, sp, 32
; RV64I-NEXT: mv a1, sp
; RV64I-NEXT: sd zero, 40(sp)
; RV64I-NEXT: call callee_large_scalars@plt
; RV64I-NEXT: call callee_large_scalars
; RV64I-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 80
; RV64I-NEXT: ret
Expand Down Expand Up @@ -210,7 +210,7 @@ define i64 @caller_large_scalars_exhausted_regs() nounwind {
; RV64I-NEXT: li a6, 7
; RV64I-NEXT: addi a7, sp, 48
; RV64I-NEXT: sd zero, 56(sp)
; RV64I-NEXT: call callee_large_scalars_exhausted_regs@plt
; RV64I-NEXT: call callee_large_scalars_exhausted_regs
; RV64I-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 96
; RV64I-NEXT: ret
Expand All @@ -227,7 +227,7 @@ define i64 @caller_mixed_scalar_libcalls(i64 %a) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __floatditf@plt
; RV64I-NEXT: call __floatditf
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
Expand Down Expand Up @@ -261,7 +261,7 @@ define i64 @caller_small_coerced_struct() nounwind {
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: li a0, 1
; RV64I-NEXT: li a1, 2
; RV64I-NEXT: call callee_small_coerced_struct@plt
; RV64I-NEXT: call callee_small_coerced_struct
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
; RV64I-NEXT: ret
Expand Down Expand Up @@ -305,7 +305,7 @@ define i64 @caller_large_struct() nounwind {
; RV64I-NEXT: sd a2, 24(sp)
; RV64I-NEXT: sd a3, 32(sp)
; RV64I-NEXT: addi a0, sp, 8
; RV64I-NEXT: call callee_large_struct@plt
; RV64I-NEXT: call callee_large_struct
; RV64I-NEXT: ld ra, 72(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 80
; RV64I-NEXT: ret
Expand Down Expand Up @@ -375,7 +375,7 @@ define void @caller_aligned_stack() nounwind {
; RV64I-NEXT: li a7, 7
; RV64I-NEXT: sd a6, 0(sp)
; RV64I-NEXT: li a6, 0
; RV64I-NEXT: call callee_aligned_stack@plt
; RV64I-NEXT: call callee_aligned_stack
; RV64I-NEXT: ld ra, 56(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 64
; RV64I-NEXT: ret
Expand All @@ -400,7 +400,7 @@ define i64 @caller_small_scalar_ret() nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call callee_small_scalar_ret@plt
; RV64I-NEXT: call callee_small_scalar_ret
; RV64I-NEXT: not a1, a1
; RV64I-NEXT: xori a0, a0, -2
; RV64I-NEXT: or a0, a0, a1
Expand Down Expand Up @@ -430,7 +430,7 @@ define i64 @caller_small_struct_ret() nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call callee_small_struct_ret@plt
; RV64I-NEXT: call callee_small_struct_ret
; RV64I-NEXT: add a0, a0, a1
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -465,7 +465,7 @@ define void @caller_large_scalar_ret() nounwind {
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv a0, sp
; RV64I-NEXT: call callee_large_scalar_ret@plt
; RV64I-NEXT: call callee_large_scalar_ret
; RV64I-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 48
; RV64I-NEXT: ret
Expand Down Expand Up @@ -507,7 +507,7 @@ define i64 @caller_large_struct_ret() nounwind {
; RV64I-NEXT: addi sp, sp, -48
; RV64I-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
; RV64I-NEXT: addi a0, sp, 8
; RV64I-NEXT: call callee_large_struct_ret@plt
; RV64I-NEXT: call callee_large_struct_ret
; RV64I-NEXT: ld a0, 8(sp)
; RV64I-NEXT: ld a1, 32(sp)
; RV64I-NEXT: add a0, a0, a1
Expand Down
16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/calling-conv-lp64.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -22,7 +22,7 @@ define i64 @callee_float_in_regs(i64 %a, float %b) nounwind {
; RV64I-FPELIM-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-FPELIM-NEXT: mv s0, a0
; RV64I-FPELIM-NEXT: mv a0, a1
; RV64I-FPELIM-NEXT: call __fixsfdi@plt
; RV64I-FPELIM-NEXT: call __fixsfdi
; RV64I-FPELIM-NEXT: add a0, s0, a0
; RV64I-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-FPELIM-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
Expand All @@ -38,7 +38,7 @@ define i64 @callee_float_in_regs(i64 %a, float %b) nounwind {
; RV64I-WITHFP-NEXT: addi s0, sp, 32
; RV64I-WITHFP-NEXT: mv s1, a0
; RV64I-WITHFP-NEXT: mv a0, a1
; RV64I-WITHFP-NEXT: call __fixsfdi@plt
; RV64I-WITHFP-NEXT: call __fixsfdi
; RV64I-WITHFP-NEXT: add a0, s1, a0
; RV64I-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
Expand All @@ -57,7 +57,7 @@ define i64 @caller_float_in_regs() nounwind {
; RV64I-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-FPELIM-NEXT: li a0, 1
; RV64I-FPELIM-NEXT: lui a1, 262144
; RV64I-FPELIM-NEXT: call callee_float_in_regs@plt
; RV64I-FPELIM-NEXT: call callee_float_in_regs
; RV64I-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-FPELIM-NEXT: addi sp, sp, 16
; RV64I-FPELIM-NEXT: ret
Expand All @@ -70,7 +70,7 @@ define i64 @caller_float_in_regs() nounwind {
; RV64I-WITHFP-NEXT: addi s0, sp, 16
; RV64I-WITHFP-NEXT: li a0, 1
; RV64I-WITHFP-NEXT: lui a1, 262144
; RV64I-WITHFP-NEXT: call callee_float_in_regs@plt
; RV64I-WITHFP-NEXT: call callee_float_in_regs
; RV64I-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -118,7 +118,7 @@ define i64 @caller_float_on_stack() nounwind {
; RV64I-FPELIM-NEXT: li a3, 0
; RV64I-FPELIM-NEXT: li a5, 0
; RV64I-FPELIM-NEXT: li a7, 0
; RV64I-FPELIM-NEXT: call callee_float_on_stack@plt
; RV64I-FPELIM-NEXT: call callee_float_on_stack
; RV64I-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-FPELIM-NEXT: addi sp, sp, 16
; RV64I-FPELIM-NEXT: ret
Expand All @@ -139,7 +139,7 @@ define i64 @caller_float_on_stack() nounwind {
; RV64I-WITHFP-NEXT: li a3, 0
; RV64I-WITHFP-NEXT: li a5, 0
; RV64I-WITHFP-NEXT: li a7, 0
; RV64I-WITHFP-NEXT: call callee_float_on_stack@plt
; RV64I-WITHFP-NEXT: call callee_float_on_stack
; RV64I-WITHFP-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: addi sp, sp, 32
Expand Down Expand Up @@ -176,7 +176,7 @@ define i64 @caller_tiny_scalar_ret() nounwind {
; RV64I-FPELIM: # %bb.0:
; RV64I-FPELIM-NEXT: addi sp, sp, -16
; RV64I-FPELIM-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-FPELIM-NEXT: call callee_tiny_scalar_ret@plt
; RV64I-FPELIM-NEXT: call callee_tiny_scalar_ret
; RV64I-FPELIM-NEXT: sext.w a0, a0
; RV64I-FPELIM-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-FPELIM-NEXT: addi sp, sp, 16
Expand All @@ -188,7 +188,7 @@ define i64 @caller_tiny_scalar_ret() nounwind {
; RV64I-WITHFP-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64I-WITHFP-NEXT: addi s0, sp, 16
; RV64I-WITHFP-NEXT: call callee_tiny_scalar_ret@plt
; RV64I-WITHFP-NEXT: call callee_tiny_scalar_ret
; RV64I-WITHFP-NEXT: sext.w a0, a0
; RV64I-WITHFP-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-WITHFP-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/calling-conv-rv32f-ilp32.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -43,7 +43,7 @@ define float @caller_onstack_f32_noop(float %a) nounwind {
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: li a5, 0
; RV32IF-NEXT: li a7, 0
; RV32IF-NEXT: call onstack_f32_noop@plt
; RV32IF-NEXT: call onstack_f32_noop
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
Expand All @@ -70,7 +70,7 @@ define float @caller_onstack_f32_fadd(float %a, float %b) nounwind {
; RV32IF-NEXT: li a3, 0
; RV32IF-NEXT: li a5, 0
; RV32IF-NEXT: li a7, 0
; RV32IF-NEXT: call onstack_f32_noop@plt
; RV32IF-NEXT: call onstack_f32_noop
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret
Expand Down
36 changes: 18 additions & 18 deletions llvm/test/CodeGen/RISCV/calling-conv-sext-zext.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -16,7 +16,7 @@ define void @pass_uint8_as_uint8(i8 zeroext %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call receive_uint8@plt
; RV32I-NEXT: call receive_uint8
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -31,7 +31,7 @@ define zeroext i8 @ret_callresult_uint8_as_uint8() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_uint8@plt
; RV32I-NEXT: call return_uint8
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -57,7 +57,7 @@ define void @pass_uint8_as_sint8(i8 zeroext %a) nounwind {
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: call receive_sint8@plt
; RV32I-NEXT: call receive_sint8
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -71,7 +71,7 @@ define signext i8 @ret_callresult_uint8_as_sint8() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_uint8@plt
; RV32I-NEXT: call return_uint8
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -96,7 +96,7 @@ define void @pass_uint8_as_anyint32(i8 zeroext %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call receive_anyint32@plt
; RV32I-NEXT: call receive_anyint32
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -110,7 +110,7 @@ define signext i32 @ret_callresult_uint8_as_anyint32() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_uint8@plt
; RV32I-NEXT: call return_uint8
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -133,7 +133,7 @@ define void @pass_sint8_as_uint8(i8 signext %a) nounwind {
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: call receive_uint8@plt
; RV32I-NEXT: call receive_uint8
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -148,7 +148,7 @@ define zeroext i8 @ret_callresult_sint8_as_uint8() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_sint8@plt
; RV32I-NEXT: call return_sint8
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -169,7 +169,7 @@ define void @pass_sint8_as_sint8(i8 signext %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call receive_sint8@plt
; RV32I-NEXT: call receive_sint8
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -182,7 +182,7 @@ define signext i8 @ret_callresult_sint8_as_sint8() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_sint8@plt
; RV32I-NEXT: call return_sint8
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -203,7 +203,7 @@ define void @pass_sint8_as_anyint32(i8 signext %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call receive_anyint32@plt
; RV32I-NEXT: call receive_anyint32
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -217,7 +217,7 @@ define signext i32 @ret_callresult_sint8_as_anyint32() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_sint8@plt
; RV32I-NEXT: call return_sint8
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -241,7 +241,7 @@ define void @pass_anyint32_as_uint8(i32 signext %a) nounwind {
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: call receive_uint8@plt
; RV32I-NEXT: call receive_uint8
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -257,7 +257,7 @@ define zeroext i8 @ret_callresult_anyint32_as_uint8() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_anyint32@plt
; RV32I-NEXT: call return_anyint32
; RV32I-NEXT: andi a0, a0, 255
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -284,7 +284,7 @@ define void @pass_anyint32_as_sint8(i32 signext %a) nounwind {
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: call receive_sint8@plt
; RV32I-NEXT: call receive_sint8
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -298,7 +298,7 @@ define signext i8 @ret_callresult_anyint32_as_sint8() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_anyint32@plt
; RV32I-NEXT: call return_anyint32
; RV32I-NEXT: slli a0, a0, 24
; RV32I-NEXT: srai a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -321,7 +321,7 @@ define void @pass_anyint32_as_anyint32(i32 signext %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call receive_anyint32@plt
; RV32I-NEXT: call receive_anyint32
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -334,7 +334,7 @@ define signext i32 @ret_callresult_anyint32_as_anyint32() nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call return_anyint32@plt
; RV32I-NEXT: call return_anyint32
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand Down
2 changes: 1 addition & 1 deletion llvm/test/CodeGen/RISCV/calling-conv-vector-on-stack.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ define void @bar() nounwind {
; CHECK-NEXT: li a6, 0
; CHECK-NEXT: li a7, 0
; CHECK-NEXT: vmv.v.i v16, 0
; CHECK-NEXT: call foo@plt
; CHECK-NEXT: call foo
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: addi sp, s0, -96
; CHECK-NEXT: ld ra, 88(sp) # 8-byte Folded Reload
Expand Down
20 changes: 10 additions & 10 deletions llvm/test/CodeGen/RISCV/calls.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ define i32 @test_call_external(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call external_function@plt
; RV32I-NEXT: call external_function
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -20,7 +20,7 @@ define i32 @test_call_external(i32 %a) nounwind {
; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi sp, sp, -16
; RV32I-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-PIC-NEXT: call external_function@plt
; RV32I-PIC-NEXT: call external_function
; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret
Expand Down Expand Up @@ -71,7 +71,7 @@ define i32 @test_call_defined(i32 %a) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call defined_function@plt
; RV32I-NEXT: call defined_function
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -80,7 +80,7 @@ define i32 @test_call_defined(i32 %a) nounwind {
; RV32I-PIC: # %bb.0:
; RV32I-PIC-NEXT: addi sp, sp, -16
; RV32I-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-PIC-NEXT: call defined_function@plt
; RV32I-PIC-NEXT: call defined_function
; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret
Expand Down Expand Up @@ -178,7 +178,7 @@ define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind {
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: call fastcc_function@plt
; RV32I-NEXT: call fastcc_function
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
Expand All @@ -191,7 +191,7 @@ define i32 @test_call_fastcc(i32 %a, i32 %b) nounwind {
; RV32I-PIC-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-PIC-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; RV32I-PIC-NEXT: mv s0, a0
; RV32I-PIC-NEXT: call fastcc_function@plt
; RV32I-PIC-NEXT: call fastcc_function
; RV32I-PIC-NEXT: mv a0, s0
; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-PIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -219,7 +219,7 @@ define i32 @test_call_external_many_args(i32 %a) nounwind {
; RV32I-NEXT: mv a5, a0
; RV32I-NEXT: mv a6, a0
; RV32I-NEXT: mv a7, a0
; RV32I-NEXT: call external_many_args@plt
; RV32I-NEXT: call external_many_args
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
Expand All @@ -241,7 +241,7 @@ define i32 @test_call_external_many_args(i32 %a) nounwind {
; RV32I-PIC-NEXT: mv a5, a0
; RV32I-PIC-NEXT: mv a6, a0
; RV32I-PIC-NEXT: mv a7, a0
; RV32I-PIC-NEXT: call external_many_args@plt
; RV32I-PIC-NEXT: call external_many_args
; RV32I-PIC-NEXT: mv a0, s0
; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-PIC-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
Expand Down Expand Up @@ -282,7 +282,7 @@ define i32 @test_call_defined_many_args(i32 %a) nounwind {
; RV32I-NEXT: mv a5, a0
; RV32I-NEXT: mv a6, a0
; RV32I-NEXT: mv a7, a0
; RV32I-NEXT: call defined_many_args@plt
; RV32I-NEXT: call defined_many_args
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
; RV32I-NEXT: ret
Expand All @@ -300,7 +300,7 @@ define i32 @test_call_defined_many_args(i32 %a) nounwind {
; RV32I-PIC-NEXT: mv a5, a0
; RV32I-PIC-NEXT: mv a6, a0
; RV32I-PIC-NEXT: mv a7, a0
; RV32I-PIC-NEXT: call defined_many_args@plt
; RV32I-PIC-NEXT: call defined_many_args
; RV32I-PIC-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-PIC-NEXT: addi sp, sp, 16
; RV32I-PIC-NEXT: ret
Expand Down
48 changes: 24 additions & 24 deletions llvm/test/CodeGen/RISCV/cm_mvas_mvsa.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -21,11 +21,11 @@ define i32 @zcmp_mv(i32 %num, i32 %f) nounwind {
; CHECK32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill
; CHECK32I-NEXT: mv s0, a1
; CHECK32I-NEXT: mv s1, a0
; CHECK32I-NEXT: call func@plt
; CHECK32I-NEXT: call func
; CHECK32I-NEXT: mv s2, a0
; CHECK32I-NEXT: mv a0, s1
; CHECK32I-NEXT: mv a1, s0
; CHECK32I-NEXT: call func@plt
; CHECK32I-NEXT: call func
; CHECK32I-NEXT: add a0, s2, s0
; CHECK32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
Expand All @@ -38,10 +38,10 @@ define i32 @zcmp_mv(i32 %num, i32 %f) nounwind {
; CHECK32ZCMP: # %bb.0:
; CHECK32ZCMP-NEXT: cm.push {ra, s0-s2}, -16
; CHECK32ZCMP-NEXT: cm.mvsa01 s1, s0
; CHECK32ZCMP-NEXT: call func@plt
; CHECK32ZCMP-NEXT: call func
; CHECK32ZCMP-NEXT: mv s2, a0
; CHECK32ZCMP-NEXT: cm.mva01s s1, s0
; CHECK32ZCMP-NEXT: call func@plt
; CHECK32ZCMP-NEXT: call func
; CHECK32ZCMP-NEXT: add a0, s2, s0
; CHECK32ZCMP-NEXT: cm.popret {ra, s0-s2}, 16
;
Expand All @@ -54,11 +54,11 @@ define i32 @zcmp_mv(i32 %num, i32 %f) nounwind {
; CHECK64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; CHECK64I-NEXT: mv s0, a1
; CHECK64I-NEXT: mv s1, a0
; CHECK64I-NEXT: call func@plt
; CHECK64I-NEXT: call func
; CHECK64I-NEXT: mv s2, a0
; CHECK64I-NEXT: mv a0, s1
; CHECK64I-NEXT: mv a1, s0
; CHECK64I-NEXT: call func@plt
; CHECK64I-NEXT: call func
; CHECK64I-NEXT: addw a0, s2, s0
; CHECK64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
Expand All @@ -71,10 +71,10 @@ define i32 @zcmp_mv(i32 %num, i32 %f) nounwind {
; CHECK64ZCMP: # %bb.0:
; CHECK64ZCMP-NEXT: cm.push {ra, s0-s2}, -32
; CHECK64ZCMP-NEXT: cm.mvsa01 s1, s0
; CHECK64ZCMP-NEXT: call func@plt
; CHECK64ZCMP-NEXT: call func
; CHECK64ZCMP-NEXT: mv s2, a0
; CHECK64ZCMP-NEXT: cm.mva01s s1, s0
; CHECK64ZCMP-NEXT: call func@plt
; CHECK64ZCMP-NEXT: call func
; CHECK64ZCMP-NEXT: addw a0, s2, s0
; CHECK64ZCMP-NEXT: cm.popret {ra, s0-s2}, 32
%call = call i32 @func(i32 %num, i32 %f)
Expand All @@ -91,15 +91,15 @@ define i32 @not_zcmp_mv(i32 %num, i32 %f) nounwind {
; CHECK32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill
; CHECK32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill
; CHECK32I-NEXT: mv s0, a1
; CHECK32I-NEXT: call foo@plt
; CHECK32I-NEXT: call foo
; CHECK32I-NEXT: mv s1, a0
; CHECK32I-NEXT: mv a0, s0
; CHECK32I-NEXT: call foo@plt
; CHECK32I-NEXT: call foo
; CHECK32I-NEXT: mv a0, s1
; CHECK32I-NEXT: call foo@plt
; CHECK32I-NEXT: call foo
; CHECK32I-NEXT: li a0, 1
; CHECK32I-NEXT: mv a1, s0
; CHECK32I-NEXT: call func@plt
; CHECK32I-NEXT: call func
; CHECK32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; CHECK32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload
; CHECK32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload
Expand All @@ -110,15 +110,15 @@ define i32 @not_zcmp_mv(i32 %num, i32 %f) nounwind {
; CHECK32ZCMP: # %bb.0:
; CHECK32ZCMP-NEXT: cm.push {ra, s0-s1}, -16
; CHECK32ZCMP-NEXT: mv s0, a1
; CHECK32ZCMP-NEXT: call foo@plt
; CHECK32ZCMP-NEXT: call foo
; CHECK32ZCMP-NEXT: mv s1, a0
; CHECK32ZCMP-NEXT: mv a0, s0
; CHECK32ZCMP-NEXT: call foo@plt
; CHECK32ZCMP-NEXT: call foo
; CHECK32ZCMP-NEXT: mv a0, s1
; CHECK32ZCMP-NEXT: call foo@plt
; CHECK32ZCMP-NEXT: call foo
; CHECK32ZCMP-NEXT: li a0, 1
; CHECK32ZCMP-NEXT: mv a1, s0
; CHECK32ZCMP-NEXT: call func@plt
; CHECK32ZCMP-NEXT: call func
; CHECK32ZCMP-NEXT: cm.popret {ra, s0-s1}, 16
;
; CHECK64I-LABEL: not_zcmp_mv:
Expand All @@ -128,15 +128,15 @@ define i32 @not_zcmp_mv(i32 %num, i32 %f) nounwind {
; CHECK64I-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; CHECK64I-NEXT: sd s1, 8(sp) # 8-byte Folded Spill
; CHECK64I-NEXT: mv s0, a1
; CHECK64I-NEXT: call foo@plt
; CHECK64I-NEXT: call foo
; CHECK64I-NEXT: mv s1, a0
; CHECK64I-NEXT: mv a0, s0
; CHECK64I-NEXT: call foo@plt
; CHECK64I-NEXT: call foo
; CHECK64I-NEXT: mv a0, s1
; CHECK64I-NEXT: call foo@plt
; CHECK64I-NEXT: call foo
; CHECK64I-NEXT: li a0, 1
; CHECK64I-NEXT: mv a1, s0
; CHECK64I-NEXT: call func@plt
; CHECK64I-NEXT: call func
; CHECK64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
; CHECK64I-NEXT: ld s0, 16(sp) # 8-byte Folded Reload
; CHECK64I-NEXT: ld s1, 8(sp) # 8-byte Folded Reload
Expand All @@ -147,15 +147,15 @@ define i32 @not_zcmp_mv(i32 %num, i32 %f) nounwind {
; CHECK64ZCMP: # %bb.0:
; CHECK64ZCMP-NEXT: cm.push {ra, s0-s1}, -32
; CHECK64ZCMP-NEXT: mv s0, a1
; CHECK64ZCMP-NEXT: call foo@plt
; CHECK64ZCMP-NEXT: call foo
; CHECK64ZCMP-NEXT: mv s1, a0
; CHECK64ZCMP-NEXT: mv a0, s0
; CHECK64ZCMP-NEXT: call foo@plt
; CHECK64ZCMP-NEXT: call foo
; CHECK64ZCMP-NEXT: mv a0, s1
; CHECK64ZCMP-NEXT: call foo@plt
; CHECK64ZCMP-NEXT: call foo
; CHECK64ZCMP-NEXT: li a0, 1
; CHECK64ZCMP-NEXT: mv a1, s0
; CHECK64ZCMP-NEXT: call func@plt
; CHECK64ZCMP-NEXT: call func
; CHECK64ZCMP-NEXT: cm.popret {ra, s0-s1}, 32
%call = call i32 @foo(i32 %num)
%call1 = call i32 @foo(i32 %f)
Expand Down
36 changes: 18 additions & 18 deletions llvm/test/CodeGen/RISCV/condops.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3092,7 +3092,7 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nou
; RV32I-NEXT: .LBB56_1: # %bb2
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call bar@plt
; RV32I-NEXT: call bar
; RV32I-NEXT: sll s1, s1, s0
; RV32I-NEXT: bnez a0, .LBB56_1
; RV32I-NEXT: # %bb.2: # %bb7
Expand All @@ -3115,7 +3115,7 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nou
; RV64I-NEXT: .LBB56_1: # %bb2
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call bar@plt
; RV64I-NEXT: call bar
; RV64I-NEXT: sllw s1, s1, s0
; RV64I-NEXT: bnez a0, .LBB56_1
; RV64I-NEXT: # %bb.2: # %bb7
Expand All @@ -3137,7 +3137,7 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nou
; RV64XVENTANACONDOPS-NEXT: .LBB56_1: # %bb2
; RV64XVENTANACONDOPS-NEXT: # =>This Inner Loop Header: Depth=1
; RV64XVENTANACONDOPS-NEXT: mv a0, s1
; RV64XVENTANACONDOPS-NEXT: call bar@plt
; RV64XVENTANACONDOPS-NEXT: call bar
; RV64XVENTANACONDOPS-NEXT: sllw s1, s1, s0
; RV64XVENTANACONDOPS-NEXT: bnez a0, .LBB56_1
; RV64XVENTANACONDOPS-NEXT: # %bb.2: # %bb7
Expand All @@ -3160,7 +3160,7 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nou
; RV64XTHEADCONDMOV-NEXT: .LBB56_1: # %bb2
; RV64XTHEADCONDMOV-NEXT: # =>This Inner Loop Header: Depth=1
; RV64XTHEADCONDMOV-NEXT: sext.w a0, s1
; RV64XTHEADCONDMOV-NEXT: call bar@plt
; RV64XTHEADCONDMOV-NEXT: call bar
; RV64XTHEADCONDMOV-NEXT: sllw s1, s1, s0
; RV64XTHEADCONDMOV-NEXT: bnez a0, .LBB56_1
; RV64XTHEADCONDMOV-NEXT: # %bb.2: # %bb7
Expand All @@ -3182,7 +3182,7 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nou
; RV32ZICOND-NEXT: .LBB56_1: # %bb2
; RV32ZICOND-NEXT: # =>This Inner Loop Header: Depth=1
; RV32ZICOND-NEXT: mv a0, s1
; RV32ZICOND-NEXT: call bar@plt
; RV32ZICOND-NEXT: call bar
; RV32ZICOND-NEXT: sll s1, s1, s0
; RV32ZICOND-NEXT: bnez a0, .LBB56_1
; RV32ZICOND-NEXT: # %bb.2: # %bb7
Expand All @@ -3204,7 +3204,7 @@ define void @sextw_removal_maskc(i1 %c, i32 signext %arg, i32 signext %arg1) nou
; RV64ZICOND-NEXT: .LBB56_1: # %bb2
; RV64ZICOND-NEXT: # =>This Inner Loop Header: Depth=1
; RV64ZICOND-NEXT: mv a0, s1
; RV64ZICOND-NEXT: call bar@plt
; RV64ZICOND-NEXT: call bar
; RV64ZICOND-NEXT: sllw s1, s1, s0
; RV64ZICOND-NEXT: bnez a0, .LBB56_1
; RV64ZICOND-NEXT: # %bb.2: # %bb7
Expand Down Expand Up @@ -3243,7 +3243,7 @@ define void @sextw_removal_maskcn(i1 %c, i32 signext %arg, i32 signext %arg1) no
; RV32I-NEXT: .LBB57_1: # %bb2
; RV32I-NEXT: # =>This Inner Loop Header: Depth=1
; RV32I-NEXT: mv a0, s1
; RV32I-NEXT: call bar@plt
; RV32I-NEXT: call bar
; RV32I-NEXT: sll s1, s1, s0
; RV32I-NEXT: bnez a0, .LBB57_1
; RV32I-NEXT: # %bb.2: # %bb7
Expand All @@ -3266,7 +3266,7 @@ define void @sextw_removal_maskcn(i1 %c, i32 signext %arg, i32 signext %arg1) no
; RV64I-NEXT: .LBB57_1: # %bb2
; RV64I-NEXT: # =>This Inner Loop Header: Depth=1
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: call bar@plt
; RV64I-NEXT: call bar
; RV64I-NEXT: sllw s1, s1, s0
; RV64I-NEXT: bnez a0, .LBB57_1
; RV64I-NEXT: # %bb.2: # %bb7
Expand All @@ -3288,7 +3288,7 @@ define void @sextw_removal_maskcn(i1 %c, i32 signext %arg, i32 signext %arg1) no
; RV64XVENTANACONDOPS-NEXT: .LBB57_1: # %bb2
; RV64XVENTANACONDOPS-NEXT: # =>This Inner Loop Header: Depth=1
; RV64XVENTANACONDOPS-NEXT: mv a0, s1
; RV64XVENTANACONDOPS-NEXT: call bar@plt
; RV64XVENTANACONDOPS-NEXT: call bar
; RV64XVENTANACONDOPS-NEXT: sllw s1, s1, s0
; RV64XVENTANACONDOPS-NEXT: bnez a0, .LBB57_1
; RV64XVENTANACONDOPS-NEXT: # %bb.2: # %bb7
Expand All @@ -3311,7 +3311,7 @@ define void @sextw_removal_maskcn(i1 %c, i32 signext %arg, i32 signext %arg1) no
; RV64XTHEADCONDMOV-NEXT: .LBB57_1: # %bb2
; RV64XTHEADCONDMOV-NEXT: # =>This Inner Loop Header: Depth=1
; RV64XTHEADCONDMOV-NEXT: sext.w a0, s1
; RV64XTHEADCONDMOV-NEXT: call bar@plt
; RV64XTHEADCONDMOV-NEXT: call bar
; RV64XTHEADCONDMOV-NEXT: sllw s1, s1, s0
; RV64XTHEADCONDMOV-NEXT: bnez a0, .LBB57_1
; RV64XTHEADCONDMOV-NEXT: # %bb.2: # %bb7
Expand All @@ -3333,7 +3333,7 @@ define void @sextw_removal_maskcn(i1 %c, i32 signext %arg, i32 signext %arg1) no
; RV32ZICOND-NEXT: .LBB57_1: # %bb2
; RV32ZICOND-NEXT: # =>This Inner Loop Header: Depth=1
; RV32ZICOND-NEXT: mv a0, s1
; RV32ZICOND-NEXT: call bar@plt
; RV32ZICOND-NEXT: call bar
; RV32ZICOND-NEXT: sll s1, s1, s0
; RV32ZICOND-NEXT: bnez a0, .LBB57_1
; RV32ZICOND-NEXT: # %bb.2: # %bb7
Expand All @@ -3355,7 +3355,7 @@ define void @sextw_removal_maskcn(i1 %c, i32 signext %arg, i32 signext %arg1) no
; RV64ZICOND-NEXT: .LBB57_1: # %bb2
; RV64ZICOND-NEXT: # =>This Inner Loop Header: Depth=1
; RV64ZICOND-NEXT: mv a0, s1
; RV64ZICOND-NEXT: call bar@plt
; RV64ZICOND-NEXT: call bar
; RV64ZICOND-NEXT: sllw s1, s1, s0
; RV64ZICOND-NEXT: bnez a0, .LBB57_1
; RV64ZICOND-NEXT: # %bb.2: # %bb7
Expand Down Expand Up @@ -3505,7 +3505,7 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
; RV32I-NEXT: beqz a1, .LBB60_4
; RV32I-NEXT: # %bb.3:
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: call bat@plt
; RV32I-NEXT: call bat
; RV32I-NEXT: .LBB60_4:
; RV32I-NEXT: mv a0, s0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -3526,7 +3526,7 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
; RV64I-NEXT: beqz a1, .LBB60_4
; RV64I-NEXT: # %bb.3:
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: call bat@plt
; RV64I-NEXT: call bat
; RV64I-NEXT: .LBB60_4:
; RV64I-NEXT: mv a0, s0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand All @@ -3545,7 +3545,7 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
; RV64XVENTANACONDOPS-NEXT: beqz a1, .LBB60_2
; RV64XVENTANACONDOPS-NEXT: # %bb.1:
; RV64XVENTANACONDOPS-NEXT: mv a0, s0
; RV64XVENTANACONDOPS-NEXT: call bat@plt
; RV64XVENTANACONDOPS-NEXT: call bat
; RV64XVENTANACONDOPS-NEXT: .LBB60_2:
; RV64XVENTANACONDOPS-NEXT: mv a0, s0
; RV64XVENTANACONDOPS-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand All @@ -3563,7 +3563,7 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
; RV64XTHEADCONDMOV-NEXT: beqz a1, .LBB60_2
; RV64XTHEADCONDMOV-NEXT: # %bb.1:
; RV64XTHEADCONDMOV-NEXT: mv a0, s0
; RV64XTHEADCONDMOV-NEXT: call bat@plt
; RV64XTHEADCONDMOV-NEXT: call bat
; RV64XTHEADCONDMOV-NEXT: .LBB60_2:
; RV64XTHEADCONDMOV-NEXT: mv a0, s0
; RV64XTHEADCONDMOV-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand All @@ -3582,7 +3582,7 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
; RV32ZICOND-NEXT: beqz a1, .LBB60_2
; RV32ZICOND-NEXT: # %bb.1:
; RV32ZICOND-NEXT: mv a0, s0
; RV32ZICOND-NEXT: call bat@plt
; RV32ZICOND-NEXT: call bat
; RV32ZICOND-NEXT: .LBB60_2:
; RV32ZICOND-NEXT: mv a0, s0
; RV32ZICOND-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -3601,7 +3601,7 @@ define signext i16 @numsignbits(i16 signext %0, i16 signext %1, i16 signext %2,
; RV64ZICOND-NEXT: beqz a1, .LBB60_2
; RV64ZICOND-NEXT: # %bb.1:
; RV64ZICOND-NEXT: mv a0, s0
; RV64ZICOND-NEXT: call bat@plt
; RV64ZICOND-NEXT: call bat
; RV64ZICOND-NEXT: .LBB60_2:
; RV64ZICOND-NEXT: mv a0, s0
; RV64ZICOND-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/copysign-casts.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -164,7 +164,7 @@ define double @fold_promote_d_h(double %a, half %b) nounwind {
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: fmv.s fa0, fa1
; RV32IFD-NEXT: call __extendhfsf2@plt
; RV32IFD-NEXT: call __extendhfsf2
; RV32IFD-NEXT: fcvt.d.s fa5, fa0
; RV32IFD-NEXT: fsgnj.d fa0, fs0, fa5
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -179,7 +179,7 @@ define double @fold_promote_d_h(double %a, half %b) nounwind {
; RV64IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs0, fa0
; RV64IFD-NEXT: fmv.s fa0, fa1
; RV64IFD-NEXT: call __extendhfsf2@plt
; RV64IFD-NEXT: call __extendhfsf2
; RV64IFD-NEXT: fcvt.d.s fa5, fa0
; RV64IFD-NEXT: fsgnj.d fa0, fs0, fa5
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -265,7 +265,7 @@ define float @fold_promote_f_h(float %a, half %b) nounwind {
; RV32IF-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.s fs0, fa0
; RV32IF-NEXT: fmv.s fa0, fa1
; RV32IF-NEXT: call __extendhfsf2@plt
; RV32IF-NEXT: call __extendhfsf2
; RV32IF-NEXT: fsgnj.s fa0, fs0, fa0
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload
Expand All @@ -279,7 +279,7 @@ define float @fold_promote_f_h(float %a, half %b) nounwind {
; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.s fs0, fa0
; RV32IFD-NEXT: fmv.s fa0, fa1
; RV32IFD-NEXT: call __extendhfsf2@plt
; RV32IFD-NEXT: call __extendhfsf2
; RV32IFD-NEXT: fsgnj.s fa0, fs0, fa0
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
Expand All @@ -293,7 +293,7 @@ define float @fold_promote_f_h(float %a, half %b) nounwind {
; RV64IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.s fs0, fa0
; RV64IFD-NEXT: fmv.s fa0, fa1
; RV64IFD-NEXT: call __extendhfsf2@plt
; RV64IFD-NEXT: call __extendhfsf2
; RV64IFD-NEXT: fsgnj.s fa0, fs0, fa0
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload
Expand Down
60 changes: 30 additions & 30 deletions llvm/test/CodeGen/RISCV/ctlz-cttz-ctpop.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -244,7 +244,7 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi a1, a1, 1329
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 27
; RV32I-NEXT: lui a1, %hi(.LCPI2_0)
; RV32I-NEXT: addi a1, a1, %lo(.LCPI2_0)
Expand All @@ -268,7 +268,7 @@ define i32 @test_cttz_i32(i32 %a) nounwind {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 30667
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 27
; RV64I-NEXT: lui a1, %hi(.LCPI2_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI2_0)
Expand Down Expand Up @@ -381,14 +381,14 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi s3, a1, 1329
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, %hi(.LCPI3_0)
; RV32I-NEXT: addi s4, a0, %lo(.LCPI3_0)
; RV32I-NEXT: neg a0, s2
; RV32I-NEXT: and a0, s2, a0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: bnez s2, .LBB3_3
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: li a0, 32
Expand Down Expand Up @@ -426,7 +426,7 @@ define i64 @test_cttz_i64(i64 %a) nounwind {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, %hi(.LCPI3_0)
; RV64I-NEXT: ld a1, %lo(.LCPI3_0)(a1)
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srli a0, a0, 58
; RV64I-NEXT: lui a1, %hi(.LCPI3_1)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI3_1)
Expand Down Expand Up @@ -706,7 +706,7 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi a1, a1, 1329
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 27
; RV32I-NEXT: lui a1, %hi(.LCPI6_0)
; RV32I-NEXT: addi a1, a1, %lo(.LCPI6_0)
Expand All @@ -724,7 +724,7 @@ define i32 @test_cttz_i32_zero_undef(i32 %a) nounwind {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 30667
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 27
; RV64I-NEXT: lui a1, %hi(.LCPI6_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_0)
Expand Down Expand Up @@ -812,14 +812,14 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi s3, a1, 1329
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lui a0, %hi(.LCPI7_0)
; RV32I-NEXT: addi s4, a0, %lo(.LCPI7_0)
; RV32I-NEXT: neg a0, s1
; RV32I-NEXT: and a0, s1, a0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: bnez s2, .LBB7_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 27
Expand Down Expand Up @@ -850,7 +850,7 @@ define i64 @test_cttz_i64_zero_undef(i64 %a) nounwind {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, %hi(.LCPI7_0)
; RV64I-NEXT: ld a1, %lo(.LCPI7_0)(a1)
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srli a0, a0, 58
; RV64I-NEXT: lui a1, %hi(.LCPI7_1)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI7_1)
Expand Down Expand Up @@ -1191,7 +1191,7 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -1236,7 +1236,7 @@ define i32 @test_ctlz_i32(i32 %a) nounwind {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -1395,7 +1395,7 @@ define i64 @test_ctlz_i64(i64 %a) nounwind {
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s3, a1, 257
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: srli a0, s2, 1
; RV32I-NEXT: or a0, s2, a0
Expand All @@ -1419,7 +1419,7 @@ define i64 @test_ctlz_i64(i64 %a) nounwind {
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: bnez s0, .LBB11_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
Expand Down Expand Up @@ -1485,7 +1485,7 @@ define i64 @test_ctlz_i64(i64 %a) nounwind {
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: slli a2, a1, 32
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -1862,7 +1862,7 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -1901,7 +1901,7 @@ define i32 @test_ctlz_i32_zero_undef(i32 %a) nounwind {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -2046,7 +2046,7 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s3, a1, 257
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: srli a0, s2, 1
; RV32I-NEXT: or a0, s2, a0
Expand All @@ -2070,7 +2070,7 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: bnez s0, .LBB15_2
; RV32I-NEXT: # %bb.1:
; RV32I-NEXT: srli a0, a0, 24
Expand Down Expand Up @@ -2134,7 +2134,7 @@ define i64 @test_ctlz_i64_zero_undef(i64 %a) nounwind {
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: slli a2, a1, 32
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -2484,7 +2484,7 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi a1, a1, 257
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -2512,7 +2512,7 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 4112
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 24
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -2598,7 +2598,7 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV32XTHEADBB-NEXT: and a0, a0, a1
; RV32XTHEADBB-NEXT: lui a1, 4112
; RV32XTHEADBB-NEXT: addi a1, a1, 257
; RV32XTHEADBB-NEXT: call __mulsi3@plt
; RV32XTHEADBB-NEXT: call __mulsi3
; RV32XTHEADBB-NEXT: srli a0, a0, 24
; RV32XTHEADBB-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32XTHEADBB-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -2626,7 +2626,7 @@ define i32 @test_ctpop_i32(i32 %a) nounwind {
; RV64XTHEADBB-NEXT: and a0, a0, a1
; RV64XTHEADBB-NEXT: lui a1, 4112
; RV64XTHEADBB-NEXT: addiw a1, a1, 257
; RV64XTHEADBB-NEXT: call __muldi3@plt
; RV64XTHEADBB-NEXT: call __muldi3
; RV64XTHEADBB-NEXT: srliw a0, a0, 24
; RV64XTHEADBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64XTHEADBB-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -2666,7 +2666,7 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s1, a1, 257
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli s5, a0, 24
; RV32I-NEXT: srli a0, s0, 1
; RV32I-NEXT: and a0, a0, s2
Expand All @@ -2679,7 +2679,7 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 24
; RV32I-NEXT: add a0, a0, s5
; RV32I-NEXT: li a1, 0
Expand Down Expand Up @@ -2723,7 +2723,7 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: slli a2, a1, 32
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srli a0, a0, 56
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -2842,7 +2842,7 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV32XTHEADBB-NEXT: lui a1, 4112
; RV32XTHEADBB-NEXT: addi s1, a1, 257
; RV32XTHEADBB-NEXT: mv a1, s1
; RV32XTHEADBB-NEXT: call __mulsi3@plt
; RV32XTHEADBB-NEXT: call __mulsi3
; RV32XTHEADBB-NEXT: srli s5, a0, 24
; RV32XTHEADBB-NEXT: srli a0, s0, 1
; RV32XTHEADBB-NEXT: and a0, a0, s2
Expand All @@ -2855,7 +2855,7 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV32XTHEADBB-NEXT: add a0, a0, a1
; RV32XTHEADBB-NEXT: and a0, a0, s4
; RV32XTHEADBB-NEXT: mv a1, s1
; RV32XTHEADBB-NEXT: call __mulsi3@plt
; RV32XTHEADBB-NEXT: call __mulsi3
; RV32XTHEADBB-NEXT: srli a0, a0, 24
; RV32XTHEADBB-NEXT: add a0, a0, s5
; RV32XTHEADBB-NEXT: li a1, 0
Expand Down Expand Up @@ -2899,7 +2899,7 @@ define i64 @test_ctpop_i64(i64 %a) nounwind {
; RV64XTHEADBB-NEXT: addiw a1, a1, 257
; RV64XTHEADBB-NEXT: slli a2, a1, 32
; RV64XTHEADBB-NEXT: add a1, a1, a2
; RV64XTHEADBB-NEXT: call __muldi3@plt
; RV64XTHEADBB-NEXT: call __muldi3
; RV64XTHEADBB-NEXT: srli a0, a0, 56
; RV64XTHEADBB-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64XTHEADBB-NEXT: addi sp, sp, 16
Expand Down
50 changes: 25 additions & 25 deletions llvm/test/CodeGen/RISCV/ctz_zero_return_test.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -46,14 +46,14 @@ define signext i32 @ctz_dereferencing_pointer(i64* %b) nounwind {
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi s1, a1, 1329
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s0, a0
; RV32I-NEXT: lui a0, %hi(.LCPI0_0)
; RV32I-NEXT: addi s3, a0, %lo(.LCPI0_0)
; RV32I-NEXT: neg a0, s4
; RV32I-NEXT: and a0, s4, a0
; RV32I-NEXT: mv a1, s1
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: bnez s4, .LBB0_3
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a0, 32
Expand Down Expand Up @@ -91,7 +91,7 @@ define signext i32 @ctz_dereferencing_pointer(i64* %b) nounwind {
; RV64I-NEXT: and a0, s0, a0
; RV64I-NEXT: lui a1, %hi(.LCPI0_0)
; RV64I-NEXT: ld a1, %lo(.LCPI0_0)(a1)
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srli a0, a0, 58
; RV64I-NEXT: lui a1, %hi(.LCPI0_1)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI0_1)
Expand Down Expand Up @@ -144,7 +144,7 @@ define i64 @ctz_dereferencing_pointer_zext(i32* %b) nounwind {
; RV32I-NEXT: and a0, s0, a0
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi a1, a1, 1329
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 27
; RV32I-NEXT: lui a1, %hi(.LCPI1_0)
; RV32I-NEXT: addi a1, a1, %lo(.LCPI1_0)
Expand All @@ -170,7 +170,7 @@ define i64 @ctz_dereferencing_pointer_zext(i32* %b) nounwind {
; RV64I-NEXT: and a0, s0, a0
; RV64I-NEXT: lui a1, 30667
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 27
; RV64I-NEXT: lui a1, %hi(.LCPI1_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI1_0)
Expand Down Expand Up @@ -220,7 +220,7 @@ define signext i32 @ctz1(i32 signext %x) nounwind {
; RV32I-NEXT: and a0, s0, a0
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi a1, a1, 1329
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 27
; RV32I-NEXT: lui a1, %hi(.LCPI2_0)
; RV32I-NEXT: addi a1, a1, %lo(.LCPI2_0)
Expand All @@ -245,7 +245,7 @@ define signext i32 @ctz1(i32 signext %x) nounwind {
; RV64I-NEXT: and a0, s0, a0
; RV64I-NEXT: lui a1, 30667
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 27
; RV64I-NEXT: lui a1, %hi(.LCPI2_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI2_0)
Expand Down Expand Up @@ -293,7 +293,7 @@ define signext i32 @ctz1_flipped(i32 signext %x) nounwind {
; RV32I-NEXT: and a0, s0, a0
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi a1, a1, 1329
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 27
; RV32I-NEXT: lui a1, %hi(.LCPI3_0)
; RV32I-NEXT: addi a1, a1, %lo(.LCPI3_0)
Expand All @@ -318,7 +318,7 @@ define signext i32 @ctz1_flipped(i32 signext %x) nounwind {
; RV64I-NEXT: and a0, s0, a0
; RV64I-NEXT: lui a1, 30667
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 27
; RV64I-NEXT: lui a1, %hi(.LCPI3_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI3_0)
Expand Down Expand Up @@ -364,7 +364,7 @@ define signext i32 @ctz2(i32 signext %x) nounwind {
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi a1, a1, 1329
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 27
; RV32I-NEXT: lui a1, %hi(.LCPI4_0)
; RV32I-NEXT: addi a1, a1, %lo(.LCPI4_0)
Expand All @@ -387,7 +387,7 @@ define signext i32 @ctz2(i32 signext %x) nounwind {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 30667
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 27
; RV64I-NEXT: lui a1, %hi(.LCPI4_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI4_0)
Expand Down Expand Up @@ -429,7 +429,7 @@ define signext i32 @ctz3(i32 signext %x) nounwind {
; RV32I-NEXT: and a0, a0, a1
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi a1, a1, 1329
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 27
; RV32I-NEXT: lui a1, %hi(.LCPI5_0)
; RV32I-NEXT: addi a1, a1, %lo(.LCPI5_0)
Expand All @@ -452,7 +452,7 @@ define signext i32 @ctz3(i32 signext %x) nounwind {
; RV64I-NEXT: and a0, a0, a1
; RV64I-NEXT: lui a1, 30667
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 27
; RV64I-NEXT: lui a1, %hi(.LCPI5_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI5_0)
Expand Down Expand Up @@ -509,14 +509,14 @@ define signext i32 @ctz4(i64 %b) nounwind {
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi s3, a1, 1329
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: lui a0, %hi(.LCPI6_0)
; RV32I-NEXT: addi s4, a0, %lo(.LCPI6_0)
; RV32I-NEXT: neg a0, s2
; RV32I-NEXT: and a0, s2, a0
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: bnez s2, .LBB6_3
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: li a0, 32
Expand Down Expand Up @@ -554,7 +554,7 @@ define signext i32 @ctz4(i64 %b) nounwind {
; RV64I-NEXT: and a0, s0, a0
; RV64I-NEXT: lui a1, %hi(.LCPI6_0)
; RV64I-NEXT: ld a1, %lo(.LCPI6_0)(a1)
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srli a0, a0, 58
; RV64I-NEXT: lui a1, %hi(.LCPI6_1)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI6_1)
Expand Down Expand Up @@ -643,7 +643,7 @@ define signext i32 @ctlz(i64 %b) nounwind {
; RV32I-NEXT: lui a1, 4112
; RV32I-NEXT: addi s3, a1, 257
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: mv s1, a0
; RV32I-NEXT: srli a0, s2, 1
; RV32I-NEXT: or a0, s2, a0
Expand All @@ -667,7 +667,7 @@ define signext i32 @ctlz(i64 %b) nounwind {
; RV32I-NEXT: add a0, a0, a1
; RV32I-NEXT: and a0, a0, s6
; RV32I-NEXT: mv a1, s3
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: bnez s0, .LBB7_2
; RV32I-NEXT: # %bb.1: # %entry
; RV32I-NEXT: srli a0, a0, 24
Expand Down Expand Up @@ -731,7 +731,7 @@ define signext i32 @ctlz(i64 %b) nounwind {
; RV64I-NEXT: addiw a1, a1, 257
; RV64I-NEXT: slli a2, a1, 32
; RV64I-NEXT: add a1, a1, a2
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: slli a0, a0, 2
; RV64I-NEXT: srli a0, a0, 58
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -772,7 +772,7 @@ define signext i32 @ctz5(i32 signext %x) nounwind {
; RV32I-NEXT: and a0, s0, a0
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi a1, a1, 1329
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 27
; RV32I-NEXT: lui a1, %hi(.LCPI8_0)
; RV32I-NEXT: addi a1, a1, %lo(.LCPI8_0)
Expand All @@ -797,7 +797,7 @@ define signext i32 @ctz5(i32 signext %x) nounwind {
; RV64I-NEXT: and a0, s0, a0
; RV64I-NEXT: lui a1, 30667
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 27
; RV64I-NEXT: lui a1, %hi(.LCPI8_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI8_0)
Expand Down Expand Up @@ -845,7 +845,7 @@ define signext i32 @ctz6(i32 signext %x) nounwind {
; RV32I-NEXT: and a0, s0, a0
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi a1, a1, 1329
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 27
; RV32I-NEXT: lui a1, %hi(.LCPI9_0)
; RV32I-NEXT: addi a1, a1, %lo(.LCPI9_0)
Expand All @@ -870,7 +870,7 @@ define signext i32 @ctz6(i32 signext %x) nounwind {
; RV64I-NEXT: and a0, s0, a0
; RV64I-NEXT: lui a1, 30667
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 27
; RV64I-NEXT: lui a1, %hi(.LCPI9_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI9_0)
Expand Down Expand Up @@ -923,7 +923,7 @@ define signext i32 @globalVar() nounwind {
; RV32I-NEXT: and a0, s0, a0
; RV32I-NEXT: lui a1, 30667
; RV32I-NEXT: addi a1, a1, 1329
; RV32I-NEXT: call __mulsi3@plt
; RV32I-NEXT: call __mulsi3
; RV32I-NEXT: srli a0, a0, 27
; RV32I-NEXT: lui a1, %hi(.LCPI10_0)
; RV32I-NEXT: addi a1, a1, %lo(.LCPI10_0)
Expand All @@ -949,7 +949,7 @@ define signext i32 @globalVar() nounwind {
; RV64I-NEXT: and a0, s0, a0
; RV64I-NEXT: lui a1, 30667
; RV64I-NEXT: addiw a1, a1, 1329
; RV64I-NEXT: call __muldi3@plt
; RV64I-NEXT: call __muldi3
; RV64I-NEXT: srliw a0, a0, 27
; RV64I-NEXT: lui a1, %hi(.LCPI10_0)
; RV64I-NEXT: addi a1, a1, %lo(.LCPI10_0)
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/div-by-constant.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -121,7 +121,7 @@ define i64 @udiv64_constant_add(i64 %a) nounwind {
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: li a2, 7
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __udivdi3@plt
; RV32-NEXT: call __udivdi3
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
Expand Down Expand Up @@ -383,7 +383,7 @@ define i64 @sdiv64_constant_no_srai(i64 %a) nounwind {
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: li a2, 3
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __divdi3@plt
; RV32-NEXT: call __divdi3
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
Expand All @@ -407,7 +407,7 @@ define i64 @sdiv64_constant_srai(i64 %a) nounwind {
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: li a2, 5
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __divdi3@plt
; RV32-NEXT: call __divdi3
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
Expand All @@ -432,7 +432,7 @@ define i64 @sdiv64_constant_add_srai(i64 %a) nounwind {
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: li a2, 15
; RV32-NEXT: li a3, 0
; RV32-NEXT: call __divdi3@plt
; RV32-NEXT: call __divdi3
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
Expand Down Expand Up @@ -460,7 +460,7 @@ define i64 @sdiv64_constant_sub_srai(i64 %a) nounwind {
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: li a2, -3
; RV32-NEXT: li a3, -1
; RV32-NEXT: call __divdi3@plt
; RV32-NEXT: call __divdi3
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
Expand Down
112 changes: 56 additions & 56 deletions llvm/test/CodeGen/RISCV/div.ll
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96 changes: 48 additions & 48 deletions llvm/test/CodeGen/RISCV/double-arith-strict.ll
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160 changes: 80 additions & 80 deletions llvm/test/CodeGen/RISCV/double-arith.ll
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136 changes: 68 additions & 68 deletions llvm/test/CodeGen/RISCV/double-br-fcmp.ll
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12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/double-calling-conv.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -62,7 +62,7 @@ define double @caller_double_inreg() nounwind {
; RV32IFD-NEXT: lui a2, 262364
; RV32IFD-NEXT: addi a3, a2, 655
; RV32IFD-NEXT: mv a2, a0
; RV32IFD-NEXT: call callee_double_inreg@plt
; RV32IFD-NEXT: call callee_double_inreg
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
Expand All @@ -78,7 +78,7 @@ define double @caller_double_inreg() nounwind {
; RV32IZFINXZDINX-NEXT: lui a2, 262364
; RV32IZFINXZDINX-NEXT: addi a3, a2, 655
; RV32IZFINXZDINX-NEXT: mv a2, a0
; RV32IZFINXZDINX-NEXT: call callee_double_inreg@plt
; RV32IZFINXZDINX-NEXT: call callee_double_inreg
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand Down Expand Up @@ -145,7 +145,7 @@ define double @caller_double_split_reg_stack() nounwind {
; RV32IFD-NEXT: li a2, 0
; RV32IFD-NEXT: li a4, 0
; RV32IFD-NEXT: mv a7, a5
; RV32IFD-NEXT: call callee_double_split_reg_stack@plt
; RV32IFD-NEXT: call callee_double_split_reg_stack
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
Expand All @@ -167,7 +167,7 @@ define double @caller_double_split_reg_stack() nounwind {
; RV32IZFINXZDINX-NEXT: li a2, 0
; RV32IZFINXZDINX-NEXT: li a4, 0
; RV32IZFINXZDINX-NEXT: mv a7, a5
; RV32IZFINXZDINX-NEXT: call callee_double_split_reg_stack@plt
; RV32IZFINXZDINX-NEXT: call callee_double_split_reg_stack
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand Down Expand Up @@ -229,7 +229,7 @@ define double @caller_double_stack() nounwind {
; RV32IFD-NEXT: li a3, 0
; RV32IFD-NEXT: li a5, 0
; RV32IFD-NEXT: li a7, 0
; RV32IFD-NEXT: call callee_double_stack@plt
; RV32IFD-NEXT: call callee_double_stack
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 32
; RV32IFD-NEXT: ret
Expand All @@ -256,7 +256,7 @@ define double @caller_double_stack() nounwind {
; RV32IZFINXZDINX-NEXT: li a3, 0
; RV32IZFINXZDINX-NEXT: li a5, 0
; RV32IZFINXZDINX-NEXT: li a7, 0
; RV32IZFINXZDINX-NEXT: call callee_double_stack@plt
; RV32IZFINXZDINX-NEXT: call callee_double_stack
; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
; RV32IZFINXZDINX-NEXT: ret
Expand Down
92 changes: 46 additions & 46 deletions llvm/test/CodeGen/RISCV/double-convert-strict.ll
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264 changes: 132 additions & 132 deletions llvm/test/CodeGen/RISCV/double-convert.ll
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128 changes: 64 additions & 64 deletions llvm/test/CodeGen/RISCV/double-fcmp-strict.ll
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64 changes: 32 additions & 32 deletions llvm/test/CodeGen/RISCV/double-fcmp.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,7 @@ define i32 @fcmp_oeq(double %a, double %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __eqdf2@plt
; RV32I-NEXT: call __eqdf2
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -77,7 +77,7 @@ define i32 @fcmp_oeq(double %a, double %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __eqdf2@plt
; RV64I-NEXT: call __eqdf2
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -117,7 +117,7 @@ define i32 @fcmp_ogt(double %a, double %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: call __gtdf2
; RV32I-NEXT: sgtz a0, a0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -127,7 +127,7 @@ define i32 @fcmp_ogt(double %a, double %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __gtdf2@plt
; RV64I-NEXT: call __gtdf2
; RV64I-NEXT: sgtz a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -167,7 +167,7 @@ define i32 @fcmp_oge(double %a, double %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: call __gedf2
; RV32I-NEXT: slti a0, a0, 0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -178,7 +178,7 @@ define i32 @fcmp_oge(double %a, double %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __gedf2@plt
; RV64I-NEXT: call __gedf2
; RV64I-NEXT: slti a0, a0, 0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -219,7 +219,7 @@ define i32 @fcmp_olt(double %a, double %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __ltdf2@plt
; RV32I-NEXT: call __ltdf2
; RV32I-NEXT: slti a0, a0, 0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -229,7 +229,7 @@ define i32 @fcmp_olt(double %a, double %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __ltdf2@plt
; RV64I-NEXT: call __ltdf2
; RV64I-NEXT: slti a0, a0, 0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -269,7 +269,7 @@ define i32 @fcmp_ole(double %a, double %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __ledf2@plt
; RV32I-NEXT: call __ledf2
; RV32I-NEXT: slti a0, a0, 1
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -279,7 +279,7 @@ define i32 @fcmp_ole(double %a, double %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __ledf2@plt
; RV64I-NEXT: call __ledf2
; RV64I-NEXT: slti a0, a0, 1
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -334,13 +334,13 @@ define i32 @fcmp_one(double %a, double %b) nounwind {
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: call __eqdf2@plt
; RV32I-NEXT: call __eqdf2
; RV32I-NEXT: snez s4, a0
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: call __unorddf2
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: and a0, a0, s4
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
Expand All @@ -361,11 +361,11 @@ define i32 @fcmp_one(double %a, double %b) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: call __eqdf2@plt
; RV64I-NEXT: call __eqdf2
; RV64I-NEXT: snez s2, a0
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unorddf2@plt
; RV64I-NEXT: call __unorddf2
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: and a0, a0, s2
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -415,7 +415,7 @@ define i32 @fcmp_ord(double %a, double %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: call __unorddf2
; RV32I-NEXT: seqz a0, a0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -425,7 +425,7 @@ define i32 @fcmp_ord(double %a, double %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __unorddf2@plt
; RV64I-NEXT: call __unorddf2
; RV64I-NEXT: seqz a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -483,13 +483,13 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind {
; RV32I-NEXT: mv s1, a2
; RV32I-NEXT: mv s2, a1
; RV32I-NEXT: mv s3, a0
; RV32I-NEXT: call __eqdf2@plt
; RV32I-NEXT: call __eqdf2
; RV32I-NEXT: seqz s4, a0
; RV32I-NEXT: mv a0, s3
; RV32I-NEXT: mv a1, s2
; RV32I-NEXT: mv a2, s1
; RV32I-NEXT: mv a3, s0
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: call __unorddf2
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: or a0, a0, s4
; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
Expand All @@ -510,11 +510,11 @@ define i32 @fcmp_ueq(double %a, double %b) nounwind {
; RV64I-NEXT: sd s2, 0(sp) # 8-byte Folded Spill
; RV64I-NEXT: mv s0, a1
; RV64I-NEXT: mv s1, a0
; RV64I-NEXT: call __eqdf2@plt
; RV64I-NEXT: call __eqdf2
; RV64I-NEXT: seqz s2, a0
; RV64I-NEXT: mv a0, s1
; RV64I-NEXT: mv a1, s0
; RV64I-NEXT: call __unorddf2@plt
; RV64I-NEXT: call __unorddf2
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: or a0, a0, s2
; RV64I-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -561,7 +561,7 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __ledf2@plt
; RV32I-NEXT: call __ledf2
; RV32I-NEXT: sgtz a0, a0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -571,7 +571,7 @@ define i32 @fcmp_ugt(double %a, double %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __ledf2@plt
; RV64I-NEXT: call __ledf2
; RV64I-NEXT: sgtz a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -614,7 +614,7 @@ define i32 @fcmp_uge(double %a, double %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __ltdf2@plt
; RV32I-NEXT: call __ltdf2
; RV32I-NEXT: slti a0, a0, 0
; RV32I-NEXT: xori a0, a0, 1
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
Expand All @@ -625,7 +625,7 @@ define i32 @fcmp_uge(double %a, double %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __ltdf2@plt
; RV64I-NEXT: call __ltdf2
; RV64I-NEXT: slti a0, a0, 0
; RV64I-NEXT: xori a0, a0, 1
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
Expand Down Expand Up @@ -669,7 +669,7 @@ define i32 @fcmp_ult(double %a, double %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __gedf2@plt
; RV32I-NEXT: call __gedf2
; RV32I-NEXT: slti a0, a0, 0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -679,7 +679,7 @@ define i32 @fcmp_ult(double %a, double %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __gedf2@plt
; RV64I-NEXT: call __gedf2
; RV64I-NEXT: slti a0, a0, 0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -722,7 +722,7 @@ define i32 @fcmp_ule(double %a, double %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __gtdf2@plt
; RV32I-NEXT: call __gtdf2
; RV32I-NEXT: slti a0, a0, 1
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -732,7 +732,7 @@ define i32 @fcmp_ule(double %a, double %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __gtdf2@plt
; RV64I-NEXT: call __gtdf2
; RV64I-NEXT: slti a0, a0, 1
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -775,7 +775,7 @@ define i32 @fcmp_une(double %a, double %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __nedf2@plt
; RV32I-NEXT: call __nedf2
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -785,7 +785,7 @@ define i32 @fcmp_une(double %a, double %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __nedf2@plt
; RV64I-NEXT: call __nedf2
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down Expand Up @@ -834,7 +834,7 @@ define i32 @fcmp_uno(double %a, double %b) nounwind {
; RV32I: # %bb.0:
; RV32I-NEXT: addi sp, sp, -16
; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32I-NEXT: call __unorddf2@plt
; RV32I-NEXT: call __unorddf2
; RV32I-NEXT: snez a0, a0
; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32I-NEXT: addi sp, sp, 16
Expand All @@ -844,7 +844,7 @@ define i32 @fcmp_uno(double %a, double %b) nounwind {
; RV64I: # %bb.0:
; RV64I-NEXT: addi sp, sp, -16
; RV64I-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64I-NEXT: call __unorddf2@plt
; RV64I-NEXT: call __unorddf2
; RV64I-NEXT: snez a0, a0
; RV64I-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64I-NEXT: addi sp, sp, 16
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/double-frem.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -11,24 +11,24 @@
define double @frem_f64(double %a, double %b) nounwind {
; RV32IFD-LABEL: frem_f64:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail fmod@plt
; RV32IFD-NEXT: tail fmod
;
; RV64IFD-LABEL: frem_f64:
; RV64IFD: # %bb.0:
; RV64IFD-NEXT: tail fmod@plt
; RV64IFD-NEXT: tail fmod
;
; RV32IZFINXZDINX-LABEL: frem_f64:
; RV32IZFINXZDINX: # %bb.0:
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: call fmod@plt
; RV32IZFINXZDINX-NEXT: call fmod
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
;
; RV64IZFINXZDINX-LABEL: frem_f64:
; RV64IZFINXZDINX: # %bb.0:
; RV64IZFINXZDINX-NEXT: tail fmod@plt
; RV64IZFINXZDINX-NEXT: tail fmod
%1 = frem double %a, %b
ret double %1
}
284 changes: 142 additions & 142 deletions llvm/test/CodeGen/RISCV/double-intrinsics-strict.ll
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230 changes: 115 additions & 115 deletions llvm/test/CodeGen/RISCV/double-intrinsics.ll
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16 changes: 8 additions & 8 deletions llvm/test/CodeGen/RISCV/double-mem.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -217,7 +217,7 @@ define dso_local double @fld_stack(double %a) nounwind {
; RV32IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: fmv.d fs0, fa0
; RV32IFD-NEXT: addi a0, sp, 8
; RV32IFD-NEXT: call notdead@plt
; RV32IFD-NEXT: call notdead
; RV32IFD-NEXT: fld fa5, 8(sp)
; RV32IFD-NEXT: fadd.d fa0, fa5, fs0
; RV32IFD-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
Expand All @@ -232,7 +232,7 @@ define dso_local double @fld_stack(double %a) nounwind {
; RV64IFD-NEXT: fsd fs0, 16(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d fs0, fa0
; RV64IFD-NEXT: addi a0, sp, 8
; RV64IFD-NEXT: call notdead@plt
; RV64IFD-NEXT: call notdead
; RV64IFD-NEXT: fld fa5, 8(sp)
; RV64IFD-NEXT: fadd.d fa0, fa5, fs0
; RV64IFD-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
Expand All @@ -251,7 +251,7 @@ define dso_local double @fld_stack(double %a) nounwind {
; RV32IZFINXZDINX-NEXT: lw s0, 0(sp)
; RV32IZFINXZDINX-NEXT: lw s1, 4(sp)
; RV32IZFINXZDINX-NEXT: addi a0, sp, 8
; RV32IZFINXZDINX-NEXT: call notdead@plt
; RV32IZFINXZDINX-NEXT: call notdead
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: fadd.d a0, a0, s0
Expand All @@ -272,7 +272,7 @@ define dso_local double @fld_stack(double %a) nounwind {
; RV64IZFINXZDINX-NEXT: sd s0, 16(sp) # 8-byte Folded Spill
; RV64IZFINXZDINX-NEXT: mv s0, a0
; RV64IZFINXZDINX-NEXT: addi a0, sp, 8
; RV64IZFINXZDINX-NEXT: call notdead@plt
; RV64IZFINXZDINX-NEXT: call notdead
; RV64IZFINXZDINX-NEXT: ld a0, 8(sp)
; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, s0
; RV64IZFINXZDINX-NEXT: ld ra, 24(sp) # 8-byte Folded Reload
Expand All @@ -294,7 +294,7 @@ define dso_local void @fsd_stack(double %a, double %b) nounwind {
; RV32IFD-NEXT: fadd.d fa5, fa0, fa1
; RV32IFD-NEXT: fsd fa5, 0(sp)
; RV32IFD-NEXT: mv a0, sp
; RV32IFD-NEXT: call notdead@plt
; RV32IFD-NEXT: call notdead
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
Expand All @@ -306,7 +306,7 @@ define dso_local void @fsd_stack(double %a, double %b) nounwind {
; RV64IFD-NEXT: fadd.d fa5, fa0, fa1
; RV64IFD-NEXT: fsd fa5, 0(sp)
; RV64IFD-NEXT: mv a0, sp
; RV64IFD-NEXT: call notdead@plt
; RV64IFD-NEXT: call notdead
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret
Expand All @@ -327,7 +327,7 @@ define dso_local void @fsd_stack(double %a, double %b) nounwind {
; RV32IZFINXZDINX-NEXT: sw a0, 16(sp)
; RV32IZFINXZDINX-NEXT: sw a1, 20(sp)
; RV32IZFINXZDINX-NEXT: addi a0, sp, 16
; RV32IZFINXZDINX-NEXT: call notdead@plt
; RV32IZFINXZDINX-NEXT: call notdead
; RV32IZFINXZDINX-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 32
; RV32IZFINXZDINX-NEXT: ret
Expand All @@ -339,7 +339,7 @@ define dso_local void @fsd_stack(double %a, double %b) nounwind {
; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, a1
; RV64IZFINXZDINX-NEXT: sd a0, 0(sp)
; RV64IZFINXZDINX-NEXT: mv a0, sp
; RV64IZFINXZDINX-NEXT: call notdead@plt
; RV64IZFINXZDINX-NEXT: call notdead
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: addi sp, sp, 16
; RV64IZFINXZDINX-NEXT: ret
Expand Down
12 changes: 6 additions & 6 deletions llvm/test/CodeGen/RISCV/double-previous-failure.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@ define i32 @main() nounwind {
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: lui a1, 262144
; RV32IFD-NEXT: li a0, 0
; RV32IFD-NEXT: call test@plt
; RV32IFD-NEXT: call test
; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld fa5, 0(sp)
Expand All @@ -39,17 +39,17 @@ define i32 @main() nounwind {
; RV32IFD-NEXT: flt.d a0, fa4, fa5
; RV32IFD-NEXT: bnez a0, .LBB1_3
; RV32IFD-NEXT: # %bb.2: # %if.end
; RV32IFD-NEXT: call exit@plt
; RV32IFD-NEXT: call exit
; RV32IFD-NEXT: .LBB1_3: # %if.then
; RV32IFD-NEXT: call abort@plt
; RV32IFD-NEXT: call abort
;
; RV32IZFINXZDINX-LABEL: main:
; RV32IZFINXZDINX: # %bb.0: # %entry
; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: lui a1, 262144
; RV32IZFINXZDINX-NEXT: li a0, 0
; RV32IZFINXZDINX-NEXT: call test@plt
; RV32IZFINXZDINX-NEXT: call test
; RV32IZFINXZDINX-NEXT: sw a0, 0(sp)
; RV32IZFINXZDINX-NEXT: sw a1, 4(sp)
; RV32IZFINXZDINX-NEXT: lw a0, 0(sp)
Expand All @@ -66,9 +66,9 @@ define i32 @main() nounwind {
; RV32IZFINXZDINX-NEXT: flt.d a0, a2, a0
; RV32IZFINXZDINX-NEXT: bnez a0, .LBB1_3
; RV32IZFINXZDINX-NEXT: # %bb.2: # %if.end
; RV32IZFINXZDINX-NEXT: call exit@plt
; RV32IZFINXZDINX-NEXT: call exit
; RV32IZFINXZDINX-NEXT: .LBB1_3: # %if.then
; RV32IZFINXZDINX-NEXT: call abort@plt
; RV32IZFINXZDINX-NEXT: call abort
entry:
%call = call double @test(double 2.000000e+00)
%cmp = fcmp olt double %call, 2.400000e-01
Expand Down
96 changes: 48 additions & 48 deletions llvm/test/CodeGen/RISCV/double-round-conv-sat.ll
View file

Large diffs are not rendered by default.

100 changes: 50 additions & 50 deletions llvm/test/CodeGen/RISCV/double-round-conv.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -106,8 +106,8 @@ define i64 @test_floor_si64(double %x) {
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: .cfi_offset ra, -4
; RV32IFD-NEXT: call floor@plt
; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: call floor
; RV32IFD-NEXT: call __fixdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
Expand All @@ -123,8 +123,8 @@ define i64 @test_floor_si64(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call floor@plt
; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt
; RV32IZFINXZDINX-NEXT: call floor
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand Down Expand Up @@ -236,8 +236,8 @@ define i64 @test_floor_ui64(double %x) {
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: .cfi_offset ra, -4
; RV32IFD-NEXT: call floor@plt
; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: call floor
; RV32IFD-NEXT: call __fixunsdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
Expand All @@ -253,8 +253,8 @@ define i64 @test_floor_ui64(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call floor@plt
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt
; RV32IZFINXZDINX-NEXT: call floor
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand Down Expand Up @@ -366,8 +366,8 @@ define i64 @test_ceil_si64(double %x) {
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: .cfi_offset ra, -4
; RV32IFD-NEXT: call ceil@plt
; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: call ceil
; RV32IFD-NEXT: call __fixdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
Expand All @@ -383,8 +383,8 @@ define i64 @test_ceil_si64(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call ceil@plt
; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt
; RV32IZFINXZDINX-NEXT: call ceil
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand Down Expand Up @@ -496,8 +496,8 @@ define i64 @test_ceil_ui64(double %x) {
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: .cfi_offset ra, -4
; RV32IFD-NEXT: call ceil@plt
; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: call ceil
; RV32IFD-NEXT: call __fixunsdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
Expand All @@ -513,8 +513,8 @@ define i64 @test_ceil_ui64(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call ceil@plt
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt
; RV32IZFINXZDINX-NEXT: call ceil
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand Down Expand Up @@ -626,8 +626,8 @@ define i64 @test_trunc_si64(double %x) {
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: .cfi_offset ra, -4
; RV32IFD-NEXT: call trunc@plt
; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: call trunc
; RV32IFD-NEXT: call __fixdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
Expand All @@ -643,8 +643,8 @@ define i64 @test_trunc_si64(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call trunc@plt
; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt
; RV32IZFINXZDINX-NEXT: call trunc
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand Down Expand Up @@ -756,8 +756,8 @@ define i64 @test_trunc_ui64(double %x) {
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: .cfi_offset ra, -4
; RV32IFD-NEXT: call trunc@plt
; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: call trunc
; RV32IFD-NEXT: call __fixunsdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
Expand All @@ -773,8 +773,8 @@ define i64 @test_trunc_ui64(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call trunc@plt
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt
; RV32IZFINXZDINX-NEXT: call trunc
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand Down Expand Up @@ -886,8 +886,8 @@ define i64 @test_round_si64(double %x) {
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: .cfi_offset ra, -4
; RV32IFD-NEXT: call round@plt
; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: call round
; RV32IFD-NEXT: call __fixdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
Expand All @@ -903,8 +903,8 @@ define i64 @test_round_si64(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call round@plt
; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt
; RV32IZFINXZDINX-NEXT: call round
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand Down Expand Up @@ -1016,8 +1016,8 @@ define i64 @test_round_ui64(double %x) {
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: .cfi_offset ra, -4
; RV32IFD-NEXT: call round@plt
; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: call round
; RV32IFD-NEXT: call __fixunsdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
Expand All @@ -1033,8 +1033,8 @@ define i64 @test_round_ui64(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call round@plt
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt
; RV32IZFINXZDINX-NEXT: call round
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand Down Expand Up @@ -1146,8 +1146,8 @@ define i64 @test_roundeven_si64(double %x) {
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: .cfi_offset ra, -4
; RV32IFD-NEXT: call roundeven@plt
; RV32IFD-NEXT: call __fixdfdi@plt
; RV32IFD-NEXT: call roundeven
; RV32IFD-NEXT: call __fixdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
Expand All @@ -1163,8 +1163,8 @@ define i64 @test_roundeven_si64(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call roundeven@plt
; RV32IZFINXZDINX-NEXT: call __fixdfdi@plt
; RV32IZFINXZDINX-NEXT: call roundeven
; RV32IZFINXZDINX-NEXT: call __fixdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand Down Expand Up @@ -1276,8 +1276,8 @@ define i64 @test_roundeven_ui64(double %x) {
; RV32IFD-NEXT: .cfi_def_cfa_offset 16
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: .cfi_offset ra, -4
; RV32IFD-NEXT: call roundeven@plt
; RV32IFD-NEXT: call __fixunsdfdi@plt
; RV32IFD-NEXT: call roundeven
; RV32IFD-NEXT: call __fixunsdfdi
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret
Expand All @@ -1293,8 +1293,8 @@ define i64 @test_roundeven_ui64(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call roundeven@plt
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi@plt
; RV32IZFINXZDINX-NEXT: call roundeven
; RV32IZFINXZDINX-NEXT: call __fixunsdfdi
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand All @@ -1311,7 +1311,7 @@ define i64 @test_roundeven_ui64(double %x) {
define double @test_floor_double(double %x) {
; RV32IFD-LABEL: test_floor_double:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail floor@plt
; RV32IFD-NEXT: tail floor
;
; RV64IFD-LABEL: test_floor_double:
; RV64IFD: # %bb.0:
Expand All @@ -1333,7 +1333,7 @@ define double @test_floor_double(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call floor@plt
; RV32IZFINXZDINX-NEXT: call floor
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand All @@ -1358,7 +1358,7 @@ define double @test_floor_double(double %x) {
define double @test_ceil_double(double %x) {
; RV32IFD-LABEL: test_ceil_double:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail ceil@plt
; RV32IFD-NEXT: tail ceil
;
; RV64IFD-LABEL: test_ceil_double:
; RV64IFD: # %bb.0:
Expand All @@ -1380,7 +1380,7 @@ define double @test_ceil_double(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call ceil@plt
; RV32IZFINXZDINX-NEXT: call ceil
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand All @@ -1405,7 +1405,7 @@ define double @test_ceil_double(double %x) {
define double @test_trunc_double(double %x) {
; RV32IFD-LABEL: test_trunc_double:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail trunc@plt
; RV32IFD-NEXT: tail trunc
;
; RV64IFD-LABEL: test_trunc_double:
; RV64IFD: # %bb.0:
Expand All @@ -1427,7 +1427,7 @@ define double @test_trunc_double(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call trunc@plt
; RV32IZFINXZDINX-NEXT: call trunc
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand All @@ -1452,7 +1452,7 @@ define double @test_trunc_double(double %x) {
define double @test_round_double(double %x) {
; RV32IFD-LABEL: test_round_double:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail round@plt
; RV32IFD-NEXT: tail round
;
; RV64IFD-LABEL: test_round_double:
; RV64IFD: # %bb.0:
Expand All @@ -1474,7 +1474,7 @@ define double @test_round_double(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call round@plt
; RV32IZFINXZDINX-NEXT: call round
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand All @@ -1499,7 +1499,7 @@ define double @test_round_double(double %x) {
define double @test_roundeven_double(double %x) {
; RV32IFD-LABEL: test_roundeven_double:
; RV32IFD: # %bb.0:
; RV32IFD-NEXT: tail roundeven@plt
; RV32IFD-NEXT: tail roundeven
;
; RV64IFD-LABEL: test_roundeven_double:
; RV64IFD: # %bb.0:
Expand All @@ -1521,7 +1521,7 @@ define double @test_roundeven_double(double %x) {
; RV32IZFINXZDINX-NEXT: .cfi_def_cfa_offset 16
; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFINXZDINX-NEXT: .cfi_offset ra, -4
; RV32IZFINXZDINX-NEXT: call roundeven@plt
; RV32IZFINXZDINX-NEXT: call roundeven
; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
; RV32IZFINXZDINX-NEXT: ret
Expand Down
8 changes: 4 additions & 4 deletions llvm/test/CodeGen/RISCV/double-stack-spill-restore.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -23,7 +23,7 @@ define double @func(double %d, i32 %n) nounwind {
; RV32IFD-NEXT: lw a0, 16(sp)
; RV32IFD-NEXT: lw a1, 20(sp)
; RV32IFD-NEXT: fsd fa5, 8(sp) # 8-byte Folded Spill
; RV32IFD-NEXT: call func@plt
; RV32IFD-NEXT: call func
; RV32IFD-NEXT: sw a0, 16(sp)
; RV32IFD-NEXT: sw a1, 20(sp)
; RV32IFD-NEXT: fld fa5, 16(sp)
Expand All @@ -48,7 +48,7 @@ define double @func(double %d, i32 %n) nounwind {
; RV64IFD-NEXT: addiw a1, a1, -1
; RV64IFD-NEXT: fmv.x.d a0, fa5
; RV64IFD-NEXT: fsd fa5, 0(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: call func@plt
; RV64IFD-NEXT: call func
; RV64IFD-NEXT: fmv.d.x fa5, a0
; RV64IFD-NEXT: fld fa4, 0(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: fadd.d fa5, fa5, fa4
Expand Down Expand Up @@ -77,7 +77,7 @@ define double @func(double %d, i32 %n) nounwind {
; RV32IZFINXZDINX-NEXT: sw s1, 12(sp)
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: call func@plt
; RV32IZFINXZDINX-NEXT: call func
; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
Expand Down Expand Up @@ -108,7 +108,7 @@ define double @func(double %d, i32 %n) nounwind {
; RV64IZFINXZDINX-NEXT: sd s0, 0(sp) # 8-byte Folded Spill
; RV64IZFINXZDINX-NEXT: addiw a1, a1, -1
; RV64IZFINXZDINX-NEXT: mv s0, a0
; RV64IZFINXZDINX-NEXT: call func@plt
; RV64IZFINXZDINX-NEXT: call func
; RV64IZFINXZDINX-NEXT: fadd.d a0, a0, s0
; RV64IZFINXZDINX-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFINXZDINX-NEXT: ld s0, 0(sp) # 8-byte Folded Reload
Expand Down
4 changes: 2 additions & 2 deletions llvm/test/CodeGen/RISCV/eh-dwarf-cfa.ll
View file
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@ define void @dwarf() {
; RV32-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32-NEXT: .cfi_offset ra, -4
; RV32-NEXT: addi a0, sp, 16
; RV32-NEXT: call foo@plt
; RV32-NEXT: call foo
; RV32-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32-NEXT: addi sp, sp, 16
; RV32-NEXT: ret
Expand All @@ -22,7 +22,7 @@ define void @dwarf() {
; RV64-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64-NEXT: .cfi_offset ra, -8
; RV64-NEXT: addi a0, sp, 16
; RV64-NEXT: call foo@plt
; RV64-NEXT: call foo
; RV64-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64-NEXT: addi sp, sp, 16
; RV64-NEXT: ret
Expand Down
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