56 changes: 32 additions & 24 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_clz.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,16 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s

#include <arm_sve.h>

#if defined __ARM_FEATURE_SME
#define MODE_ATTR __arm_streaming
#else
#define MODE_ATTR
#endif

#ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
Expand All @@ -24,7 +32,7 @@
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
svuint8_t test_svclz_s8_z(svbool_t pg, svint8_t op)
svuint8_t test_svclz_s8_z(svbool_t pg, svint8_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_s8,_z,)(pg, op);
}
Expand All @@ -41,7 +49,7 @@ svuint8_t test_svclz_s8_z(svbool_t pg, svint8_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svuint16_t test_svclz_s16_z(svbool_t pg, svint16_t op)
svuint16_t test_svclz_s16_z(svbool_t pg, svint16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_s16,_z,)(pg, op);
}
Expand All @@ -58,7 +66,7 @@ svuint16_t test_svclz_s16_z(svbool_t pg, svint16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
svuint32_t test_svclz_s32_z(svbool_t pg, svint32_t op)
svuint32_t test_svclz_s32_z(svbool_t pg, svint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_s32,_z,)(pg, op);
}
Expand All @@ -75,7 +83,7 @@ svuint32_t test_svclz_s32_z(svbool_t pg, svint32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
svuint64_t test_svclz_s64_z(svbool_t pg, svint64_t op)
svuint64_t test_svclz_s64_z(svbool_t pg, svint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_s64,_z,)(pg, op);
}
Expand All @@ -90,7 +98,7 @@ svuint64_t test_svclz_s64_z(svbool_t pg, svint64_t op)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
svuint8_t test_svclz_u8_z(svbool_t pg, svuint8_t op)
svuint8_t test_svclz_u8_z(svbool_t pg, svuint8_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_u8,_z,)(pg, op);
}
Expand All @@ -107,7 +115,7 @@ svuint8_t test_svclz_u8_z(svbool_t pg, svuint8_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svuint16_t test_svclz_u16_z(svbool_t pg, svuint16_t op)
svuint16_t test_svclz_u16_z(svbool_t pg, svuint16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_u16,_z,)(pg, op);
}
Expand All @@ -124,7 +132,7 @@ svuint16_t test_svclz_u16_z(svbool_t pg, svuint16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
svuint32_t test_svclz_u32_z(svbool_t pg, svuint32_t op)
svuint32_t test_svclz_u32_z(svbool_t pg, svuint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_u32,_z,)(pg, op);
}
Expand All @@ -141,7 +149,7 @@ svuint32_t test_svclz_u32_z(svbool_t pg, svuint32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
svuint64_t test_svclz_u64_z(svbool_t pg, svuint64_t op)
svuint64_t test_svclz_u64_z(svbool_t pg, svuint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_u64,_z,)(pg, op);
}
Expand All @@ -156,7 +164,7 @@ svuint64_t test_svclz_u64_z(svbool_t pg, svuint64_t op)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> [[INACTIVE:%.*]], <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
svuint8_t test_svclz_s8_m(svuint8_t inactive, svbool_t pg, svint8_t op)
svuint8_t test_svclz_s8_m(svuint8_t inactive, svbool_t pg, svint8_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_s8,_m,)(inactive, pg, op);
}
Expand All @@ -173,7 +181,7 @@ svuint8_t test_svclz_s8_m(svuint8_t inactive, svbool_t pg, svint8_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> [[INACTIVE:%.*]], <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svuint16_t test_svclz_s16_m(svuint16_t inactive, svbool_t pg, svint16_t op)
svuint16_t test_svclz_s16_m(svuint16_t inactive, svbool_t pg, svint16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_s16,_m,)(inactive, pg, op);
}
Expand All @@ -190,7 +198,7 @@ svuint16_t test_svclz_s16_m(svuint16_t inactive, svbool_t pg, svint16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> [[INACTIVE:%.*]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
svuint32_t test_svclz_s32_m(svuint32_t inactive, svbool_t pg, svint32_t op)
svuint32_t test_svclz_s32_m(svuint32_t inactive, svbool_t pg, svint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_s32,_m,)(inactive, pg, op);
}
Expand All @@ -207,7 +215,7 @@ svuint32_t test_svclz_s32_m(svuint32_t inactive, svbool_t pg, svint32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> [[INACTIVE:%.*]], <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
svuint64_t test_svclz_s64_m(svuint64_t inactive, svbool_t pg, svint64_t op)
svuint64_t test_svclz_s64_m(svuint64_t inactive, svbool_t pg, svint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_s64,_m,)(inactive, pg, op);
}
Expand All @@ -222,7 +230,7 @@ svuint64_t test_svclz_s64_m(svuint64_t inactive, svbool_t pg, svint64_t op)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> [[INACTIVE:%.*]], <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
svuint8_t test_svclz_u8_m(svuint8_t inactive, svbool_t pg, svuint8_t op)
svuint8_t test_svclz_u8_m(svuint8_t inactive, svbool_t pg, svuint8_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_u8,_m,)(inactive, pg, op);
}
Expand All @@ -239,7 +247,7 @@ svuint8_t test_svclz_u8_m(svuint8_t inactive, svbool_t pg, svuint8_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> [[INACTIVE:%.*]], <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svuint16_t test_svclz_u16_m(svuint16_t inactive, svbool_t pg, svuint16_t op)
svuint16_t test_svclz_u16_m(svuint16_t inactive, svbool_t pg, svuint16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_u16,_m,)(inactive, pg, op);
}
Expand All @@ -256,7 +264,7 @@ svuint16_t test_svclz_u16_m(svuint16_t inactive, svbool_t pg, svuint16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> [[INACTIVE:%.*]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
svuint32_t test_svclz_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op)
svuint32_t test_svclz_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_u32,_m,)(inactive, pg, op);
}
Expand All @@ -273,7 +281,7 @@ svuint32_t test_svclz_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> [[INACTIVE:%.*]], <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
svuint64_t test_svclz_u64_m(svuint64_t inactive, svbool_t pg, svuint64_t op)
svuint64_t test_svclz_u64_m(svuint64_t inactive, svbool_t pg, svuint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_u64,_m,)(inactive, pg, op);
}
Expand All @@ -288,7 +296,7 @@ svuint64_t test_svclz_u64_m(svuint64_t inactive, svbool_t pg, svuint64_t op)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
svuint8_t test_svclz_s8_x(svbool_t pg, svint8_t op)
svuint8_t test_svclz_s8_x(svbool_t pg, svint8_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_s8,_x,)(pg, op);
}
Expand All @@ -305,7 +313,7 @@ svuint8_t test_svclz_s8_x(svbool_t pg, svint8_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svuint16_t test_svclz_s16_x(svbool_t pg, svint16_t op)
svuint16_t test_svclz_s16_x(svbool_t pg, svint16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_s16,_x,)(pg, op);
}
Expand All @@ -322,7 +330,7 @@ svuint16_t test_svclz_s16_x(svbool_t pg, svint16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
svuint32_t test_svclz_s32_x(svbool_t pg, svint32_t op)
svuint32_t test_svclz_s32_x(svbool_t pg, svint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_s32,_x,)(pg, op);
}
Expand All @@ -339,7 +347,7 @@ svuint32_t test_svclz_s32_x(svbool_t pg, svint32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
svuint64_t test_svclz_s64_x(svbool_t pg, svint64_t op)
svuint64_t test_svclz_s64_x(svbool_t pg, svint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_s64,_x,)(pg, op);
}
Expand All @@ -354,7 +362,7 @@ svuint64_t test_svclz_s64_x(svbool_t pg, svint64_t op)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.clz.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
svuint8_t test_svclz_u8_x(svbool_t pg, svuint8_t op)
svuint8_t test_svclz_u8_x(svbool_t pg, svuint8_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_u8,_x,)(pg, op);
}
Expand All @@ -371,7 +379,7 @@ svuint8_t test_svclz_u8_x(svbool_t pg, svuint8_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.clz.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svuint16_t test_svclz_u16_x(svbool_t pg, svuint16_t op)
svuint16_t test_svclz_u16_x(svbool_t pg, svuint16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_u16,_x,)(pg, op);
}
Expand All @@ -388,7 +396,7 @@ svuint16_t test_svclz_u16_x(svbool_t pg, svuint16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.clz.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
svuint32_t test_svclz_u32_x(svbool_t pg, svuint32_t op)
svuint32_t test_svclz_u32_x(svbool_t pg, svuint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_u32,_x,)(pg, op);
}
Expand All @@ -405,7 +413,7 @@ svuint32_t test_svclz_u32_x(svbool_t pg, svuint32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.clz.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
svuint64_t test_svclz_u64_x(svbool_t pg, svuint64_t op)
svuint64_t test_svclz_u64_x(svbool_t pg, svuint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svclz,_u64,_x,)(pg, op);
}
40 changes: 24 additions & 16 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmla.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,16 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s

#include <arm_sve.h>

#if defined __ARM_FEATURE_SME
#define MODE_ATTR __arm_streaming
#else
#define MODE_ATTR
#endif

#ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
Expand All @@ -28,7 +36,7 @@
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 0)
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]
//
svfloat16_t test_svcmla_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
svfloat16_t test_svcmla_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmla,_f16,_z,)(pg, op1, op2, op3, 0);
}
Expand All @@ -47,7 +55,7 @@ svfloat16_t test_svcmla_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 90)
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]
//
svfloat16_t test_svcmla_f16_z_1(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
svfloat16_t test_svcmla_f16_z_1(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmla,_f16,_z,)(pg, op1, op2, op3, 90);
}
Expand All @@ -66,7 +74,7 @@ svfloat16_t test_svcmla_f16_z_1(svbool_t pg, svfloat16_t op1, svfloat16_t op2, s
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 180)
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]
//
svfloat16_t test_svcmla_f16_z_2(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
svfloat16_t test_svcmla_f16_z_2(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmla,_f16,_z,)(pg, op1, op2, op3, 180);
}
Expand All @@ -85,7 +93,7 @@ svfloat16_t test_svcmla_f16_z_2(svbool_t pg, svfloat16_t op1, svfloat16_t op2, s
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[TMP1]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 270)
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP2]]
//
svfloat16_t test_svcmla_f16_z_3(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
svfloat16_t test_svcmla_f16_z_3(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmla,_f16,_z,)(pg, op1, op2, op3, 270);
}
Expand All @@ -104,7 +112,7 @@ svfloat16_t test_svcmla_f16_z_3(svbool_t pg, svfloat16_t op1, svfloat16_t op2, s
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[TMP1]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x float> [[OP3:%.*]], i32 0)
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP2]]
//
svfloat32_t test_svcmla_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfloat32_t op3)
svfloat32_t test_svcmla_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfloat32_t op3) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmla,_f32,_z,)(pg, op1, op2, op3, 0);
}
Expand All @@ -123,7 +131,7 @@ svfloat32_t test_svcmla_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[TMP1]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x double> [[OP3:%.*]], i32 90)
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP2]]
//
svfloat64_t test_svcmla_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3)
svfloat64_t test_svcmla_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmla,_f64,_z,)(pg, op1, op2, op3, 90);
}
Expand All @@ -140,7 +148,7 @@ svfloat64_t test_svcmla_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 180)
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
svfloat16_t test_svcmla_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
svfloat16_t test_svcmla_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmla,_f16,_m,)(pg, op1, op2, op3, 180);
}
Expand All @@ -157,7 +165,7 @@ svfloat16_t test_svcmla_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x float> [[OP3:%.*]], i32 270)
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
//
svfloat32_t test_svcmla_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfloat32_t op3)
svfloat32_t test_svcmla_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfloat32_t op3) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmla,_f32,_m,)(pg, op1, op2, op3, 270);
}
Expand All @@ -174,7 +182,7 @@ svfloat32_t test_svcmla_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x double> [[OP3:%.*]], i32 0)
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
//
svfloat64_t test_svcmla_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3)
svfloat64_t test_svcmla_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmla,_f64,_m,)(pg, op1, op2, op3, 0);
}
Expand All @@ -191,7 +199,7 @@ svfloat64_t test_svcmla_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.nxv8f16(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 90)
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP1]]
//
svfloat16_t test_svcmla_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
svfloat16_t test_svcmla_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svfloat16_t op3) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmla,_f16,_x,)(pg, op1, op2, op3, 90);
}
Expand All @@ -208,7 +216,7 @@ svfloat16_t test_svcmla_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2, svf
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.nxv4f32(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x float> [[OP3:%.*]], i32 180)
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP1]]
//
svfloat32_t test_svcmla_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfloat32_t op3)
svfloat32_t test_svcmla_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svfloat32_t op3) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmla,_f32,_x,)(pg, op1, op2, op3, 180);
}
Expand All @@ -225,7 +233,7 @@ svfloat32_t test_svcmla_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2, svf
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x double> @llvm.aarch64.sve.fcmla.nxv2f64(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x double> [[OP1:%.*]], <vscale x 2 x double> [[OP2:%.*]], <vscale x 2 x double> [[OP3:%.*]], i32 270)
// CPP-CHECK-NEXT: ret <vscale x 2 x double> [[TMP1]]
//
svfloat64_t test_svcmla_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3)
svfloat64_t test_svcmla_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svfloat64_t op3) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmla,_f64,_x,)(pg, op1, op2, op3, 270);
}
Expand All @@ -240,7 +248,7 @@ svfloat64_t test_svcmla_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2, svf
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.lane.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 0, i32 0)
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
svfloat16_t test_svcmla_lane_f16(svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
svfloat16_t test_svcmla_lane_f16(svfloat16_t op1, svfloat16_t op2, svfloat16_t op3) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmla_lane,_f16,,)(op1, op2, op3, 0, 0);
}
Expand All @@ -255,7 +263,7 @@ svfloat16_t test_svcmla_lane_f16(svfloat16_t op1, svfloat16_t op2, svfloat16_t o
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 8 x half> @llvm.aarch64.sve.fcmla.lane.nxv8f16(<vscale x 8 x half> [[OP1:%.*]], <vscale x 8 x half> [[OP2:%.*]], <vscale x 8 x half> [[OP3:%.*]], i32 3, i32 90)
// CPP-CHECK-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
svfloat16_t test_svcmla_lane_f16_1(svfloat16_t op1, svfloat16_t op2, svfloat16_t op3)
svfloat16_t test_svcmla_lane_f16_1(svfloat16_t op1, svfloat16_t op2, svfloat16_t op3) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmla_lane,_f16,,)(op1, op2, op3, 3, 90);
}
Expand All @@ -270,7 +278,7 @@ svfloat16_t test_svcmla_lane_f16_1(svfloat16_t op1, svfloat16_t op2, svfloat16_t
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.lane.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x float> [[OP3:%.*]], i32 0, i32 180)
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
svfloat32_t test_svcmla_lane_f32(svfloat32_t op1, svfloat32_t op2, svfloat32_t op3)
svfloat32_t test_svcmla_lane_f32(svfloat32_t op1, svfloat32_t op2, svfloat32_t op3) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmla_lane,_f32,,)(op1, op2, op3, 0, 180);
}
Expand All @@ -285,7 +293,7 @@ svfloat32_t test_svcmla_lane_f32(svfloat32_t op1, svfloat32_t op2, svfloat32_t o
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 4 x float> @llvm.aarch64.sve.fcmla.lane.nxv4f32(<vscale x 4 x float> [[OP1:%.*]], <vscale x 4 x float> [[OP2:%.*]], <vscale x 4 x float> [[OP3:%.*]], i32 1, i32 270)
// CPP-CHECK-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
svfloat32_t test_svcmla_lane_f32_1(svfloat32_t op1, svfloat32_t op2, svfloat32_t op3)
svfloat32_t test_svcmla_lane_f32_1(svfloat32_t op1, svfloat32_t op2, svfloat32_t op3) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmla_lane,_f32,,)(op1, op2, op3, 1, 270);
}
64 changes: 36 additions & 28 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpeq.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,16 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -o /dev/null %s

#include <arm_sve.h>

#if defined __ARM_FEATURE_SME
#define MODE_ATTR __arm_streaming
#else
#define MODE_ATTR
#endif

#ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
Expand All @@ -24,7 +32,7 @@
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
svbool_t test_svcmpeq_s8(svbool_t pg, svint8_t op1, svint8_t op2)
svbool_t test_svcmpeq_s8(svbool_t pg, svint8_t op1, svint8_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_s8,,)(pg, op1, op2);
}
Expand All @@ -43,7 +51,7 @@ svbool_t test_svcmpeq_s8(svbool_t pg, svint8_t op1, svint8_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_s16(svbool_t pg, svint16_t op1, svint16_t op2)
svbool_t test_svcmpeq_s16(svbool_t pg, svint16_t op1, svint16_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_s16,,)(pg, op1, op2);
}
Expand All @@ -62,7 +70,7 @@ svbool_t test_svcmpeq_s16(svbool_t pg, svint16_t op1, svint16_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_s32(svbool_t pg, svint32_t op1, svint32_t op2)
svbool_t test_svcmpeq_s32(svbool_t pg, svint32_t op1, svint32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_s32,,)(pg, op1, op2);
}
Expand All @@ -81,7 +89,7 @@ svbool_t test_svcmpeq_s32(svbool_t pg, svint32_t op1, svint32_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_s64(svbool_t pg, svint64_t op1, svint64_t op2)
svbool_t test_svcmpeq_s64(svbool_t pg, svint64_t op1, svint64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_s64,,)(pg, op1, op2);
}
Expand All @@ -96,7 +104,7 @@ svbool_t test_svcmpeq_s64(svbool_t pg, svint64_t op1, svint64_t op2)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
svbool_t test_svcmpeq_u8(svbool_t pg, svuint8_t op1, svuint8_t op2)
svbool_t test_svcmpeq_u8(svbool_t pg, svuint8_t op1, svuint8_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_u8,,)(pg, op1, op2);
}
Expand All @@ -115,7 +123,7 @@ svbool_t test_svcmpeq_u8(svbool_t pg, svuint8_t op1, svuint8_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_u16(svbool_t pg, svuint16_t op1, svuint16_t op2)
svbool_t test_svcmpeq_u16(svbool_t pg, svuint16_t op1, svuint16_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_u16,,)(pg, op1, op2);
}
Expand All @@ -134,7 +142,7 @@ svbool_t test_svcmpeq_u16(svbool_t pg, svuint16_t op1, svuint16_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_u32(svbool_t pg, svuint32_t op1, svuint32_t op2)
svbool_t test_svcmpeq_u32(svbool_t pg, svuint32_t op1, svuint32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_u32,,)(pg, op1, op2);
}
Expand All @@ -153,7 +161,7 @@ svbool_t test_svcmpeq_u32(svbool_t pg, svuint32_t op1, svuint32_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_u64(svbool_t pg, svuint64_t op1, svuint64_t op2)
svbool_t test_svcmpeq_u64(svbool_t pg, svuint64_t op1, svuint64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_u64,,)(pg, op1, op2);
}
Expand All @@ -176,7 +184,7 @@ svbool_t test_svcmpeq_u64(svbool_t pg, svuint64_t op1, svuint64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_n_s64(svbool_t pg, svint64_t op1, int64_t op2)
svbool_t test_svcmpeq_n_s64(svbool_t pg, svint64_t op1, int64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_n_s64,,)(pg, op1, op2);
}
Expand All @@ -199,7 +207,7 @@ svbool_t test_svcmpeq_n_s64(svbool_t pg, svint64_t op1, int64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_n_u64(svbool_t pg, svuint64_t op1, uint64_t op2)
svbool_t test_svcmpeq_n_u64(svbool_t pg, svuint64_t op1, uint64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_n_u64,,)(pg, op1, op2);
}
Expand All @@ -214,7 +222,7 @@ svbool_t test_svcmpeq_n_u64(svbool_t pg, svuint64_t op1, uint64_t op2)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
svbool_t test_svcmpeq_wide_s8(svbool_t pg, svint8_t op1, svint64_t op2)
svbool_t test_svcmpeq_wide_s8(svbool_t pg, svint8_t op1, svint64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq_wide,_s8,,)(pg, op1, op2);
}
Expand All @@ -233,7 +241,7 @@ svbool_t test_svcmpeq_wide_s8(svbool_t pg, svint8_t op1, svint64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_wide_s16(svbool_t pg, svint16_t op1, svint64_t op2)
svbool_t test_svcmpeq_wide_s16(svbool_t pg, svint16_t op1, svint64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq_wide,_s16,,)(pg, op1, op2);
}
Expand All @@ -252,7 +260,7 @@ svbool_t test_svcmpeq_wide_s16(svbool_t pg, svint16_t op1, svint64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_wide_s32(svbool_t pg, svint32_t op1, svint64_t op2)
svbool_t test_svcmpeq_wide_s32(svbool_t pg, svint32_t op1, svint64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq_wide,_s32,,)(pg, op1, op2);
}
Expand All @@ -271,7 +279,7 @@ svbool_t test_svcmpeq_wide_s32(svbool_t pg, svint32_t op1, svint64_t op2)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
svbool_t test_svcmpeq_n_s8(svbool_t pg, svint8_t op1, int8_t op2)
svbool_t test_svcmpeq_n_s8(svbool_t pg, svint8_t op1, int8_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_n_s8,,)(pg, op1, op2);
}
Expand All @@ -294,7 +302,7 @@ svbool_t test_svcmpeq_n_s8(svbool_t pg, svint8_t op1, int8_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_n_s16(svbool_t pg, svint16_t op1, int16_t op2)
svbool_t test_svcmpeq_n_s16(svbool_t pg, svint16_t op1, int16_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_n_s16,,)(pg, op1, op2);
}
Expand All @@ -317,7 +325,7 @@ svbool_t test_svcmpeq_n_s16(svbool_t pg, svint16_t op1, int16_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_n_s32(svbool_t pg, svint32_t op1, int32_t op2)
svbool_t test_svcmpeq_n_s32(svbool_t pg, svint32_t op1, int32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_n_s32,,)(pg, op1, op2);
}
Expand All @@ -336,7 +344,7 @@ svbool_t test_svcmpeq_n_s32(svbool_t pg, svint32_t op1, int32_t op2)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
svbool_t test_svcmpeq_n_u8(svbool_t pg, svuint8_t op1, uint8_t op2)
svbool_t test_svcmpeq_n_u8(svbool_t pg, svuint8_t op1, uint8_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_n_u8,,)(pg, op1, op2);
}
Expand All @@ -359,7 +367,7 @@ svbool_t test_svcmpeq_n_u8(svbool_t pg, svuint8_t op1, uint8_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_n_u16(svbool_t pg, svuint16_t op1, uint16_t op2)
svbool_t test_svcmpeq_n_u16(svbool_t pg, svuint16_t op1, uint16_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_n_u16,,)(pg, op1, op2);
}
Expand All @@ -382,7 +390,7 @@ svbool_t test_svcmpeq_n_u16(svbool_t pg, svuint16_t op1, uint16_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_n_u32(svbool_t pg, svuint32_t op1, uint32_t op2)
svbool_t test_svcmpeq_n_u32(svbool_t pg, svuint32_t op1, uint32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_n_u32,,)(pg, op1, op2);
}
Expand All @@ -401,7 +409,7 @@ svbool_t test_svcmpeq_n_u32(svbool_t pg, svuint32_t op1, uint32_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2)
svbool_t test_svcmpeq_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_f16,,)(pg, op1, op2);
}
Expand All @@ -420,7 +428,7 @@ svbool_t test_svcmpeq_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
svbool_t test_svcmpeq_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_f32,,)(pg, op1, op2);
}
Expand All @@ -439,7 +447,7 @@ svbool_t test_svcmpeq_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
svbool_t test_svcmpeq_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_f64,,)(pg, op1, op2);
}
Expand All @@ -462,7 +470,7 @@ svbool_t test_svcmpeq_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_n_f16(svbool_t pg, svfloat16_t op1, float16_t op2)
svbool_t test_svcmpeq_n_f16(svbool_t pg, svfloat16_t op1, float16_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_n_f16,,)(pg, op1, op2);
}
Expand All @@ -485,7 +493,7 @@ svbool_t test_svcmpeq_n_f16(svbool_t pg, svfloat16_t op1, float16_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_n_f32(svbool_t pg, svfloat32_t op1, float32_t op2)
svbool_t test_svcmpeq_n_f32(svbool_t pg, svfloat32_t op1, float32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_n_f32,,)(pg, op1, op2);
}
Expand All @@ -508,7 +516,7 @@ svbool_t test_svcmpeq_n_f32(svbool_t pg, svfloat32_t op1, float32_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_n_f64(svbool_t pg, svfloat64_t op1, float64_t op2)
svbool_t test_svcmpeq_n_f64(svbool_t pg, svfloat64_t op1, float64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq,_n_f64,,)(pg, op1, op2);
}
Expand All @@ -527,7 +535,7 @@ svbool_t test_svcmpeq_n_f64(svbool_t pg, svfloat64_t op1, float64_t op2)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpeq.wide.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 2 x i64> [[DOTSPLAT]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
svbool_t test_svcmpeq_wide_n_s8(svbool_t pg, svint8_t op1, int64_t op2)
svbool_t test_svcmpeq_wide_n_s8(svbool_t pg, svint8_t op1, int64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq_wide,_n_s8,,)(pg, op1, op2);
}
Expand All @@ -550,7 +558,7 @@ svbool_t test_svcmpeq_wide_n_s8(svbool_t pg, svint8_t op1, int64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_wide_n_s16(svbool_t pg, svint16_t op1, int64_t op2)
svbool_t test_svcmpeq_wide_n_s16(svbool_t pg, svint16_t op1, int64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq_wide,_n_s16,,)(pg, op1, op2);
}
Expand All @@ -573,7 +581,7 @@ svbool_t test_svcmpeq_wide_n_s16(svbool_t pg, svint16_t op1, int64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpeq_wide_n_s32(svbool_t pg, svint32_t op1, int64_t op2)
svbool_t test_svcmpeq_wide_n_s32(svbool_t pg, svint32_t op1, int64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpeq_wide,_n_s32,,)(pg, op1, op2);
}
76 changes: 42 additions & 34 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpge.c
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76 changes: 42 additions & 34 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpgt.c
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76 changes: 42 additions & 34 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmple.c
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76 changes: 42 additions & 34 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmplt.c
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64 changes: 36 additions & 28 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpne.c
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Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,16 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -o /dev/null %s

#include <arm_sve.h>

#if defined __ARM_FEATURE_SME
#define MODE_ATTR __arm_streaming
#else
#define MODE_ATTR
#endif

#ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
Expand All @@ -24,7 +32,7 @@
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
svbool_t test_svcmpne_s8(svbool_t pg, svint8_t op1, svint8_t op2)
svbool_t test_svcmpne_s8(svbool_t pg, svint8_t op1, svint8_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_s8,,)(pg, op1, op2);
}
Expand All @@ -43,7 +51,7 @@ svbool_t test_svcmpne_s8(svbool_t pg, svint8_t op1, svint8_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_s16(svbool_t pg, svint16_t op1, svint16_t op2)
svbool_t test_svcmpne_s16(svbool_t pg, svint16_t op1, svint16_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_s16,,)(pg, op1, op2);
}
Expand All @@ -62,7 +70,7 @@ svbool_t test_svcmpne_s16(svbool_t pg, svint16_t op1, svint16_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_s32(svbool_t pg, svint32_t op1, svint32_t op2)
svbool_t test_svcmpne_s32(svbool_t pg, svint32_t op1, svint32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_s32,,)(pg, op1, op2);
}
Expand All @@ -81,7 +89,7 @@ svbool_t test_svcmpne_s32(svbool_t pg, svint32_t op1, svint32_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_s64(svbool_t pg, svint64_t op1, svint64_t op2)
svbool_t test_svcmpne_s64(svbool_t pg, svint64_t op1, svint64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_s64,,)(pg, op1, op2);
}
Expand All @@ -96,7 +104,7 @@ svbool_t test_svcmpne_s64(svbool_t pg, svint64_t op1, svint64_t op2)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[OP2:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
svbool_t test_svcmpne_u8(svbool_t pg, svuint8_t op1, svuint8_t op2)
svbool_t test_svcmpne_u8(svbool_t pg, svuint8_t op1, svuint8_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_u8,,)(pg, op1, op2);
}
Expand All @@ -115,7 +123,7 @@ svbool_t test_svcmpne_u8(svbool_t pg, svuint8_t op1, svuint8_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_u16(svbool_t pg, svuint16_t op1, svuint16_t op2)
svbool_t test_svcmpne_u16(svbool_t pg, svuint16_t op1, svuint16_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_u16,,)(pg, op1, op2);
}
Expand All @@ -134,7 +142,7 @@ svbool_t test_svcmpne_u16(svbool_t pg, svuint16_t op1, svuint16_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_u32(svbool_t pg, svuint32_t op1, svuint32_t op2)
svbool_t test_svcmpne_u32(svbool_t pg, svuint32_t op1, svuint32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_u32,,)(pg, op1, op2);
}
Expand All @@ -153,7 +161,7 @@ svbool_t test_svcmpne_u32(svbool_t pg, svuint32_t op1, svuint32_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_u64(svbool_t pg, svuint64_t op1, svuint64_t op2)
svbool_t test_svcmpne_u64(svbool_t pg, svuint64_t op1, svuint64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_u64,,)(pg, op1, op2);
}
Expand All @@ -176,7 +184,7 @@ svbool_t test_svcmpne_u64(svbool_t pg, svuint64_t op1, svuint64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_n_s64(svbool_t pg, svint64_t op1, int64_t op2)
svbool_t test_svcmpne_n_s64(svbool_t pg, svint64_t op1, int64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_n_s64,,)(pg, op1, op2);
}
Expand All @@ -199,7 +207,7 @@ svbool_t test_svcmpne_n_s64(svbool_t pg, svint64_t op1, int64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_n_u64(svbool_t pg, svuint64_t op1, uint64_t op2)
svbool_t test_svcmpne_n_u64(svbool_t pg, svuint64_t op1, uint64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_n_u64,,)(pg, op1, op2);
}
Expand All @@ -214,7 +222,7 @@ svbool_t test_svcmpne_n_u64(svbool_t pg, svuint64_t op1, uint64_t op2)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 2 x i64> [[OP2:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
svbool_t test_svcmpne_wide_s8(svbool_t pg, svint8_t op1, svint64_t op2)
svbool_t test_svcmpne_wide_s8(svbool_t pg, svint8_t op1, svint64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne_wide,_s8,,)(pg, op1, op2);
}
Expand All @@ -233,7 +241,7 @@ svbool_t test_svcmpne_wide_s8(svbool_t pg, svint8_t op1, svint64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_wide_s16(svbool_t pg, svint16_t op1, svint64_t op2)
svbool_t test_svcmpne_wide_s16(svbool_t pg, svint16_t op1, svint64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne_wide,_s16,,)(pg, op1, op2);
}
Expand All @@ -252,7 +260,7 @@ svbool_t test_svcmpne_wide_s16(svbool_t pg, svint16_t op1, svint64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_wide_s32(svbool_t pg, svint32_t op1, svint64_t op2)
svbool_t test_svcmpne_wide_s32(svbool_t pg, svint32_t op1, svint64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne_wide,_s32,,)(pg, op1, op2);
}
Expand All @@ -271,7 +279,7 @@ svbool_t test_svcmpne_wide_s32(svbool_t pg, svint32_t op1, svint64_t op2)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
svbool_t test_svcmpne_n_s8(svbool_t pg, svint8_t op1, int8_t op2)
svbool_t test_svcmpne_n_s8(svbool_t pg, svint8_t op1, int8_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_n_s8,,)(pg, op1, op2);
}
Expand All @@ -294,7 +302,7 @@ svbool_t test_svcmpne_n_s8(svbool_t pg, svint8_t op1, int8_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_n_s16(svbool_t pg, svint16_t op1, int16_t op2)
svbool_t test_svcmpne_n_s16(svbool_t pg, svint16_t op1, int16_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_n_s16,,)(pg, op1, op2);
}
Expand All @@ -317,7 +325,7 @@ svbool_t test_svcmpne_n_s16(svbool_t pg, svint16_t op1, int16_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_n_s32(svbool_t pg, svint32_t op1, int32_t op2)
svbool_t test_svcmpne_n_s32(svbool_t pg, svint32_t op1, int32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_n_s32,,)(pg, op1, op2);
}
Expand All @@ -336,7 +344,7 @@ svbool_t test_svcmpne_n_s32(svbool_t pg, svint32_t op1, int32_t op2)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 16 x i8> [[DOTSPLAT]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
svbool_t test_svcmpne_n_u8(svbool_t pg, svuint8_t op1, uint8_t op2)
svbool_t test_svcmpne_n_u8(svbool_t pg, svuint8_t op1, uint8_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_n_u8,,)(pg, op1, op2);
}
Expand All @@ -359,7 +367,7 @@ svbool_t test_svcmpne_n_u8(svbool_t pg, svuint8_t op1, uint8_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_n_u16(svbool_t pg, svuint16_t op1, uint16_t op2)
svbool_t test_svcmpne_n_u16(svbool_t pg, svuint16_t op1, uint16_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_n_u16,,)(pg, op1, op2);
}
Expand All @@ -382,7 +390,7 @@ svbool_t test_svcmpne_n_u16(svbool_t pg, svuint16_t op1, uint16_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_n_u32(svbool_t pg, svuint32_t op1, uint32_t op2)
svbool_t test_svcmpne_n_u32(svbool_t pg, svuint32_t op1, uint32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_n_u32,,)(pg, op1, op2);
}
Expand All @@ -401,7 +409,7 @@ svbool_t test_svcmpne_n_u32(svbool_t pg, svuint32_t op1, uint32_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2)
svbool_t test_svcmpne_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_f16,,)(pg, op1, op2);
}
Expand All @@ -420,7 +428,7 @@ svbool_t test_svcmpne_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
svbool_t test_svcmpne_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_f32,,)(pg, op1, op2);
}
Expand All @@ -439,7 +447,7 @@ svbool_t test_svcmpne_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
svbool_t test_svcmpne_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_f64,,)(pg, op1, op2);
}
Expand All @@ -462,7 +470,7 @@ svbool_t test_svcmpne_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_n_f16(svbool_t pg, svfloat16_t op1, float16_t op2)
svbool_t test_svcmpne_n_f16(svbool_t pg, svfloat16_t op1, float16_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_n_f16,,)(pg, op1, op2);
}
Expand All @@ -485,7 +493,7 @@ svbool_t test_svcmpne_n_f16(svbool_t pg, svfloat16_t op1, float16_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_n_f32(svbool_t pg, svfloat32_t op1, float32_t op2)
svbool_t test_svcmpne_n_f32(svbool_t pg, svfloat32_t op1, float32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_n_f32,,)(pg, op1, op2);
}
Expand All @@ -508,7 +516,7 @@ svbool_t test_svcmpne_n_f32(svbool_t pg, svfloat32_t op1, float32_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_n_f64(svbool_t pg, svfloat64_t op1, float64_t op2)
svbool_t test_svcmpne_n_f64(svbool_t pg, svfloat64_t op1, float64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne,_n_f64,,)(pg, op1, op2);
}
Expand All @@ -527,7 +535,7 @@ svbool_t test_svcmpne_n_f64(svbool_t pg, svfloat64_t op1, float64_t op2)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpne.wide.nxv16i8(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP1:%.*]], <vscale x 2 x i64> [[DOTSPLAT]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP0]]
//
svbool_t test_svcmpne_wide_n_s8(svbool_t pg, svint8_t op1, int64_t op2)
svbool_t test_svcmpne_wide_n_s8(svbool_t pg, svint8_t op1, int64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne_wide,_n_s8,,)(pg, op1, op2);
}
Expand All @@ -550,7 +558,7 @@ svbool_t test_svcmpne_wide_n_s8(svbool_t pg, svint8_t op1, int64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_wide_n_s16(svbool_t pg, svint16_t op1, int64_t op2)
svbool_t test_svcmpne_wide_n_s16(svbool_t pg, svint16_t op1, int64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne_wide,_n_s16,,)(pg, op1, op2);
}
Expand All @@ -573,7 +581,7 @@ svbool_t test_svcmpne_wide_n_s16(svbool_t pg, svint16_t op1, int64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpne_wide_n_s32(svbool_t pg, svint32_t op1, int64_t op2)
svbool_t test_svcmpne_wide_n_s32(svbool_t pg, svint32_t op1, int64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpne_wide,_n_s32,,)(pg, op1, op2);
}
20 changes: 14 additions & 6 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cmpuo.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,16 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -o /dev/null %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -o /dev/null %s

#include <arm_sve.h>

#if defined __ARM_FEATURE_SME
#define MODE_ATTR __arm_streaming
#else
#define MODE_ATTR
#endif

#ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
Expand All @@ -28,7 +36,7 @@
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpuo_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2)
svbool_t test_svcmpuo_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpuo,_f16,,)(pg, op1, op2);
}
Expand All @@ -47,7 +55,7 @@ svbool_t test_svcmpuo_f16(svbool_t pg, svfloat16_t op1, svfloat16_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpuo_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
svbool_t test_svcmpuo_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpuo,_f32,,)(pg, op1, op2);
}
Expand All @@ -66,7 +74,7 @@ svbool_t test_svcmpuo_f32(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpuo_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
svbool_t test_svcmpuo_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpuo,_f64,,)(pg, op1, op2);
}
Expand All @@ -89,7 +97,7 @@ svbool_t test_svcmpuo_f64(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpuo_n_f16(svbool_t pg, svfloat16_t op1, float16_t op2)
svbool_t test_svcmpuo_n_f16(svbool_t pg, svfloat16_t op1, float16_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpuo,_n_f16,,)(pg, op1, op2);
}
Expand All @@ -112,7 +120,7 @@ svbool_t test_svcmpuo_n_f16(svbool_t pg, svfloat16_t op1, float16_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv4i1(<vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpuo_n_f32(svbool_t pg, svfloat32_t op1, float32_t op2)
svbool_t test_svcmpuo_n_f32(svbool_t pg, svfloat32_t op1, float32_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpuo,_n_f32,,)(pg, op1, op2);
}
Expand All @@ -135,7 +143,7 @@ svbool_t test_svcmpuo_n_f32(svbool_t pg, svfloat32_t op1, float32_t op2)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i1> [[TMP2]]
//
svbool_t test_svcmpuo_n_f64(svbool_t pg, svfloat64_t op1, float64_t op2)
svbool_t test_svcmpuo_n_f64(svbool_t pg, svfloat64_t op1, float64_t op2) MODE_ATTR
{
return SVE_ACLE_FUNC(svcmpuo,_n_f64,,)(pg, op1, op2);
}
56 changes: 32 additions & 24 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnot.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,16 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s

#include <arm_sve.h>

#if defined __ARM_FEATURE_SME
#define MODE_ATTR __arm_streaming
#else
#define MODE_ATTR
#endif

#ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1,A2_UNUSED,A3,A4_UNUSED) A1##A3
Expand All @@ -24,7 +32,7 @@
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
svint8_t test_svcnot_s8_z(svbool_t pg, svint8_t op)
svint8_t test_svcnot_s8_z(svbool_t pg, svint8_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_s8,_z,)(pg, op);
}
Expand All @@ -41,7 +49,7 @@ svint8_t test_svcnot_s8_z(svbool_t pg, svint8_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svint16_t test_svcnot_s16_z(svbool_t pg, svint16_t op)
svint16_t test_svcnot_s16_z(svbool_t pg, svint16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_s16,_z,)(pg, op);
}
Expand All @@ -58,7 +66,7 @@ svint16_t test_svcnot_s16_z(svbool_t pg, svint16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
svint32_t test_svcnot_s32_z(svbool_t pg, svint32_t op)
svint32_t test_svcnot_s32_z(svbool_t pg, svint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_s32,_z,)(pg, op);
}
Expand All @@ -75,7 +83,7 @@ svint32_t test_svcnot_s32_z(svbool_t pg, svint32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
svint64_t test_svcnot_s64_z(svbool_t pg, svint64_t op)
svint64_t test_svcnot_s64_z(svbool_t pg, svint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_s64,_z,)(pg, op);
}
Expand All @@ -90,7 +98,7 @@ svint64_t test_svcnot_s64_z(svbool_t pg, svint64_t op)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> zeroinitializer, <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
svuint8_t test_svcnot_u8_z(svbool_t pg, svuint8_t op)
svuint8_t test_svcnot_u8_z(svbool_t pg, svuint8_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_u8,_z,)(pg, op);
}
Expand All @@ -107,7 +115,7 @@ svuint8_t test_svcnot_u8_z(svbool_t pg, svuint8_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svuint16_t test_svcnot_u16_z(svbool_t pg, svuint16_t op)
svuint16_t test_svcnot_u16_z(svbool_t pg, svuint16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_u16,_z,)(pg, op);
}
Expand All @@ -124,7 +132,7 @@ svuint16_t test_svcnot_u16_z(svbool_t pg, svuint16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> zeroinitializer, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
svuint32_t test_svcnot_u32_z(svbool_t pg, svuint32_t op)
svuint32_t test_svcnot_u32_z(svbool_t pg, svuint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_u32,_z,)(pg, op);
}
Expand All @@ -141,7 +149,7 @@ svuint32_t test_svcnot_u32_z(svbool_t pg, svuint32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> zeroinitializer, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
svuint64_t test_svcnot_u64_z(svbool_t pg, svuint64_t op)
svuint64_t test_svcnot_u64_z(svbool_t pg, svuint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_u64,_z,)(pg, op);
}
Expand All @@ -156,7 +164,7 @@ svuint64_t test_svcnot_u64_z(svbool_t pg, svuint64_t op)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> [[INACTIVE:%.*]], <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
svint8_t test_svcnot_s8_m(svint8_t inactive, svbool_t pg, svint8_t op)
svint8_t test_svcnot_s8_m(svint8_t inactive, svbool_t pg, svint8_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_s8,_m,)(inactive, pg, op);
}
Expand All @@ -173,7 +181,7 @@ svint8_t test_svcnot_s8_m(svint8_t inactive, svbool_t pg, svint8_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> [[INACTIVE:%.*]], <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svint16_t test_svcnot_s16_m(svint16_t inactive, svbool_t pg, svint16_t op)
svint16_t test_svcnot_s16_m(svint16_t inactive, svbool_t pg, svint16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_s16,_m,)(inactive, pg, op);
}
Expand All @@ -190,7 +198,7 @@ svint16_t test_svcnot_s16_m(svint16_t inactive, svbool_t pg, svint16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> [[INACTIVE:%.*]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
svint32_t test_svcnot_s32_m(svint32_t inactive, svbool_t pg, svint32_t op)
svint32_t test_svcnot_s32_m(svint32_t inactive, svbool_t pg, svint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_s32,_m,)(inactive, pg, op);
}
Expand All @@ -207,7 +215,7 @@ svint32_t test_svcnot_s32_m(svint32_t inactive, svbool_t pg, svint32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> [[INACTIVE:%.*]], <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
svint64_t test_svcnot_s64_m(svint64_t inactive, svbool_t pg, svint64_t op)
svint64_t test_svcnot_s64_m(svint64_t inactive, svbool_t pg, svint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_s64,_m,)(inactive, pg, op);
}
Expand All @@ -222,7 +230,7 @@ svint64_t test_svcnot_s64_m(svint64_t inactive, svbool_t pg, svint64_t op)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> [[INACTIVE:%.*]], <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
svuint8_t test_svcnot_u8_m(svuint8_t inactive, svbool_t pg, svuint8_t op)
svuint8_t test_svcnot_u8_m(svuint8_t inactive, svbool_t pg, svuint8_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_u8,_m,)(inactive, pg, op);
}
Expand All @@ -239,7 +247,7 @@ svuint8_t test_svcnot_u8_m(svuint8_t inactive, svbool_t pg, svuint8_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> [[INACTIVE:%.*]], <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svuint16_t test_svcnot_u16_m(svuint16_t inactive, svbool_t pg, svuint16_t op)
svuint16_t test_svcnot_u16_m(svuint16_t inactive, svbool_t pg, svuint16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_u16,_m,)(inactive, pg, op);
}
Expand All @@ -256,7 +264,7 @@ svuint16_t test_svcnot_u16_m(svuint16_t inactive, svbool_t pg, svuint16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> [[INACTIVE:%.*]], <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
svuint32_t test_svcnot_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op)
svuint32_t test_svcnot_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_u32,_m,)(inactive, pg, op);
}
Expand All @@ -273,7 +281,7 @@ svuint32_t test_svcnot_u32_m(svuint32_t inactive, svbool_t pg, svuint32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> [[INACTIVE:%.*]], <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
svuint64_t test_svcnot_u64_m(svuint64_t inactive, svbool_t pg, svuint64_t op)
svuint64_t test_svcnot_u64_m(svuint64_t inactive, svbool_t pg, svuint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_u64,_m,)(inactive, pg, op);
}
Expand All @@ -288,7 +296,7 @@ svuint64_t test_svcnot_u64_m(svuint64_t inactive, svbool_t pg, svuint64_t op)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
svint8_t test_svcnot_s8_x(svbool_t pg, svint8_t op)
svint8_t test_svcnot_s8_x(svbool_t pg, svint8_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_s8,_x,)(pg, op);
}
Expand All @@ -305,7 +313,7 @@ svint8_t test_svcnot_s8_x(svbool_t pg, svint8_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svint16_t test_svcnot_s16_x(svbool_t pg, svint16_t op)
svint16_t test_svcnot_s16_x(svbool_t pg, svint16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_s16,_x,)(pg, op);
}
Expand All @@ -322,7 +330,7 @@ svint16_t test_svcnot_s16_x(svbool_t pg, svint16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
svint32_t test_svcnot_s32_x(svbool_t pg, svint32_t op)
svint32_t test_svcnot_s32_x(svbool_t pg, svint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_s32,_x,)(pg, op);
}
Expand All @@ -339,7 +347,7 @@ svint32_t test_svcnot_s32_x(svbool_t pg, svint32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
svint64_t test_svcnot_s64_x(svbool_t pg, svint64_t op)
svint64_t test_svcnot_s64_x(svbool_t pg, svint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_s64,_x,)(pg, op);
}
Expand All @@ -354,7 +362,7 @@ svint64_t test_svcnot_s64_x(svbool_t pg, svint64_t op)
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call <vscale x 16 x i8> @llvm.aarch64.sve.cnot.nxv16i8(<vscale x 16 x i8> undef, <vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i8> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 16 x i8> [[TMP0]]
//
svuint8_t test_svcnot_u8_x(svbool_t pg, svuint8_t op)
svuint8_t test_svcnot_u8_x(svbool_t pg, svuint8_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_u8,_x,)(pg, op);
}
Expand All @@ -371,7 +379,7 @@ svuint8_t test_svcnot_u8_x(svbool_t pg, svuint8_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnot.nxv8i16(<vscale x 8 x i16> undef, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x i16> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svuint16_t test_svcnot_u16_x(svbool_t pg, svuint16_t op)
svuint16_t test_svcnot_u16_x(svbool_t pg, svuint16_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_u16,_x,)(pg, op);
}
Expand All @@ -388,7 +396,7 @@ svuint16_t test_svcnot_u16_x(svbool_t pg, svuint16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 4 x i32> @llvm.aarch64.sve.cnot.nxv4i32(<vscale x 4 x i32> undef, <vscale x 4 x i1> [[TMP0]], <vscale x 4 x i32> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
//
svuint32_t test_svcnot_u32_x(svbool_t pg, svuint32_t op)
svuint32_t test_svcnot_u32_x(svbool_t pg, svuint32_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_u32,_x,)(pg, op);
}
Expand All @@ -405,7 +413,7 @@ svuint32_t test_svcnot_u32_x(svbool_t pg, svuint32_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 2 x i64> @llvm.aarch64.sve.cnot.nxv2i64(<vscale x 2 x i64> undef, <vscale x 2 x i1> [[TMP0]], <vscale x 2 x i64> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 2 x i64> [[TMP1]]
//
svuint64_t test_svcnot_u64_x(svbool_t pg, svuint64_t op)
svuint64_t test_svcnot_u64_x(svbool_t pg, svuint64_t op) MODE_ATTR
{
return SVE_ACLE_FUNC(svcnot,_u64,_x,)(pg, op);
}
14 changes: 11 additions & 3 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt-bfloat.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -6,8 +6,16 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64 -target-feature +sve -target-feature +bf16 -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK

// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s

#include <arm_sve.h>

#if defined __ARM_FEATURE_SME
#define MODE_ATTR __arm_streaming
#else
#define MODE_ATTR
#endif

#ifdef SVE_OVERLOADED_FORMS
// A simple used,unused... macro, long enough to represent any SVE builtin.
#define SVE_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED) A1##A3
Expand All @@ -27,7 +35,7 @@
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8bf16(<vscale x 8 x i16> zeroinitializer, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x bfloat> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svuint16_t test_svcnt_bf16_z(svbool_t pg, svbfloat16_t op) {
svuint16_t test_svcnt_bf16_z(svbool_t pg, svbfloat16_t op) MODE_ATTR {
// expected-warning@+1 {{implicit declaration of function 'svcnt_bf16_z'}}
return SVE_ACLE_FUNC(svcnt, _bf16, _z, )(pg, op);
}
Expand All @@ -44,7 +52,7 @@ svuint16_t test_svcnt_bf16_z(svbool_t pg, svbfloat16_t op) {
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8bf16(<vscale x 8 x i16> [[INACTIVE:%.*]], <vscale x 8 x i1> [[TMP0]], <vscale x 8 x bfloat> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svuint16_t test_svcnt_bf16_m(svuint16_t inactive, svbool_t pg, svbfloat16_t op) {
svuint16_t test_svcnt_bf16_m(svuint16_t inactive, svbool_t pg, svbfloat16_t op) MODE_ATTR {
// expected-warning@+1 {{implicit declaration of function 'svcnt_bf16_m'}}
return SVE_ACLE_FUNC(svcnt, _bf16, _m, )(inactive, pg, op);
}
Expand All @@ -60,7 +68,7 @@ svuint16_t test_svcnt_bf16_m(svuint16_t inactive, svbool_t pg, svbfloat16_t op)
// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.cnt.nxv8bf16(<vscale x 8 x i16> undef, <vscale x 8 x i1> [[TMP0]], <vscale x 8 x bfloat> [[OP:%.*]])
// CPP-CHECK-NEXT: ret <vscale x 8 x i16> [[TMP1]]
//
svuint16_t test_svcnt_bf16_x(svbool_t pg, svbfloat16_t op) {
svuint16_t test_svcnt_bf16_x(svbool_t pg, svbfloat16_t op) MODE_ATTR {
// expected-warning@+1 {{implicit declaration of function 'svcnt_bf16_x'}}
return SVE_ACLE_FUNC(svcnt, _bf16, _x, )(pg, op);
}
74 changes: 41 additions & 33 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnt.c
View file

Large diffs are not rendered by default.

44 changes: 26 additions & 18 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntb.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,16 @@
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s

#include <arm_sve.h>

#if defined __ARM_FEATURE_SME
#define MODE_ATTR __arm_streaming
#else
#define MODE_ATTR
#endif

// CHECK-LABEL: @test_svcntb(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
Expand All @@ -17,7 +25,7 @@
// CPP-CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 4
// CPP-CHECK-NEXT: ret i64 [[TMP1]]
//
uint64_t test_svcntb()
uint64_t test_svcntb(void) MODE_ATTR
{
return svcntb();
}
Expand All @@ -32,7 +40,7 @@ uint64_t test_svcntb()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntb(i32 0)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntb_pat()
uint64_t test_svcntb_pat(void) MODE_ATTR
{
return svcntb_pat(SV_POW2);
}
Expand All @@ -45,7 +53,7 @@ uint64_t test_svcntb_pat()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 1
//
uint64_t test_svcntb_pat_1()
uint64_t test_svcntb_pat_1(void) MODE_ATTR
{
return svcntb_pat(SV_VL1);
}
Expand All @@ -58,7 +66,7 @@ uint64_t test_svcntb_pat_1()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 2
//
uint64_t test_svcntb_pat_2()
uint64_t test_svcntb_pat_2(void) MODE_ATTR
{
return svcntb_pat(SV_VL2);
}
Expand All @@ -71,7 +79,7 @@ uint64_t test_svcntb_pat_2()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 3
//
uint64_t test_svcntb_pat_3()
uint64_t test_svcntb_pat_3(void) MODE_ATTR
{
return svcntb_pat(SV_VL3);
}
Expand All @@ -84,7 +92,7 @@ uint64_t test_svcntb_pat_3()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 4
//
uint64_t test_svcntb_pat_4()
uint64_t test_svcntb_pat_4(void) MODE_ATTR
{
return svcntb_pat(SV_VL4);
}
Expand All @@ -97,7 +105,7 @@ uint64_t test_svcntb_pat_4()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 5
//
uint64_t test_svcntb_pat_5()
uint64_t test_svcntb_pat_5(void) MODE_ATTR
{
return svcntb_pat(SV_VL5);
}
Expand All @@ -110,7 +118,7 @@ uint64_t test_svcntb_pat_5()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 6
//
uint64_t test_svcntb_pat_6()
uint64_t test_svcntb_pat_6(void) MODE_ATTR
{
return svcntb_pat(SV_VL6);
}
Expand All @@ -123,7 +131,7 @@ uint64_t test_svcntb_pat_6()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 7
//
uint64_t test_svcntb_pat_7()
uint64_t test_svcntb_pat_7(void) MODE_ATTR
{
return svcntb_pat(SV_VL7);
}
Expand All @@ -136,7 +144,7 @@ uint64_t test_svcntb_pat_7()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 8
//
uint64_t test_svcntb_pat_8()
uint64_t test_svcntb_pat_8(void) MODE_ATTR
{
return svcntb_pat(SV_VL8);
}
Expand All @@ -149,7 +157,7 @@ uint64_t test_svcntb_pat_8()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 16
//
uint64_t test_svcntb_pat_9()
uint64_t test_svcntb_pat_9(void) MODE_ATTR
{
return svcntb_pat(SV_VL16);
}
Expand All @@ -164,7 +172,7 @@ uint64_t test_svcntb_pat_9()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntb(i32 10)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntb_pat_10()
uint64_t test_svcntb_pat_10(void) MODE_ATTR
{
return svcntb_pat(SV_VL32);
}
Expand All @@ -179,7 +187,7 @@ uint64_t test_svcntb_pat_10()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntb(i32 11)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntb_pat_11()
uint64_t test_svcntb_pat_11(void) MODE_ATTR
{
return svcntb_pat(SV_VL64);
}
Expand All @@ -194,7 +202,7 @@ uint64_t test_svcntb_pat_11()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntb(i32 12)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntb_pat_12()
uint64_t test_svcntb_pat_12(void) MODE_ATTR
{
return svcntb_pat(SV_VL128);
}
Expand All @@ -209,7 +217,7 @@ uint64_t test_svcntb_pat_12()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntb(i32 13)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntb_pat_13()
uint64_t test_svcntb_pat_13(void) MODE_ATTR
{
return svcntb_pat(SV_VL256);
}
Expand All @@ -224,7 +232,7 @@ uint64_t test_svcntb_pat_13()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntb(i32 29)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntb_pat_14()
uint64_t test_svcntb_pat_14(void) MODE_ATTR
{
return svcntb_pat(SV_MUL4);
}
Expand All @@ -239,7 +247,7 @@ uint64_t test_svcntb_pat_14()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntb(i32 30)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntb_pat_15()
uint64_t test_svcntb_pat_15(void) MODE_ATTR
{
return svcntb_pat(SV_MUL3);
}
Expand All @@ -256,7 +264,7 @@ uint64_t test_svcntb_pat_15()
// CPP-CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 4
// CPP-CHECK-NEXT: ret i64 [[TMP1]]
//
uint64_t test_svcntb_pat_16()
uint64_t test_svcntb_pat_16(void) MODE_ATTR
{
return svcntb_pat(SV_ALL);
}
44 changes: 26 additions & 18 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntd.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,16 @@
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s

#include <arm_sve.h>

#if defined __ARM_FEATURE_SME
#define MODE_ATTR __arm_streaming
#else
#define MODE_ATTR
#endif

// CHECK-LABEL: @test_svcntd(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
Expand All @@ -17,7 +25,7 @@
// CPP-CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 1
// CPP-CHECK-NEXT: ret i64 [[TMP1]]
//
uint64_t test_svcntd()
uint64_t test_svcntd(void) MODE_ATTR
{
return svcntd();
}
Expand All @@ -32,7 +40,7 @@ uint64_t test_svcntd()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntd(i32 0)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntd_pat()
uint64_t test_svcntd_pat(void) MODE_ATTR
{
return svcntd_pat(SV_POW2);
}
Expand All @@ -45,7 +53,7 @@ uint64_t test_svcntd_pat()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 1
//
uint64_t test_svcntd_pat_1()
uint64_t test_svcntd_pat_1(void) MODE_ATTR
{
return svcntd_pat(SV_VL1);
}
Expand All @@ -58,7 +66,7 @@ uint64_t test_svcntd_pat_1()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 2
//
uint64_t test_svcntd_pat_2()
uint64_t test_svcntd_pat_2(void) MODE_ATTR
{
return svcntd_pat(SV_VL2);
}
Expand All @@ -73,7 +81,7 @@ uint64_t test_svcntd_pat_2()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntd(i32 3)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntd_pat_3()
uint64_t test_svcntd_pat_3(void) MODE_ATTR
{
return svcntd_pat(SV_VL3);
}
Expand All @@ -88,7 +96,7 @@ uint64_t test_svcntd_pat_3()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntd(i32 4)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntd_pat_4()
uint64_t test_svcntd_pat_4(void) MODE_ATTR
{
return svcntd_pat(SV_VL4);
}
Expand All @@ -103,7 +111,7 @@ uint64_t test_svcntd_pat_4()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntd(i32 5)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntd_pat_5()
uint64_t test_svcntd_pat_5(void) MODE_ATTR
{
return svcntd_pat(SV_VL5);
}
Expand All @@ -118,7 +126,7 @@ uint64_t test_svcntd_pat_5()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntd(i32 6)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntd_pat_6()
uint64_t test_svcntd_pat_6(void) MODE_ATTR
{
return svcntd_pat(SV_VL6);
}
Expand All @@ -133,7 +141,7 @@ uint64_t test_svcntd_pat_6()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntd(i32 7)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntd_pat_7()
uint64_t test_svcntd_pat_7(void) MODE_ATTR
{
return svcntd_pat(SV_VL7);
}
Expand All @@ -148,7 +156,7 @@ uint64_t test_svcntd_pat_7()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntd(i32 8)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntd_pat_8()
uint64_t test_svcntd_pat_8(void) MODE_ATTR
{
return svcntd_pat(SV_VL8);
}
Expand All @@ -163,7 +171,7 @@ uint64_t test_svcntd_pat_8()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntd(i32 9)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntd_pat_9()
uint64_t test_svcntd_pat_9(void) MODE_ATTR
{
return svcntd_pat(SV_VL16);
}
Expand All @@ -178,7 +186,7 @@ uint64_t test_svcntd_pat_9()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntd(i32 10)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntd_pat_10()
uint64_t test_svcntd_pat_10(void) MODE_ATTR
{
return svcntd_pat(SV_VL32);
}
Expand All @@ -193,7 +201,7 @@ uint64_t test_svcntd_pat_10()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntd(i32 11)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntd_pat_11()
uint64_t test_svcntd_pat_11(void) MODE_ATTR
{
return svcntd_pat(SV_VL64);
}
Expand All @@ -208,7 +216,7 @@ uint64_t test_svcntd_pat_11()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntd(i32 12)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntd_pat_12()
uint64_t test_svcntd_pat_12(void) MODE_ATTR
{
return svcntd_pat(SV_VL128);
}
Expand All @@ -223,7 +231,7 @@ uint64_t test_svcntd_pat_12()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntd(i32 13)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntd_pat_13()
uint64_t test_svcntd_pat_13(void) MODE_ATTR
{
return svcntd_pat(SV_VL256);
}
Expand All @@ -238,7 +246,7 @@ uint64_t test_svcntd_pat_13()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntd(i32 29)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntd_pat_14()
uint64_t test_svcntd_pat_14(void) MODE_ATTR
{
return svcntd_pat(SV_MUL4);
}
Expand All @@ -253,7 +261,7 @@ uint64_t test_svcntd_pat_14()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntd(i32 30)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntd_pat_15()
uint64_t test_svcntd_pat_15(void) MODE_ATTR
{
return svcntd_pat(SV_MUL3);
}
Expand All @@ -270,7 +278,7 @@ uint64_t test_svcntd_pat_15()
// CPP-CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 1
// CPP-CHECK-NEXT: ret i64 [[TMP1]]
//
uint64_t test_svcntd_pat_16()
uint64_t test_svcntd_pat_16(void) MODE_ATTR
{
return svcntd_pat(SV_ALL);
}
44 changes: 26 additions & 18 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cnth.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,16 @@
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s

#include <arm_sve.h>

#if defined __ARM_FEATURE_SME
#define MODE_ATTR __arm_streaming
#else
#define MODE_ATTR
#endif

// CHECK-LABEL: @test_svcnth(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
Expand All @@ -17,7 +25,7 @@
// CPP-CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 3
// CPP-CHECK-NEXT: ret i64 [[TMP1]]
//
uint64_t test_svcnth()
uint64_t test_svcnth(void) MODE_ATTR
{
return svcnth();
}
Expand All @@ -32,7 +40,7 @@ uint64_t test_svcnth()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 0)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcnth_pat()
uint64_t test_svcnth_pat(void) MODE_ATTR
{
return svcnth_pat(SV_POW2);
}
Expand All @@ -45,7 +53,7 @@ uint64_t test_svcnth_pat()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 1
//
uint64_t test_svcnth_pat_1()
uint64_t test_svcnth_pat_1(void) MODE_ATTR
{
return svcnth_pat(SV_VL1);
}
Expand All @@ -58,7 +66,7 @@ uint64_t test_svcnth_pat_1()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 2
//
uint64_t test_svcnth_pat_2()
uint64_t test_svcnth_pat_2(void) MODE_ATTR
{
return svcnth_pat(SV_VL2);
}
Expand All @@ -71,7 +79,7 @@ uint64_t test_svcnth_pat_2()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 3
//
uint64_t test_svcnth_pat_3()
uint64_t test_svcnth_pat_3(void) MODE_ATTR
{
return svcnth_pat(SV_VL3);
}
Expand All @@ -84,7 +92,7 @@ uint64_t test_svcnth_pat_3()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 4
//
uint64_t test_svcnth_pat_4()
uint64_t test_svcnth_pat_4(void) MODE_ATTR
{
return svcnth_pat(SV_VL4);
}
Expand All @@ -97,7 +105,7 @@ uint64_t test_svcnth_pat_4()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 5
//
uint64_t test_svcnth_pat_5()
uint64_t test_svcnth_pat_5(void) MODE_ATTR
{
return svcnth_pat(SV_VL5);
}
Expand All @@ -110,7 +118,7 @@ uint64_t test_svcnth_pat_5()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 6
//
uint64_t test_svcnth_pat_6()
uint64_t test_svcnth_pat_6(void) MODE_ATTR
{
return svcnth_pat(SV_VL6);
}
Expand All @@ -123,7 +131,7 @@ uint64_t test_svcnth_pat_6()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 7
//
uint64_t test_svcnth_pat_7()
uint64_t test_svcnth_pat_7(void) MODE_ATTR
{
return svcnth_pat(SV_VL7);
}
Expand All @@ -136,7 +144,7 @@ uint64_t test_svcnth_pat_7()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 8
//
uint64_t test_svcnth_pat_8()
uint64_t test_svcnth_pat_8(void) MODE_ATTR
{
return svcnth_pat(SV_VL8);
}
Expand All @@ -151,7 +159,7 @@ uint64_t test_svcnth_pat_8()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 9)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcnth_pat_9()
uint64_t test_svcnth_pat_9(void) MODE_ATTR
{
return svcnth_pat(SV_VL16);
}
Expand All @@ -166,7 +174,7 @@ uint64_t test_svcnth_pat_9()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 10)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcnth_pat_10()
uint64_t test_svcnth_pat_10(void) MODE_ATTR
{
return svcnth_pat(SV_VL32);
}
Expand All @@ -181,7 +189,7 @@ uint64_t test_svcnth_pat_10()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 11)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcnth_pat_11()
uint64_t test_svcnth_pat_11(void) MODE_ATTR
{
return svcnth_pat(SV_VL64);
}
Expand All @@ -196,7 +204,7 @@ uint64_t test_svcnth_pat_11()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 12)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcnth_pat_12()
uint64_t test_svcnth_pat_12(void) MODE_ATTR
{
return svcnth_pat(SV_VL128);
}
Expand All @@ -211,7 +219,7 @@ uint64_t test_svcnth_pat_12()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 13)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcnth_pat_13()
uint64_t test_svcnth_pat_13(void) MODE_ATTR
{
return svcnth_pat(SV_VL256);
}
Expand All @@ -226,7 +234,7 @@ uint64_t test_svcnth_pat_13()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 29)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcnth_pat_14()
uint64_t test_svcnth_pat_14(void) MODE_ATTR
{
return svcnth_pat(SV_MUL4);
}
Expand All @@ -241,7 +249,7 @@ uint64_t test_svcnth_pat_14()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cnth(i32 30)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcnth_pat_15()
uint64_t test_svcnth_pat_15(void) MODE_ATTR
{
return svcnth_pat(SV_MUL3);
}
Expand All @@ -258,7 +266,7 @@ uint64_t test_svcnth_pat_15()
// CPP-CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 3
// CPP-CHECK-NEXT: ret i64 [[TMP1]]
//
uint64_t test_svcnth_pat_16()
uint64_t test_svcnth_pat_16(void) MODE_ATTR
{
return svcnth_pat(SV_ALL);
}
16 changes: 12 additions & 4 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntp.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,16 @@
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s

#include <arm_sve.h>

#if defined __ARM_FEATURE_SME
#define MODE_ATTR __arm_streaming
#else
#define MODE_ATTR
#endif

// CHECK-LABEL: @test_svcntp_b8(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[OP:%.*]])
Expand All @@ -15,7 +23,7 @@
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.nxv16i1(<vscale x 16 x i1> [[PG:%.*]], <vscale x 16 x i1> [[OP:%.*]])
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntp_b8(svbool_t pg, svbool_t op)
uint64_t test_svcntp_b8(svbool_t pg, svbool_t op) MODE_ATTR
{
return svcntp_b8(pg, op);
}
Expand All @@ -34,7 +42,7 @@ uint64_t test_svcntp_b8(svbool_t pg, svbool_t op)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.nxv8i1(<vscale x 8 x i1> [[TMP0]], <vscale x 8 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret i64 [[TMP2]]
//
uint64_t test_svcntp_b16(svbool_t pg, svbool_t op)
uint64_t test_svcntp_b16(svbool_t pg, svbool_t op) MODE_ATTR
{
return svcntp_b16(pg, op);
}
Expand All @@ -53,7 +61,7 @@ uint64_t test_svcntp_b16(svbool_t pg, svbool_t op)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.nxv4i1(<vscale x 4 x i1> [[TMP0]], <vscale x 4 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret i64 [[TMP2]]
//
uint64_t test_svcntp_b32(svbool_t pg, svbool_t op)
uint64_t test_svcntp_b32(svbool_t pg, svbool_t op) MODE_ATTR
{
return svcntp_b32(pg, op);
}
Expand All @@ -72,7 +80,7 @@ uint64_t test_svcntp_b32(svbool_t pg, svbool_t op)
// CPP-CHECK-NEXT: [[TMP2:%.*]] = tail call i64 @llvm.aarch64.sve.cntp.nxv2i1(<vscale x 2 x i1> [[TMP0]], <vscale x 2 x i1> [[TMP1]])
// CPP-CHECK-NEXT: ret i64 [[TMP2]]
//
uint64_t test_svcntp_b64(svbool_t pg, svbool_t op)
uint64_t test_svcntp_b64(svbool_t pg, svbool_t op) MODE_ATTR
{
return svcntp_b64(pg, op);
}
44 changes: 26 additions & 18 deletions clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cntw.c
View file
Original file line number Diff line number Diff line change
Expand Up @@ -3,8 +3,16 @@
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK
// RUN: %clang_cc1 -triple aarch64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s
// RUN: %clang_cc1 -triple aarch64 -target-feature +sme -S -disable-O0-optnone -Werror -Wall -o /dev/null %s

#include <arm_sve.h>

#if defined __ARM_FEATURE_SME
#define MODE_ATTR __arm_streaming
#else
#define MODE_ATTR
#endif

// CHECK-LABEL: @test_svcntw(
// CHECK-NEXT: entry:
// CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.vscale.i64()
Expand All @@ -17,7 +25,7 @@
// CPP-CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 2
// CPP-CHECK-NEXT: ret i64 [[TMP1]]
//
uint64_t test_svcntw()
uint64_t test_svcntw(void) MODE_ATTR
{
return svcntw();
}
Expand All @@ -32,7 +40,7 @@ uint64_t test_svcntw()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 0)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntw_pat()
uint64_t test_svcntw_pat(void) MODE_ATTR
{
return svcntw_pat(SV_POW2);
}
Expand All @@ -45,7 +53,7 @@ uint64_t test_svcntw_pat()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 1
//
uint64_t test_svcntw_pat_1()
uint64_t test_svcntw_pat_1(void) MODE_ATTR
{
return svcntw_pat(SV_VL1);
}
Expand All @@ -58,7 +66,7 @@ uint64_t test_svcntw_pat_1()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 2
//
uint64_t test_svcntw_pat_2()
uint64_t test_svcntw_pat_2(void) MODE_ATTR
{
return svcntw_pat(SV_VL2);
}
Expand All @@ -71,7 +79,7 @@ uint64_t test_svcntw_pat_2()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 3
//
uint64_t test_svcntw_pat_3()
uint64_t test_svcntw_pat_3(void) MODE_ATTR
{
return svcntw_pat(SV_VL3);
}
Expand All @@ -84,7 +92,7 @@ uint64_t test_svcntw_pat_3()
// CPP-CHECK-NEXT: entry:
// CPP-CHECK-NEXT: ret i64 4
//
uint64_t test_svcntw_pat_4()
uint64_t test_svcntw_pat_4(void) MODE_ATTR
{
return svcntw_pat(SV_VL4);
}
Expand All @@ -99,7 +107,7 @@ uint64_t test_svcntw_pat_4()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 5)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntw_pat_5()
uint64_t test_svcntw_pat_5(void) MODE_ATTR
{
return svcntw_pat(SV_VL5);
}
Expand All @@ -114,7 +122,7 @@ uint64_t test_svcntw_pat_5()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 6)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntw_pat_6()
uint64_t test_svcntw_pat_6(void) MODE_ATTR
{
return svcntw_pat(SV_VL6);
}
Expand All @@ -129,7 +137,7 @@ uint64_t test_svcntw_pat_6()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 7)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntw_pat_7()
uint64_t test_svcntw_pat_7(void) MODE_ATTR
{
return svcntw_pat(SV_VL7);
}
Expand All @@ -144,7 +152,7 @@ uint64_t test_svcntw_pat_7()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 8)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntw_pat_8()
uint64_t test_svcntw_pat_8(void) MODE_ATTR
{
return svcntw_pat(SV_VL8);
}
Expand All @@ -159,7 +167,7 @@ uint64_t test_svcntw_pat_8()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 9)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntw_pat_9()
uint64_t test_svcntw_pat_9(void) MODE_ATTR
{
return svcntw_pat(SV_VL16);
}
Expand All @@ -174,7 +182,7 @@ uint64_t test_svcntw_pat_9()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 10)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntw_pat_10()
uint64_t test_svcntw_pat_10(void) MODE_ATTR
{
return svcntw_pat(SV_VL32);
}
Expand All @@ -189,7 +197,7 @@ uint64_t test_svcntw_pat_10()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 11)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntw_pat_11()
uint64_t test_svcntw_pat_11(void) MODE_ATTR
{
return svcntw_pat(SV_VL64);
}
Expand All @@ -204,7 +212,7 @@ uint64_t test_svcntw_pat_11()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 12)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntw_pat_12()
uint64_t test_svcntw_pat_12(void) MODE_ATTR
{
return svcntw_pat(SV_VL128);
}
Expand All @@ -219,7 +227,7 @@ uint64_t test_svcntw_pat_12()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 13)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntw_pat_13()
uint64_t test_svcntw_pat_13(void) MODE_ATTR
{
return svcntw_pat(SV_VL256);
}
Expand All @@ -234,7 +242,7 @@ uint64_t test_svcntw_pat_13()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 29)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntw_pat_14()
uint64_t test_svcntw_pat_14(void) MODE_ATTR
{
return svcntw_pat(SV_MUL4);
}
Expand All @@ -249,7 +257,7 @@ uint64_t test_svcntw_pat_14()
// CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call i64 @llvm.aarch64.sve.cntw(i32 30)
// CPP-CHECK-NEXT: ret i64 [[TMP0]]
//
uint64_t test_svcntw_pat_15()
uint64_t test_svcntw_pat_15(void) MODE_ATTR
{
return svcntw_pat(SV_MUL3);
}
Expand All @@ -266,7 +274,7 @@ uint64_t test_svcntw_pat_15()
// CPP-CHECK-NEXT: [[TMP1:%.*]] = shl nuw nsw i64 [[TMP0]], 2
// CPP-CHECK-NEXT: ret i64 [[TMP1]]
//
uint64_t test_svcntw_pat_16()
uint64_t test_svcntw_pat_16(void) MODE_ATTR
{
return svcntw_pat(SV_ALL);
}
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