diff --git a/lldb/test/API/commands/command/script/add/test_commands.py b/lldb/test/API/commands/command/script/add/test_commands.py
@@ -6,6 +6,7 @@
 import lldb
 from lldb.plugins.parsed_cmd import ParsedCommand
 
+
 class ReportingCmd(ParsedCommand):
     def __init__(self, debugger, unused):
         super().__init__(debugger, unused)
@@ -16,16 +17,21 @@ def __call__(self, debugger, args_array, exe_ctx, result):
             result.AppendMessage("Options:\n")
             for long_option, elem in opt_def.items():
                 dest = elem["dest"]
-                result.AppendMessage(f"{long_option} (set: {elem['_value_set']}): {object.__getattribute__(self.ov_parser, dest)}\n")
+                result.AppendMessage(
+                    f"{long_option} (set: {elem['_value_set']}): {object.__getattribute__(self.ov_parser, dest)}\n"
+                )
         else:
             result.AppendMessage("No options\n")
 
         num_args = args_array.GetSize()
         if num_args > 0:
             result.AppendMessage(f"{num_args} arguments:")
-        for idx in range(0,num_args):
-          result.AppendMessage(f"{idx}: {args_array.GetItemAtIndex(idx).GetStringValue(10000)}\n")
-
+        for idx in range(0, num_args):
+            result.AppendMessage(
+                f"{idx}: {args_array.GetItemAtIndex(idx).GetStringValue(10000)}\n"
+            )
+
+
 class NoArgsCommand(ReportingCmd):
     program = "no-args"
 
@@ -41,59 +47,62 @@ def setup_command_definition(self):
             "b",
             "bool-arg",
             "a boolean arg, defaults to True",
-            value_type = lldb.eArgTypeBoolean,
-            groups = [1,2],
-            dest = "bool_arg",
-            default = True
+            value_type=lldb.eArgTypeBoolean,
+            groups=[1, 2],
+            dest="bool_arg",
+            default=True,
         )
 
         self.ov_parser.add_option(
             "s",
             "shlib-name",
             "A shared library name.",
             value_type=lldb.eArgTypeShlibName,
-            groups = [1, [3,4]],
-            dest = "shlib_name",
-            default = None
+            groups=[1, [3, 4]],
+            dest="shlib_name",
+            default=None,
         )
 
         self.ov_parser.add_option(
             "d",
             "disk-file-name",
             "An on disk filename",
-            value_type = lldb.eArgTypeFilename,
-            dest = "disk_file_name",
-            default = None
+            value_type=lldb.eArgTypeFilename,
+            dest="disk_file_name",
+            default=None,
         )
 
         self.ov_parser.add_option(
             "l",
             "line-num",
             "A line number",
-            value_type = lldb.eArgTypeLineNum,
-            groups = 3,
-            dest = "line_num",
-            default = 0
+            value_type=lldb.eArgTypeLineNum,
+            groups=3,
+            dest="line_num",
+            default=0,
         )
-        
+
         self.ov_parser.add_option(
             "e",
             "enum-option",
             "An enum, doesn't actually do anything",
-            enum_values = [["foo", "does foo things"],
-                           ["bar", "does bar things"],
-                           ["baz", "does baz things"]],
-            groups = 4,
-            dest = "enum_option",
-            default = "foo"
+            enum_values=[
+                ["foo", "does foo things"],
+                ["bar", "does bar things"],
+                ["baz", "does baz things"],
+            ],
+            groups=4,
+            dest="enum_option",
+            default="foo",
         )
-        
+
     def get_short_help(self):
         return "Example command for use in debugging"
 
     def get_long_help(self):
         return self.help_string
 
+
 class OneArgCommandNoOptions(ReportingCmd):
     program = "one-arg-no-opt"
 
@@ -105,14 +114,17 @@ def register_lldb_command(cls, debugger, module_name):
         ParsedCommand.do_register_cmd(cls, debugger, module_name)
 
     def setup_command_definition(self):
-        self.ov_parser.add_argument_set([self.ov_parser.make_argument_element(lldb.eArgTypeSourceFile, "plain")])
-
+        self.ov_parser.add_argument_set(
+            [self.ov_parser.make_argument_element(lldb.eArgTypeSourceFile, "plain")]
+        )
+
     def get_short_help(self):
         return "Example command for use in debugging"
 
     def get_long_help(self):
         return self.help_string
 
+
 class TwoArgGroupsCommand(ReportingCmd):
     program = "two-args"
 
@@ -128,43 +140,60 @@ def setup_command_definition(self):
             "l",
             "language",
             "language defaults to None",
-            value_type = lldb.eArgTypeLanguage,
-            groups = [1,2],
-            dest = "language",
-            default = None
+            value_type=lldb.eArgTypeLanguage,
+            groups=[1, 2],
+            dest="language",
+            default=None,
         )
 
         self.ov_parser.add_option(
             "c",
             "log-channel",
             "log channel - defaults to lldb",
             value_type=lldb.eArgTypeLogChannel,
-            groups = [1, 3],
-            dest = "log_channel",
-            default = "lldb"
+            groups=[1, 3],
+            dest="log_channel",
+            default="lldb",
         )
 
         self.ov_parser.add_option(
             "p",
             "process-name",
             "A process name, defaults to None",
-            value_type = lldb.eArgTypeProcessName,
-            dest = "proc_name",
-            default = None
+            value_type=lldb.eArgTypeProcessName,
+            dest="proc_name",
+            default=None,
+        )
+
+        self.ov_parser.add_argument_set(
+            [
+                self.ov_parser.make_argument_element(
+                    lldb.eArgTypeClassName, "plain", [1, 2]
+                ),
+                self.ov_parser.make_argument_element(
+                    lldb.eArgTypeOffset, "optional", [1, 2]
+                ),
+            ]
         )
 
-        self.ov_parser.add_argument_set([self.ov_parser.make_argument_element(lldb.eArgTypeClassName, "plain", [1,2]),
-                         self.ov_parser.make_argument_element(lldb.eArgTypeOffset, "optional", [1,2])])
+        self.ov_parser.add_argument_set(
+            [
+                self.ov_parser.make_argument_element(
+                    lldb.eArgTypePythonClass, "plain", [3, 4]
+                ),
+                self.ov_parser.make_argument_element(
+                    lldb.eArgTypePid, "optional", [3, 4]
+                ),
+            ]
+        )
 
-        self.ov_parser.add_argument_set([self.ov_parser.make_argument_element(lldb.eArgTypePythonClass, "plain", [3,4]),
-                         self.ov_parser.make_argument_element(lldb.eArgTypePid, "optional", [3,4])])
-
     def get_short_help(self):
         return "Example command for use in debugging"
 
     def get_long_help(self):
         return self.help_string
 
+
 def __lldb_init_module(debugger, dict):
     # Register all classes that have a register_lldb_command method
     for _name, cls in inspect.getmembers(sys.modules[__name__]):

diff --git a/lldb/test/API/commands/expression/nested/TestNestedExpressions.py b/lldb/test/API/commands/expression/nested/TestNestedExpressions.py
@@ -9,22 +9,23 @@
 
 
 class NestedExpressions(TestBase):
-
     def test_enum_in_nested_structs(self):
         """
-            Test expressions that references an enumeration in nested structs.
+        Test expressions that references an enumeration in nested structs.
         """
         self.build()
         exe_path = self.getBuildArtifact("a.out")
         target = self.dbg.CreateTarget(exe_path)
         self.assertTrue(target, "Target: %s is not valid." % (exe_path))
-        self.expect_expr("A::B::C::EnumType::Eleven",
-                         result_type="A::B::C::EnumType",
-                         result_value="Eleven")
+        self.expect_expr(
+            "A::B::C::EnumType::Eleven",
+            result_type="A::B::C::EnumType",
+            result_value="Eleven",
+        )
 
     def test_struct_in_nested_structs(self):
         """
-            Test expressions that references a struct in nested structs.
+        Test expressions that references a struct in nested structs.
         """
         self.build()
         exe_path = self.getBuildArtifact("a.out")
@@ -37,36 +38,36 @@ def test_struct_in_nested_structs(self):
     @skipIfWindows
     def test_static_in_nested_structs(self):
         """
-            Test expressions that references a static variable in nested structs.
+        Test expressions that references a static variable in nested structs.
         """
         self.build()
         (target, process, thread, bkpt) = lldbutil.run_to_source_breakpoint(
             self, "Stop here to evaluate expressions", lldb.SBFileSpec("main.cpp")
         )
-        self.expect_expr("A::B::C::enum_static",
-                         result_type="A::B::C::EnumType",
-                         result_value="Eleven")
+        self.expect_expr(
+            "A::B::C::enum_static",
+            result_type="A::B::C::EnumType",
+            result_value="Eleven",
+        )
 
     def test_enum_in_nested_namespaces(self):
         """
-            Test expressions that references an enumeration in nested namespaces.
+        Test expressions that references an enumeration in nested namespaces.
         """
         self.build()
         exe_path = self.getBuildArtifact("a.out")
         target = self.dbg.CreateTarget(exe_path)
         self.assertTrue(target, "Target: %s is not valid." % (exe_path))
-        self.expect_expr("a::b::c::Color::Blue",
-                         result_type="a::b::c::Color",
-                         result_value="Blue")
+        self.expect_expr(
+            "a::b::c::Color::Blue", result_type="a::b::c::Color", result_value="Blue"
+        )
 
     def test_static_in_nested_namespaces(self):
         """
-            Test expressions that references an enumeration in nested namespaces.
+        Test expressions that references an enumeration in nested namespaces.
         """
         self.build()
         (target, process, thread, bkpt) = lldbutil.run_to_source_breakpoint(
             self, "Stop here to evaluate expressions", lldb.SBFileSpec("main.cpp")
         )
-        self.expect_expr("a::b::c::d",
-                         result_type="int",
-                         result_value="12")
+        self.expect_expr("a::b::c::d", result_type="int", result_value="12")
diff --git a/lldb/test/API/commands/process/attach/TestProcessAttach.py b/lldb/test/API/commands/process/attach/TestProcessAttach.py
@@ -128,4 +128,3 @@ def tearDown(self):
 
         # Call super's tearDown().
         TestBase.tearDown(self)
-
diff --git a/lldb/test/API/commands/watchpoints/step_over_watchpoint/TestStepOverWatchpoint.py b/lldb/test/API/commands/watchpoints/step_over_watchpoint/TestStepOverWatchpoint.py
@@ -20,7 +20,7 @@ def get_to_start(self, bkpt_text):
 
     @add_test_categories(["basic_process"])
     @expectedFailureAll(
-        oslist=["ios", "watchos", "tvos", "bridgeos", "macosx"],
+        macos_version=["<", "14.4"],
         archs=["aarch64", "arm"],
         bugnumber="<rdar://problem/106868647>",
     )
@@ -63,7 +63,7 @@ def test_step_over_read_watchpoint(self):
 
     @add_test_categories(["basic_process"])
     @expectedFailureAll(
-        oslist=["ios", "watchos", "tvos", "bridgeos", "macosx"],
+        macos_version=["<", "14.4"],
         archs=["aarch64", "arm"],
         bugnumber="<rdar://problem/106868647>",
     )

diff --git a/lldb/test/API/functionalities/data-formatter/data-formatter-advanced/TestDataFormatterAdv.py b/lldb/test/API/functionalities/data-formatter/data-formatter-advanced/TestDataFormatterAdv.py
@@ -299,11 +299,11 @@ def cleanup():
         self.runCmd("settings set target.max-string-summary-length 5")
         some_string = self.frame().FindVariable("some_string")
         some_string_summary = some_string.GetSummary()
-        if (re.match(r"^std::__\w+::", some_string.GetTypeName())):
-          self.assertEqual(some_string_summary, '"01234"...')
+        if re.match(r"^std::__\w+::", some_string.GetTypeName()):
+            self.assertEqual(some_string_summary, '"01234"...')
         else:
-          #libstdc++ string formatter suffers from the same problem as some_cstring below
-          pass
+            # libstdc++ string formatter suffers from the same problem as some_cstring below
+            pass
 
         some_carr = self.frame().FindVariable("some_carr")
         some_carr_summary = some_carr.GetSummary()

diff --git a/lldb/test/API/functionalities/executable_first/TestExecutableFirst.py b/lldb/test/API/functionalities/executable_first/TestExecutableFirst.py
@@ -12,7 +12,7 @@ class TestExecutableIsFirst(TestBase):
 
     # ELF does not have a hard distinction between shared libraries and
     # (position-independent) executables
-    @skipIf(oslist=no_match(lldbplatformutil.getDarwinOSTriples()+["windows"]))
+    @skipIf(oslist=no_match(lldbplatformutil.getDarwinOSTriples() + ["windows"]))
     def test_executable_is_first_before_run(self):
         self.build()
 
@@ -44,8 +44,10 @@ def test_executable_is_first_before_run(self):
     def test_executable_is_first_during_run(self):
         self.build()
         (target, process, thread, bkpt) = lldbutil.run_to_source_breakpoint(
-            self, "break after function call", lldb.SBFileSpec("main.cpp"),
-            extra_images=["bar"]
+            self,
+            "break after function call",
+            lldb.SBFileSpec("main.cpp"),
+            extra_images=["bar"],
         )
 
         first_module = target.GetModuleAtIndex(0)

diff --git a/lldb/test/API/functionalities/inline-sourcefile/TestInlineSourceFiles.py b/lldb/test/API/functionalities/inline-sourcefile/TestInlineSourceFiles.py
@@ -13,5 +13,5 @@ class InlineSourceFilesTestCase(TestBase):
     def test(self):
         """Test DWARF inline source files."""
         self.build()
-        lldbutil.run_to_name_breakpoint(self, 'f')
+        lldbutil.run_to_name_breakpoint(self, "f")
         self.expect("list f", substrs=["This is inline source code"])
diff --git a/lldb/test/API/functionalities/process_save_core_minidump/TestProcessSaveCoreMinidump.py b/lldb/test/API/functionalities/process_save_core_minidump/TestProcessSaveCoreMinidump.py
@@ -11,9 +11,9 @@
 
 
 class ProcessSaveCoreMinidumpTestCase(TestBase):
-
-    def verify_core_file(self, core_path, expected_pid, expected_modules,
-                         expected_threads):
+    def verify_core_file(
+        self, core_path, expected_pid, expected_modules, expected_threads
+    ):
         # To verify, we'll launch with the mini dump
         target = self.dbg.CreateTarget(None)
         process = target.LoadCore(core_path)
@@ -77,50 +77,47 @@ def test_save_linux_mini_dump(self):
 
             # save core and, kill process and verify corefile existence
             base_command = "process save-core --plugin-name=minidump "
-            self.runCmd(
-                base_command + " --style=stack '%s'" % (core_stack)
-            )
+            self.runCmd(base_command + " --style=stack '%s'" % (core_stack))
             self.assertTrue(os.path.isfile(core_stack))
-            self.verify_core_file(core_stack, expected_pid, expected_modules,
-                                  expected_threads)
-
-            self.runCmd(
-                base_command + " --style=modified-memory '%s'" % (core_dirty)
+            self.verify_core_file(
+                core_stack, expected_pid, expected_modules, expected_threads
             )
-            self.assertTrue(os.path.isfile(core_dirty))
-            self.verify_core_file(core_dirty, expected_pid, expected_modules,
-                                  expected_threads)
 
-            self.runCmd(
-                base_command + " --style=full '%s'" % (core_full)
+            self.runCmd(base_command + " --style=modified-memory '%s'" % (core_dirty))
+            self.assertTrue(os.path.isfile(core_dirty))
+            self.verify_core_file(
+                core_dirty, expected_pid, expected_modules, expected_threads
             )
+
+            self.runCmd(base_command + " --style=full '%s'" % (core_full))
             self.assertTrue(os.path.isfile(core_full))
-            self.verify_core_file(core_full, expected_pid, expected_modules,
-                                  expected_threads)
+            self.verify_core_file(
+                core_full, expected_pid, expected_modules, expected_threads
+            )
 
             # validate saving via SBProcess
-            error = process.SaveCore(core_sb_stack, "minidump",
-                                     lldb.eSaveCoreStackOnly)
+            error = process.SaveCore(core_sb_stack, "minidump", lldb.eSaveCoreStackOnly)
             self.assertTrue(error.Success())
             self.assertTrue(os.path.isfile(core_sb_stack))
-            self.verify_core_file(core_sb_stack, expected_pid,
-                                  expected_modules, expected_threads)
+            self.verify_core_file(
+                core_sb_stack, expected_pid, expected_modules, expected_threads
+            )
 
-            error = process.SaveCore(core_sb_dirty, "minidump",
-                                     lldb.eSaveCoreDirtyOnly)
+            error = process.SaveCore(core_sb_dirty, "minidump", lldb.eSaveCoreDirtyOnly)
             self.assertTrue(error.Success())
             self.assertTrue(os.path.isfile(core_sb_dirty))
-            self.verify_core_file(core_sb_dirty, expected_pid, expected_modules,
-                                  expected_threads)
+            self.verify_core_file(
+                core_sb_dirty, expected_pid, expected_modules, expected_threads
+            )
 
             # Minidump can now save full core files, but they will be huge and
             # they might cause this test to timeout.
-            error = process.SaveCore(core_sb_full, "minidump",
-                                     lldb.eSaveCoreFull)
+            error = process.SaveCore(core_sb_full, "minidump", lldb.eSaveCoreFull)
             self.assertTrue(error.Success())
             self.assertTrue(os.path.isfile(core_sb_full))
-            self.verify_core_file(core_sb_full, expected_pid, expected_modules,
-                                  expected_threads)
+            self.verify_core_file(
+                core_sb_full, expected_pid, expected_modules, expected_threads
+            )
 
             self.assertSuccess(process.Kill())
         finally:

diff --git a/lldb/test/API/functionalities/type_find_first/TestFindFirstType.py b/lldb/test/API/functionalities/type_find_first/TestFindFirstType.py
@@ -8,18 +8,17 @@
 
 
 class TypeFindFirstTestCase(TestBase):
-
     NO_DEBUG_INFO_TESTCASE = True
 
     def test_find_first_type(self):
         """
-            Test SBTarget::FindFirstType() and SBModule::FindFirstType() APIs.
+        Test SBTarget::FindFirstType() and SBModule::FindFirstType() APIs.
 
-            This function had regressed after some past modification of the type
-            lookup internal code where if we had multiple types with the same
-            basename, FindFirstType() could end up failing depending on which
-            type was found first in the debug info indexes. This test will
-            ensure this doesn't regress in the future.
+        This function had regressed after some past modification of the type
+        lookup internal code where if we had multiple types with the same
+        basename, FindFirstType() could end up failing depending on which
+        type was found first in the debug info indexes. This test will
+        ensure this doesn't regress in the future.
         """
         self.build()
         target = self.createTestTarget()

diff --git a/lldb/test/API/functionalities/vtable/TestVTableValue.py b/lldb/test/API/functionalities/vtable/TestVTableValue.py
@@ -8,6 +8,7 @@
 from lldbsuite.test.decorators import *
 from lldbsuite.test.lldbtest import *
 
+
 class TestVTableValue(TestBase):
     # If your test case doesn't stress debug info, then
     # set this to true.  That way it won't be run once for
@@ -36,7 +37,7 @@ def test_vtable(self):
         expected_addr = self.expected_vtable_addr(shape)
         self.assertEquals(vtable_addr, expected_addr)
 
-        for (idx, vtable_entry) in enumerate(vtable.children):
+        for idx, vtable_entry in enumerate(vtable.children):
             self.verify_vtable_entry(vtable_entry, vtable_addr, idx)
 
         # Test a shape reference to make sure we get the vtable correctly.
@@ -53,10 +54,9 @@ def test_vtable(self):
         expected_addr = self.expected_vtable_addr(shape)
         self.assertEquals(vtable_addr, expected_addr)
 
-        for (idx, vtable_entry) in enumerate(vtable.children):
+        for idx, vtable_entry in enumerate(vtable.children):
             self.verify_vtable_entry(vtable_entry, vtable_addr, idx)
 
-
         # Test we get the right vtable for the Rectangle instance.
         rect = self.frame().FindVariable("rect")
         vtable = rect.GetVTable()
@@ -72,7 +72,7 @@ def test_vtable(self):
         expected_addr = self.expected_vtable_addr(rect)
         self.assertEquals(vtable_addr, expected_addr)
 
-        for (idx, vtable_entry) in enumerate(vtable.children):
+        for idx, vtable_entry in enumerate(vtable.children):
             self.verify_vtable_entry(vtable_entry, vtable_addr, idx)
 
     @skipIf(compiler="clang", compiler_version=["<", "9.0"])
@@ -90,13 +90,11 @@ def test_base_class_ptr(self):
         shape_ptr_vtable = shape_ptr.GetVTable()
         self.assertEquals(shape_ptr_vtable.GetName(), "vtable for Rectangle")
         self.assertEquals(shape_ptr_vtable.GetNumChildren(), 5)
-        self.assertEquals(shape_ptr.GetValueAsUnsigned(0),
-                          rect.GetLoadAddress())
+        self.assertEquals(shape_ptr.GetValueAsUnsigned(0), rect.GetLoadAddress())
         lldbutil.continue_to_source_breakpoint(
             self, process, "Shape is Shape", lldb.SBFileSpec("main.cpp")
         )
-        self.assertEquals(shape_ptr.GetValueAsUnsigned(0),
-                          shape.GetLoadAddress())
+        self.assertEquals(shape_ptr.GetValueAsUnsigned(0), shape.GetLoadAddress())
         self.assertEquals(shape_ptr_vtable.GetNumChildren(), 4)
         self.assertEquals(shape_ptr_vtable.GetName(), "vtable for Shape")
 
@@ -108,12 +106,16 @@ def test_no_vtable(self):
         )
 
         var = self.frame().FindVariable("not_virtual")
-        self.assertEqual(var.GetVTable().GetError().GetCString(),
-                         'type "NotVirtual" doesn\'t have a vtable')
+        self.assertEqual(
+            var.GetVTable().GetError().GetCString(),
+            'type "NotVirtual" doesn\'t have a vtable',
+        )
 
         var = self.frame().FindVariable("argc")
-        self.assertEqual(var.GetVTable().GetError().GetCString(),
-                         'no language runtime support for the language "c"')
+        self.assertEqual(
+            var.GetVTable().GetError().GetCString(),
+            'no language runtime support for the language "c"',
+        )
 
     @skipUnlessPlatform(["linux", "macosx"])
     def test_overwrite_vtable(self):
@@ -161,13 +163,15 @@ def expected_vtable_addr(self, var: lldb.SBValue) -> int:
     def expected_vtable_entry_func_ptr(self, vtable_addr: int, idx: int):
         vtable_entry_addr = vtable_addr + idx * self.process().GetAddressByteSize()
         read_func_ptr_error = lldb.SBError()
-        func_ptr = self.process().ReadPointerFromMemory(vtable_entry_addr,
-                                                        read_func_ptr_error)
+        func_ptr = self.process().ReadPointerFromMemory(
+            vtable_entry_addr, read_func_ptr_error
+        )
         self.assertTrue(read_func_ptr_error.Success())
         return func_ptr
 
-    def verify_vtable_entry(self, vtable_entry: lldb.SBValue, vtable_addr: int,
-                            idx: int):
+    def verify_vtable_entry(
+        self, vtable_entry: lldb.SBValue, vtable_addr: int, idx: int
+    ):
         """Verify the vtable entry looks something like:
 
         (double ()) [0] = 0x0000000100003a10 a.out`Rectangle::Area() at main.cpp:14
@@ -186,8 +190,7 @@ def verify_vtable_entry(self, vtable_entry: lldb.SBValue, vtable_addr: int,
         # Make sure the type is the same as the function type
         func_type = sym_ctx.GetFunction().GetType()
         if func_type.IsValid():
-            self.assertEquals(vtable_entry.GetType(),
-                              func_type.GetPointerType())
+            self.assertEquals(vtable_entry.GetType(), func_type.GetPointerType())
 
         # The summary should be the address description of the function pointer
         summary = vtable_entry.GetSummary()

diff --git a/lldb/test/API/lang/cpp/union-static-data-members/TestCppUnionStaticMembers.py b/lldb/test/API/lang/cpp/union-static-data-members/TestCppUnionStaticMembers.py
@@ -7,6 +7,7 @@
 from lldbsuite.test.decorators import *
 import lldbsuite.test.lldbutil as lldbutil
 
+
 class CppUnionStaticMembersTestCase(TestBase):
     def test_print_union(self):
         """Tests that frame variable and expr work
@@ -20,12 +21,16 @@ def test_print_union(self):
         self.expect("frame variable foo", substrs=["val = 42"])
         self.expect("frame variable bar", substrs=["val = 137"])
 
-        self.expect_expr("foo", result_type="Foo", result_children=[ValueCheck(
-                name="val", value="42"
-            )])
-        self.expect_expr("bar", result_type="Bar", result_children=[ValueCheck(
-                name="val", value="137"
-            )])
+        self.expect_expr(
+            "foo",
+            result_type="Foo",
+            result_children=[ValueCheck(name="val", value="42")],
+        )
+        self.expect_expr(
+            "bar",
+            result_type="Bar",
+            result_children=[ValueCheck(name="val", value="137")],
+        )
 
     @expectedFailureWindows
     def test_expr_union_static_members(self):
@@ -38,22 +43,26 @@ def test_expr_union_static_members(self):
         )
 
         self.expect_expr("Foo::sVal1", result_type="const int", result_value="-42")
-        self.expect_expr("Foo::sVal2", result_type="Foo", result_children=[ValueCheck(
-                name="val", value="42"
-            )])
+        self.expect_expr(
+            "Foo::sVal2",
+            result_type="Foo",
+            result_children=[ValueCheck(name="val", value="42")],
+        )
 
     @expectedFailureWindows
     def test_union_in_anon_namespace(self):
         """Tests that frame variable and expr work
-           for union static data members in anonymous
-           namespaces"""
+        for union static data members in anonymous
+        namespaces"""
         self.build()
 
         (target, process, main_thread, _) = lldbutil.run_to_source_breakpoint(
             self, "return 0", lldb.SBFileSpec("main.cpp")
         )
 
         self.expect_expr("Bar::sVal1", result_type="const int", result_value="-137")
-        self.expect_expr("Bar::sVal2", result_type="Bar", result_children=[ValueCheck(
-                name="val", value="137"
-            )])
+        self.expect_expr(
+            "Bar::sVal2",
+            result_type="Bar",
+            result_children=[ValueCheck(name="val", value="137")],
+        )
diff --git a/lldb/test/API/lang/cpp/unique-types4/TestUniqueTypes4.py b/lldb/test/API/lang/cpp/unique-types4/TestUniqueTypes4.py
@@ -17,27 +17,35 @@ def do_test(self, debug_flags):
         )
         # FIXME: these should successfully print the values
         self.expect(
-            "expression ns::Foo<double>::value", substrs=["'Foo' in namespace 'ns'"], error=True
+            "expression ns::Foo<double>::value",
+            substrs=["'Foo' in namespace 'ns'"],
+            error=True,
         )
         self.expect(
-            "expression ns::Foo<int>::value", substrs=["'Foo' in namespace 'ns'"], error=True
+            "expression ns::Foo<int>::value",
+            substrs=["'Foo' in namespace 'ns'"],
+            error=True,
         )
         self.expect(
-            "expression ns::Bar<double>::value", substrs=["'Bar' in namespace 'ns'"], error=True
+            "expression ns::Bar<double>::value",
+            substrs=["'Bar' in namespace 'ns'"],
+            error=True,
         )
         self.expect(
-            "expression ns::Bar<int>::value", substrs=["'Bar' in namespace 'ns'"], error=True
+            "expression ns::Bar<int>::value",
+            substrs=["'Bar' in namespace 'ns'"],
+            error=True,
         )
         self.expect_expr("ns::FooDouble::value", result_type="double", result_value="0")
         self.expect_expr("ns::FooInt::value", result_type="int", result_value="0")
 
-    @skipIfWindows # https://github.com/llvm/llvm-project/issues/75936
+    @skipIfWindows  # https://github.com/llvm/llvm-project/issues/75936
     @skipIf(compiler=no_match("clang"))
     @skipIf(compiler_version=["<", "15.0"])
     def test_simple_template_names(self):
         self.do_test(dict(CFLAGS_EXTRAS="-gsimple-template-names"))
 
-    @skipIfWindows # https://github.com/llvm/llvm-project/issues/75936
+    @skipIfWindows  # https://github.com/llvm/llvm-project/issues/75936
     @skipIf(compiler=no_match("clang"))
     @skipIf(compiler_version=["<", "15.0"])
     def test_no_simple_template_names(self):

diff --git a/lldb/test/API/lang/objc/charstar_dyntype/TestCharStarDynType.py b/lldb/test/API/lang/objc/charstar_dyntype/TestCharStarDynType.py
@@ -7,6 +7,7 @@
 from lldbsuite.test.lldbtest import *
 from lldbsuite.test import lldbutil
 
+
 class TestCaseCharStarDynType(TestBase):
     def setUp(self):
         # Call super's setUp().

diff --git a/lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py b/lldb/test/API/python_api/global_module_cache/TestGlobalModuleCache.py
@@ -12,6 +12,7 @@
 from pathlib import Path
 import time
 
+
 class GlobalModuleCacheTestCase(TestBase):
     # NO_DEBUG_INFO_TESTCASE = True
 
@@ -112,6 +113,7 @@ def do_test(self, one_target, one_debugger):
                 new_debugger = lldb.SBDebugger().Create()
                 self.old_debugger = self.dbg
                 self.dbg = new_debugger
+
                 def cleanupDebugger(self):
                     lldb.SBDebugger.Destroy(self.dbg)
                     self.dbg = self.old_debugger
@@ -143,7 +145,7 @@ def cleanupDebugger(self):
         fail_msg = ""
         if error != "":
             fail_msg = "Error before MPD: " + error
-            
+
         if error_after_mpd != "":
             fail_msg = fail_msg + "\nError after MPD: " + error_after_mpd
         if fail_msg != "":
@@ -172,11 +174,13 @@ def check_image_list_result(self, num_a_dot_out, num_main_dot_o):
                 found_a_dot_out += 1
             if "main.o" in line:
                 found_main_dot_o += 1
-        
+
         if num_a_dot_out != found_a_dot_out:
             return f"Got {found_a_dot_out} number of a.out's, expected {num_a_dot_out}"
-            
+
         if found_main_dot_o > 0 and num_main_dot_o != found_main_dot_o:
-            return f"Got {found_main_dot_o} number of main.o's, expected {num_main_dot_o}"
+            return (
+                f"Got {found_main_dot_o} number of main.o's, expected {num_main_dot_o}"
+            )
 
         return ""
diff --git a/lldb/test/API/python_api/process/cancel_attach/TestCancelAttach.py b/lldb/test/API/python_api/process/cancel_attach/TestCancelAttach.py
@@ -28,10 +28,12 @@ def __init__(self, target, error):
                 threading.Thread.__init__(self, daemon=True)
                 self.target = target
                 self.error = error
-                
+
             def run(self):
-                self.target.AttachToProcessWithName(lldb.SBListener(), "LLDB-No-Such-Process", True, self.error)
-
+                self.target.AttachToProcessWithName(
+                    lldb.SBListener(), "LLDB-No-Such-Process", True, self.error
+                )
+
         error = lldb.SBError()
         thread = AttachThread(target, error)
         thread.start()
@@ -50,8 +52,7 @@ def run(self):
         # We don't want to stall if we can't interrupt, so join with a timeout:
         thread.join(60)
         if thread.is_alive():
-          self.fail("The attach thread is alive after timeout interval")
+            self.fail("The attach thread is alive after timeout interval")
 
         # Now check the error, should say the attach was interrupted:
         self.assertTrue(error.Fail(), "We succeeded in not attaching")
-
diff --git a/lldb/test/API/python_api/value/TestValueAPI.py b/lldb/test/API/python_api/value/TestValueAPI.py
@@ -212,7 +212,9 @@ def test(self):
             frame0.FindVariable("fixed_int_ptr").GetValue(),
             "0x000000aa" if target.addr_size == 4 else "0x00000000000000aa",
         )
-        self.runCmd("settings set target.show-hex-variable-values-with-leading-zeroes false")
+        self.runCmd(
+            "settings set target.show-hex-variable-values-with-leading-zeroes false"
+        )
         self.assertEqual(
             frame0.FindVariable("another_fixed_int_ptr").GetValue(),
             "0xaa",

diff --git a/lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_logpoints.py b/lldb/test/API/tools/lldb-dap/breakpoint/TestDAP_logpoints.py
@@ -77,7 +77,9 @@ def test_logmessage_basic(self):
         # Verify log message match
         for idx, logMessage_line in enumerate(logMessage_output):
             result = idx + 3
-            reg_str = f"{logMessage_prefix}{result}, {message_addr_pattern} {message_content}"
+            reg_str = (
+                f"{logMessage_prefix}{result}, {message_addr_pattern} {message_content}"
+            )
             self.assertRegex(logMessage_line, reg_str)
 
     @skipIfWindows

diff --git a/llvm/docs/CommandGuide/llvm-objcopy.rst b/llvm/docs/CommandGuide/llvm-objcopy.rst
@@ -543,6 +543,10 @@ options. For GNU :program:`objcopy` compatibility, the values are all bfdnames.
 - `elf64-tradlittlemips`
 - `elf32-sparc`
 - `elf32-sparcel`
+- `elf32-hexagon`
+- `elf32-loongarch`
+- `elf64-loongarch`
+- `elf64-s390`
 
 The following formats are suppoprted by :program:`llvm-objcopy` for the
 :option:`--output-target` only:

diff --git a/llvm/docs/NVPTXUsage.rst b/llvm/docs/NVPTXUsage.rst
@@ -53,15 +53,15 @@ function ``@my_kernel`` is callable from host code, but ``@my_fmad`` is not.
       ret float %add
     }
 
-    define void @my_kernel(float* %ptr) {
-      %val = load float, float* %ptr
+    define void @my_kernel(ptr %ptr) {
+      %val = load float, ptr %ptr
       %ret = call float @my_fmad(float %val, float %val, float %val)
-      store float %ret, float* %ptr
+      store float %ret, ptr %ptr
       ret void
     }
 
     !nvvm.annotations = !{!1}
-    !1 = !{void (float*)* @my_kernel, !"kernel", i32 1}
+    !1 = !{ptr @my_kernel, !"kernel", i32 1}
 
 When compiled, the PTX kernel functions are callable by host-side code.
 
@@ -140,10 +140,10 @@ These are overloaded intrinsics.  You can use these on any pointer types.
 
 .. code-block:: llvm
 
-    declare i8* @llvm.nvvm.ptr.global.to.gen.p0i8.p1i8(i8 addrspace(1)*)
-    declare i8* @llvm.nvvm.ptr.shared.to.gen.p0i8.p3i8(i8 addrspace(3)*)
-    declare i8* @llvm.nvvm.ptr.constant.to.gen.p0i8.p4i8(i8 addrspace(4)*)
-    declare i8* @llvm.nvvm.ptr.local.to.gen.p0i8.p5i8(i8 addrspace(5)*)
+    declare ptr @llvm.nvvm.ptr.global.to.gen.p0.p1(ptr addrspace(1))
+    declare ptr @llvm.nvvm.ptr.shared.to.gen.p0.p3(ptr addrspace(3))
+    declare ptr @llvm.nvvm.ptr.constant.to.gen.p0.p4(ptr addrspace(4))
+    declare ptr @llvm.nvvm.ptr.local.to.gen.p0.p5(ptr addrspace(5))
 
 Overview:
 """""""""
@@ -168,10 +168,10 @@ These are overloaded intrinsics.  You can use these on any pointer types.
 
 .. code-block:: llvm
 
-    declare i8 addrspace(1)* @llvm.nvvm.ptr.gen.to.global.p1i8.p0i8(i8*)
-    declare i8 addrspace(3)* @llvm.nvvm.ptr.gen.to.shared.p3i8.p0i8(i8*)
-    declare i8 addrspace(4)* @llvm.nvvm.ptr.gen.to.constant.p4i8.p0i8(i8*)
-    declare i8 addrspace(5)* @llvm.nvvm.ptr.gen.to.local.p5i8.p0i8(i8*)
+    declare ptr addrspace(1) @llvm.nvvm.ptr.gen.to.global.p1.p0(ptr)
+    declare ptr addrspace(3) @llvm.nvvm.ptr.gen.to.shared.p3.p0(ptr)
+    declare ptr addrspace(4) @llvm.nvvm.ptr.gen.to.constant.p4.p0(ptr)
+    declare ptr addrspace(5) @llvm.nvvm.ptr.gen.to.local.p5.p0(ptr)
 
 Overview:
 """""""""
@@ -436,35 +436,33 @@ The Kernel
   ; Intrinsic to read X component of thread ID
   declare i32 @llvm.nvvm.read.ptx.sreg.tid.x() readnone nounwind
 
-  define void @kernel(float addrspace(1)* %A,
-                      float addrspace(1)* %B,
-                      float addrspace(1)* %C) {
+  define void @kernel(ptr addrspace(1) %A,
+                      ptr addrspace(1) %B,
+                      ptr addrspace(1) %C) {
   entry:
     ; What is my ID?
     %id = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x() readnone nounwind
 
     ; Compute pointers into A, B, and C
-    %ptrA = getelementptr float, float addrspace(1)* %A, i32 %id
-    %ptrB = getelementptr float, float addrspace(1)* %B, i32 %id
-    %ptrC = getelementptr float, float addrspace(1)* %C, i32 %id
+    %ptrA = getelementptr float, ptr addrspace(1) %A, i32 %id
+    %ptrB = getelementptr float, ptr addrspace(1) %B, i32 %id
+    %ptrC = getelementptr float, ptr addrspace(1) %C, i32 %id
 
     ; Read A, B
-    %valA = load float, float addrspace(1)* %ptrA, align 4
-    %valB = load float, float addrspace(1)* %ptrB, align 4
+    %valA = load float, ptr addrspace(1) %ptrA, align 4
+    %valB = load float, ptr addrspace(1) %ptrB, align 4
 
     ; Compute C = A + B
     %valC = fadd float %valA, %valB
 
     ; Store back to C
-    store float %valC, float addrspace(1)* %ptrC, align 4
+    store float %valC, ptr addrspace(1) %ptrC, align 4
 
     ret void
   }
 
   !nvvm.annotations = !{!0}
-  !0 = !{void (float addrspace(1)*,
-               float addrspace(1)*,
-               float addrspace(1)*)* @kernel, !"kernel", i32 1}
+  !0 = !{ptr @kernel, !"kernel", i32 1}
 
 
 We can use the LLVM ``llc`` tool to directly run the NVPTX code generator:
@@ -613,9 +611,7 @@ For the previous example, we have:
 .. code-block:: llvm
 
   !nvvm.annotations = !{!0}
-  !0 = !{void (float addrspace(1)*,
-               float addrspace(1)*,
-               float addrspace(1)*)* @kernel, !"kernel", i32 1}
+  !0 = !{ptr @kernel, !"kernel", i32 1}
 
 Here, we have a single metadata declaration in ``nvvm.annotations``. This
 metadata annotates our ``@kernel`` function with the ``kernel`` attribute.
@@ -820,35 +816,33 @@ Libdevice provides an ``__nv_powf`` function that we will use.
   ; libdevice function
   declare float @__nv_powf(float, float)
 
-  define void @kernel(float addrspace(1)* %A,
-                      float addrspace(1)* %B,
-                      float addrspace(1)* %C) {
+  define void @kernel(ptr addrspace(1) %A,
+                      ptr addrspace(1) %B,
+                      ptr addrspace(1) %C) {
   entry:
     ; What is my ID?
     %id = tail call i32 @llvm.nvvm.read.ptx.sreg.tid.x() readnone nounwind
 
     ; Compute pointers into A, B, and C
-    %ptrA = getelementptr float, float addrspace(1)* %A, i32 %id
-    %ptrB = getelementptr float, float addrspace(1)* %B, i32 %id
-    %ptrC = getelementptr float, float addrspace(1)* %C, i32 %id
+    %ptrA = getelementptr float, ptr addrspace(1) %A, i32 %id
+    %ptrB = getelementptr float, ptr addrspace(1) %B, i32 %id
+    %ptrC = getelementptr float, ptr addrspace(1) %C, i32 %id
 
     ; Read A, B
-    %valA = load float, float addrspace(1)* %ptrA, align 4
-    %valB = load float, float addrspace(1)* %ptrB, align 4
+    %valA = load float, ptr addrspace(1) %ptrA, align 4
+    %valB = load float, ptr addrspace(1) %ptrB, align 4
 
     ; Compute C = pow(A, B)
     %valC = call float @__nv_powf(float %valA, float %valB)
 
     ; Store back to C
-    store float %valC, float addrspace(1)* %ptrC, align 4
+    store float %valC, ptr addrspace(1) %ptrC, align 4
 
     ret void
   }
 
   !nvvm.annotations = !{!0}
-  !0 = !{void (float addrspace(1)*,
-               float addrspace(1)*,
-               float addrspace(1)*)* @kernel, !"kernel", i32 1}
+  !0 = !{ptr @kernel, !"kernel", i32 1}
 
 
 To compile this kernel, we perform the following steps:

diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst
@@ -250,7 +250,7 @@ The primary goal of experimental support is to assist in the process of ratifica
   LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1>`_.
 
 ``experimental-zabha``
-  LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-zabha/tree/v1.0-rc1>`__.
+  LLVM implements the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-zabha/tree/v1.0-rc1>`__.
 
 ``experimental-zacas``
   LLVM implements the `1.0-rc1 draft specification <https://github.com/riscv/riscv-zacas/releases/tag/v1.0-rc1>`__.

diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst
@@ -94,7 +94,7 @@ Changes to the PowerPC Backend
 Changes to the RISC-V Backend
 -----------------------------
 
-* Added assembler/disassembler support for the experimental Zabha (Byte and
+* Added full support for the experimental Zabha (Byte and
   Halfword Atomic Memory Operations) extension.
 * Added assembler/disassembler support for the experimenatl Zalasr
   (Load-Acquire and Store-Release) extension.
@@ -136,6 +136,12 @@ Changes to the Debug Info
 
 Changes to the LLVM tools
 ---------------------------------
+* llvm-nm and llvm-objdump can now print symbol information from linked
+  WebAssembly binaries, using information from exports or the "name"
+  section for functions, globals and data segments. Symbol addresses and sizes
+  are printed as offsets in the file, allowing for binary size analysis. Wasm
+  files using reference types and GC are also supported (but also only for
+  functions, globals, and data, and only for listing symbols and names).
 
 Changes to LLDB
 ---------------------------------

diff --git a/llvm/docs/_themes/llvm-theme/static/llvm-theme.css b/llvm/docs/_themes/llvm-theme/static/llvm-theme.css
@@ -26,6 +26,7 @@ body {
     border: 1px solid #aaa;
     margin: 0px 80px 0px 80px;
     min-width: 740px;
+    position: relative;
 }
 
 div.logo {
@@ -94,9 +95,11 @@ div.sphinxsidebar {
     margin: 0;
     padding: 0.5em 15px 15px 0;
     width: 210px;
-    float: right;
     font-size: 1em;
     text-align: left;
+    float: none;
+    position: absolute;
+    right: 0;
 }
 
 div.sphinxsidebar h3, div.sphinxsidebar h4 {

diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -48,6 +48,7 @@
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
+#include "llvm/Transforms/Utils/LoopUtils.h"
 #include <algorithm>
 #include <cassert>
 #include <cstdint>
@@ -2013,50 +2014,27 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
                                             CostKind);
     }
     case Intrinsic::vector_reduce_add:
-      return thisT()->getArithmeticReductionCost(Instruction::Add, VecOpTy,
-                                                 std::nullopt, CostKind);
     case Intrinsic::vector_reduce_mul:
-      return thisT()->getArithmeticReductionCost(Instruction::Mul, VecOpTy,
-                                                 std::nullopt, CostKind);
     case Intrinsic::vector_reduce_and:
-      return thisT()->getArithmeticReductionCost(Instruction::And, VecOpTy,
-                                                 std::nullopt, CostKind);
     case Intrinsic::vector_reduce_or:
-      return thisT()->getArithmeticReductionCost(Instruction::Or, VecOpTy,
-                                                 std::nullopt, CostKind);
     case Intrinsic::vector_reduce_xor:
-      return thisT()->getArithmeticReductionCost(Instruction::Xor, VecOpTy,
-                                                 std::nullopt, CostKind);
+      return thisT()->getArithmeticReductionCost(
+          getArithmeticReductionInstruction(IID), VecOpTy, std::nullopt,
+          CostKind);
     case Intrinsic::vector_reduce_fadd:
-      return thisT()->getArithmeticReductionCost(Instruction::FAdd, VecOpTy,
-                                                 FMF, CostKind);
     case Intrinsic::vector_reduce_fmul:
-      return thisT()->getArithmeticReductionCost(Instruction::FMul, VecOpTy,
-                                                 FMF, CostKind);
+      return thisT()->getArithmeticReductionCost(
+          getArithmeticReductionInstruction(IID), VecOpTy, FMF, CostKind);
     case Intrinsic::vector_reduce_smax:
-      return thisT()->getMinMaxReductionCost(Intrinsic::smax, VecOpTy,
-                                             ICA.getFlags(), CostKind);
     case Intrinsic::vector_reduce_smin:
-      return thisT()->getMinMaxReductionCost(Intrinsic::smin, VecOpTy,
-                                             ICA.getFlags(), CostKind);
     case Intrinsic::vector_reduce_umax:
-      return thisT()->getMinMaxReductionCost(Intrinsic::umax, VecOpTy,
-                                             ICA.getFlags(), CostKind);
     case Intrinsic::vector_reduce_umin:
-      return thisT()->getMinMaxReductionCost(Intrinsic::umin, VecOpTy,
-                                             ICA.getFlags(), CostKind);
     case Intrinsic::vector_reduce_fmax:
-      return thisT()->getMinMaxReductionCost(Intrinsic::maxnum, VecOpTy,
-                                             ICA.getFlags(), CostKind);
     case Intrinsic::vector_reduce_fmin:
-      return thisT()->getMinMaxReductionCost(Intrinsic::minnum, VecOpTy,
-                                             ICA.getFlags(), CostKind);
     case Intrinsic::vector_reduce_fmaximum:
-      return thisT()->getMinMaxReductionCost(Intrinsic::maximum, VecOpTy,
-                                             ICA.getFlags(), CostKind);
     case Intrinsic::vector_reduce_fminimum:
-      return thisT()->getMinMaxReductionCost(Intrinsic::minimum, VecOpTy,
-                                             ICA.getFlags(), CostKind);
+      return thisT()->getMinMaxReductionCost(getMinMaxReductionIntrinsicOp(IID),
+                                             VecOpTy, ICA.getFlags(), CostKind);
     case Intrinsic::abs: {
       // abs(X) = select(icmp(X,0),X,sub(0,X))
       Type *CondTy = RetTy->getWithNewBitWidth(1);

diff --git a/llvm/include/llvm/Transforms/Utils/LoopUtils.h b/llvm/include/llvm/Transforms/Utils/LoopUtils.h
@@ -357,9 +357,18 @@ bool canSinkOrHoistInst(Instruction &I, AAResults *AA, DominatorTree *DT,
                         SinkAndHoistLICMFlags &LICMFlags,
                         OptimizationRemarkEmitter *ORE = nullptr);
 
+/// Returns the arithmetic instruction opcode used when expanding a reduction.
+unsigned getArithmeticReductionInstruction(Intrinsic::ID RdxID);
+
+/// Returns the min/max intrinsic used when expanding a min/max reduction.
+Intrinsic::ID getMinMaxReductionIntrinsicOp(Intrinsic::ID RdxID);
+
 /// Returns the min/max intrinsic used when expanding a min/max reduction.
 Intrinsic::ID getMinMaxReductionIntrinsicOp(RecurKind RK);
 
+/// Returns the recurence kind used when expanding a min/max reduction.
+RecurKind getMinMaxReductionRecurKind(Intrinsic::ID RdxID);
+
 /// Returns the comparison predicate used when expanding a min/max reduction.
 CmpInst::Predicate getMinMaxReductionPredicate(RecurKind RK);
 

diff --git a/llvm/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp b/llvm/lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp
@@ -224,12 +224,15 @@ bool DebugHandlerBase::isUnsignedDIType(const DIType *Ty) {
           Encoding == dwarf::DW_ATE_float || Encoding == dwarf::DW_ATE_UTF ||
           Encoding == dwarf::DW_ATE_boolean ||
           Encoding == dwarf::DW_ATE_complex_float ||
+          Encoding == dwarf::DW_ATE_signed_fixed ||
+          Encoding == dwarf::DW_ATE_unsigned_fixed ||
           (Ty->getTag() == dwarf::DW_TAG_unspecified_type &&
            Ty->getName() == "decltype(nullptr)")) &&
          "Unsupported encoding");
   return Encoding == dwarf::DW_ATE_unsigned ||
          Encoding == dwarf::DW_ATE_unsigned_char ||
          Encoding == dwarf::DW_ATE_UTF || Encoding == dwarf::DW_ATE_boolean ||
+         Encoding == llvm::dwarf::DW_ATE_unsigned_fixed ||
          Ty->getTag() == dwarf::DW_TAG_unspecified_type;
 }
 

diff --git a/llvm/lib/CodeGen/ExpandReductions.cpp b/llvm/lib/CodeGen/ExpandReductions.cpp
@@ -26,54 +26,6 @@ using namespace llvm;
 
 namespace {
 
-unsigned getOpcode(Intrinsic::ID ID) {
-  switch (ID) {
-  case Intrinsic::vector_reduce_fadd:
-    return Instruction::FAdd;
-  case Intrinsic::vector_reduce_fmul:
-    return Instruction::FMul;
-  case Intrinsic::vector_reduce_add:
-    return Instruction::Add;
-  case Intrinsic::vector_reduce_mul:
-    return Instruction::Mul;
-  case Intrinsic::vector_reduce_and:
-    return Instruction::And;
-  case Intrinsic::vector_reduce_or:
-    return Instruction::Or;
-  case Intrinsic::vector_reduce_xor:
-    return Instruction::Xor;
-  case Intrinsic::vector_reduce_smax:
-  case Intrinsic::vector_reduce_smin:
-  case Intrinsic::vector_reduce_umax:
-  case Intrinsic::vector_reduce_umin:
-    return Instruction::ICmp;
-  case Intrinsic::vector_reduce_fmax:
-  case Intrinsic::vector_reduce_fmin:
-    return Instruction::FCmp;
-  default:
-    llvm_unreachable("Unexpected ID");
-  }
-}
-
-RecurKind getRK(Intrinsic::ID ID) {
-  switch (ID) {
-  case Intrinsic::vector_reduce_smax:
-    return RecurKind::SMax;
-  case Intrinsic::vector_reduce_smin:
-    return RecurKind::SMin;
-  case Intrinsic::vector_reduce_umax:
-    return RecurKind::UMax;
-  case Intrinsic::vector_reduce_umin:
-    return RecurKind::UMin;
-  case Intrinsic::vector_reduce_fmax:
-    return RecurKind::FMax;
-  case Intrinsic::vector_reduce_fmin:
-    return RecurKind::FMin;
-  default:
-    return RecurKind::None;
-  }
-}
-
 bool expandReductions(Function &F, const TargetTransformInfo *TTI) {
   bool Changed = false;
   SmallVector<IntrinsicInst *, 4> Worklist;
@@ -106,7 +58,7 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI) {
     FastMathFlags FMF =
         isa<FPMathOperator>(II) ? II->getFastMathFlags() : FastMathFlags{};
     Intrinsic::ID ID = II->getIntrinsicID();
-    RecurKind RK = getRK(ID);
+    RecurKind RK = getMinMaxReductionRecurKind(ID);
 
     Value *Rdx = nullptr;
     IRBuilder<> Builder(II);
@@ -120,16 +72,16 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI) {
       // and it can't be handled by generating a shuffle sequence.
       Value *Acc = II->getArgOperand(0);
       Value *Vec = II->getArgOperand(1);
+      unsigned RdxOpcode = getArithmeticReductionInstruction(ID);
       if (!FMF.allowReassoc())
-        Rdx = getOrderedReduction(Builder, Acc, Vec, getOpcode(ID), RK);
+        Rdx = getOrderedReduction(Builder, Acc, Vec, RdxOpcode, RK);
       else {
         if (!isPowerOf2_32(
                 cast<FixedVectorType>(Vec->getType())->getNumElements()))
           continue;
-
-        Rdx = getShuffleReduction(Builder, Vec, getOpcode(ID), RK);
-        Rdx = Builder.CreateBinOp((Instruction::BinaryOps)getOpcode(ID),
-                                  Acc, Rdx, "bin.rdx");
+        Rdx = getShuffleReduction(Builder, Vec, RdxOpcode, RK);
+        Rdx = Builder.CreateBinOp((Instruction::BinaryOps)RdxOpcode, Acc, Rdx,
+                                  "bin.rdx");
       }
       break;
     }
@@ -159,8 +111,8 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI) {
         }
         break;
       }
-
-      Rdx = getShuffleReduction(Builder, Vec, getOpcode(ID), RK);
+      unsigned RdxOpcode = getArithmeticReductionInstruction(ID);
+      Rdx = getShuffleReduction(Builder, Vec, RdxOpcode, RK);
       break;
     }
     case Intrinsic::vector_reduce_add:
@@ -174,8 +126,8 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI) {
       if (!isPowerOf2_32(
               cast<FixedVectorType>(Vec->getType())->getNumElements()))
         continue;
-
-      Rdx = getShuffleReduction(Builder, Vec, getOpcode(ID), RK);
+      unsigned RdxOpcode = getArithmeticReductionInstruction(ID);
+      Rdx = getShuffleReduction(Builder, Vec, RdxOpcode, RK);
       break;
     }
     case Intrinsic::vector_reduce_fmax:
@@ -187,8 +139,8 @@ bool expandReductions(Function &F, const TargetTransformInfo *TTI) {
               cast<FixedVectorType>(Vec->getType())->getNumElements()) ||
           !FMF.noNaNs())
         continue;
-
-      Rdx = getShuffleReduction(Builder, Vec, getOpcode(ID), RK);
+      unsigned RdxOpcode = getArithmeticReductionInstruction(ID);
+      Rdx = getShuffleReduction(Builder, Vec, RdxOpcode, RK);
       break;
     }
     }

diff --git a/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp b/llvm/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -403,13 +403,16 @@ static unsigned getFixedObjectSize(const MachineFunction &MF,
   if (!IsWin64 || IsFunclet) {
     return AFI->getTailCallReservedStack();
   } else {
-    if (AFI->getTailCallReservedStack() != 0)
+    if (AFI->getTailCallReservedStack() != 0 &&
+        !MF.getFunction().getAttributes().hasAttrSomewhere(
+            Attribute::SwiftAsync))
       report_fatal_error("cannot generate ABI-changing tail call for Win64");
     // Var args are stored here in the primary function.
     const unsigned VarArgsArea = AFI->getVarArgsGPRSize();
     // To support EH funclets we allocate an UnwindHelp object
     const unsigned UnwindHelpObject = (MF.hasEHFunclets() ? 8 : 0);
-    return alignTo(VarArgsArea + UnwindHelpObject, 16);
+    return AFI->getTailCallReservedStack() +
+           alignTo(VarArgsArea + UnwindHelpObject, 16);
   }
 }
 

diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h
@@ -363,6 +363,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
     case CallingConv::C:
     case CallingConv::Fast:
     case CallingConv::Swift:
+    case CallingConv::SwiftTail:
       return isTargetWindows();
     case CallingConv::Win64:
       return true;

diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -527,16 +527,16 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
     let ssamp = 0 in {
       if op.HAS_GFX10M then {
         def _V1 : MIMG_NoSampler_Helper <op, asm, dst_rc, VGPR_32,
-                                         !if(enableDisasm, "AMDGPU", "")>;
+                                         !if(enableDisasm, "GFX10", "")>;
         if !not(ExtendedImageInst) then
         def _V1_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VGPR_32,
                                        !if(enableDisasm, "GFX90A", "")>;
         def _V1_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VGPR_32,
-                                             !if(enableDisasm, "AMDGPU", "")>;
+                                             !if(enableDisasm, "GFX10", "")>;
       }
       if op.HAS_GFX11 then {
         def _V1_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VGPR_32,
-                                             !if(enableDisasm, "AMDGPU", "")>;
+                                             !if(enableDisasm, "GFX11", "")>;
       }
     }
     if op.HAS_GFX12 then {
@@ -606,12 +606,12 @@ multiclass MIMG_NoSampler_Src_Helper <mimgopc op, string asm,
         def _V4_gfx90a : MIMG_NoSampler_Helper_gfx90a <op, asm, dst_rc, VReg_128>;
         def _V4_gfx10 : MIMG_NoSampler_gfx10<op, asm, dst_rc, VReg_128>;
         def _V4_nsa_gfx10 : MIMG_NoSampler_nsa_gfx10<op, asm, dst_rc, 4,
-                                                     !if(enableDisasm, "AMDGPU", "")>;
+                                                     !if(enableDisasm, "GFX10", "")>;
       }
       if op.HAS_GFX11 then {
         def _V4_gfx11 : MIMG_NoSampler_gfx11<op, asm, dst_rc, VReg_128>;
         def _V4_nsa_gfx11 : MIMG_NoSampler_nsa_gfx11<op, asm, dst_rc, 4,
-                                                     !if(enableDisasm, "AMDGPU", "")>;
+                                                     !if(enableDisasm, "GFX11", "")>;
       }
     }
     if op.HAS_GFX12 then {
@@ -754,16 +754,16 @@ multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm,
       let ssamp = 0 in {
         if op.HAS_GFX10M then {
           def _V1 : MIMG_Store_Helper <op, asm, data_rc, VGPR_32,
-                                      !if(enableDisasm, "AMDGPU", "")>;
+                                      !if(enableDisasm, "GFX10", "")>;
           let hasPostISelHook = 1 in
           def _V1_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VGPR_32,
                                       !if(enableDisasm, "GFX90A", "")>;
           def _V1_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VGPR_32,
-                                            !if(enableDisasm, "AMDGPU", "")>;
+                                            !if(enableDisasm, "GFX10", "")>;
         }
         if op.HAS_GFX11 then {
           def _V1_gfx11 : MIMG_Store_gfx11 <op, asm, data_rc, VGPR_32,
-                                            !if(enableDisasm, "AMDGPU", "")>;
+                                            !if(enableDisasm, "GFX11", "")>;
         }
       }
       if op.HAS_GFX12 then {
@@ -812,12 +812,12 @@ multiclass MIMG_Store_Addr_Helper <mimgopc op, string asm,
           def _V4_gfx90a : MIMG_Store_Helper_gfx90a <op, asm, data_rc, VReg_128>;
           def _V4_gfx10 : MIMG_Store_gfx10 <op, asm, data_rc, VReg_128>;
           def _V4_nsa_gfx10 : MIMG_Store_nsa_gfx10 <op, asm, data_rc, 4,
-                                                          !if(enableDisasm, "AMDGPU", "")>;
+                                                          !if(enableDisasm, "GFX10", "")>;
         }
         if op.HAS_GFX11 then {
           def _V4_gfx11 : MIMG_Store_gfx11 <op, asm, data_rc, VReg_128>;
           def _V4_nsa_gfx11 : MIMG_Store_nsa_gfx11 <op, asm, data_rc, 4,
-                                                          !if(enableDisasm, "AMDGPU", "")>;
+                                                          !if(enableDisasm, "GFX11", "")>;
         }
       }
       if op.HAS_GFX12 then {
@@ -897,7 +897,7 @@ class MIMG_Atomic_gfx10<mimgopc op, string opcode,
                         RegisterClass DataRC, RegisterClass AddrRC,
                         bit enableDisasm = 0>
   : MIMG_gfx10<!cast<int>(op.GFX10M), (outs DataRC:$vdst),
-               !if(enableDisasm, "AMDGPU", "")> {
+               !if(enableDisasm, "GFX10", "")> {
   let Constraints = "$vdst = $vdata";
 
   let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
@@ -910,7 +910,7 @@ class MIMG_Atomic_nsa_gfx10<mimgopc op, string opcode,
                             RegisterClass DataRC, int num_addrs,
                             bit enableDisasm = 0>
   : MIMG_nsa_gfx10<!cast<int>(op.GFX10M), (outs DataRC:$vdst), num_addrs,
-                   !if(enableDisasm, "AMDGPU", "")> {
+                   !if(enableDisasm, "GFX10", "")> {
   let Constraints = "$vdst = $vdata";
 
   let InOperandList = !con((ins DataRC:$vdata),
@@ -925,7 +925,7 @@ class MIMG_Atomic_gfx11<mimgopc op, string opcode,
                         RegisterClass DataRC, RegisterClass AddrRC,
                         bit enableDisasm = 0>
   : MIMG_gfx11<!cast<int>(op.GFX11), (outs DataRC:$vdst),
-               !if(enableDisasm, "AMDGPU", "")> {
+               !if(enableDisasm, "GFX11", "")> {
   let Constraints = "$vdst = $vdata";
 
   let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
@@ -938,7 +938,7 @@ class MIMG_Atomic_nsa_gfx11<mimgopc op, string opcode,
                             RegisterClass DataRC, int num_addrs,
                             bit enableDisasm = 0>
   : MIMG_nsa_gfx11<!cast<int>(op.GFX11), (outs DataRC:$vdst), num_addrs,
-                   !if(enableDisasm, "AMDGPU", "")> {
+                   !if(enableDisasm, "GFX11", "")> {
   let Constraints = "$vdst = $vdata";
 
   let InOperandList = !con((ins DataRC:$vdata),
@@ -1298,19 +1298,19 @@ multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm,
       if op.HAS_GFX10M then {
         def _V # addr.NumWords
           : MIMG_Sampler_Helper <op, asm, dst_rc, addr.RegClass,
-                                 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
+                                 !if(!and(enableDisasm, addr.Disassemble), "GFX10", "")>;
         if !not(ExtendedImageInst) then
         def _V # addr.NumWords # _gfx90a
           : MIMG_Sampler_gfx90a <op, asm, dst_rc, addr.RegClass,
                                  !if(!and(enableDisasm, addr.Disassemble), "GFX90A", "")>;
         def _V # addr.NumWords # _gfx10
           : MIMG_Sampler_gfx10 <op, asm, dst_rc, addr.RegClass,
-                                 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
+                                 !if(!and(enableDisasm, addr.Disassemble), "GFX10", "")>;
       }
       if op.HAS_GFX11 then {
         def _V # addr.NumWords # _gfx11
           : MIMG_Sampler_gfx11 <op, asm, dst_rc, addr.RegClass,
-                                 !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
+                                 !if(!and(enableDisasm, addr.Disassemble), "GFX11", "")>;
       }
     }
   }
@@ -1320,7 +1320,7 @@ multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm,
       if op.HAS_GFX10M then {
         def _V # addr.NumWords # _nsa_gfx10
           : MIMG_Sampler_nsa_gfx10<op, asm, dst_rc, addr.NumWords,
-                                   !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
+                                   !if(!and(enableDisasm, addr.Disassemble), "GFX10", "")>;
       }
     }
   }
@@ -1330,7 +1330,7 @@ multiclass MIMG_Sampler_Src_Helper <mimgopc op, string asm,
       if op.HAS_GFX11 then {
         def _V # addr.NumWords # _nsa_gfx11
           : MIMG_Sampler_nsa_gfx11<op, asm, dst_rc, addr.NumWords, addr.RegClass,
-                                   !if(!and(enableDisasm, addr.Disassemble), "AMDGPU", "")>;
+                                   !if(!and(enableDisasm, addr.Disassemble), "GFX11", "")>;
       }
     }
   }
@@ -1416,21 +1416,21 @@ class MIMG_IntersectRay_Helper<bit Is64, bit IsA16> {
 }
 
 class MIMG_IntersectRay_gfx10<mimgopc op, string opcode, RegisterClass AddrRC>
-    : MIMG_gfx10<op.GFX10M, (outs VReg_128:$vdata), "AMDGPU"> {
+    : MIMG_gfx10<op.GFX10M, (outs VReg_128:$vdata), "GFX10"> {
   let InOperandList = (ins AddrRC:$vaddr0, SReg_128:$srsrc, A16:$a16);
   let AsmString = opcode#" $vdata, $vaddr0, $srsrc$a16";
 
   let nsa = 0;
 }
 
 class MIMG_IntersectRay_nsa_gfx10<mimgopc op, string opcode, int num_addrs>
-    : MIMG_nsa_gfx10<op.GFX10M, (outs VReg_128:$vdata), num_addrs, "AMDGPU"> {
+    : MIMG_nsa_gfx10<op.GFX10M, (outs VReg_128:$vdata), num_addrs, "GFX10"> {
   let InOperandList = !con(nsah.AddrIns, (ins SReg_128:$srsrc, A16:$a16));
   let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc$a16";
 }
 
 class MIMG_IntersectRay_gfx11<mimgopc op, string opcode, RegisterClass AddrRC>
-    : MIMG_gfx11<op.GFX11, (outs VReg_128:$vdata), "AMDGPU"> {
+    : MIMG_gfx11<op.GFX11, (outs VReg_128:$vdata), "GFX11"> {
   let InOperandList = (ins AddrRC:$vaddr0, SReg_128:$srsrc, A16:$a16);
   let AsmString = opcode#" $vdata, $vaddr0, $srsrc$a16";
 
@@ -1439,7 +1439,7 @@ class MIMG_IntersectRay_gfx11<mimgopc op, string opcode, RegisterClass AddrRC>
 
 class MIMG_IntersectRay_nsa_gfx11<mimgopc op, string opcode, int num_addrs,
                                   list<RegisterClass> addr_types>
-    : MIMG_nsa_gfx11<op.GFX11, (outs VReg_128:$vdata), num_addrs, "AMDGPU",
+    : MIMG_nsa_gfx11<op.GFX11, (outs VReg_128:$vdata), num_addrs, "GFX11",
                      addr_types> {
   let InOperandList = !con(nsah.AddrIns, (ins SReg_128:$srsrc, A16:$a16));
   let AsmString = opcode#" $vdata, "#nsah.AddrAsm#", $srsrc$a16";

diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -104,14 +104,14 @@ class VOP1_DPP_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
   VOP_DPP_Pseudo <OpName, P, pattern> {
 }
 
-class getVOP1Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {
+class getVOP1Pat <SDPatternOperator node, VOPProfile P> : LetDummies {
   list<dag> ret =
     !if(P.HasModifiers,
         [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods P.Src0VT:$src0, i32:$src0_modifiers))))],
         !if(P.HasOMod,
             [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3OMods P.Src0VT:$src0,
                                                   i1:$clamp, i32:$omod))))],
-            [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]
+            [(set P.DstVT:$vdst, (node P.Src0RC32:$src0))]
         )
     );
 }
@@ -233,35 +233,18 @@ let SubtargetPredicate = isGFX940Plus, SchedRW = [Write64Bit] in
 defm V_MOV_B64 : VOP1Inst <"v_mov_b64", VOP_I64_I64>;
 } // End isMoveImm = 1
 
-// FIXME: Specify SchedRW for READFIRSTLANE_B32
-// TODO: Make profile for this, there is VOP3 encoding also
-def V_READFIRSTLANE_B32 :
-  InstSI <(outs SReg_32:$vdst),
-    (ins VRegOrLdsSrc_32:$src0),
-    "v_readfirstlane_b32 $vdst, $src0",
-    [(set i32:$vdst, (int_amdgcn_readfirstlane (i32 VRegOrLdsSrc_32:$src0)))]>,
-  Enc32 {
-
-  let isCodeGenOnly = 0;
-  let UseNamedOperandTable = 1;
-
-  let Size = 4;
-  let mayLoad = 0;
-  let mayStore = 0;
-  let hasSideEffects = 0;
+def VOP_READFIRSTLANE : VOPProfile <[i32, i32, untyped, untyped]> {
+  let DstRC = RegisterOperand<SReg_32>;
+  let Src0RC32 = VRegOrLdsSrc_32;
+  let Asm32 = " $vdst, $src0";
+}
 
-  let VOP1 = 1;
-  let VALU = 1;
-  let Uses = [EXEC];
+// FIXME: Specify SchedRW for READFIRSTLANE_B32
+// TODO: There is VOP3 encoding also
+def V_READFIRSTLANE_B32 : VOP1_Pseudo <"v_readfirstlane_b32", VOP_READFIRSTLANE,
+                                       getVOP1Pat<int_amdgcn_readfirstlane,
+                                                  VOP_READFIRSTLANE>.ret, 1> {
   let isConvergent = 1;
-
-  bits<8> vdst;
-  bits<9> src0;
-
-  let Inst{8-0}   = src0;
-  let Inst{16-9}  = 0x2;
-  let Inst{24-17} = vdst;
-  let Inst{31-25} = 0x3f; //encoding
 }
 
 let isReMaterializable = 1 in {
@@ -726,8 +709,8 @@ def V_ACCVGPR_MOV_B32 : VOP1_Pseudo<"v_accvgpr_mov_b32", VOPProfileAccMov, [], 1
 let SubtargetPredicate = isGFX11Plus in {
   // Restrict src0 to be VGPR
   def V_PERMLANE64_B32 : VOP1_Pseudo<"v_permlane64_b32", VOP_MOVRELS,
-                                      getVOP1Pat64<int_amdgcn_permlane64,
-                                                   VOP_MOVRELS>.ret,
+                                      getVOP1Pat<int_amdgcn_permlane64,
+                                                 VOP_MOVRELS>.ret,
                                       /*VOP1Only=*/ 1>;
   defm V_MOV_B16_t16    : VOP1Inst<"v_mov_b16_t16", VOPProfile_True16<VOP_I16_I16>>;
   defm V_NOT_B16        : VOP1Inst_t16<"v_not_b16", VOP_I16_I16>;
@@ -1109,6 +1092,11 @@ let AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7" in {
       VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
       VOP3e_gfx6_gfx7<{1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
   }
+  multiclass VOP1Only_Real_gfx6_gfx7<bits<9> op> {
+    def _gfx6_gfx7 :
+      VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.SI>,
+      VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME).Pfl>;
+  }
 } // End AssemblerPredicate = isGFX6GFX7, DecoderNamespace = "GFX6GFX7"
 
 multiclass VOP1_Real_gfx6_gfx7<bits<9> op> :
@@ -1125,6 +1113,9 @@ multiclass VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<bits<9> op> :
   VOP1_Real_gfx6_gfx7_gfx10<op>, VOP1_Real_NO_DPP<GFX11Gen, op>,
   VOP1_Real_NO_DPP<GFX12Gen, op>;
 
+multiclass VOP1Only_Real_gfx6_gfx7_gfx10_gfx11_gfx12<bits<9> op> :
+  VOP1Only_Real_gfx6_gfx7<op>, VOP1Only_Real_gfx10_gfx11_gfx12<op>;
+
 defm V_LOG_CLAMP_F32     : VOP1_Real_gfx6_gfx7<0x026>;
 defm V_RCP_CLAMP_F32     : VOP1_Real_gfx6_gfx7<0x028>;
 defm V_RCP_LEGACY_F32    : VOP1_Real_gfx6_gfx7<0x029>;
@@ -1135,6 +1126,7 @@ defm V_RSQ_CLAMP_F64     : VOP1_Real_gfx6_gfx7<0x032>;
 
 defm V_NOP               : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x000>;
 defm V_MOV_B32           : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x001>;
+defm V_READFIRSTLANE_B32 : VOP1Only_Real_gfx6_gfx7_gfx10_gfx11_gfx12<0x002>;
 defm V_CVT_I32_F64       : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x003>;
 defm V_CVT_F64_I32       : VOP1_Real_gfx6_gfx7_gfx10_NO_DPP_gfx11_gfx12<0x004>;
 defm V_CVT_F32_I32       : VOP1_Real_gfx6_gfx7_gfx10_FULL_gfx11_gfx12<0x005>;
@@ -1238,6 +1230,7 @@ multiclass VOP1_Real_vi <bits<10> op> {
 
 defm V_NOP               : VOP1_Real_vi <0x0>;
 defm V_MOV_B32           : VOP1_Real_vi <0x1>;
+defm V_READFIRSTLANE_B32 : VOP1Only_Real_vi <0x2>;
 defm V_CVT_I32_F64       : VOP1_Real_vi <0x3>;
 defm V_CVT_F64_I32       : VOP1_Real_vi <0x4>;
 defm V_CVT_F32_I32       : VOP1_Real_vi <0x5>;

diff --git a/llvm/lib/Target/ARM/ARMTargetObjectFile.cpp b/llvm/lib/Target/ARM/ARMTargetObjectFile.cpp
@@ -16,6 +16,7 @@
 #include "llvm/MC/MCExpr.h"
 #include "llvm/MC/MCSectionELF.h"
 #include "llvm/MC/MCTargetOptions.h"
+#include "llvm/MC/MCValue.h"
 #include "llvm/MC/SectionKind.h"
 #include "llvm/Target/TargetMachine.h"
 #include <cassert>
@@ -56,6 +57,16 @@ void ARMElfTargetObjectFile::Initialize(MCContext &Ctx,
 
 MCRegister ARMElfTargetObjectFile::getStaticBase() const { return ARM::R9; }
 
+const MCExpr *ARMElfTargetObjectFile::getIndirectSymViaGOTPCRel(
+    const GlobalValue *GV, const MCSymbol *Sym, const MCValue &MV,
+    int64_t Offset, MachineModuleInfo *MMI, MCStreamer &Streamer) const {
+  int64_t FinalOffset = Offset + MV.getConstant();
+  const MCExpr *Res = MCSymbolRefExpr::create(
+      Sym, MCSymbolRefExpr::VK_ARM_GOT_PREL, getContext());
+  const MCExpr *Off = MCConstantExpr::create(FinalOffset, getContext());
+  return MCBinaryExpr::createAdd(Res, Off, getContext());
+}
+
 const MCExpr *ARMElfTargetObjectFile::
 getIndirectSymViaRWPI(const MCSymbol *Sym) const {
   return MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_ARM_SBREL,

diff --git a/llvm/lib/Target/ARM/ARMTargetObjectFile.h b/llvm/lib/Target/ARM/ARMTargetObjectFile.h
@@ -19,12 +19,19 @@ class ARMElfTargetObjectFile : public TargetLoweringObjectFileELF {
 public:
   ARMElfTargetObjectFile() {
     PLTRelativeVariantKind = MCSymbolRefExpr::VK_ARM_PREL31;
+    SupportIndirectSymViaGOTPCRel = true;
   }
 
   void Initialize(MCContext &Ctx, const TargetMachine &TM) override;
 
   MCRegister getStaticBase() const override;
 
+  const MCExpr *getIndirectSymViaGOTPCRel(const GlobalValue *GV,
+                                          const MCSymbol *Sym,
+                                          const MCValue &MV, int64_t Offset,
+                                          MachineModuleInfo *MMI,
+                                          MCStreamer &Streamer) const override;
+
   const MCExpr *getIndirectSymViaRWPI(const MCSymbol *Sym) const override;
 
   const MCExpr *getTTypeGlobalReference(const GlobalValue *GV,

diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -641,7 +641,10 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
 
   if (Subtarget.hasStdExtA()) {
     setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
-    setMinCmpXchgSizeInBits(32);
+    if (Subtarget.hasStdExtZabha() && Subtarget.hasStdExtZacas())
+      setMinCmpXchgSizeInBits(8);
+    else
+      setMinCmpXchgSizeInBits(32);
   } else if (Subtarget.hasForcedAtomics()) {
     setMaxAtomicSizeInBitsSupported(Subtarget.getXLen());
   } else {
@@ -19731,12 +19734,16 @@ RISCVTargetLowering::shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const {
     return AtomicExpansionKind::None;
 
   unsigned Size = AI->getType()->getPrimitiveSizeInBits();
-  if (Size == 8 || Size == 16)
-    return AtomicExpansionKind::MaskedIntrinsic;
+  if (AI->getOperation() == AtomicRMWInst::Nand) {
+    if (Subtarget.hasStdExtZacas() &&
+        (Size >= 32 || Subtarget.hasStdExtZabha()))
+      return AtomicExpansionKind::CmpXChg;
+    if (Size < 32)
+      return AtomicExpansionKind::MaskedIntrinsic;
+  }
 
-  if (Subtarget.hasStdExtZacas() && AI->getOperation() == AtomicRMWInst::Nand &&
-      (Size == Subtarget.getXLen() || Size == 32))
-    return AtomicExpansionKind::CmpXChg;
+  if (Size < 32 && !Subtarget.hasStdExtZabha())
+    return AtomicExpansionKind::MaskedIntrinsic;
 
   return AtomicExpansionKind::None;
 }
@@ -19859,7 +19866,8 @@ RISCVTargetLowering::shouldExpandAtomicCmpXchgInIR(
     return AtomicExpansionKind::None;
 
   unsigned Size = CI->getCompareOperand()->getType()->getPrimitiveSizeInBits();
-  if (Size == 8 || Size == 16)
+  if (!(Subtarget.hasStdExtZabha() && Subtarget.hasStdExtZacas()) &&
+      (Size == 8 || Size == 16))
     return AtomicExpansionKind::MaskedIntrinsic;
   return AtomicExpansionKind::None;
 }

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1211,13 +1211,7 @@ bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const {
     if (!Op.isReg())
       return false;
     Register Reg = Op.getReg();
-    if (Reg == RISCV::X0) {
-      Imm = 0;
-      return true;
-    }
-    if (!Reg.isVirtual())
-      return false;
-    return isLoadImm(MRI.getVRegDef(Op.getReg()), Imm);
+    return Reg.isVirtual() && isLoadImm(MRI.getVRegDef(Reg), Imm);
   };
 
   MachineOperand &LHS = MI.getOperand(0);
@@ -1228,7 +1222,8 @@ bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const {
     MachineBasicBlock::reverse_iterator II(&MI), E = MBB->rend();
     auto DefC1 = std::find_if(++II, E, [&](const MachineInstr &I) -> bool {
       int64_t Imm;
-      return isLoadImm(&I, Imm) && Imm == C1;
+      return isLoadImm(&I, Imm) && Imm == C1 &&
+             I.getOperand(0).getReg().isVirtual();
     });
     if (DefC1 != E)
       return DefC1->getOperand(0).getReg();

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZa.td
@@ -185,3 +185,30 @@ let Predicates = [HasStdExtZabha, HasStdExtZacas] in {
 defm AMOCAS_B : AMO_cas_aq_rl<0b00101, 0b000, "amocas.b", GPR>;
 defm AMOCAS_H : AMO_cas_aq_rl<0b00101, 0b001, "amocas.h", GPR>;
 }
+
+/// AMOs
+
+defm : AMOPat<"atomic_swap_8", "AMOSWAP_B", XLenVT, [HasStdExtZabha]>;
+defm : AMOPat<"atomic_load_add_8", "AMOADD_B", XLenVT, [HasStdExtZabha]>;
+defm : AMOPat<"atomic_load_and_8", "AMOAND_B", XLenVT, [HasStdExtZabha]>;
+defm : AMOPat<"atomic_load_or_8", "AMOOR_B", XLenVT, [HasStdExtZabha]>;
+defm : AMOPat<"atomic_load_xor_8", "AMOXOR_B", XLenVT, [HasStdExtZabha]>;
+defm : AMOPat<"atomic_load_max_8", "AMOMAX_B", XLenVT, [HasStdExtZabha]>;
+defm : AMOPat<"atomic_load_min_8", "AMOMIN_B", XLenVT, [HasStdExtZabha]>;
+defm : AMOPat<"atomic_load_umax_8", "AMOMAXU_B", XLenVT, [HasStdExtZabha]>;
+defm : AMOPat<"atomic_load_umin_8", "AMOMINU_B", XLenVT, [HasStdExtZabha]>;
+
+defm : AMOPat<"atomic_swap_16", "AMOSWAP_H", XLenVT, [HasStdExtZabha]>;
+defm : AMOPat<"atomic_load_add_16", "AMOADD_H", XLenVT, [HasStdExtZabha]>;
+defm : AMOPat<"atomic_load_and_16", "AMOAND_H", XLenVT, [HasStdExtZabha]>;
+defm : AMOPat<"atomic_load_or_16", "AMOOR_H", XLenVT, [HasStdExtZabha]>;
+defm : AMOPat<"atomic_load_xor_16", "AMOXOR_H", XLenVT, [HasStdExtZabha]>;
+defm : AMOPat<"atomic_load_max_16", "AMOMAX_H", XLenVT, [HasStdExtZabha]>;
+defm : AMOPat<"atomic_load_min_16", "AMOMIN_H", XLenVT, [HasStdExtZabha]>;
+defm : AMOPat<"atomic_load_umax_16", "AMOMAXU_H", XLenVT, [HasStdExtZabha]>;
+defm : AMOPat<"atomic_load_umin_16", "AMOMINU_H", XLenVT, [HasStdExtZabha]>;
+
+/// AMOCAS
+
+defm : AMOCASPat<"atomic_cmp_swap_8", "AMOCAS_B", XLenVT, [HasStdExtZabha]>;
+defm : AMOCASPat<"atomic_cmp_swap_16", "AMOCAS_H", XLenVT, [HasStdExtZabha]>;
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -432,6 +432,10 @@ InstructionCost RISCVTTIImpl::getShuffleCost(TTI::ShuffleKind Kind,
     // must be implemented here.
     break;
   case TTI::SK_ExtractSubvector:
+    // Extract at zero is always a subregister extract
+    if (Index == 0)
+      return TTI::TCC_Free;
+
     // Example sequence:
     // vsetivli     zero, 4, e8, mf2, tu, ma (ignored)
     // vslidedown.vi  v8, v9, 2

diff --git a/llvm/lib/ToolDrivers/llvm-dlltool/DlltoolDriver.cpp b/llvm/lib/ToolDrivers/llvm-dlltool/DlltoolDriver.cpp
@@ -205,12 +205,12 @@ int llvm::dlltoolDriverMain(llvm::ArrayRef<const char *> ArgsArr) {
 
   std::vector<COFFShortExport> Exports, NativeExports;
 
-  if (Args.hasArg(OPT_n)) {
+  if (Args.hasArg(OPT_N)) {
     if (!isArm64EC(Machine)) {
       llvm::errs() << "native .def file is supported only on arm64ec target\n";
       return 1;
     }
-    if (!parseModuleDefinition(Args.getLastArg(OPT_n)->getValue(),
+    if (!parseModuleDefinition(Args.getLastArg(OPT_N)->getValue(),
                                IMAGE_FILE_MACHINE_ARM64, AddUnderscores,
                                NativeExports, OutputFile))
       return 1;

diff --git a/llvm/lib/ToolDrivers/llvm-dlltool/Options.td b/llvm/lib/ToolDrivers/llvm-dlltool/Options.td
@@ -12,8 +12,8 @@ def D_long : JoinedOrSeparate<["--"], "dllname">, Alias<D>;
 def d: JoinedOrSeparate<["-"], "d">, HelpText<"Input .def File">;
 def d_long : JoinedOrSeparate<["--"], "input-def">, Alias<d>;
 
-def n: JoinedOrSeparate<["-"], "n">, HelpText<"Input native .def File on ARM64EC">;
-def n_long : JoinedOrSeparate<["--"], "input-native-def">, Alias<d>;
+def N: JoinedOrSeparate<["-"], "N">, HelpText<"Input native .def File on ARM64EC">;
+def N_long : JoinedOrSeparate<["--"], "input-native-def">, Alias<N>;
 
 def k: Flag<["-"], "k">, HelpText<"Kill @n Symbol from export">;
 def k_alias: Flag<["--"], "kill-at">, Alias<k>;

diff --git a/llvm/lib/Transforms/Utils/LoopUtils.cpp b/llvm/lib/Transforms/Utils/LoopUtils.cpp
@@ -917,6 +917,58 @@ bool llvm::hasIterationCountInvariantInParent(Loop *InnerLoop,
   return true;
 }
 
+unsigned llvm::getArithmeticReductionInstruction(Intrinsic::ID RdxID) {
+  switch (RdxID) {
+  case Intrinsic::vector_reduce_fadd:
+    return Instruction::FAdd;
+  case Intrinsic::vector_reduce_fmul:
+    return Instruction::FMul;
+  case Intrinsic::vector_reduce_add:
+    return Instruction::Add;
+  case Intrinsic::vector_reduce_mul:
+    return Instruction::Mul;
+  case Intrinsic::vector_reduce_and:
+    return Instruction::And;
+  case Intrinsic::vector_reduce_or:
+    return Instruction::Or;
+  case Intrinsic::vector_reduce_xor:
+    return Instruction::Xor;
+  case Intrinsic::vector_reduce_smax:
+  case Intrinsic::vector_reduce_smin:
+  case Intrinsic::vector_reduce_umax:
+  case Intrinsic::vector_reduce_umin:
+    return Instruction::ICmp;
+  case Intrinsic::vector_reduce_fmax:
+  case Intrinsic::vector_reduce_fmin:
+    return Instruction::FCmp;
+  default:
+    llvm_unreachable("Unexpected ID");
+  }
+}
+
+Intrinsic::ID llvm::getMinMaxReductionIntrinsicOp(Intrinsic::ID RdxID) {
+  switch (RdxID) {
+  default:
+    llvm_unreachable("Unknown min/max recurrence kind");
+  case Intrinsic::vector_reduce_umin:
+    return Intrinsic::umin;
+  case Intrinsic::vector_reduce_umax:
+    return Intrinsic::umax;
+  case Intrinsic::vector_reduce_smin:
+    return Intrinsic::smin;
+  case Intrinsic::vector_reduce_smax:
+    return Intrinsic::smax;
+  case Intrinsic::vector_reduce_fmin:
+    return Intrinsic::minnum;
+  case Intrinsic::vector_reduce_fmax:
+    return Intrinsic::maxnum;
+  case Intrinsic::vector_reduce_fminimum:
+    return Intrinsic::minimum;
+  case Intrinsic::vector_reduce_fmaximum:
+    return Intrinsic::maximum;
+  }
+}
+
 Intrinsic::ID llvm::getMinMaxReductionIntrinsicOp(RecurKind RK) {
   switch (RK) {
   default:
@@ -940,6 +992,25 @@ Intrinsic::ID llvm::getMinMaxReductionIntrinsicOp(RecurKind RK) {
   }
 }
 
+RecurKind llvm::getMinMaxReductionRecurKind(Intrinsic::ID RdxID) {
+  switch (RdxID) {
+  case Intrinsic::vector_reduce_smax:
+    return RecurKind::SMax;
+  case Intrinsic::vector_reduce_smin:
+    return RecurKind::SMin;
+  case Intrinsic::vector_reduce_umax:
+    return RecurKind::UMax;
+  case Intrinsic::vector_reduce_umin:
+    return RecurKind::UMin;
+  case Intrinsic::vector_reduce_fmax:
+    return RecurKind::FMax;
+  case Intrinsic::vector_reduce_fmin:
+    return RecurKind::FMin;
+  default:
+    return RecurKind::None;
+  }
+}
+
 CmpInst::Predicate llvm::getMinMaxReductionPredicate(RecurKind RK) {
   switch (RK) {
   default:

diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll
@@ -52,14 +52,14 @@ define void  @vector_broadcast() {
 
 define void @vector_insert_extract(<vscale x 4 x i32> %v0, <vscale x 16 x i32> %v1, <16 x i32> %v2) {
 ; CHECK-LABEL: 'vector_insert_extract'
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %extract_fixed_from_scalable = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0)
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %extract_fixed_from_scalable = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0)
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %insert_fixed_into_scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> %v0, <16 x i32> %v2, i64 0)
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %extract_scalable_from_scalable = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %v1, i64 0)
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert_scalable_into_scalable = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> %v1, <vscale x 4 x i32> %v0, i64 0)
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
 ;
 ; SIZE-LABEL: 'vector_insert_extract'
-; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %extract_fixed_from_scalable = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0)
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %extract_fixed_from_scalable = call <16 x i32> @llvm.vector.extract.v16i32.nxv4i32(<vscale x 4 x i32> %v0, i64 0)
 ; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert_fixed_into_scalable = call <vscale x 4 x i32> @llvm.vector.insert.nxv4i32.v16i32(<vscale x 4 x i32> %v0, <16 x i32> %v2, i64 0)
 ; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %extract_scalable_from_scalable = call <vscale x 4 x i32> @llvm.vector.extract.nxv4i32.nxv16i32(<vscale x 16 x i32> %v1, i64 0)
 ; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %insert_scalable_into_scalable = call <vscale x 16 x i32> @llvm.vector.insert.nxv16i32.nxv4i32(<vscale x 16 x i32> %v1, <vscale x 4 x i32> %v0, i64 0)

diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-vectorextract.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-vectorextract.ll
@@ -11,13 +11,13 @@ define void @vector_extract_nxv128i8_0(<vscale x 128 x i8> %v) {
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %scalable_m2 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %scalable_m4 = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %scalable_m8 = call <vscale x 64 x i8> @llvm.vector.extract.nxv64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 16 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
 ;
 ; SIZE-LABEL: 'vector_extract_nxv128i8_0'
@@ -28,13 +28,13 @@ define void @vector_extract_nxv128i8_0(<vscale x 128 x i8> %v) {
 ; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %scalable_m2 = call <vscale x 16 x i8> @llvm.vector.extract.nxv16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
 ; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %scalable_m4 = call <vscale x 32 x i8> @llvm.vector.extract.nxv32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
 ; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %scalable_m8 = call <vscale x 64 x i8> @llvm.vector.extract.nxv64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
-; SIZE-NEXT:  Cost Model: Found an estimated cost of 2 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
 ; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret void
 ;
   %scalable_mf8 = call <vscale x 1 x i8> @llvm.vector.extract.nxv1i8.nxv128i8(<vscale x 128 x i8> %v, i64 0)
@@ -110,23 +110,23 @@ define void @vector_extract_nxv128i8_1(<vscale x 128 x i8> %v) {
 
 define void @vector_extract_v128i8_0(<128 x i8> %v) {
 ; CHECK-LABEL: 'vector_extract_v128i8_0'
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.v128i8(<128 x i8> %v, i64 0)
-; CHECK-NEXT:  Cost Model: Found an estimated cost of 8 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.v128i8(<128 x i8> %v, i64 0)
+; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.v128i8(<128 x i8> %v, i64 0)
 ; CHECK-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: ret void
 ;
 ; SIZE-LABEL: 'vector_extract_v128i8_0'
-; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.v128i8(<128 x i8> %v, i64 0)
-; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf4 = call <4 x i8> @llvm.vector.extract.v4i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_mf2 = call <8 x i8> @llvm.vector.extract.v8i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_m1 = call <16 x i8> @llvm.vector.extract.v16i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_m2 = call <32 x i8> @llvm.vector.extract.v32i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_m4 = call <64 x i8> @llvm.vector.extract.v64i8.v128i8(<128 x i8> %v, i64 0)
+; SIZE-NEXT:  Cost Model: Found an estimated cost of 0 for instruction: %fixed_m8 = call <128 x i8> @llvm.vector.extract.v128i8.v128i8(<128 x i8> %v, i64 0)
 ; SIZE-NEXT:  Cost Model: Found an estimated cost of 1 for instruction: ret void
 ;
   %fixed_mf8 = call <2 x i8> @llvm.vector.extract.v2i8.v128i8(<128 x i8> %v, i64 0)
Original file line number	Diff line number	Diff line change
Expand Up		@@ -128,4 +128,3 @@ def tearDown(self):

		# Call super's tearDown().
		TestBase.tearDown(self)